1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
5 * Rick Chang <rick.chang@mediatek.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <media/media-device.h>
21 #include <media/videobuf2-core.h>
22 #include <media/videobuf2-v4l2.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-dev.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fh.h>
27 #include <media/v4l2-event.h>
28
29 #include "mtk_jpeg_core.h"
30 #include "mtk_jpeg_dec_hw.h"
31
32 #define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
33
34 enum mtk_jpeg_color {
35 MTK_JPEG_COLOR_420 = 0x00221111,
36 MTK_JPEG_COLOR_422 = 0x00211111,
37 MTK_JPEG_COLOR_444 = 0x00111111,
38 MTK_JPEG_COLOR_422V = 0x00121111,
39 MTK_JPEG_COLOR_422X2 = 0x00412121,
40 MTK_JPEG_COLOR_422VX2 = 0x00222121,
41 MTK_JPEG_COLOR_400 = 0x00110000
42 };
43
44 static const struct of_device_id mtk_jpegdec_hw_ids[] = {
45 {
46 .compatible = "mediatek,mt8195-jpgdec-hw",
47 },
48 {},
49 };
50 MODULE_DEVICE_TABLE(of, mtk_jpegdec_hw_ids);
51
mtk_jpeg_verify_align(u32 val,int align,u32 reg)52 static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg)
53 {
54 if (val & (align - 1)) {
55 pr_err("mtk-jpeg: write reg %x without %d align\n", reg, align);
56 return -1;
57 }
58
59 return 0;
60 }
61
mtk_jpeg_decide_format(struct mtk_jpeg_dec_param * param)62 static int mtk_jpeg_decide_format(struct mtk_jpeg_dec_param *param)
63 {
64 param->src_color = (param->sampling_w[0] << 20) |
65 (param->sampling_h[0] << 16) |
66 (param->sampling_w[1] << 12) |
67 (param->sampling_h[1] << 8) |
68 (param->sampling_w[2] << 4) |
69 (param->sampling_h[2]);
70
71 param->uv_brz_w = 0;
72 switch (param->src_color) {
73 case MTK_JPEG_COLOR_444:
74 param->uv_brz_w = 1;
75 param->dst_fourcc = V4L2_PIX_FMT_YUV422M;
76 break;
77 case MTK_JPEG_COLOR_422X2:
78 case MTK_JPEG_COLOR_422:
79 param->dst_fourcc = V4L2_PIX_FMT_YUV422M;
80 break;
81 case MTK_JPEG_COLOR_422V:
82 case MTK_JPEG_COLOR_422VX2:
83 param->uv_brz_w = 1;
84 param->dst_fourcc = V4L2_PIX_FMT_YUV420M;
85 break;
86 case MTK_JPEG_COLOR_420:
87 param->dst_fourcc = V4L2_PIX_FMT_YUV420M;
88 break;
89 case MTK_JPEG_COLOR_400:
90 param->dst_fourcc = V4L2_PIX_FMT_GREY;
91 break;
92 default:
93 param->dst_fourcc = 0;
94 return -1;
95 }
96
97 return 0;
98 }
99
mtk_jpeg_calc_mcu(struct mtk_jpeg_dec_param * param)100 static void mtk_jpeg_calc_mcu(struct mtk_jpeg_dec_param *param)
101 {
102 u32 factor_w, factor_h;
103 u32 i, comp, blk;
104
105 factor_w = 2 + param->sampling_w[0];
106 factor_h = 2 + param->sampling_h[0];
107 param->mcu_w = (param->pic_w + (1 << factor_w) - 1) >> factor_w;
108 param->mcu_h = (param->pic_h + (1 << factor_h) - 1) >> factor_h;
109 param->total_mcu = param->mcu_w * param->mcu_h;
110 param->unit_num = ((param->pic_w + 7) >> 3) * ((param->pic_h + 7) >> 3);
111 param->blk_num = 0;
112 for (i = 0; i < MTK_JPEG_COMP_MAX; i++) {
113 param->blk_comp[i] = 0;
114 if (i >= param->comp_num)
115 continue;
116 param->blk_comp[i] = param->sampling_w[i] *
117 param->sampling_h[i];
118 param->blk_num += param->blk_comp[i];
119 }
120
121 param->membership = 0;
122 for (i = 0, blk = 0, comp = 0; i < MTK_JPEG_BLOCK_MAX; i++) {
123 if (i < param->blk_num && comp < param->comp_num) {
124 u32 tmp;
125
126 tmp = (0x04 + (comp & 0x3));
127 param->membership |= tmp << (i * 3);
128 if (++blk == param->blk_comp[comp]) {
129 comp++;
130 blk = 0;
131 }
132 } else {
133 param->membership |= 7 << (i * 3);
134 }
135 }
136 }
137
mtk_jpeg_calc_dma_group(struct mtk_jpeg_dec_param * param)138 static void mtk_jpeg_calc_dma_group(struct mtk_jpeg_dec_param *param)
139 {
140 u32 factor_mcu = 3;
141
142 if (param->src_color == MTK_JPEG_COLOR_444 &&
143 param->dst_fourcc == V4L2_PIX_FMT_YUV422M)
144 factor_mcu = 4;
145 else if (param->src_color == MTK_JPEG_COLOR_422V &&
146 param->dst_fourcc == V4L2_PIX_FMT_YUV420M)
147 factor_mcu = 4;
148 else if (param->src_color == MTK_JPEG_COLOR_422X2 &&
149 param->dst_fourcc == V4L2_PIX_FMT_YUV422M)
150 factor_mcu = 2;
151 else if (param->src_color == MTK_JPEG_COLOR_400 ||
152 (param->src_color & 0x0FFFF) == 0)
153 factor_mcu = 4;
154
155 param->dma_mcu = 1 << factor_mcu;
156 param->dma_group = param->mcu_w / param->dma_mcu;
157 param->dma_last_mcu = param->mcu_w % param->dma_mcu;
158 if (param->dma_last_mcu)
159 param->dma_group++;
160 else
161 param->dma_last_mcu = param->dma_mcu;
162 }
163
mtk_jpeg_calc_dst_size(struct mtk_jpeg_dec_param * param)164 static int mtk_jpeg_calc_dst_size(struct mtk_jpeg_dec_param *param)
165 {
166 u32 i, padding_w;
167 u32 ds_row_h[3];
168 u32 brz_w[3];
169
170 brz_w[0] = 0;
171 brz_w[1] = param->uv_brz_w;
172 brz_w[2] = brz_w[1];
173
174 for (i = 0; i < param->comp_num; i++) {
175 if (brz_w[i] > 3)
176 return -1;
177
178 padding_w = param->mcu_w * MTK_JPEG_DCTSIZE *
179 param->sampling_w[i];
180 /* output format is 420/422 */
181 param->comp_w[i] = padding_w >> brz_w[i];
182 param->comp_w[i] = round_up(param->comp_w[i],
183 MTK_JPEG_DCTSIZE);
184 param->img_stride[i] = i ? round_up(param->comp_w[i], 16)
185 : round_up(param->comp_w[i], 32);
186 ds_row_h[i] = (MTK_JPEG_DCTSIZE * param->sampling_h[i]);
187 }
188 param->dec_w = param->img_stride[0];
189 param->dec_h = ds_row_h[0] * param->mcu_h;
190
191 for (i = 0; i < MTK_JPEG_COMP_MAX; i++) {
192 /* They must be equal in frame mode. */
193 param->mem_stride[i] = param->img_stride[i];
194 param->comp_size[i] = param->mem_stride[i] * ds_row_h[i] *
195 param->mcu_h;
196 }
197
198 param->y_size = param->comp_size[0];
199 param->uv_size = param->comp_size[1];
200 param->dec_size = param->y_size + (param->uv_size << 1);
201
202 return 0;
203 }
204
mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param * param)205 int mtk_jpeg_dec_fill_param(struct mtk_jpeg_dec_param *param)
206 {
207 if (mtk_jpeg_decide_format(param))
208 return -1;
209
210 mtk_jpeg_calc_mcu(param);
211 mtk_jpeg_calc_dma_group(param);
212 if (mtk_jpeg_calc_dst_size(param))
213 return -2;
214
215 return 0;
216 }
217 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_fill_param);
218
mtk_jpeg_dec_get_int_status(void __iomem * base)219 u32 mtk_jpeg_dec_get_int_status(void __iomem *base)
220 {
221 u32 ret;
222
223 ret = readl(base + JPGDEC_REG_INTERRUPT_STATUS) & BIT_INQST_MASK_ALLIRQ;
224 if (ret)
225 writel(ret, base + JPGDEC_REG_INTERRUPT_STATUS);
226
227 return ret;
228 }
229 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_get_int_status);
230
mtk_jpeg_dec_enum_result(u32 irq_result)231 u32 mtk_jpeg_dec_enum_result(u32 irq_result)
232 {
233 if (irq_result & BIT_INQST_MASK_EOF)
234 return MTK_JPEG_DEC_RESULT_EOF_DONE;
235 if (irq_result & BIT_INQST_MASK_PAUSE)
236 return MTK_JPEG_DEC_RESULT_PAUSE;
237 if (irq_result & BIT_INQST_MASK_UNDERFLOW)
238 return MTK_JPEG_DEC_RESULT_UNDERFLOW;
239 if (irq_result & BIT_INQST_MASK_OVERFLOW)
240 return MTK_JPEG_DEC_RESULT_OVERFLOW;
241 if (irq_result & BIT_INQST_MASK_ERROR_BS)
242 return MTK_JPEG_DEC_RESULT_ERROR_BS;
243
244 return MTK_JPEG_DEC_RESULT_ERROR_UNKNOWN;
245 }
246 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_enum_result);
247
mtk_jpeg_dec_start(void __iomem * base)248 void mtk_jpeg_dec_start(void __iomem *base)
249 {
250 writel(0, base + JPGDEC_REG_TRIG);
251 }
252 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_start);
253
mtk_jpeg_dec_soft_reset(void __iomem * base)254 static void mtk_jpeg_dec_soft_reset(void __iomem *base)
255 {
256 writel(0x0000FFFF, base + JPGDEC_REG_INTERRUPT_STATUS);
257 writel(0x00, base + JPGDEC_REG_RESET);
258 writel(0x01, base + JPGDEC_REG_RESET);
259 }
260
mtk_jpeg_dec_hard_reset(void __iomem * base)261 static void mtk_jpeg_dec_hard_reset(void __iomem *base)
262 {
263 writel(0x00, base + JPGDEC_REG_RESET);
264 writel(0x10, base + JPGDEC_REG_RESET);
265 }
266
mtk_jpeg_dec_reset(void __iomem * base)267 void mtk_jpeg_dec_reset(void __iomem *base)
268 {
269 mtk_jpeg_dec_soft_reset(base);
270 mtk_jpeg_dec_hard_reset(base);
271 }
272 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_reset);
273
mtk_jpeg_dec_set_brz_factor(void __iomem * base,u8 yscale_w,u8 yscale_h,u8 uvscale_w,u8 uvscale_h)274 static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w,
275 u8 yscale_h, u8 uvscale_w, u8 uvscale_h)
276 {
277 u32 val;
278
279 val = (uvscale_h << 12) | (uvscale_w << 8) |
280 (yscale_h << 4) | yscale_w;
281 writel(val, base + JPGDEC_REG_BRZ_FACTOR);
282 }
283
mtk_jpeg_dec_set_dst_bank0(void __iomem * base,bool support_34bit,dma_addr_t addr_y,dma_addr_t addr_u,dma_addr_t addr_v)284 static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, bool support_34bit,
285 dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
286 {
287 u32 val;
288
289 mtk_jpeg_verify_align(addr_y, 16, JPGDEC_REG_DEST_ADDR0_Y);
290 writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR0_Y);
291 mtk_jpeg_verify_align(addr_u, 16, JPGDEC_REG_DEST_ADDR0_U);
292 writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR0_U);
293 mtk_jpeg_verify_align(addr_v, 16, JPGDEC_REG_DEST_ADDR0_V);
294 writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR0_V);
295 if (support_34bit) {
296 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));
297 writel(val, base + JPGDEC_REG_DEST_ADDR0_Y_EXT);
298 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));
299 writel(val, base + JPGDEC_REG_DEST_ADDR0_U_EXT);
300 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));
301 writel(val, base + JPGDEC_REG_DEST_ADDR0_V_EXT);
302 }
303 }
304
mtk_jpeg_dec_set_dst_bank1(void __iomem * base,bool support_34bit,dma_addr_t addr_y,dma_addr_t addr_u,dma_addr_t addr_v)305 static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, bool support_34bit,
306 dma_addr_t addr_y, dma_addr_t addr_u, dma_addr_t addr_v)
307 {
308 u32 val;
309
310 writel(lower_32_bits(addr_y), base + JPGDEC_REG_DEST_ADDR1_Y);
311 writel(lower_32_bits(addr_u), base + JPGDEC_REG_DEST_ADDR1_U);
312 writel(lower_32_bits(addr_v), base + JPGDEC_REG_DEST_ADDR1_V);
313 if (support_34bit) {
314 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_y));
315 writel(val, base + JPGDEC_REG_DEST_ADDR1_Y_EXT);
316 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_u));
317 writel(val, base + JPGDEC_REG_DEST_ADDR1_U_EXT);
318 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr_v));
319 writel(val, base + JPGDEC_REG_DEST_ADDR1_V_EXT);
320 }
321 }
322
mtk_jpeg_dec_set_mem_stride(void __iomem * base,u32 stride_y,u32 stride_uv)323 static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y,
324 u32 stride_uv)
325 {
326 writel((stride_y & 0xFFFF), base + JPGDEC_REG_STRIDE_Y);
327 writel((stride_uv & 0xFFFF), base + JPGDEC_REG_STRIDE_UV);
328 }
329
mtk_jpeg_dec_set_img_stride(void __iomem * base,u32 stride_y,u32 stride_uv)330 static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y,
331 u32 stride_uv)
332 {
333 writel((stride_y & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_Y);
334 writel((stride_uv & 0xFFFF), base + JPGDEC_REG_IMG_STRIDE_UV);
335 }
336
mtk_jpeg_dec_set_pause_mcu_idx(void __iomem * base,u32 idx)337 static void mtk_jpeg_dec_set_pause_mcu_idx(void __iomem *base, u32 idx)
338 {
339 writel(idx & 0x0003FFFFFF, base + JPGDEC_REG_PAUSE_MCU_NUM);
340 }
341
mtk_jpeg_dec_set_dec_mode(void __iomem * base,u32 mode)342 static void mtk_jpeg_dec_set_dec_mode(void __iomem *base, u32 mode)
343 {
344 writel(mode & 0x03, base + JPGDEC_REG_OPERATION_MODE);
345 }
346
mtk_jpeg_dec_set_bs_write_ptr(void __iomem * base,bool support_34bit,dma_addr_t ptr)347 static void mtk_jpeg_dec_set_bs_write_ptr(void __iomem *base, bool support_34bit, dma_addr_t ptr)
348 {
349 u32 val;
350
351 mtk_jpeg_verify_align(ptr, 16, JPGDEC_REG_FILE_BRP);
352 writel(lower_32_bits(ptr), base + JPGDEC_REG_FILE_BRP);
353 if (support_34bit) {
354 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(ptr));
355 writel(val, base + JPGDEC_REG_FILE_BRP_EXT);
356 }
357 }
358
mtk_jpeg_dec_set_bs_info(void __iomem * base,bool support_34bit,dma_addr_t addr,u32 size,u32 bitstream_size)359 static void mtk_jpeg_dec_set_bs_info(void __iomem *base, bool support_34bit,
360 dma_addr_t addr, u32 size, u32 bitstream_size)
361 {
362 u32 val;
363
364 mtk_jpeg_verify_align(addr, 16, JPGDEC_REG_FILE_ADDR);
365 mtk_jpeg_verify_align(size, 128, JPGDEC_REG_FILE_TOTAL_SIZE);
366 writel(lower_32_bits(addr), base + JPGDEC_REG_FILE_ADDR);
367 if (support_34bit) {
368 val = FIELD_PREP(MTK_JPEG_ADDR_MASK, upper_32_bits(addr));
369 writel(val, base + JPGDEC_REG_FILE_ADDR_EXT);
370 }
371 writel(size, base + JPGDEC_REG_FILE_TOTAL_SIZE);
372 writel(bitstream_size, base + JPGDEC_REG_BIT_STREAM_SIZE);
373 }
374
mtk_jpeg_dec_set_comp_id(void __iomem * base,u32 id_y,u32 id_u,u32 id_v)375 static void mtk_jpeg_dec_set_comp_id(void __iomem *base, u32 id_y, u32 id_u,
376 u32 id_v)
377 {
378 u32 val;
379
380 val = ((id_y & 0x00FF) << 24) | ((id_u & 0x00FF) << 16) |
381 ((id_v & 0x00FF) << 8);
382 writel(val, base + JPGDEC_REG_COMP_ID);
383 }
384
mtk_jpeg_dec_set_total_mcu(void __iomem * base,u32 num)385 static void mtk_jpeg_dec_set_total_mcu(void __iomem *base, u32 num)
386 {
387 writel(num - 1, base + JPGDEC_REG_TOTAL_MCU_NUM);
388 }
389
mtk_jpeg_dec_set_comp0_du(void __iomem * base,u32 num)390 static void mtk_jpeg_dec_set_comp0_du(void __iomem *base, u32 num)
391 {
392 writel(num - 1, base + JPGDEC_REG_COMP0_DATA_UNIT_NUM);
393 }
394
mtk_jpeg_dec_set_du_membership(void __iomem * base,u32 member,u32 gmc,u32 isgray)395 static void mtk_jpeg_dec_set_du_membership(void __iomem *base, u32 member,
396 u32 gmc, u32 isgray)
397 {
398 if (isgray)
399 member = 0x3FFFFFFC;
400 member |= (isgray << 31) | (gmc << 30);
401 writel(member, base + JPGDEC_REG_DU_CTRL);
402 }
403
mtk_jpeg_dec_set_q_table(void __iomem * base,u32 id0,u32 id1,u32 id2)404 static void mtk_jpeg_dec_set_q_table(void __iomem *base, u32 id0, u32 id1,
405 u32 id2)
406 {
407 u32 val;
408
409 val = ((id0 & 0x0f) << 8) | ((id1 & 0x0f) << 4) | ((id2 & 0x0f) << 0);
410 writel(val, base + JPGDEC_REG_QT_ID);
411 }
412
mtk_jpeg_dec_set_dma_group(void __iomem * base,u32 mcu_group,u32 group_num,u32 last_mcu)413 static void mtk_jpeg_dec_set_dma_group(void __iomem *base, u32 mcu_group,
414 u32 group_num, u32 last_mcu)
415 {
416 u32 val;
417
418 val = (((mcu_group - 1) & 0x00FF) << 16) |
419 (((group_num - 1) & 0x007F) << 8) |
420 ((last_mcu - 1) & 0x00FF);
421 writel(val, base + JPGDEC_REG_WDMA_CTRL);
422 }
423
mtk_jpeg_dec_set_sampling_factor(void __iomem * base,u32 comp_num,u32 y_w,u32 y_h,u32 u_w,u32 u_h,u32 v_w,u32 v_h)424 static void mtk_jpeg_dec_set_sampling_factor(void __iomem *base, u32 comp_num,
425 u32 y_w, u32 y_h, u32 u_w,
426 u32 u_h, u32 v_w, u32 v_h)
427 {
428 u32 val;
429 u32 y_wh = (MTK_JPEG_DUNUM_MASK(y_w) << 2) | MTK_JPEG_DUNUM_MASK(y_h);
430 u32 u_wh = (MTK_JPEG_DUNUM_MASK(u_w) << 2) | MTK_JPEG_DUNUM_MASK(u_h);
431 u32 v_wh = (MTK_JPEG_DUNUM_MASK(v_w) << 2) | MTK_JPEG_DUNUM_MASK(v_h);
432
433 if (comp_num == 1)
434 val = 0;
435 else
436 val = (y_wh << 8) | (u_wh << 4) | v_wh;
437 writel(val, base + JPGDEC_REG_DU_NUM);
438 }
439
mtk_jpeg_dec_set_config(void __iomem * base,bool support_34bits,struct mtk_jpeg_dec_param * cfg,u32 bitstream_size,struct mtk_jpeg_bs * bs,struct mtk_jpeg_fb * fb)440 void mtk_jpeg_dec_set_config(void __iomem *base,
441 bool support_34bits,
442 struct mtk_jpeg_dec_param *cfg,
443 u32 bitstream_size,
444 struct mtk_jpeg_bs *bs,
445 struct mtk_jpeg_fb *fb)
446 {
447 mtk_jpeg_dec_set_brz_factor(base, 0, 0, cfg->uv_brz_w, 0);
448 mtk_jpeg_dec_set_dec_mode(base, 0);
449 mtk_jpeg_dec_set_comp0_du(base, cfg->unit_num);
450 mtk_jpeg_dec_set_total_mcu(base, cfg->total_mcu);
451 mtk_jpeg_dec_set_bs_info(base, support_34bits, bs->str_addr, bs->size, bitstream_size);
452 mtk_jpeg_dec_set_bs_write_ptr(base, support_34bits, bs->end_addr);
453 mtk_jpeg_dec_set_du_membership(base, cfg->membership, 1,
454 (cfg->comp_num == 1) ? 1 : 0);
455 mtk_jpeg_dec_set_comp_id(base, cfg->comp_id[0], cfg->comp_id[1],
456 cfg->comp_id[2]);
457 mtk_jpeg_dec_set_q_table(base, cfg->qtbl_num[0],
458 cfg->qtbl_num[1], cfg->qtbl_num[2]);
459 mtk_jpeg_dec_set_sampling_factor(base, cfg->comp_num,
460 cfg->sampling_w[0],
461 cfg->sampling_h[0],
462 cfg->sampling_w[1],
463 cfg->sampling_h[1],
464 cfg->sampling_w[2],
465 cfg->sampling_h[2]);
466 mtk_jpeg_dec_set_mem_stride(base, cfg->mem_stride[0],
467 cfg->mem_stride[1]);
468 mtk_jpeg_dec_set_img_stride(base, cfg->img_stride[0],
469 cfg->img_stride[1]);
470 mtk_jpeg_dec_set_dst_bank0(base, support_34bits, fb->plane_addr[0],
471 fb->plane_addr[1], fb->plane_addr[2]);
472 mtk_jpeg_dec_set_dst_bank1(base, support_34bits, 0, 0, 0);
473 mtk_jpeg_dec_set_dma_group(base, cfg->dma_mcu, cfg->dma_group,
474 cfg->dma_last_mcu);
475 mtk_jpeg_dec_set_pause_mcu_idx(base, cfg->total_mcu);
476 }
477 EXPORT_SYMBOL_GPL(mtk_jpeg_dec_set_config);
478
mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev * jpeg)479 static void mtk_jpegdec_put_buf(struct mtk_jpegdec_comp_dev *jpeg)
480 {
481 struct mtk_jpeg_src_buf *dst_done_buf, *tmp_dst_done_buf;
482 struct vb2_v4l2_buffer *dst_buffer;
483 struct list_head *temp_entry;
484 struct list_head *pos = NULL;
485 struct mtk_jpeg_ctx *ctx;
486 unsigned long flags;
487
488 ctx = jpeg->hw_param.curr_ctx;
489 if (unlikely(!ctx)) {
490 dev_err(jpeg->dev, "comp_jpeg ctx fail !!!\n");
491 return;
492 }
493
494 dst_buffer = jpeg->hw_param.dst_buffer;
495 if (!dst_buffer) {
496 dev_err(jpeg->dev, "comp_jpeg dst_buffer fail !!!\n");
497 return;
498 }
499
500 dst_done_buf = container_of(dst_buffer, struct mtk_jpeg_src_buf, b);
501
502 spin_lock_irqsave(&ctx->done_queue_lock, flags);
503 list_add_tail(&dst_done_buf->list, &ctx->dst_done_queue);
504 while (!list_empty(&ctx->dst_done_queue) &&
505 (pos != &ctx->dst_done_queue)) {
506 list_for_each_prev_safe(pos, temp_entry, &ctx->dst_done_queue) {
507 tmp_dst_done_buf = list_entry(pos,
508 struct mtk_jpeg_src_buf,
509 list);
510 if (tmp_dst_done_buf->frame_num ==
511 ctx->last_done_frame_num) {
512 list_del(&tmp_dst_done_buf->list);
513 v4l2_m2m_buf_done(&tmp_dst_done_buf->b,
514 VB2_BUF_STATE_DONE);
515 ctx->last_done_frame_num++;
516 }
517 }
518 }
519 spin_unlock_irqrestore(&ctx->done_queue_lock, flags);
520 }
521
mtk_jpegdec_timeout_work(struct work_struct * work)522 static void mtk_jpegdec_timeout_work(struct work_struct *work)
523 {
524 enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
525 struct mtk_jpegdec_comp_dev *cjpeg =
526 container_of(work, struct mtk_jpegdec_comp_dev,
527 job_timeout_work.work);
528 struct mtk_jpeg_dev *master_jpeg = cjpeg->master_dev;
529 struct vb2_v4l2_buffer *src_buf, *dst_buf;
530
531 src_buf = cjpeg->hw_param.src_buffer;
532 dst_buf = cjpeg->hw_param.dst_buffer;
533 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
534
535 mtk_jpeg_dec_reset(cjpeg->reg_base);
536 clk_disable_unprepare(cjpeg->jdec_clk.clks->clk);
537 pm_runtime_put(cjpeg->dev);
538 cjpeg->hw_state = MTK_JPEG_HW_IDLE;
539 atomic_inc(&master_jpeg->hw_rdy);
540 wake_up(&master_jpeg->hw_wq);
541 v4l2_m2m_buf_done(src_buf, buf_state);
542 mtk_jpegdec_put_buf(cjpeg);
543 }
544
mtk_jpegdec_hw_irq_handler(int irq,void * priv)545 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv)
546 {
547 struct vb2_v4l2_buffer *src_buf, *dst_buf;
548 struct mtk_jpeg_src_buf *jpeg_src_buf;
549 enum vb2_buffer_state buf_state;
550 struct mtk_jpeg_ctx *ctx;
551 u32 dec_irq_ret;
552 u32 irq_status;
553 int i;
554
555 struct mtk_jpegdec_comp_dev *jpeg = priv;
556 struct mtk_jpeg_dev *master_jpeg = jpeg->master_dev;
557
558 cancel_delayed_work(&jpeg->job_timeout_work);
559
560 ctx = jpeg->hw_param.curr_ctx;
561 src_buf = jpeg->hw_param.src_buffer;
562 dst_buf = jpeg->hw_param.dst_buffer;
563 v4l2_m2m_buf_copy_metadata(src_buf, dst_buf);
564
565 irq_status = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
566 dec_irq_ret = mtk_jpeg_dec_enum_result(irq_status);
567 if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
568 mtk_jpeg_dec_reset(jpeg->reg_base);
569
570 if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE)
571 dev_warn(jpeg->dev, "Jpg Dec occurs unknown Err.");
572
573 jpeg_src_buf =
574 container_of(src_buf, struct mtk_jpeg_src_buf, b);
575
576 for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
577 vb2_set_plane_payload(&dst_buf->vb2_buf, i,
578 jpeg_src_buf->dec_param.comp_size[i]);
579
580 buf_state = VB2_BUF_STATE_DONE;
581 v4l2_m2m_buf_done(src_buf, buf_state);
582 mtk_jpegdec_put_buf(jpeg);
583 pm_runtime_put(ctx->jpeg->dev);
584 clk_disable_unprepare(jpeg->jdec_clk.clks->clk);
585
586 jpeg->hw_state = MTK_JPEG_HW_IDLE;
587 wake_up(&master_jpeg->hw_wq);
588 atomic_inc(&master_jpeg->hw_rdy);
589
590 return IRQ_HANDLED;
591 }
592
mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev * dev)593 static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev)
594 {
595 struct platform_device *pdev = dev->plat_dev;
596 int ret;
597
598 dev->jpegdec_irq = platform_get_irq(pdev, 0);
599 if (dev->jpegdec_irq < 0)
600 return dev->jpegdec_irq;
601
602 ret = devm_request_irq(&pdev->dev,
603 dev->jpegdec_irq,
604 mtk_jpegdec_hw_irq_handler,
605 0,
606 pdev->name, dev);
607 if (ret) {
608 dev_err(&pdev->dev, "Failed to devm_request_irq %d (%d)",
609 dev->jpegdec_irq, ret);
610 return ret;
611 }
612
613 return 0;
614 }
615
mtk_jpegdec_hw_probe(struct platform_device * pdev)616 static int mtk_jpegdec_hw_probe(struct platform_device *pdev)
617 {
618 struct mtk_jpegdec_clk *jpegdec_clk;
619 struct mtk_jpeg_dev *master_dev;
620 struct mtk_jpegdec_comp_dev *dev;
621 int ret, i;
622
623 struct device *decs = &pdev->dev;
624
625 if (!decs->parent)
626 return -EPROBE_DEFER;
627
628 master_dev = dev_get_drvdata(decs->parent);
629 if (!master_dev)
630 return -EPROBE_DEFER;
631
632 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
633 if (!dev)
634 return -ENOMEM;
635
636 dev->plat_dev = pdev;
637 dev->dev = &pdev->dev;
638
639 spin_lock_init(&dev->hw_lock);
640 dev->hw_state = MTK_JPEG_HW_IDLE;
641
642 INIT_DELAYED_WORK(&dev->job_timeout_work,
643 mtk_jpegdec_timeout_work);
644
645 jpegdec_clk = &dev->jdec_clk;
646
647 jpegdec_clk->clk_num = devm_clk_bulk_get_all(&pdev->dev,
648 &jpegdec_clk->clks);
649 if (jpegdec_clk->clk_num < 0)
650 return dev_err_probe(&pdev->dev,
651 jpegdec_clk->clk_num,
652 "Failed to get jpegdec clock count.\n");
653
654 dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
655 if (IS_ERR(dev->reg_base))
656 return PTR_ERR(dev->reg_base);
657
658 ret = mtk_jpegdec_hw_init_irq(dev);
659 if (ret)
660 return dev_err_probe(&pdev->dev, ret,
661 "Failed to register JPEGDEC irq handler.\n");
662
663 i = atomic_add_return(1, &master_dev->hw_index) - 1;
664 master_dev->dec_hw_dev[i] = dev;
665 master_dev->reg_decbase[i] = dev->reg_base;
666 dev->master_dev = master_dev;
667
668 platform_set_drvdata(pdev, dev);
669 pm_runtime_enable(&pdev->dev);
670
671 return 0;
672 }
673
674 static struct platform_driver mtk_jpegdec_hw_driver = {
675 .probe = mtk_jpegdec_hw_probe,
676 .driver = {
677 .name = "mtk-jpegdec-hw",
678 .of_match_table = mtk_jpegdec_hw_ids,
679 },
680 };
681
682 module_platform_driver(mtk_jpegdec_hw_driver);
683
684 MODULE_DESCRIPTION("MediaTek JPEG decode HW driver");
685 MODULE_LICENSE("GPL");
686