xref: /qemu/target/sh4/cpu.c (revision 3072961b6edc99abfbd87caac3de29bb58a52ccf)
1 /*
2  * QEMU SuperH CPU
3  *
4  * Copyright (c) 2005 Samuel Tardieu
5  * Copyright (c) 2012 SUSE LINUX Products GmbH
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see
19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
20  */
21 
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
25 #include "cpu.h"
26 #include "migration/vmstate.h"
27 #include "exec/translation-block.h"
28 #include "fpu/softfloat-helpers.h"
29 #include "accel/tcg/cpu-ops.h"
30 #include "tcg/tcg.h"
31 
superh_cpu_set_pc(CPUState * cs,vaddr value)32 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
33 {
34     SuperHCPU *cpu = SUPERH_CPU(cs);
35 
36     cpu->env.pc = value;
37 }
38 
superh_cpu_get_pc(CPUState * cs)39 static vaddr superh_cpu_get_pc(CPUState *cs)
40 {
41     SuperHCPU *cpu = SUPERH_CPU(cs);
42 
43     return cpu->env.pc;
44 }
45 
superh_get_tb_cpu_state(CPUState * cs)46 static TCGTBCPUState superh_get_tb_cpu_state(CPUState *cs)
47 {
48     CPUSH4State *env = cpu_env(cs);
49     uint32_t flags;
50 
51     flags = env->flags
52             | (env->fpscr & TB_FLAG_FPSCR_MASK)
53             | (env->sr & TB_FLAG_SR_MASK)
54             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
55 #ifdef CONFIG_USER_ONLY
56     flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus;
57 #endif
58 
59     return (TCGTBCPUState){
60         .pc = env->pc,
61         .flags = flags,
62 #ifdef CONFIG_USER_ONLY
63         /* For a gUSA region, notice the end of the region.  */
64         .cs_base = flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0,
65 #endif
66     };
67 }
68 
superh_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)69 static void superh_cpu_synchronize_from_tb(CPUState *cs,
70                                            const TranslationBlock *tb)
71 {
72     SuperHCPU *cpu = SUPERH_CPU(cs);
73 
74     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
75     cpu->env.pc = tb->pc;
76     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
77 }
78 
superh_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)79 static void superh_restore_state_to_opc(CPUState *cs,
80                                         const TranslationBlock *tb,
81                                         const uint64_t *data)
82 {
83     SuperHCPU *cpu = SUPERH_CPU(cs);
84 
85     cpu->env.pc = data[0];
86     cpu->env.flags = data[1];
87     /*
88      * Theoretically delayed_pc should also be restored. In practice the
89      * branch instruction is re-executed after exception, so the delayed
90      * branch target will be recomputed.
91      */
92 }
93 
94 #ifndef CONFIG_USER_ONLY
superh_io_recompile_replay_branch(CPUState * cs,const TranslationBlock * tb)95 static bool superh_io_recompile_replay_branch(CPUState *cs,
96                                               const TranslationBlock *tb)
97 {
98     CPUSH4State *env = cpu_env(cs);
99 
100     if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
101         && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) {
102         env->pc -= 2;
103         env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
104         return true;
105     }
106     return false;
107 }
108 
superh_cpu_has_work(CPUState * cs)109 static bool superh_cpu_has_work(CPUState *cs)
110 {
111     return cs->interrupt_request & CPU_INTERRUPT_HARD;
112 }
113 #endif /* !CONFIG_USER_ONLY */
114 
sh4_cpu_mmu_index(CPUState * cs,bool ifetch)115 static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
116 {
117     CPUSH4State *env = cpu_env(cs);
118 
119     /*
120      * The instruction in a RTE delay slot is fetched in privileged mode,
121      * but executed in user mode.
122      */
123     if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
124         return 0;
125     } else {
126         return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
127     }
128 }
129 
superh_cpu_reset_hold(Object * obj,ResetType type)130 static void superh_cpu_reset_hold(Object *obj, ResetType type)
131 {
132     CPUState *cs = CPU(obj);
133     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj);
134     CPUSH4State *env = cpu_env(cs);
135 
136     if (scc->parent_phases.hold) {
137         scc->parent_phases.hold(obj, type);
138     }
139 
140     memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
141 
142     env->pc = 0xA0000000;
143 #if defined(CONFIG_USER_ONLY)
144     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
145     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
146 #else
147     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
148               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
149     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
150     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
151     set_flush_to_zero(1, &env->fp_status);
152 #endif
153     set_default_nan_mode(1, &env->fp_status);
154     set_snan_bit_is_one(true, &env->fp_status);
155     /* sign bit clear, set all frac bits other than msb */
156     set_float_default_nan_pattern(0b00111111, &env->fp_status);
157     /*
158      * TODO: "SH-4 CPU Core Architecture ADCS 7182230F" doesn't say whether
159      * it detects tininess before or after rounding. Section 6.4 is clear
160      * that flush-to-zero happens when the result underflows, though, so
161      * either this should be "detect ftz after rounding" or else we should
162      * be setting "detect tininess before rounding".
163      */
164     set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
165 }
166 
superh_cpu_disas_set_info(CPUState * cpu,disassemble_info * info)167 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
168 {
169     info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
170                                      : BFD_ENDIAN_LITTLE;
171     info->mach = bfd_mach_sh4;
172     info->print_insn = print_insn_sh;
173 }
174 
superh_cpu_class_by_name(const char * cpu_model)175 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
176 {
177     ObjectClass *oc;
178     char *s, *typename = NULL;
179 
180     s = g_ascii_strdown(cpu_model, -1);
181     if (strcmp(s, "any") == 0) {
182         oc = object_class_by_name(TYPE_SH7750R_CPU);
183         goto out;
184     }
185 
186     typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
187     oc = object_class_by_name(typename);
188 
189 out:
190     g_free(s);
191     g_free(typename);
192     return oc;
193 }
194 
sh7750r_cpu_initfn(Object * obj)195 static void sh7750r_cpu_initfn(Object *obj)
196 {
197     CPUSH4State *env = cpu_env(CPU(obj));
198 
199     env->id = SH_CPU_SH7750R;
200     env->features = SH_FEATURE_BCR3_AND_BCR4;
201 }
202 
sh7750r_class_init(ObjectClass * oc,const void * data)203 static void sh7750r_class_init(ObjectClass *oc, const void *data)
204 {
205     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
206 
207     scc->pvr = 0x00050000;
208     scc->prr = 0x00000100;
209     scc->cvr = 0x00110000;
210 }
211 
sh7751r_cpu_initfn(Object * obj)212 static void sh7751r_cpu_initfn(Object *obj)
213 {
214     CPUSH4State *env = cpu_env(CPU(obj));
215 
216     env->id = SH_CPU_SH7751R;
217     env->features = SH_FEATURE_BCR3_AND_BCR4;
218 }
219 
sh7751r_class_init(ObjectClass * oc,const void * data)220 static void sh7751r_class_init(ObjectClass *oc, const void *data)
221 {
222     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
223 
224     scc->pvr = 0x04050005;
225     scc->prr = 0x00000113;
226     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
227 }
228 
sh7785_cpu_initfn(Object * obj)229 static void sh7785_cpu_initfn(Object *obj)
230 {
231     CPUSH4State *env = cpu_env(CPU(obj));
232 
233     env->id = SH_CPU_SH7785;
234     env->features = SH_FEATURE_SH4A;
235 }
236 
sh7785_class_init(ObjectClass * oc,const void * data)237 static void sh7785_class_init(ObjectClass *oc, const void *data)
238 {
239     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
240 
241     scc->pvr = 0x10300700;
242     scc->prr = 0x00000200;
243     scc->cvr = 0x71440211;
244 }
245 
superh_cpu_realizefn(DeviceState * dev,Error ** errp)246 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
247 {
248     CPUState *cs = CPU(dev);
249     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
250     Error *local_err = NULL;
251 
252     cpu_exec_realizefn(cs, &local_err);
253     if (local_err != NULL) {
254         error_propagate(errp, local_err);
255         return;
256     }
257 
258     cpu_reset(cs);
259     qemu_init_vcpu(cs);
260 
261     scc->parent_realize(dev, errp);
262 }
263 
superh_cpu_initfn(Object * obj)264 static void superh_cpu_initfn(Object *obj)
265 {
266     CPUSH4State *env = cpu_env(CPU(obj));
267 
268     env->movcal_backup_tail = &(env->movcal_backup);
269 }
270 
271 #ifndef CONFIG_USER_ONLY
272 static const VMStateDescription vmstate_sh_cpu = {
273     .name = "cpu",
274     .unmigratable = 1,
275 };
276 
277 #include "hw/core/sysemu-cpu-ops.h"
278 
279 static const struct SysemuCPUOps sh4_sysemu_ops = {
280     .has_work = superh_cpu_has_work,
281     .get_phys_page_debug = superh_cpu_get_phys_page_debug,
282 };
283 #endif
284 
285 static const TCGCPUOps superh_tcg_ops = {
286     /* MTTCG not yet supported: require strict ordering */
287     .guest_default_memory_order = TCG_MO_ALL,
288     .mttcg_supported = false,
289 
290     .initialize = sh4_translate_init,
291     .translate_code = sh4_translate_code,
292     .get_tb_cpu_state = superh_get_tb_cpu_state,
293     .synchronize_from_tb = superh_cpu_synchronize_from_tb,
294     .restore_state_to_opc = superh_restore_state_to_opc,
295     .mmu_index = sh4_cpu_mmu_index,
296 
297 #ifndef CONFIG_USER_ONLY
298     .tlb_fill = superh_cpu_tlb_fill,
299     .pointer_wrap = cpu_pointer_wrap_notreached,
300     .cpu_exec_interrupt = superh_cpu_exec_interrupt,
301     .cpu_exec_halt = superh_cpu_has_work,
302     .cpu_exec_reset = cpu_reset,
303     .do_interrupt = superh_cpu_do_interrupt,
304     .do_unaligned_access = superh_cpu_do_unaligned_access,
305     .io_recompile_replay_branch = superh_io_recompile_replay_branch,
306 #endif /* !CONFIG_USER_ONLY */
307 };
308 
superh_cpu_class_init(ObjectClass * oc,const void * data)309 static void superh_cpu_class_init(ObjectClass *oc, const void *data)
310 {
311     DeviceClass *dc = DEVICE_CLASS(oc);
312     CPUClass *cc = CPU_CLASS(oc);
313     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
314     ResettableClass *rc = RESETTABLE_CLASS(oc);
315 
316     device_class_set_parent_realize(dc, superh_cpu_realizefn,
317                                     &scc->parent_realize);
318 
319     resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
320                                        &scc->parent_phases);
321 
322     cc->class_by_name = superh_cpu_class_by_name;
323     cc->dump_state = superh_cpu_dump_state;
324     cc->set_pc = superh_cpu_set_pc;
325     cc->get_pc = superh_cpu_get_pc;
326     cc->gdb_read_register = superh_cpu_gdb_read_register;
327     cc->gdb_write_register = superh_cpu_gdb_write_register;
328 #ifndef CONFIG_USER_ONLY
329     cc->sysemu_ops = &sh4_sysemu_ops;
330     dc->vmsd = &vmstate_sh_cpu;
331 #endif
332     cc->disas_set_info = superh_cpu_disas_set_info;
333 
334     cc->gdb_num_core_regs = 59;
335     cc->tcg_ops = &superh_tcg_ops;
336 }
337 
338 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
339     {                                                    \
340         .name = type_name,                               \
341         .parent = TYPE_SUPERH_CPU,                       \
342         .class_init = cinit,                             \
343         .instance_init = initfn,                         \
344     }
345 static const TypeInfo superh_cpu_type_infos[] = {
346     {
347         .name = TYPE_SUPERH_CPU,
348         .parent = TYPE_CPU,
349         .instance_size = sizeof(SuperHCPU),
350         .instance_align = __alignof(SuperHCPU),
351         .instance_init = superh_cpu_initfn,
352         .abstract = true,
353         .class_size = sizeof(SuperHCPUClass),
354         .class_init = superh_cpu_class_init,
355     },
356     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
357                            sh7750r_cpu_initfn),
358     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
359                            sh7751r_cpu_initfn),
360     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
361                            sh7785_cpu_initfn),
362 
363 };
364 
365 DEFINE_TYPES(superh_cpu_type_infos)
366