1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
31 */
32
33 #ifndef _GVT_H_
34 #define _GVT_H_
35
36 #include <uapi/linux/pci_regs.h>
37 #include <linux/vfio.h>
38 #include <linux/mdev.h>
39
40 #include <asm/kvm_page_track.h>
41
42 #include "gt/intel_gt.h"
43 #include "intel_gvt.h"
44
45 #include "debug.h"
46 #include "mmio.h"
47 #include "reg.h"
48 #include "interrupt.h"
49 #include "gtt.h"
50 #include "display.h"
51 #include "edid.h"
52 #include "execlist.h"
53 #include "scheduler.h"
54 #include "sched_policy.h"
55 #include "mmio_context.h"
56 #include "cmd_parser.h"
57 #include "fb_decoder.h"
58 #include "dmabuf.h"
59 #include "page_track.h"
60
61 #define GVT_MAX_VGPU 8
62
63 struct engine_mmio;
64
65 /* Describe per-platform limitations. */
66 struct intel_gvt_device_info {
67 u32 max_support_vgpus;
68 u32 cfg_space_size;
69 u32 mmio_size;
70 u32 mmio_bar;
71 unsigned long msi_cap_offset;
72 u32 gtt_start_offset;
73 u32 gtt_entry_size;
74 u32 gtt_entry_size_shift;
75 int gmadr_bytes_in_cmd;
76 u32 max_surface_size;
77 };
78
79 /* GM resources owned by a vGPU */
80 struct intel_vgpu_gm {
81 u64 aperture_sz;
82 u64 hidden_sz;
83 struct drm_mm_node low_gm_node;
84 struct drm_mm_node high_gm_node;
85 };
86
87 #define INTEL_GVT_MAX_NUM_FENCES 32
88
89 /* Fences owned by a vGPU */
90 struct intel_vgpu_fence {
91 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
92 u32 base;
93 u32 size;
94 };
95
96 struct intel_vgpu_mmio {
97 void *vreg;
98 };
99
100 #define INTEL_GVT_MAX_BAR_NUM 4
101
102 struct intel_vgpu_pci_bar {
103 u64 size;
104 bool tracked;
105 };
106
107 struct intel_vgpu_cfg_space {
108 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
109 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
110 u32 pmcsr_off;
111 };
112
113 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
114
115 struct intel_vgpu_irq {
116 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
117 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
118 INTEL_GVT_EVENT_MAX);
119 };
120
121 struct intel_vgpu_opregion {
122 bool mapped;
123 void *va;
124 u32 gfn[INTEL_GVT_OPREGION_PAGES];
125 };
126
127 #define vgpu_opregion(vgpu) (&(vgpu->opregion))
128
129 struct intel_vgpu_display {
130 struct intel_vgpu_i2c_edid i2c_edid;
131 struct intel_vgpu_port ports[I915_MAX_PORTS];
132 struct intel_vgpu_sbi sbi;
133 enum port port_num;
134 };
135
136 struct vgpu_sched_ctl {
137 int weight;
138 };
139
140 enum {
141 INTEL_VGPU_EXECLIST_SUBMISSION = 1,
142 INTEL_VGPU_GUC_SUBMISSION,
143 };
144
145 struct intel_vgpu_submission_ops {
146 const char *name;
147 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
148 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
149 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
150 };
151
152 struct intel_vgpu_submission {
153 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
154 struct list_head workload_q_head[I915_NUM_ENGINES];
155 struct intel_context *shadow[I915_NUM_ENGINES];
156 struct kmem_cache *workloads;
157 atomic_t running_workload_num;
158 union {
159 u64 i915_context_pml4;
160 u64 i915_context_pdps[GEN8_3LVL_PDPES];
161 };
162 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
163 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
164 void *ring_scan_buffer[I915_NUM_ENGINES];
165 int ring_scan_buffer_size[I915_NUM_ENGINES];
166 const struct intel_vgpu_submission_ops *ops;
167 int virtual_submission_interface;
168 bool active;
169 struct {
170 u32 lrca;
171 bool valid;
172 u64 ring_context_gpa;
173 } last_ctx[I915_NUM_ENGINES];
174 };
175
176 #define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries"
177
178 enum {
179 INTEL_VGPU_STATUS_ATTACHED = 0,
180 INTEL_VGPU_STATUS_ACTIVE,
181 INTEL_VGPU_STATUS_NR_BITS,
182 };
183
184 struct intel_vgpu {
185 struct vfio_device vfio_device;
186 struct intel_gvt *gvt;
187 struct mutex vgpu_lock;
188 int id;
189 DECLARE_BITMAP(status, INTEL_VGPU_STATUS_NR_BITS);
190 bool pv_notified;
191 bool failsafe;
192 unsigned int resetting_eng;
193
194 /* Both sched_data and sched_ctl can be seen a part of the global gvt
195 * scheduler structure. So below 2 vgpu data are protected
196 * by sched_lock, not vgpu_lock.
197 */
198 void *sched_data;
199 struct vgpu_sched_ctl sched_ctl;
200
201 struct intel_vgpu_fence fence;
202 struct intel_vgpu_gm gm;
203 struct intel_vgpu_cfg_space cfg_space;
204 struct intel_vgpu_mmio mmio;
205 struct intel_vgpu_irq irq;
206 struct intel_vgpu_gtt gtt;
207 struct intel_vgpu_opregion opregion;
208 struct intel_vgpu_display display;
209 struct intel_vgpu_submission submission;
210 struct radix_tree_root page_track_tree;
211 u32 hws_pga[I915_NUM_ENGINES];
212 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
213 bool d3_entered;
214
215 struct dentry *debugfs;
216
217 struct list_head dmabuf_obj_list_head;
218 struct mutex dmabuf_lock;
219 struct idr object_idr;
220 struct intel_vgpu_vblank_timer vblank_timer;
221
222 u32 scan_nonprivbb;
223
224 struct vfio_region *region;
225 int num_regions;
226 struct eventfd_ctx *intx_trigger;
227 struct eventfd_ctx *msi_trigger;
228
229 /*
230 * Two caches are used to avoid mapping duplicated pages (eg.
231 * scratch pages). This help to reduce dma setup overhead.
232 */
233 struct rb_root gfn_cache;
234 struct rb_root dma_addr_cache;
235 unsigned long nr_cache_entries;
236 struct mutex cache_lock;
237
238 struct kvm_page_track_notifier_node track_node;
239 #define NR_BKT (1 << 18)
240 struct hlist_head ptable[NR_BKT];
241 #undef NR_BKT
242 };
243
244 /* validating GM healthy status*/
245 #define vgpu_is_vm_unhealthy(ret_val) \
246 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
247
248 struct intel_gvt_gm {
249 unsigned long vgpu_allocated_low_gm_size;
250 unsigned long vgpu_allocated_high_gm_size;
251 };
252
253 struct intel_gvt_fence {
254 unsigned long vgpu_allocated_fence_num;
255 };
256
257 /* Special MMIO blocks. */
258 struct gvt_mmio_block {
259 unsigned int device;
260 i915_reg_t offset;
261 unsigned int size;
262 gvt_mmio_func read;
263 gvt_mmio_func write;
264 };
265
266 #define INTEL_GVT_MMIO_HASH_BITS 11
267
268 struct intel_gvt_mmio {
269 u16 *mmio_attribute;
270 /* Register contains RO bits */
271 #define F_RO (1 << 0)
272 /* Register contains graphics address */
273 #define F_GMADR (1 << 1)
274 /* Mode mask registers with high 16 bits as the mask bits */
275 #define F_MODE_MASK (1 << 2)
276 /* This reg can be accessed by GPU commands */
277 #define F_CMD_ACCESS (1 << 3)
278 /* This reg has been accessed by a VM */
279 #define F_ACCESSED (1 << 4)
280 /* This reg requires save & restore during host PM suspend/resume */
281 #define F_PM_SAVE (1 << 5)
282 /* This reg could be accessed by unaligned address */
283 #define F_UNALIGN (1 << 6)
284 /* This reg is in GVT's mmio save-restor list and in hardware
285 * logical context image
286 */
287 #define F_SR_IN_CTX (1 << 7)
288 /* Value of command write of this reg needs to be patched */
289 #define F_CMD_WRITE_PATCH (1 << 8)
290
291 struct gvt_mmio_block *mmio_block;
292 unsigned int num_mmio_block;
293
294 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
295 unsigned long num_tracked_mmio;
296 };
297
298 struct intel_gvt_firmware {
299 void *cfg_space;
300 void *mmio;
301 bool firmware_loaded;
302 };
303
304 struct intel_vgpu_config {
305 unsigned int low_mm;
306 unsigned int high_mm;
307 unsigned int fence;
308
309 /*
310 * A vGPU with a weight of 8 will get twice as much GPU as a vGPU with
311 * a weight of 4 on a contended host, different vGPU type has different
312 * weight set. Legal weights range from 1 to 16.
313 */
314 unsigned int weight;
315 enum intel_vgpu_edid edid;
316 const char *name;
317 };
318
319 struct intel_vgpu_type {
320 struct mdev_type type;
321 char name[16];
322 const struct intel_vgpu_config *conf;
323 };
324
325 struct intel_gvt {
326 /* GVT scope lock, protect GVT itself, and all resource currently
327 * not yet protected by special locks(vgpu and scheduler lock).
328 */
329 struct mutex lock;
330 /* scheduler scope lock, protect gvt and vgpu schedule related data */
331 struct mutex sched_lock;
332
333 struct intel_gt *gt;
334 struct idr vgpu_idr; /* vGPU IDR pool */
335
336 struct intel_gvt_device_info device_info;
337 struct intel_gvt_gm gm;
338 struct intel_gvt_fence fence;
339 struct intel_gvt_mmio mmio;
340 struct intel_gvt_firmware firmware;
341 struct intel_gvt_irq irq;
342 struct intel_gvt_gtt gtt;
343 struct intel_gvt_workload_scheduler scheduler;
344 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
345 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
346 struct mdev_parent parent;
347 struct mdev_type **mdev_types;
348 struct intel_vgpu_type *types;
349 unsigned int num_types;
350 struct intel_vgpu *idle_vgpu;
351
352 struct task_struct *service_thread;
353 wait_queue_head_t service_thread_wq;
354
355 /* service_request is always used in bit operation, we should always
356 * use it with atomic bit ops so that no need to use gvt big lock.
357 */
358 unsigned long service_request;
359
360 struct {
361 struct engine_mmio *mmio;
362 int ctx_mmio_count[I915_NUM_ENGINES];
363 u32 *tlb_mmio_offset_list;
364 u32 tlb_mmio_offset_list_cnt;
365 u32 *mocs_mmio_offset_list;
366 u32 mocs_mmio_offset_list_cnt;
367 } engine_mmio_list;
368 bool is_reg_whitelist_updated;
369
370 struct dentry *debugfs_root;
371 };
372
373 enum {
374 /* Scheduling trigger by timer */
375 INTEL_GVT_REQUEST_SCHED = 0,
376
377 /* Scheduling trigger by event */
378 INTEL_GVT_REQUEST_EVENT_SCHED = 1,
379
380 /* per-vGPU vblank emulation request */
381 INTEL_GVT_REQUEST_EMULATE_VBLANK = 2,
382 INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK
383 + GVT_MAX_VGPU,
384 };
385
intel_gvt_request_service(struct intel_gvt * gvt,int service)386 static inline void intel_gvt_request_service(struct intel_gvt *gvt,
387 int service)
388 {
389 set_bit(service, (void *)&gvt->service_request);
390 wake_up(&gvt->service_thread_wq);
391 }
392
393 void intel_gvt_free_firmware(struct intel_gvt *gvt);
394 int intel_gvt_load_firmware(struct intel_gvt *gvt);
395
396 /* Aperture/GM space definitions for GVT device */
397 #define MB_TO_BYTES(mb) ((mb) << 20ULL)
398 #define BYTES_TO_MB(b) ((b) >> 20ULL)
399
400 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
401 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
402 #define HOST_FENCE 4
403
404 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
405
406 /* Aperture/GM space definitions for GVT device */
407 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
408 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
409
410 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
411 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
412 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
413
414 #define gvt_aperture_gmadr_base(gvt) (0)
415 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
416 + gvt_aperture_sz(gvt) - 1)
417
418 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
419 + gvt_aperture_sz(gvt))
420 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
421 + gvt_hidden_sz(gvt) - 1)
422
423 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
424
425 /* Aperture/GM space definitions for vGPU */
426 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
427 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
428 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
429 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
430
431 #define vgpu_aperture_pa_base(vgpu) \
432 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
433
434 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
435
436 #define vgpu_aperture_pa_end(vgpu) \
437 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
438
439 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
440 #define vgpu_aperture_gmadr_end(vgpu) \
441 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
442
443 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
444 #define vgpu_hidden_gmadr_end(vgpu) \
445 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
446
447 #define vgpu_fence_base(vgpu) (vgpu->fence.base)
448 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
449
450 /* ring context size i.e. the first 0x50 dwords*/
451 #define RING_CTX_SIZE 320
452
453 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
454 const struct intel_vgpu_config *conf);
455 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
456 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
457 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
458 u32 fence, u64 value);
459
460 /* Macros for easily accessing vGPU virtual/shadow register.
461 Explicitly seperate use for typed MMIO reg or real offset.*/
462 #define vgpu_vreg_t(vgpu, reg) \
463 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
464 #define vgpu_vreg(vgpu, offset) \
465 (*(u32 *)(vgpu->mmio.vreg + (offset)))
466 #define vgpu_vreg64_t(vgpu, reg) \
467 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
468 #define vgpu_vreg64(vgpu, offset) \
469 (*(u64 *)(vgpu->mmio.vreg + (offset)))
470
471 #define for_each_active_vgpu(gvt, vgpu, id) \
472 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
473 for_each_if(test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
474
intel_vgpu_write_pci_bar(struct intel_vgpu * vgpu,u32 offset,u32 val,bool low)475 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
476 u32 offset, u32 val, bool low)
477 {
478 u32 *pval;
479
480 /* BAR offset should be 32 bits algiend */
481 offset = rounddown(offset, 4);
482 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
483
484 if (low) {
485 /*
486 * only update bit 31 - bit 4,
487 * leave the bit 3 - bit 0 unchanged.
488 */
489 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
490 } else {
491 *pval = val;
492 }
493 }
494
495 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
496 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
497
498 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
499 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
500 int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
501 const struct intel_vgpu_config *conf);
502 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
503 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
504 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
505 intel_engine_mask_t engine_mask);
506 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
507 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
508 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
509
510 int intel_gvt_set_opregion(struct intel_vgpu *vgpu);
511 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num);
512
513 /* validating GM functions */
514 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \
515 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
516 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
517
518 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \
519 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
520 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
521
522 #define vgpu_gmadr_is_valid(vgpu, gmadr) \
523 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
524 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
525
526 #define gvt_gmadr_is_aperture(gvt, gmadr) \
527 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
528 (gmadr <= gvt_aperture_gmadr_end(gvt)))
529
530 #define gvt_gmadr_is_hidden(gvt, gmadr) \
531 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
532 (gmadr <= gvt_hidden_gmadr_end(gvt)))
533
534 #define gvt_gmadr_is_valid(gvt, gmadr) \
535 (gvt_gmadr_is_aperture(gvt, gmadr) || \
536 gvt_gmadr_is_hidden(gvt, gmadr))
537
538 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
539 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
540 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
541 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
542 unsigned long *h_index);
543 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
544 unsigned long *g_index);
545
546 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
547 bool primary);
548 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
549
550 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
551 void *p_data, unsigned int bytes);
552
553 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
554 void *p_data, unsigned int bytes);
555
556 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
557
intel_vgpu_get_bar_gpa(struct intel_vgpu * vgpu,int bar)558 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
559 {
560 /* We are 64bit bar. */
561 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
562 PCI_BASE_ADDRESS_MEM_MASK;
563 }
564
565 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
566 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
567 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
568
569 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
570 void populate_pvinfo_page(struct intel_vgpu *vgpu);
571
572 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
573 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
574 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu);
575
576 enum {
577 GVT_FAILSAFE_UNSUPPORTED_GUEST,
578 GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
579 GVT_FAILSAFE_GUEST_ERR,
580 };
581
mmio_hw_access_pre(struct intel_gt * gt)582 static inline void mmio_hw_access_pre(struct intel_gt *gt)
583 {
584 intel_runtime_pm_get(gt->uncore->rpm);
585 }
586
mmio_hw_access_post(struct intel_gt * gt)587 static inline void mmio_hw_access_post(struct intel_gt *gt)
588 {
589 intel_runtime_pm_put_unchecked(gt->uncore->rpm);
590 }
591
592 /**
593 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
594 * @gvt: a GVT device
595 * @offset: register offset
596 *
597 */
intel_gvt_mmio_set_accessed(struct intel_gvt * gvt,unsigned int offset)598 static inline void intel_gvt_mmio_set_accessed(
599 struct intel_gvt *gvt, unsigned int offset)
600 {
601 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
602 }
603
604 /**
605 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command
606 * @gvt: a GVT device
607 * @offset: register offset
608 *
609 * Returns:
610 * True if an MMIO is able to be accessed by GPU commands
611 */
intel_gvt_mmio_is_cmd_accessible(struct intel_gvt * gvt,unsigned int offset)612 static inline bool intel_gvt_mmio_is_cmd_accessible(
613 struct intel_gvt *gvt, unsigned int offset)
614 {
615 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
616 }
617
618 /**
619 * intel_gvt_mmio_set_cmd_accessible -
620 * mark a MMIO could be accessible by command
621 * @gvt: a GVT device
622 * @offset: register offset
623 *
624 */
intel_gvt_mmio_set_cmd_accessible(struct intel_gvt * gvt,unsigned int offset)625 static inline void intel_gvt_mmio_set_cmd_accessible(
626 struct intel_gvt *gvt, unsigned int offset)
627 {
628 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;
629 }
630
631 /**
632 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
633 * @gvt: a GVT device
634 * @offset: register offset
635 *
636 */
intel_gvt_mmio_is_unalign(struct intel_gvt * gvt,unsigned int offset)637 static inline bool intel_gvt_mmio_is_unalign(
638 struct intel_gvt *gvt, unsigned int offset)
639 {
640 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
641 }
642
643 /**
644 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
645 * @gvt: a GVT device
646 * @offset: register offset
647 *
648 * Returns:
649 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
650 *
651 */
intel_gvt_mmio_has_mode_mask(struct intel_gvt * gvt,unsigned int offset)652 static inline bool intel_gvt_mmio_has_mode_mask(
653 struct intel_gvt *gvt, unsigned int offset)
654 {
655 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
656 }
657
658 /**
659 * intel_gvt_mmio_is_sr_in_ctx -
660 * check if an MMIO has F_SR_IN_CTX mask
661 * @gvt: a GVT device
662 * @offset: register offset
663 *
664 * Returns:
665 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't.
666 *
667 */
intel_gvt_mmio_is_sr_in_ctx(struct intel_gvt * gvt,unsigned int offset)668 static inline bool intel_gvt_mmio_is_sr_in_ctx(
669 struct intel_gvt *gvt, unsigned int offset)
670 {
671 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
672 }
673
674 /**
675 * intel_gvt_mmio_set_sr_in_ctx -
676 * mask an MMIO in GVT's mmio save-restore list and also
677 * in hardware logical context image
678 * @gvt: a GVT device
679 * @offset: register offset
680 *
681 */
intel_gvt_mmio_set_sr_in_ctx(struct intel_gvt * gvt,unsigned int offset)682 static inline void intel_gvt_mmio_set_sr_in_ctx(
683 struct intel_gvt *gvt, unsigned int offset)
684 {
685 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
686 }
687
688 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
689 /**
690 * intel_gvt_mmio_set_cmd_write_patch -
691 * mark an MMIO if its cmd write needs to be
692 * patched
693 * @gvt: a GVT device
694 * @offset: register offset
695 *
696 */
intel_gvt_mmio_set_cmd_write_patch(struct intel_gvt * gvt,unsigned int offset)697 static inline void intel_gvt_mmio_set_cmd_write_patch(
698 struct intel_gvt *gvt, unsigned int offset)
699 {
700 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH;
701 }
702
703 /**
704 * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to
705 * be patched
706 * @gvt: a GVT device
707 * @offset: register offset
708 *
709 * Returns:
710 * True if GPU commmand write to an MMIO should be patched
711 */
intel_gvt_mmio_is_cmd_write_patch(struct intel_gvt * gvt,unsigned int offset)712 static inline bool intel_gvt_mmio_is_cmd_write_patch(
713 struct intel_gvt *gvt, unsigned int offset)
714 {
715 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH;
716 }
717
718 /**
719 * intel_gvt_read_gpa - copy data from GPA to host data buffer
720 * @vgpu: a vGPU
721 * @gpa: guest physical address
722 * @buf: host data buffer
723 * @len: data length
724 *
725 * Returns:
726 * Zero on success, negative error code if failed.
727 */
intel_gvt_read_gpa(struct intel_vgpu * vgpu,unsigned long gpa,void * buf,unsigned long len)728 static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa,
729 void *buf, unsigned long len)
730 {
731 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
732 return -ESRCH;
733 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);
734 }
735
736 /**
737 * intel_gvt_write_gpa - copy data from host data buffer to GPA
738 * @vgpu: a vGPU
739 * @gpa: guest physical address
740 * @buf: host data buffer
741 * @len: data length
742 *
743 * Returns:
744 * Zero on success, negative error code if failed.
745 */
intel_gvt_write_gpa(struct intel_vgpu * vgpu,unsigned long gpa,void * buf,unsigned long len)746 static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu,
747 unsigned long gpa, void *buf, unsigned long len)
748 {
749 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
750 return -ESRCH;
751 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);
752 }
753
754 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
755 void intel_gvt_debugfs_init(struct intel_gvt *gvt);
756 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
757
758 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn);
759 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn);
760 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr);
761 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
762 unsigned long size, dma_addr_t *dma_addr);
763 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu,
764 dma_addr_t dma_addr);
765
766 #include "trace.h"
767
768 #endif
769