xref: /qemu/target/s390x/tcg/crypto_helper.c (revision 84307cd6027c4602913177ff09aeefa4743b7234)
1 /*
2  *  s390x crypto helpers
3  *
4  *  Copyright (C) 2022 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
5  *  Copyright (c) 2017 Red Hat Inc
6  *
7  *  Authors:
8  *   David Hildenbrand <david@redhat.com>
9  *   Jason A. Donenfeld <Jason@zx2c4.com>
10  *
11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
12  * See the COPYING file in the top-level directory.
13  */
14 
15 #include "qemu/osdep.h"
16 #include "qemu/guest-random.h"
17 #include "s390x-internal.h"
18 #include "tcg_s390x.h"
19 #include "exec/helper-proto.h"
20 #include "accel/tcg/cpu-ldst.h"
21 
R(uint64_t x,int c)22 static uint64_t R(uint64_t x, int c)
23 {
24     return (x >> c) | (x << (64 - c));
25 }
Ch(uint64_t x,uint64_t y,uint64_t z)26 static uint64_t Ch(uint64_t x, uint64_t y, uint64_t z)
27 {
28     return (x & y) ^ (~x & z);
29 }
Maj(uint64_t x,uint64_t y,uint64_t z)30 static uint64_t Maj(uint64_t x, uint64_t y, uint64_t z)
31 {
32     return (x & y) ^ (x & z) ^ (y & z);
33 }
Sigma0(uint64_t x)34 static uint64_t Sigma0(uint64_t x)
35 {
36     return R(x, 28) ^ R(x, 34) ^ R(x, 39);
37 }
Sigma1(uint64_t x)38 static uint64_t Sigma1(uint64_t x)
39 {
40     return R(x, 14) ^ R(x, 18) ^ R(x, 41);
41 }
sigma0(uint64_t x)42 static uint64_t sigma0(uint64_t x)
43 {
44     return R(x, 1) ^ R(x, 8) ^ (x >> 7);
45 }
sigma1(uint64_t x)46 static uint64_t sigma1(uint64_t x)
47 {
48     return R(x, 19) ^ R(x, 61) ^ (x >> 6);
49 }
50 
51 static const uint64_t K[80] = {
52     0x428a2f98d728ae22ULL, 0x7137449123ef65cdULL, 0xb5c0fbcfec4d3b2fULL,
53     0xe9b5dba58189dbbcULL, 0x3956c25bf348b538ULL, 0x59f111f1b605d019ULL,
54     0x923f82a4af194f9bULL, 0xab1c5ed5da6d8118ULL, 0xd807aa98a3030242ULL,
55     0x12835b0145706fbeULL, 0x243185be4ee4b28cULL, 0x550c7dc3d5ffb4e2ULL,
56     0x72be5d74f27b896fULL, 0x80deb1fe3b1696b1ULL, 0x9bdc06a725c71235ULL,
57     0xc19bf174cf692694ULL, 0xe49b69c19ef14ad2ULL, 0xefbe4786384f25e3ULL,
58     0x0fc19dc68b8cd5b5ULL, 0x240ca1cc77ac9c65ULL, 0x2de92c6f592b0275ULL,
59     0x4a7484aa6ea6e483ULL, 0x5cb0a9dcbd41fbd4ULL, 0x76f988da831153b5ULL,
60     0x983e5152ee66dfabULL, 0xa831c66d2db43210ULL, 0xb00327c898fb213fULL,
61     0xbf597fc7beef0ee4ULL, 0xc6e00bf33da88fc2ULL, 0xd5a79147930aa725ULL,
62     0x06ca6351e003826fULL, 0x142929670a0e6e70ULL, 0x27b70a8546d22ffcULL,
63     0x2e1b21385c26c926ULL, 0x4d2c6dfc5ac42aedULL, 0x53380d139d95b3dfULL,
64     0x650a73548baf63deULL, 0x766a0abb3c77b2a8ULL, 0x81c2c92e47edaee6ULL,
65     0x92722c851482353bULL, 0xa2bfe8a14cf10364ULL, 0xa81a664bbc423001ULL,
66     0xc24b8b70d0f89791ULL, 0xc76c51a30654be30ULL, 0xd192e819d6ef5218ULL,
67     0xd69906245565a910ULL, 0xf40e35855771202aULL, 0x106aa07032bbd1b8ULL,
68     0x19a4c116b8d2d0c8ULL, 0x1e376c085141ab53ULL, 0x2748774cdf8eeb99ULL,
69     0x34b0bcb5e19b48a8ULL, 0x391c0cb3c5c95a63ULL, 0x4ed8aa4ae3418acbULL,
70     0x5b9cca4f7763e373ULL, 0x682e6ff3d6b2b8a3ULL, 0x748f82ee5defb2fcULL,
71     0x78a5636f43172f60ULL, 0x84c87814a1f0ab72ULL, 0x8cc702081a6439ecULL,
72     0x90befffa23631e28ULL, 0xa4506cebde82bde9ULL, 0xbef9a3f7b2c67915ULL,
73     0xc67178f2e372532bULL, 0xca273eceea26619cULL, 0xd186b8c721c0c207ULL,
74     0xeada7dd6cde0eb1eULL, 0xf57d4f7fee6ed178ULL, 0x06f067aa72176fbaULL,
75     0x0a637dc5a2c898a6ULL, 0x113f9804bef90daeULL, 0x1b710b35131c471bULL,
76     0x28db77f523047d84ULL, 0x32caab7b40c72493ULL, 0x3c9ebe0a15c9bebcULL,
77     0x431d67c49c100d4cULL, 0x4cc5d4becb3e42b6ULL, 0x597f299cfc657e2aULL,
78     0x5fcb6fab3ad6faecULL, 0x6c44198c4a475817ULL
79 };
80 
81 /* a is icv/ocv, w is a single message block. w will get reused internally. */
sha512_bda(uint64_t a[8],uint64_t w[16])82 static void sha512_bda(uint64_t a[8], uint64_t w[16])
83 {
84     uint64_t t, z[8], b[8];
85     int i, j;
86 
87     memcpy(z, a, sizeof(z));
88     for (i = 0; i < 80; i++) {
89         memcpy(b, a, sizeof(b));
90 
91         t = a[7] + Sigma1(a[4]) + Ch(a[4], a[5], a[6]) + K[i] + w[i % 16];
92         b[7] = t + Sigma0(a[0]) + Maj(a[0], a[1], a[2]);
93         b[3] += t;
94         for (j = 0; j < 8; ++j) {
95             a[(j + 1) % 8] = b[j];
96         }
97         if (i % 16 == 15) {
98             for (j = 0; j < 16; ++j) {
99                 w[j] += w[(j + 9) % 16] + sigma0(w[(j + 1) % 16]) +
100                         sigma1(w[(j + 14) % 16]);
101             }
102         }
103     }
104 
105     for (i = 0; i < 8; i++) {
106         a[i] += z[i];
107     }
108 }
109 
110 /* a is icv/ocv, w is a single message block that needs be64 conversion. */
sha512_bda_be64(uint64_t a[8],uint64_t w[16])111 static void sha512_bda_be64(uint64_t a[8], uint64_t w[16])
112 {
113     uint64_t t[16];
114     int i;
115 
116     for (i = 0; i < 16; i++) {
117         t[i] = be64_to_cpu(w[i]);
118     }
119     sha512_bda(a, t);
120 }
121 
sha512_read_icv(CPUS390XState * env,uint64_t addr,uint64_t a[8],uintptr_t ra)122 static void sha512_read_icv(CPUS390XState *env, uint64_t addr,
123                             uint64_t a[8], uintptr_t ra)
124 {
125     int i;
126 
127     for (i = 0; i < 8; i++, addr += 8) {
128         addr = wrap_address(env, addr);
129         a[i] = cpu_ldq_be_data_ra(env, addr, ra);
130     }
131 }
132 
sha512_write_ocv(CPUS390XState * env,uint64_t addr,uint64_t a[8],uintptr_t ra)133 static void sha512_write_ocv(CPUS390XState *env, uint64_t addr,
134                              uint64_t a[8], uintptr_t ra)
135 {
136     int i;
137 
138     for (i = 0; i < 8; i++, addr += 8) {
139         addr = wrap_address(env, addr);
140         cpu_stq_be_data_ra(env, addr, a[i], ra);
141     }
142 }
143 
sha512_read_block(CPUS390XState * env,uint64_t addr,uint64_t a[16],uintptr_t ra)144 static void sha512_read_block(CPUS390XState *env, uint64_t addr,
145                               uint64_t a[16], uintptr_t ra)
146 {
147     int i;
148 
149     for (i = 0; i < 16; i++, addr += 8) {
150         addr = wrap_address(env, addr);
151         a[i] = cpu_ldq_be_data_ra(env, addr, ra);
152     }
153 }
154 
sha512_read_mbl_be64(CPUS390XState * env,uint64_t addr,uint8_t a[16],uintptr_t ra)155 static void sha512_read_mbl_be64(CPUS390XState *env, uint64_t addr,
156                                  uint8_t a[16], uintptr_t ra)
157 {
158     int i;
159 
160     for (i = 0; i < 16; i++, addr += 1) {
161         addr = wrap_address(env, addr);
162         a[i] = cpu_ldub_data_ra(env, addr, ra);
163     }
164 }
165 
cpacf_sha512(CPUS390XState * env,uintptr_t ra,uint64_t param_addr,uint64_t * message_reg,uint64_t * len_reg,uint32_t type)166 static int cpacf_sha512(CPUS390XState *env, uintptr_t ra, uint64_t param_addr,
167                       uint64_t *message_reg, uint64_t *len_reg, uint32_t type)
168 {
169     enum { MAX_BLOCKS_PER_RUN = 64 }; /* Arbitrary: keep interactivity. */
170     uint64_t len = *len_reg, a[8], processed = 0;
171     int i, message_reg_len = 64;
172 
173     g_assert(type == S390_FEAT_TYPE_KIMD || type == S390_FEAT_TYPE_KLMD);
174 
175     if (!(env->psw.mask & PSW_MASK_64)) {
176         len = (uint32_t)len;
177         message_reg_len = (env->psw.mask & PSW_MASK_32) ? 32 : 24;
178     }
179 
180     /* KIMD: length has to be properly aligned. */
181     if (type == S390_FEAT_TYPE_KIMD && !QEMU_IS_ALIGNED(len, 128)) {
182         tcg_s390_program_interrupt(env, PGM_SPECIFICATION, ra);
183     }
184 
185     sha512_read_icv(env, param_addr, a, ra);
186 
187     /* Process full blocks first. */
188     for (; len >= 128; len -= 128, processed += 128) {
189         uint64_t w[16];
190 
191         if (processed >= MAX_BLOCKS_PER_RUN * 128) {
192             break;
193         }
194 
195         sha512_read_block(env, *message_reg + processed, w, ra);
196         sha512_bda(a, w);
197     }
198 
199     /* KLMD: Process partial/empty block last. */
200     if (type == S390_FEAT_TYPE_KLMD && len < 128) {
201         uint8_t x[128];
202 
203         /* Read the remainder of the message byte-per-byte. */
204         for (i = 0; i < len; i++) {
205             uint64_t addr = wrap_address(env, *message_reg + processed + i);
206 
207             x[i] = cpu_ldub_data_ra(env, addr, ra);
208         }
209         /* Pad the remainder with zero and set the top bit. */
210         memset(x + len, 0, 128 - len);
211         x[len] = 128;
212 
213         /*
214          * Place the MBL either into this block (if there is space left),
215          * or use an additional one.
216          */
217         if (len < 112) {
218             sha512_read_mbl_be64(env, param_addr + 64, x + 112, ra);
219         }
220         sha512_bda_be64(a, (uint64_t *)x);
221 
222         if (len >= 112) {
223             memset(x, 0, 112);
224             sha512_read_mbl_be64(env, param_addr + 64, x + 112, ra);
225             sha512_bda_be64(a, (uint64_t *)x);
226         }
227 
228         processed += len;
229         len = 0;
230     }
231 
232     /*
233      * Modify memory after we read all inputs and modify registers only after
234      * writing memory succeeded.
235      *
236      * TODO: if writing fails halfway through (e.g., when crossing page
237      * boundaries), we're in trouble. We'd need something like access_prepare().
238      */
239     sha512_write_ocv(env, param_addr, a, ra);
240     *message_reg = deposit64(*message_reg, 0, message_reg_len,
241                              *message_reg + processed);
242     *len_reg -= processed;
243     return !len ? 0 : 3;
244 }
245 
fill_buf_random(CPUS390XState * env,uintptr_t ra,uint64_t * buf_reg,uint64_t * len_reg)246 static void fill_buf_random(CPUS390XState *env, uintptr_t ra,
247                             uint64_t *buf_reg, uint64_t *len_reg)
248 {
249     uint8_t tmp[256];
250     uint64_t len = *len_reg;
251     int buf_reg_len = 64;
252 
253     if (!(env->psw.mask & PSW_MASK_64)) {
254         len = (uint32_t)len;
255         buf_reg_len = (env->psw.mask & PSW_MASK_32) ? 32 : 24;
256     }
257 
258     while (len) {
259         size_t block = MIN(len, sizeof(tmp));
260 
261         qemu_guest_getrandom_nofail(tmp, block);
262         for (size_t i = 0; i < block; ++i) {
263             cpu_stb_data_ra(env, wrap_address(env, *buf_reg), tmp[i], ra);
264             *buf_reg = deposit64(*buf_reg, 0, buf_reg_len, *buf_reg + 1);
265             --*len_reg;
266         }
267         len -= block;
268     }
269 }
270 
HELPER(msa)271 uint32_t HELPER(msa)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3,
272                      uint32_t type)
273 {
274     const uintptr_t ra = GETPC();
275     const uint8_t mod = env->regs[0] & 0x80ULL;
276     const uint8_t fc = env->regs[0] & 0x7fULL;
277     uint8_t subfunc[16] = { 0 };
278     uint64_t param_addr;
279     int i;
280 
281     switch (type) {
282     case S390_FEAT_TYPE_KMAC:
283     case S390_FEAT_TYPE_KIMD:
284     case S390_FEAT_TYPE_KLMD:
285     case S390_FEAT_TYPE_PCKMO:
286     case S390_FEAT_TYPE_PCC:
287         if (mod) {
288             tcg_s390_program_interrupt(env, PGM_SPECIFICATION, ra);
289         }
290         break;
291     }
292 
293     s390_get_feat_block(type, subfunc);
294     if (!test_be_bit(fc, subfunc)) {
295         tcg_s390_program_interrupt(env, PGM_SPECIFICATION, ra);
296     }
297 
298     switch (fc) {
299     case 0: /* query subfunction */
300         for (i = 0; i < 16; i++) {
301             param_addr = wrap_address(env, env->regs[1] + i);
302             cpu_stb_data_ra(env, param_addr, subfunc[i], ra);
303         }
304         break;
305     case 3: /* CPACF_*_SHA_512 */
306         return cpacf_sha512(env, ra, env->regs[1], &env->regs[r2],
307                             &env->regs[r2 + 1], type);
308     case 114: /* CPACF_PRNO_TRNG */
309         fill_buf_random(env, ra, &env->regs[r1], &env->regs[r1 + 1]);
310         fill_buf_random(env, ra, &env->regs[r2], &env->regs[r2 + 1]);
311         break;
312     default:
313         /* we don't implement any other subfunction yet */
314         g_assert_not_reached();
315     }
316 
317     return 0;
318 }
319