1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_TOP_DISPLAY_CFG_TYPES_H__ 6 #define __DML_TOP_DISPLAY_CFG_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 10 #define DML2_MAX_PLANES 8 11 #define DML2_MAX_DCN_PIPES 8 12 #define DML2_MAX_MCACHES 8 // assume plane is going to be supported by a max of 8 mcaches 13 #define DML2_MAX_WRITEBACK 3 14 15 enum dml2_swizzle_mode { 16 dml2_sw_linear, // SW_LINEAR accepts 256 byte aligned pitch and also 128 byte aligned pitch if DCC is not enabled 17 dml2_sw_256b_2d, 18 dml2_sw_4kb_2d, 19 dml2_sw_64kb_2d, 20 dml2_sw_256kb_2d, 21 22 dml2_gfx11_sw_linear, 23 dml2_gfx11_sw_64kb_d, 24 dml2_gfx11_sw_64kb_d_t, 25 dml2_gfx11_sw_64kb_d_x, 26 dml2_gfx11_sw_64kb_r_x, 27 dml2_gfx11_sw_256kb_d_x, 28 dml2_gfx11_sw_256kb_r_x, 29 30 }; 31 32 enum dml2_source_format_class { 33 dml2_444_8 = 0, 34 dml2_444_16 = 1, 35 dml2_444_32 = 2, 36 dml2_444_64 = 3, 37 dml2_420_8 = 4, 38 dml2_420_10 = 5, 39 dml2_420_12 = 6, 40 dml2_rgbe_alpha = 9, 41 dml2_rgbe = 10, 42 dml2_mono_8 = 11, 43 dml2_mono_16 = 12, 44 dml2_422_planar_8 = 13, 45 dml2_422_planar_10 = 14, 46 dml2_422_planar_12 = 15, 47 dml2_422_packed_8 = 16, 48 dml2_422_packed_10 = 17, 49 dml2_422_packed_12 = 18 50 }; 51 52 enum dml2_rotation_angle { 53 dml2_rotation_0 = 0, 54 dml2_rotation_90 = 1, 55 dml2_rotation_180 = 2, 56 dml2_rotation_270 = 3 57 }; 58 59 enum dml2_output_format_class { 60 dml2_444 = 0, 61 dml2_s422 = 1, 62 dml2_n422 = 2, 63 dml2_420 = 3 64 }; 65 66 enum dml2_output_encoder_class { 67 dml2_dp = 0, 68 dml2_edp = 1, 69 dml2_dp2p0 = 2, 70 dml2_hdmi = 3, 71 dml2_hdmifrl = 4, 72 dml2_none = 5 73 }; 74 75 enum dml2_output_link_dp_rate { 76 dml2_dp_rate_na = 0, 77 dml2_dp_rate_hbr = 1, 78 dml2_dp_rate_hbr2 = 2, 79 dml2_dp_rate_hbr3 = 3, 80 dml2_dp_rate_uhbr10 = 4, 81 dml2_dp_rate_uhbr13p5 = 5, 82 dml2_dp_rate_uhbr20 = 6 83 }; 84 85 enum dml2_uclk_pstate_change_strategy { 86 dml2_uclk_pstate_change_strategy_auto = 0, 87 dml2_uclk_pstate_change_strategy_force_vactive = 1, 88 dml2_uclk_pstate_change_strategy_force_vblank = 2, 89 dml2_uclk_pstate_change_strategy_force_drr = 3, 90 dml2_uclk_pstate_change_strategy_force_mall_svp = 4, 91 dml2_uclk_pstate_change_strategy_force_mall_full_frame = 5, 92 }; 93 94 enum dml2_svp_mode_override { 95 dml2_svp_mode_override_auto = 0, 96 dml2_svp_mode_override_main_pipe = 1, 97 dml2_svp_mode_override_phantom_pipe = 2, //does not need to be defined explicitly, main overrides result in implicit phantom additions 98 dml2_svp_mode_override_phantom_pipe_no_data_return = 3, 99 dml2_svp_mode_override_imall = 4 100 }; 101 102 enum dml2_refresh_from_mall_mode_override { 103 dml2_refresh_from_mall_mode_override_auto = 0, 104 dml2_refresh_from_mall_mode_override_force_disable = 1, 105 dml2_refresh_from_mall_mode_override_force_enable = 2 106 }; 107 108 enum dml2_odm_mode { 109 dml2_odm_mode_auto = 0, 110 dml2_odm_mode_bypass, 111 dml2_odm_mode_combine_2to1, 112 dml2_odm_mode_combine_3to1, 113 dml2_odm_mode_combine_4to1, 114 dml2_odm_mode_split_1to2, 115 dml2_odm_mode_mso_1to2, 116 dml2_odm_mode_mso_1to4 117 }; 118 119 enum dml2_scaling_transform { 120 dml2_scaling_transform_explicit = 0, 121 dml2_scaling_transform_fullscreen, 122 dml2_scaling_transform_aspect_ratio, 123 dml2_scaling_transform_centered 124 }; 125 126 enum dml2_dsc_enable_option { 127 dml2_dsc_disable = 0, 128 dml2_dsc_enable = 1, 129 dml2_dsc_enable_if_necessary = 2 130 }; 131 132 enum dml2_tdlut_addressing_mode { 133 dml2_tdlut_sw_linear = 0, 134 dml2_tdlut_simple_linear = 1 135 }; 136 137 enum dml2_tdlut_width_mode { 138 dml2_tdlut_width_17_cube = 0, 139 dml2_tdlut_width_33_cube = 1 140 }; 141 142 enum dml2_twait_budgeting_setting { 143 dml2_twait_budgeting_setting_ignore = 0,// Ignore this budget in twait 144 145 dml2_twait_budgeting_setting_if_needed, // Budget for it only if needed 146 //(i.e. UCLK/FCLK DPM cannot be supported in active) 147 148 dml2_twait_budgeting_setting_try, // Budget for it as long as there is an SoC state that 149 // can support it 150 }; 151 152 struct dml2_get_cursor_dlg_reg{ 153 unsigned int cursor_x_position; 154 unsigned int cursor_hotspot_x; 155 unsigned int cursor_primary_offset; 156 unsigned int cursor_secondary_offset; 157 bool cursor_stereo_en; 158 bool cursor_2x_magnify; 159 double hratio; 160 double pixel_rate_mhz; 161 double dlg_refclk_mhz; 162 }; 163 164 /// @brief Surface Parameters 165 struct dml2_surface_cfg { 166 enum dml2_swizzle_mode tiling; 167 168 struct { 169 unsigned long pitch; // In elements, two pixels per element in 422 packed format 170 unsigned long width; 171 unsigned long height; 172 } plane0; 173 174 175 struct { 176 unsigned long pitch; 177 unsigned long width; 178 unsigned long height; 179 } plane1; 180 181 struct { 182 bool enable; 183 struct { 184 unsigned long pitch; 185 } plane0; 186 struct { 187 unsigned long pitch; 188 } plane1; 189 190 struct { 191 double dcc_rate_plane0; 192 double dcc_rate_plane1; 193 double fraction_of_zero_size_request_plane0; 194 double fraction_of_zero_size_request_plane1; 195 } informative; 196 } dcc; 197 }; 198 199 200 struct dml2_composition_cfg { 201 enum dml2_rotation_angle rotation_angle; 202 bool mirrored; 203 enum dml2_scaling_transform scaling_transform; 204 bool rect_out_height_spans_vactive; 205 206 struct { 207 bool stationary; 208 struct { 209 unsigned long width; 210 unsigned long height; 211 unsigned long x_start; 212 unsigned long y_start; 213 } plane0; 214 215 struct { 216 unsigned long width; 217 unsigned long height; 218 unsigned long x_start; 219 unsigned long y_start; 220 } plane1; 221 } viewport; 222 223 struct { 224 bool enabled; 225 bool upsp_enabled; 226 struct { 227 double h_ratio; 228 double v_ratio; 229 unsigned int h_taps; 230 unsigned int v_taps; 231 } plane0; 232 233 struct { 234 double h_ratio; 235 double v_ratio; 236 unsigned int h_taps; 237 unsigned int v_taps; 238 } plane1; 239 240 unsigned long rect_out_width; 241 } scaler_info; 242 }; 243 244 struct dml2_timing_cfg { 245 unsigned long h_total; 246 unsigned long v_total; 247 unsigned long h_blank_end; 248 unsigned long v_blank_end; 249 unsigned long h_front_porch; 250 unsigned long v_front_porch; 251 unsigned long h_sync_width; 252 unsigned long pixel_clock_khz; 253 unsigned long h_active; 254 unsigned long v_active; 255 unsigned int bpc; //FIXME: review with Jun 256 struct { 257 enum dml2_dsc_enable_option enable; 258 unsigned int dsc_compressed_bpp_x16; 259 struct { 260 // for dv to specify num dsc slices to use 261 unsigned int num_slices; 262 } overrides; 263 } dsc; 264 bool interlaced; 265 struct { 266 /* static */ 267 bool enabled; 268 unsigned long min_refresh_uhz; 269 unsigned int max_instant_vtotal_delta; 270 /* dynamic */ 271 bool disallowed; 272 bool drr_active_variable; 273 bool drr_active_fixed; 274 } drr_config; 275 unsigned long vblank_nom; 276 }; 277 278 struct dml2_link_output_cfg { 279 enum dml2_output_format_class output_format; 280 enum dml2_output_encoder_class output_encoder; 281 unsigned int output_dp_lane_count; 282 enum dml2_output_link_dp_rate output_dp_link_rate; 283 unsigned long audio_sample_rate; 284 unsigned long audio_sample_layout; 285 bool output_disabled; // The stream does not go to a backend for output to a physical 286 //connector (e.g. writeback only, phantom pipe) goes to writeback 287 bool validate_output; // Do not validate the link configuration for this display stream. 288 }; 289 290 struct dml2_writeback_info { 291 enum dml2_source_format_class pixel_format; 292 unsigned long input_width; 293 unsigned long input_height; 294 unsigned long output_width; 295 unsigned long output_height; 296 unsigned long v_taps; 297 unsigned long h_taps; 298 unsigned long v_taps_chroma; 299 unsigned long h_taps_chroma; 300 double h_ratio; 301 double v_ratio; 302 }; 303 304 struct dml2_writeback_cfg { 305 unsigned int active_writebacks_per_stream; 306 struct dml2_writeback_info writeback_stream[DML2_MAX_WRITEBACK]; 307 }; 308 309 struct dml2_plane_parameters { 310 unsigned int stream_index; // Identifies which plane will be composed 311 312 enum dml2_source_format_class pixel_format; 313 /* 314 * The surface and composition structures use 315 * the terms plane0 and plane1. These planes 316 * are expected to hold the following data based 317 * on the pixel format. 318 * 319 * RGB or YUV Non-Planar Types: 320 * dml2_444_8 321 * dml2_444_16 322 * dml2_444_32 323 * dml2_444_64 324 * dml2_rgbe 325 * 326 * plane0 = argb or rgbe 327 * plane1 = not used 328 * 329 * YUV Planar-Types: 330 * dml2_420_8 331 * dml2_420_10 332 * dml2_420_12 333 * 334 * plane0 = luma 335 * plane1 = chroma 336 * 337 * RGB Planar Types: 338 * dml2_rgbe_alpha 339 * 340 * plane0 = rgbe 341 * plane1 = alpha 342 * 343 * Mono Non-Planar Types: 344 * dml2_mono_8 345 * dml2_mono_16 346 * 347 * plane0 = luma 348 * plane1 = not used 349 */ 350 351 struct dml2_surface_cfg surface; 352 struct dml2_composition_cfg composition; 353 354 struct { 355 bool enable; 356 unsigned long lines_before_active_required; 357 unsigned long transmitted_bytes; 358 } dynamic_meta_data; 359 360 struct { 361 unsigned int num_cursors; 362 unsigned long cursor_width; 363 unsigned long cursor_bpp; 364 } cursor; 365 366 // For TDLUT, SW would assume TDLUT is setup and enable all the time and 367 // budget for worst case addressing/width mode 368 struct { 369 bool setup_for_tdlut; 370 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 371 enum dml2_tdlut_width_mode tdlut_width_mode; 372 bool tdlut_mpc_width_flag; 373 } tdlut; 374 375 bool immediate_flip; 376 377 struct { 378 // Logical overrides to power management policies (usually) 379 enum dml2_uclk_pstate_change_strategy uclk_pstate_change_strategy; 380 enum dml2_refresh_from_mall_mode_override refresh_from_mall; 381 unsigned int det_size_override_kb; 382 unsigned int mpcc_combine_factor; 383 384 // reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait 385 // The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override. 386 long reserved_vblank_time_ns; 387 unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay 388 unsigned int gpuvm_min_page_size_kbytes; 389 unsigned int hostvm_min_page_size_kbytes; 390 391 enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config 392 393 struct { 394 // HW specific overrides, there's almost no reason to mess with these 395 // generally used for debugging or simulation 396 bool force_one_row_for_frame; 397 struct { 398 bool enable; 399 bool value; 400 } force_pte_buffer_mode; 401 double dppclk_mhz; 402 } hw; 403 } overrides; 404 }; 405 406 struct dml2_stream_parameters { 407 struct dml2_timing_cfg timing; 408 struct dml2_link_output_cfg output; 409 struct dml2_writeback_cfg writeback; 410 411 struct { 412 enum dml2_odm_mode odm_mode; 413 bool disable_dynamic_odm; 414 bool disable_subvp; 415 int minimum_vblank_idle_requirement_us; 416 bool minimize_active_latency_hiding; 417 418 struct { 419 struct { 420 enum dml2_twait_budgeting_setting uclk_pstate; 421 enum dml2_twait_budgeting_setting fclk_pstate; 422 enum dml2_twait_budgeting_setting stutter_enter_exit; 423 } twait_budgeting; 424 } hw; 425 } overrides; 426 }; 427 428 struct dml2_display_cfg { 429 bool gpuvm_enable; 430 bool ffbm_enable; 431 bool hostvm_enable; 432 433 // Allocate DET proportionally between streams based on pixel rate 434 // and then allocate proportionally between planes. 435 bool minimize_det_reallocation; 436 437 unsigned int gpuvm_max_page_table_levels; 438 unsigned int hostvm_max_non_cached_page_table_levels; 439 440 struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES]; 441 struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES]; 442 443 unsigned int num_planes; 444 unsigned int num_streams; 445 446 struct { 447 struct { 448 // HW specific overrides, there's almost no reason to mess with these 449 // generally used for debugging or simulation 450 struct { 451 bool enable; 452 bool value; 453 } force_unbounded_requesting; 454 455 struct { 456 bool enable; 457 bool value; 458 } force_nom_det_size_kbytes; 459 bool mode_support_check_disable; 460 bool mcache_admissibility_check_disable; 461 bool surface_viewport_size_check_disable; 462 double dlg_ref_clk_mhz; 463 double dispclk_mhz; 464 double dcfclk_mhz; 465 bool optimize_tdlut_scheduling; // TBD: for DV, will set this to 1, to ensure tdlut schedule is calculated based on address/width mode 466 } hw; 467 468 struct { 469 bool uclk_pstate_change_disable; 470 bool fclk_pstate_change_disable; 471 bool g6_temp_read_pstate_disable; 472 bool g7_ppt_pstate_disable; 473 } power_management; 474 475 bool enhanced_prefetch_schedule_acceleration; 476 bool dcc_programming_assumes_scan_direction_unknown; 477 bool synchronize_timings; 478 bool synchronize_ddr_displays_for_uclk_pstate_change; 479 bool max_outstanding_when_urgent_expected_disable; 480 bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming 481 unsigned int best_effort_min_active_latency_hiding_us; 482 bool all_streams_blanked; 483 } overrides; 484 }; 485 486 struct dml2_pipe_configuration_descriptor { 487 struct { 488 unsigned int viewport_x_start; 489 unsigned int viewport_width; 490 } plane0; 491 492 struct { 493 unsigned int viewport_x_start; 494 unsigned int viewport_width; 495 } plane1; 496 497 bool plane1_enabled; 498 bool imall_enabled; 499 }; 500 501 struct dml2_plane_mcache_configuration_descriptor { 502 const struct dml2_plane_parameters *plane_descriptor; 503 const struct dml2_mcache_surface_allocation *mcache_allocation; 504 505 struct dml2_pipe_configuration_descriptor pipe_configurations[DML2_MAX_DCN_PIPES]; 506 char num_pipes; 507 }; 508 509 #endif 510