1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/input.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_profile.h> 18 19 #define POLICY_BUF_MAX_SZ 0x4b000 20 #define POLICY_SIGN_COOKIE 0x31535024 21 #define POLICY_COOKIE_OFFSET 0x10 22 23 /* List of supported CPU ids */ 24 #define AMD_CPU_ID_RMB 0x14b5 25 #define AMD_CPU_ID_PS 0x14e8 26 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 27 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 28 29 struct cookie_header { 30 u32 sign; 31 u32 length; 32 } __packed; 33 34 /* APMF Functions */ 35 #define APMF_FUNC_VERIFY_INTERFACE 0 36 #define APMF_FUNC_GET_SYS_PARAMS 1 37 #define APMF_FUNC_SBIOS_REQUESTS 2 38 #define APMF_FUNC_SBIOS_HEARTBEAT 4 39 #define APMF_FUNC_AUTO_MODE 5 40 #define APMF_FUNC_SET_FAN_IDX 7 41 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 42 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 43 #define APMF_FUNC_DYN_SLIDER_AC 11 44 #define APMF_FUNC_DYN_SLIDER_DC 12 45 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 46 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 47 48 /* Message Definitions */ 49 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 50 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 51 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 52 #define GET_SPL 0x0B 53 #define GET_SPPT 0x0D 54 #define GET_FPPT 0x0F 55 #define SET_DRAM_ADDR_HIGH 0x14 56 #define SET_DRAM_ADDR_LOW 0x15 57 #define SET_TRANSFER_TABLE 0x16 58 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 59 #define SET_STT_LIMIT_APU 0x19 60 #define SET_STT_LIMIT_HS2 0x1A 61 #define SET_SPPT_APU_ONLY 0x1D 62 #define GET_SPPT_APU_ONLY 0x1E 63 #define GET_STT_MIN_LIMIT 0x1F 64 #define GET_STT_LIMIT_APU 0x20 65 #define GET_STT_LIMIT_HS2 0x21 66 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 67 #define SET_PMF_PPT 0x25 68 #define SET_PMF_PPT_APU_ONLY 0x26 69 70 /* OS slider update notification */ 71 #define DC_BEST_PERF 0 72 #define DC_BETTER_PERF 1 73 #define DC_BATTERY_SAVER 3 74 #define AC_BEST_PERF 4 75 #define AC_BETTER_PERF 5 76 #define AC_BETTER_BATTERY 6 77 78 /* Fan Index for Auto Mode */ 79 #define FAN_INDEX_AUTO 0xFFFFFFFF 80 81 #define ARG_NONE 0 82 #define AVG_SAMPLE_SIZE 3 83 84 /* Policy Actions */ 85 #define PMF_POLICY_SPL 2 86 #define PMF_POLICY_SPPT 3 87 #define PMF_POLICY_FPPT 4 88 #define PMF_POLICY_SPPT_APU_ONLY 5 89 #define PMF_POLICY_STT_MIN 6 90 #define PMF_POLICY_STT_SKINTEMP_APU 7 91 #define PMF_POLICY_STT_SKINTEMP_HS2 8 92 #define PMF_POLICY_SYSTEM_STATE 9 93 #define PMF_POLICY_BIOS_OUTPUT_1 10 94 #define PMF_POLICY_BIOS_OUTPUT_2 11 95 #define PMF_POLICY_P3T 38 96 #define PMF_POLICY_BIOS_OUTPUT_3 57 97 #define PMF_POLICY_BIOS_OUTPUT_4 58 98 #define PMF_POLICY_BIOS_OUTPUT_5 59 99 #define PMF_POLICY_BIOS_OUTPUT_6 60 100 #define PMF_POLICY_BIOS_OUTPUT_7 61 101 #define PMF_POLICY_BIOS_OUTPUT_8 62 102 #define PMF_POLICY_BIOS_OUTPUT_9 63 103 #define PMF_POLICY_BIOS_OUTPUT_10 64 104 105 /* TA macros */ 106 #define PMF_TA_IF_VERSION_MAJOR 1 107 #define TA_PMF_ACTION_MAX 32 108 #define TA_PMF_UNDO_MAX 8 109 #define TA_OUTPUT_RESERVED_MEM 922 110 #define MAX_OPERATION_PARAMS 4 111 112 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 113 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 114 115 #define PMF_IF_V1 1 116 #define PMF_IF_V2 2 117 118 #define APTS_MAX_STATES 16 119 120 /* APTS PMF BIOS Interface */ 121 struct amd_pmf_apts_output { 122 u16 table_version; 123 u32 fan_table_idx; 124 u32 pmf_ppt; 125 u32 ppt_pmf_apu_only; 126 u32 stt_min_limit; 127 u8 stt_skin_temp_limit_apu; 128 u8 stt_skin_temp_limit_hs2; 129 } __packed; 130 131 struct amd_pmf_apts_granular_output { 132 u16 size; 133 struct amd_pmf_apts_output val; 134 } __packed; 135 136 struct amd_pmf_apts_granular { 137 u16 size; 138 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 139 }; 140 141 struct sbios_hb_event_v2 { 142 u16 size; 143 u8 load; 144 u8 unload; 145 u8 suspend; 146 u8 resume; 147 } __packed; 148 149 enum sbios_hb_v2 { 150 ON_LOAD, 151 ON_UNLOAD, 152 ON_SUSPEND, 153 ON_RESUME, 154 }; 155 156 /* AMD PMF BIOS interfaces */ 157 struct apmf_verify_interface { 158 u16 size; 159 u16 version; 160 u32 notification_mask; 161 u32 supported_functions; 162 } __packed; 163 164 struct apmf_system_params { 165 u16 size; 166 u32 valid_mask; 167 u32 flags; 168 u8 command_code; 169 u32 heartbeat_int; 170 } __packed; 171 172 struct apmf_sbios_req { 173 u16 size; 174 u32 pending_req; 175 u8 rsd; 176 u8 cql_event; 177 u8 amt_event; 178 u32 fppt; 179 u32 sppt; 180 u32 fppt_apu_only; 181 u32 spl; 182 u32 stt_min_limit; 183 u8 skin_temp_apu; 184 u8 skin_temp_hs2; 185 } __packed; 186 187 struct apmf_sbios_req_v2 { 188 u16 size; 189 u32 pending_req; 190 u8 rsd; 191 u32 ppt_pmf; 192 u32 ppt_pmf_apu_only; 193 u32 stt_min_limit; 194 u8 skin_temp_apu; 195 u8 skin_temp_hs2; 196 u32 custom_policy[10]; 197 } __packed; 198 199 struct apmf_fan_idx { 200 u16 size; 201 u8 fan_ctl_mode; 202 u32 fan_ctl_idx; 203 } __packed; 204 205 struct smu_pmf_metrics_v2 { 206 u16 core_frequency[16]; /* MHz */ 207 u16 core_power[16]; /* mW */ 208 u16 core_temp[16]; /* centi-C */ 209 u16 gfx_temp; /* centi-C */ 210 u16 soc_temp; /* centi-C */ 211 u16 stapm_opn_limit; /* mW */ 212 u16 stapm_cur_limit; /* mW */ 213 u16 infra_cpu_maxfreq; /* MHz */ 214 u16 infra_gfx_maxfreq; /* MHz */ 215 u16 skin_temp; /* centi-C */ 216 u16 gfxclk_freq; /* MHz */ 217 u16 fclk_freq; /* MHz */ 218 u16 gfx_activity; /* GFX busy % [0-100] */ 219 u16 socclk_freq; /* MHz */ 220 u16 vclk_freq; /* MHz */ 221 u16 vcn_activity; /* VCN busy % [0-100] */ 222 u16 vpeclk_freq; /* MHz */ 223 u16 ipuclk_freq; /* MHz */ 224 u16 ipu_busy[8]; /* NPU busy % [0-100] */ 225 u16 dram_reads; /* MB/sec */ 226 u16 dram_writes; /* MB/sec */ 227 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 228 u16 ipu_power; /* mW */ 229 u32 apu_power; /* mW */ 230 u32 gfx_power; /* mW */ 231 u32 dgpu_power; /* mW */ 232 u32 socket_power; /* mW */ 233 u32 all_core_power; /* mW */ 234 u32 filter_alpha_value; /* time constant [us] */ 235 u32 metrics_counter; 236 u16 memclk_freq; /* MHz */ 237 u16 mpipuclk_freq; /* MHz */ 238 u16 ipu_reads; /* MB/sec */ 239 u16 ipu_writes; /* MB/sec */ 240 u32 throttle_residency_prochot; 241 u32 throttle_residency_spl; 242 u32 throttle_residency_fppt; 243 u32 throttle_residency_sppt; 244 u32 throttle_residency_thm_core; 245 u32 throttle_residency_thm_gfx; 246 u32 throttle_residency_thm_soc; 247 u16 psys; 248 u16 spare1; 249 u32 spare[6]; 250 } __packed; 251 252 struct smu_pmf_metrics { 253 u16 gfxclk_freq; /* in MHz */ 254 u16 socclk_freq; /* in MHz */ 255 u16 vclk_freq; /* in MHz */ 256 u16 dclk_freq; /* in MHz */ 257 u16 memclk_freq; /* in MHz */ 258 u16 spare; 259 u16 gfx_activity; /* in Centi */ 260 u16 uvd_activity; /* in Centi */ 261 u16 voltage[2]; /* in mV */ 262 u16 currents[2]; /* in mA */ 263 u16 power[2];/* in mW */ 264 u16 core_freq[8]; /* in MHz */ 265 u16 core_power[8]; /* in mW */ 266 u16 core_temp[8]; /* in centi-Celsius */ 267 u16 l3_freq; /* in MHz */ 268 u16 l3_temp; /* in centi-Celsius */ 269 u16 gfx_temp; /* in centi-Celsius */ 270 u16 soc_temp; /* in centi-Celsius */ 271 u16 throttler_status; 272 u16 current_socketpower; /* in mW */ 273 u16 stapm_orig_limit; /* in W */ 274 u16 stapm_cur_limit; /* in W */ 275 u32 apu_power; /* in mW */ 276 u32 dgpu_power; /* in mW */ 277 u16 vdd_tdc_val; /* in mA */ 278 u16 soc_tdc_val; /* in mA */ 279 u16 vdd_edc_val; /* in mA */ 280 u16 soc_edcv_al; /* in mA */ 281 u16 infra_cpu_maxfreq; /* in MHz */ 282 u16 infra_gfx_maxfreq; /* in MHz */ 283 u16 skin_temp; /* in centi-Celsius */ 284 u16 device_state; 285 u16 curtemp; /* in centi-Celsius */ 286 u16 filter_alpha_value; 287 u16 avg_gfx_clkfrequency; 288 u16 avg_fclk_frequency; 289 u16 avg_gfx_activity; 290 u16 avg_socclk_frequency; 291 u16 avg_vclk_frequency; 292 u16 avg_vcn_activity; 293 u16 avg_dram_reads; 294 u16 avg_dram_writes; 295 u16 avg_socket_power; 296 u16 avg_core_power[2]; 297 u16 avg_core_c0residency[16]; 298 u16 spare1; 299 u32 metrics_counter; 300 } __packed; 301 302 enum amd_stt_skin_temp { 303 STT_TEMP_APU, 304 STT_TEMP_HS2, 305 STT_TEMP_COUNT, 306 }; 307 308 enum amd_slider_op { 309 SLIDER_OP_GET, 310 SLIDER_OP_SET, 311 }; 312 313 enum power_source { 314 POWER_SOURCE_AC, 315 POWER_SOURCE_DC, 316 POWER_SOURCE_MAX, 317 }; 318 319 enum power_modes { 320 POWER_MODE_PERFORMANCE, 321 POWER_MODE_BALANCED_POWER, 322 POWER_MODE_POWER_SAVER, 323 POWER_MODE_MAX, 324 }; 325 326 enum power_modes_v2 { 327 POWER_MODE_BEST_PERFORMANCE, 328 POWER_MODE_BALANCED, 329 POWER_MODE_BEST_POWER_EFFICIENCY, 330 POWER_MODE_ENERGY_SAVE, 331 POWER_MODE_V2_MAX, 332 }; 333 334 struct amd_pmf_dev { 335 void __iomem *regbase; 336 void __iomem *smu_virt_addr; 337 void *buf; 338 u32 base_addr; 339 u32 cpu_id; 340 struct device *dev; 341 struct mutex lock; /* protects the PMF interface */ 342 u32 supported_func; 343 enum platform_profile_option current_profile; 344 struct device *ppdev; /* platform profile class device */ 345 struct dentry *dbgfs_dir; 346 int hb_interval; /* SBIOS heartbeat interval */ 347 struct delayed_work heart_beat; 348 struct smu_pmf_metrics m_table; 349 struct smu_pmf_metrics_v2 m_table_v2; 350 struct delayed_work work_buffer; 351 ktime_t start_time; 352 int socket_power_history[AVG_SAMPLE_SIZE]; 353 int socket_power_history_idx; 354 bool amt_enabled; 355 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 356 bool cnqf_enabled; 357 bool cnqf_supported; 358 struct notifier_block pwr_src_notifier; 359 /* Smart PC solution builder */ 360 struct dentry *esbin; 361 unsigned char *policy_buf; 362 resource_size_t policy_sz; 363 struct tee_context *tee_ctx; 364 struct tee_shm *fw_shm_pool; 365 u32 session_id; 366 void *shbuf; 367 struct delayed_work pb_work; 368 struct pmf_action_table *prev_data; 369 resource_size_t policy_addr; 370 void __iomem *policy_base; 371 bool smart_pc_enabled; 372 u16 pmf_if_version; 373 struct input_dev *pmf_idev; 374 size_t mtable_size; 375 struct resource *res; 376 struct apmf_sbios_req_v2 req; /* To get custom bios pending request */ 377 struct mutex cb_mutex; 378 }; 379 380 struct apmf_sps_prop_granular_v2 { 381 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 382 } __packed; 383 384 struct apmf_sps_prop_granular { 385 u32 fppt; 386 u32 sppt; 387 u32 sppt_apu_only; 388 u32 spl; 389 u32 stt_min; 390 u8 stt_skin_temp[STT_TEMP_COUNT]; 391 u32 fan_id; 392 } __packed; 393 394 /* Static Slider */ 395 struct apmf_static_slider_granular_output { 396 u16 size; 397 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 398 } __packed; 399 400 struct amd_pmf_static_slider_granular { 401 u16 size; 402 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 403 }; 404 405 struct apmf_static_slider_granular_output_v2 { 406 u16 size; 407 struct apmf_sps_prop_granular_v2 sps_idx; 408 } __packed; 409 410 struct amd_pmf_static_slider_granular_v2 { 411 u16 size; 412 struct apmf_sps_prop_granular_v2 sps_idx; 413 }; 414 415 struct os_power_slider { 416 u16 size; 417 u8 slider_event; 418 } __packed; 419 420 struct amd_pmf_notify_smart_pc_update { 421 u16 size; 422 u32 pending_req; 423 u32 custom_bios[10]; 424 } __packed; 425 426 struct fan_table_control { 427 bool manual; 428 unsigned long fan_id; 429 }; 430 431 struct power_table_control { 432 u32 spl; 433 u32 sppt; 434 u32 fppt; 435 u32 sppt_apu_only; 436 u32 stt_min; 437 u32 stt_skin_temp[STT_TEMP_COUNT]; 438 u32 reserved[16]; 439 }; 440 441 /* Auto Mode Layer */ 442 enum auto_mode_transition_priority { 443 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 444 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 445 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 446 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 447 AUTO_TRANSITION_MAX, 448 }; 449 450 enum auto_mode_mode { 451 AUTO_QUIET, 452 AUTO_BALANCE, 453 AUTO_PERFORMANCE_ON_LAP, 454 AUTO_PERFORMANCE, 455 AUTO_MODE_MAX, 456 }; 457 458 struct auto_mode_trans_params { 459 u32 time_constant; /* minimum time required to switch to next mode */ 460 u32 power_delta; /* delta power to shift mode */ 461 u32 power_threshold; 462 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 463 u32 applied; 464 enum auto_mode_mode target_mode; 465 u32 shifting_up; 466 }; 467 468 struct auto_mode_mode_settings { 469 struct power_table_control power_control; 470 struct fan_table_control fan_control; 471 u32 power_floor; 472 }; 473 474 struct auto_mode_mode_config { 475 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 476 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 477 enum auto_mode_mode current_mode; 478 }; 479 480 struct apmf_auto_mode { 481 u16 size; 482 /* time constant */ 483 u32 balanced_to_perf; 484 u32 perf_to_balanced; 485 u32 quiet_to_balanced; 486 u32 balanced_to_quiet; 487 /* power floor */ 488 u32 pfloor_perf; 489 u32 pfloor_balanced; 490 u32 pfloor_quiet; 491 /* Power delta for mode change */ 492 u32 pd_balanced_to_perf; 493 u32 pd_perf_to_balanced; 494 u32 pd_quiet_to_balanced; 495 u32 pd_balanced_to_quiet; 496 /* skin temperature limits */ 497 u8 stt_apu_perf_on_lap; /* CQL ON */ 498 u8 stt_hs2_perf_on_lap; /* CQL ON */ 499 u8 stt_apu_perf; 500 u8 stt_hs2_perf; 501 u8 stt_apu_balanced; 502 u8 stt_hs2_balanced; 503 u8 stt_apu_quiet; 504 u8 stt_hs2_quiet; 505 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 506 u32 stt_min_limit_perf; 507 u32 stt_min_limit_balanced; 508 u32 stt_min_limit_quiet; 509 /* SPL based */ 510 u32 fppt_perf_on_lap; /* CQL ON */ 511 u32 sppt_perf_on_lap; /* CQL ON */ 512 u32 spl_perf_on_lap; /* CQL ON */ 513 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 514 u32 fppt_perf; 515 u32 sppt_perf; 516 u32 spl_perf; 517 u32 sppt_apu_only_perf; 518 u32 fppt_balanced; 519 u32 sppt_balanced; 520 u32 spl_balanced; 521 u32 sppt_apu_only_balanced; 522 u32 fppt_quiet; 523 u32 sppt_quiet; 524 u32 spl_quiet; 525 u32 sppt_apu_only_quiet; 526 /* Fan ID */ 527 u32 fan_id_perf; 528 u32 fan_id_balanced; 529 u32 fan_id_quiet; 530 } __packed; 531 532 /* CnQF Layer */ 533 enum cnqf_trans_priority { 534 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 535 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 536 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 537 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 538 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 539 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 540 CNQF_TRANSITION_MAX, 541 }; 542 543 enum cnqf_mode { 544 CNQF_MODE_QUIET, 545 CNQF_MODE_BALANCE, 546 CNQF_MODE_PERFORMANCE, 547 CNQF_MODE_TURBO, 548 CNQF_MODE_MAX, 549 }; 550 551 enum apmf_cnqf_pos { 552 APMF_CNQF_TURBO, 553 APMF_CNQF_PERFORMANCE, 554 APMF_CNQF_BALANCE, 555 APMF_CNQF_QUIET, 556 APMF_CNQF_MAX, 557 }; 558 559 struct cnqf_mode_settings { 560 struct power_table_control power_control; 561 struct fan_table_control fan_control; 562 u32 power_floor; 563 }; 564 565 struct cnqf_tran_params { 566 u32 time_constant; /* minimum time required to switch to next mode */ 567 u32 power_threshold; 568 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 569 u32 total_power; 570 u32 count; 571 bool priority; 572 bool shifting_up; 573 enum cnqf_mode target_mode; 574 }; 575 576 struct cnqf_config { 577 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 578 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 579 struct power_table_control defaults; 580 enum cnqf_mode current_mode; 581 u32 power_src; 582 u32 avg_power; 583 }; 584 585 struct apmf_cnqf_power_set { 586 u32 pfloor; 587 u32 fppt; 588 u32 sppt; 589 u32 sppt_apu_only; 590 u32 spl; 591 u32 stt_min_limit; 592 u8 stt_skintemp[STT_TEMP_COUNT]; 593 u32 fan_id; 594 } __packed; 595 596 struct apmf_dyn_slider_output { 597 u16 size; 598 u16 flags; 599 u32 t_perf_to_turbo; 600 u32 t_balanced_to_perf; 601 u32 t_quiet_to_balanced; 602 u32 t_balanced_to_quiet; 603 u32 t_perf_to_balanced; 604 u32 t_turbo_to_perf; 605 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 606 } __packed; 607 608 /* Smart PC - TA internals */ 609 enum system_state { 610 SYSTEM_STATE_S0i3, 611 SYSTEM_STATE_S4, 612 SYSTEM_STATE_SCREEN_LOCK, 613 SYSTEM_STATE_MAX, 614 }; 615 616 enum ta_slider { 617 TA_BEST_BATTERY, 618 TA_BETTER_BATTERY, 619 TA_BETTER_PERFORMANCE, 620 TA_BEST_PERFORMANCE, 621 TA_MAX, 622 }; 623 624 enum apmf_smartpc_custom_bios_inputs { 625 APMF_SMARTPC_CUSTOM_BIOS_INPUT1, 626 APMF_SMARTPC_CUSTOM_BIOS_INPUT2, 627 }; 628 629 enum apmf_preq_smartpc { 630 NOTIFY_CUSTOM_BIOS_INPUT1 = 5, 631 NOTIFY_CUSTOM_BIOS_INPUT2, 632 }; 633 634 enum platform_type { 635 PTYPE_UNKNOWN = 0, 636 LID_CLOSE, 637 CLAMSHELL, 638 FLAT, 639 TENT, 640 STAND, 641 TABLET, 642 BOOK, 643 PRESENTATION, 644 PULL_FWD, 645 PTYPE_INVALID = 0xf, 646 }; 647 648 /* Command ids for TA communication */ 649 enum ta_pmf_command { 650 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 651 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 652 }; 653 654 enum ta_pmf_error_type { 655 TA_PMF_TYPE_SUCCESS, 656 TA_PMF_ERROR_TYPE_GENERIC, 657 TA_PMF_ERROR_TYPE_CRYPTO, 658 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 659 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 660 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 661 TA_PMF_ERROR_TYPE_PB_CONVERT, 662 TA_PMF_ERROR_TYPE_PB_SETUP, 663 TA_PMF_ERROR_TYPE_PB_ENACT, 664 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 665 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 666 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 667 TA_PMF_ERROR_TYPE_MAX, 668 }; 669 670 struct pmf_action_table { 671 enum system_state system_state; 672 u32 spl; /* in mW */ 673 u32 sppt; /* in mW */ 674 u32 sppt_apuonly; /* in mW */ 675 u32 fppt; /* in mW */ 676 u32 stt_minlimit; /* in mW */ 677 u32 stt_skintemp_apu; /* in C */ 678 u32 stt_skintemp_hs2; /* in C */ 679 u32 p3t_limit; /* in mW */ 680 }; 681 682 /* Input conditions */ 683 struct ta_pmf_condition_info { 684 u32 power_source; 685 u32 bat_percentage; 686 u32 power_slider; 687 u32 lid_state; 688 bool user_present; 689 u32 bios_input1; 690 u32 bios_input2; 691 u32 monitor_count; 692 u32 rsvd2[2]; 693 u32 bat_design; 694 u32 full_charge_capacity; 695 int drain_rate; 696 bool user_engaged; 697 u32 device_state; 698 u32 socket_power; 699 u32 skin_temperature; 700 u32 rsvd3[2]; 701 u32 platform_type; 702 u32 rsvd3_1[2]; 703 u32 ambient_light; 704 u32 length; 705 u32 avg_c0residency; 706 u32 max_c0residency; 707 u32 s0i3_entry; 708 u32 gfx_busy; 709 u32 rsvd4[7]; 710 bool camera_state; 711 u32 workload_type; 712 u32 display_type; 713 u32 display_state; 714 u32 rsvd5[150]; 715 }; 716 717 struct ta_pmf_load_policy_table { 718 u32 table_size; 719 u8 table[POLICY_BUF_MAX_SZ]; 720 }; 721 722 /* TA initialization params */ 723 struct ta_pmf_init_table { 724 u32 frequency; /* SMU sampling frequency */ 725 bool validate; 726 bool sku_check; 727 bool metadata_macrocheck; 728 struct ta_pmf_load_policy_table policies_table; 729 }; 730 731 /* Everything the TA needs to Enact Policies */ 732 struct ta_pmf_enact_table { 733 struct ta_pmf_condition_info ev_info; 734 u32 name; 735 }; 736 737 struct ta_pmf_action { 738 u32 action_index; 739 u32 value; 740 }; 741 742 /* Output actions from TA */ 743 struct ta_pmf_enact_result { 744 u32 actions_count; 745 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 746 u32 undo_count; 747 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 748 }; 749 750 union ta_pmf_input { 751 struct ta_pmf_enact_table enact_table; 752 struct ta_pmf_init_table init_table; 753 }; 754 755 union ta_pmf_output { 756 struct ta_pmf_enact_result policy_apply_table; 757 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 758 }; 759 760 struct ta_pmf_shared_memory { 761 int command_id; 762 int resp_id; 763 u32 pmf_result; 764 u32 if_version; 765 union ta_pmf_output pmf_output; 766 union ta_pmf_input pmf_input; 767 }; 768 769 /* Core Layer */ 770 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 771 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 772 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 773 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 774 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 775 int amd_pmf_get_power_source(void); 776 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 777 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 778 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 779 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 780 u32 fixp_q88_fromint(u32 val); 781 782 /* SPS Layer */ 783 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 784 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 785 struct amd_pmf_static_slider_granular *table); 786 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 787 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 788 struct apmf_static_slider_granular_output *output); 789 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 790 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 791 const char *amd_pmf_source_as_str(unsigned int state); 792 793 const char *amd_pmf_source_as_str(unsigned int state); 794 795 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 796 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 797 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 798 struct apmf_static_slider_granular_output_v2 *data); 799 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 800 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 801 802 /* Auto Mode Layer */ 803 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 804 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 805 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 806 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 807 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 808 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 809 810 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 811 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 812 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 813 814 /* CnQF Layer */ 815 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 816 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 817 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 818 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 819 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 820 extern const struct attribute_group cnqf_feature_attribute_group; 821 822 /* Smart PC builder Layer */ 823 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 824 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 825 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 826 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 827 828 /* Smart PC - TA interfaces */ 829 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 830 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 831 832 #endif /* PMF_H */ 833