1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <kunit/static_stub.h> 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/wmfw.h> 14 #include <linux/fs.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/stddef.h> 22 #include <linux/string.h> 23 #include <linux/string_choices.h> 24 #include <linux/types.h> 25 #include <sound/cs-amp-lib.h> 26 27 #include "cs35l56.h" 28 29 static const struct reg_sequence cs35l56_asp_patch[] = { 30 /* 31 * Firmware can change these to non-defaults to satisfy SDCA. 32 * Ensure that they are at known defaults. 33 */ 34 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 35 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 36 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 37 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 42 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 43 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 44 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 45 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 46 }; 47 48 int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base) 49 { 50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_asp_patch, 51 ARRAY_SIZE(cs35l56_asp_patch)); 52 } 53 EXPORT_SYMBOL_NS_GPL(cs35l56_set_asp_patch, "SND_SOC_CS35L56_SHARED"); 54 55 static const struct reg_sequence cs35l56_patch[] = { 56 /* 57 * Firmware can change these to non-defaults to satisfy SDCA. 58 * Ensure that they are at known defaults. 59 */ 60 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 61 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 62 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 63 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 64 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 65 }; 66 67 static const struct reg_sequence cs35l56_patch_fw[] = { 68 /* These are not reset by a soft-reset, so patch to defaults. */ 69 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 70 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 71 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 72 }; 73 74 static const struct reg_sequence cs35l63_patch_fw[] = { 75 /* These are not reset by a soft-reset, so patch to defaults. */ 76 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 77 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 78 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 79 }; 80 81 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 82 { 83 int ret; 84 85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 86 ARRAY_SIZE(cs35l56_patch)); 87 if (ret) 88 return ret; 89 90 91 switch (cs35l56_base->type) { 92 case 0x54: 93 case 0x56: 94 case 0x57: 95 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 96 ARRAY_SIZE(cs35l56_patch_fw)); 97 break; 98 case 0x63: 99 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 100 ARRAY_SIZE(cs35l63_patch_fw)); 101 break; 102 default: 103 break; 104 } 105 106 return ret; 107 } 108 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 109 110 static const struct reg_default cs35l56_reg_defaults[] = { 111 /* no defaults for OTP_MEM - first read populates cache */ 112 113 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 114 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 115 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 116 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 117 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 118 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 119 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 120 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 121 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 122 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 123 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 124 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 125 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 126 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 127 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 128 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 129 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 130 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 131 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 132 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 133 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 134 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 135 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 136 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 137 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 138 }; 139 140 static const struct reg_default cs35l63_reg_defaults[] = { 141 /* no defaults for OTP_MEM - first read populates cache */ 142 143 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 144 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 145 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 146 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 147 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 148 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 149 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 150 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 151 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 152 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 153 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 154 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 155 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 156 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 157 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 158 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 159 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 160 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 161 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 162 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 163 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 164 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 165 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 166 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 167 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 168 }; 169 170 static bool cs35l56_is_dsp_memory(unsigned int reg) 171 { 172 switch (reg) { 173 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 174 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 175 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 176 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 177 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 178 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 179 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 180 return true; 181 default: 182 return false; 183 } 184 } 185 186 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 187 { 188 switch (reg) { 189 case CS35L56_DEVID: 190 case CS35L56_REVID: 191 case CS35L56_RELID: 192 case CS35L56_OTPID: 193 case CS35L56_SFT_RESET: 194 case CS35L56_GLOBAL_ENABLES: 195 case CS35L56_BLOCK_ENABLES: 196 case CS35L56_BLOCK_ENABLES2: 197 case CS35L56_REFCLK_INPUT: 198 case CS35L56_GLOBAL_SAMPLE_RATE: 199 case CS35L56_OTP_MEM_53: 200 case CS35L56_OTP_MEM_54: 201 case CS35L56_OTP_MEM_55: 202 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 203 case CS35L56_UPDATE_REGS: 204 case CS35L56_ASP1_ENABLES1: 205 case CS35L56_ASP1_CONTROL1: 206 case CS35L56_ASP1_CONTROL2: 207 case CS35L56_ASP1_CONTROL3: 208 case CS35L56_ASP1_FRAME_CONTROL1: 209 case CS35L56_ASP1_FRAME_CONTROL5: 210 case CS35L56_ASP1_DATA_CONTROL1: 211 case CS35L56_ASP1_DATA_CONTROL5: 212 case CS35L56_DACPCM1_INPUT: 213 case CS35L56_DACPCM2_INPUT: 214 case CS35L56_ASP1TX1_INPUT: 215 case CS35L56_ASP1TX2_INPUT: 216 case CS35L56_ASP1TX3_INPUT: 217 case CS35L56_ASP1TX4_INPUT: 218 case CS35L56_DSP1RX1_INPUT: 219 case CS35L56_DSP1RX2_INPUT: 220 case CS35L56_SWIRE_DP3_CH1_INPUT: 221 case CS35L56_SWIRE_DP3_CH2_INPUT: 222 case CS35L56_SWIRE_DP3_CH3_INPUT: 223 case CS35L56_SWIRE_DP3_CH4_INPUT: 224 case CS35L56_IRQ1_CFG: 225 case CS35L56_IRQ1_STATUS: 226 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 227 case CS35L56_IRQ1_EINT_18: 228 case CS35L56_IRQ1_EINT_20: 229 case CS35L56_IRQ1_MASK_1: 230 case CS35L56_IRQ1_MASK_2: 231 case CS35L56_IRQ1_MASK_4: 232 case CS35L56_IRQ1_MASK_8: 233 case CS35L56_IRQ1_MASK_18: 234 case CS35L56_IRQ1_MASK_20: 235 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 236 case CS35L56_MIXER_NGATE_CH1_CFG: 237 case CS35L56_MIXER_NGATE_CH2_CFG: 238 case CS35L56_DSP_VIRTUAL1_MBOX_1: 239 case CS35L56_DSP_VIRTUAL1_MBOX_2: 240 case CS35L56_DSP_VIRTUAL1_MBOX_3: 241 case CS35L56_DSP_VIRTUAL1_MBOX_4: 242 case CS35L56_DSP_VIRTUAL1_MBOX_5: 243 case CS35L56_DSP_VIRTUAL1_MBOX_6: 244 case CS35L56_DSP_VIRTUAL1_MBOX_7: 245 case CS35L56_DSP_VIRTUAL1_MBOX_8: 246 case CS35L56_DIE_STS1: 247 case CS35L56_DIE_STS2: 248 case CS35L56_DSP_RESTRICT_STS1: 249 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 250 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 251 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 252 case CS35L56_DSP1_SCRATCH1: 253 case CS35L56_DSP1_SCRATCH2: 254 case CS35L56_DSP1_SCRATCH3: 255 case CS35L56_DSP1_SCRATCH4: 256 return true; 257 default: 258 return cs35l56_is_dsp_memory(reg); 259 } 260 } 261 262 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 263 { 264 switch (reg) { 265 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 266 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 267 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 268 return true; 269 default: 270 return false; 271 } 272 } 273 274 static bool cs35l56_common_volatile_reg(unsigned int reg) 275 { 276 switch (reg) { 277 case CS35L56_DEVID: 278 case CS35L56_REVID: 279 case CS35L56_RELID: 280 case CS35L56_OTPID: 281 case CS35L56_SFT_RESET: 282 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 283 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 284 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 285 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 286 case CS35L56_UPDATE_REGS: 287 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 288 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 289 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 290 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 291 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 292 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 293 case CS35L56_IRQ1_STATUS: 294 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 295 case CS35L56_IRQ1_EINT_18: 296 case CS35L56_IRQ1_EINT_20: 297 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 298 case CS35L56_MIXER_NGATE_CH1_CFG: 299 case CS35L56_MIXER_NGATE_CH2_CFG: 300 case CS35L56_DSP_VIRTUAL1_MBOX_1: 301 case CS35L56_DSP_VIRTUAL1_MBOX_2: 302 case CS35L56_DSP_VIRTUAL1_MBOX_3: 303 case CS35L56_DSP_VIRTUAL1_MBOX_4: 304 case CS35L56_DSP_VIRTUAL1_MBOX_5: 305 case CS35L56_DSP_VIRTUAL1_MBOX_6: 306 case CS35L56_DSP_VIRTUAL1_MBOX_7: 307 case CS35L56_DSP_VIRTUAL1_MBOX_8: 308 case CS35L56_DSP_RESTRICT_STS1: 309 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 310 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 311 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 312 case CS35L56_DSP1_SCRATCH1: 313 case CS35L56_DSP1_SCRATCH2: 314 case CS35L56_DSP1_SCRATCH3: 315 case CS35L56_DSP1_SCRATCH4: 316 return true; 317 default: 318 return cs35l56_is_dsp_memory(reg); 319 } 320 } 321 322 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 323 { 324 switch (reg) { 325 case CS35L56_MAIN_RENDER_USER_MUTE: 326 case CS35L56_MAIN_RENDER_USER_VOLUME: 327 case CS35L56_MAIN_POSTURE_NUMBER: 328 return false; 329 default: 330 return cs35l56_common_volatile_reg(reg); 331 } 332 } 333 334 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 335 { 336 switch (reg) { 337 case CS35L63_MAIN_RENDER_USER_MUTE: 338 case CS35L63_MAIN_RENDER_USER_VOLUME: 339 case CS35L63_MAIN_POSTURE_NUMBER: 340 return false; 341 default: 342 return cs35l56_common_volatile_reg(reg); 343 } 344 } 345 346 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 347 .fw_ver = CS35L56_DSP1_FW_VER, 348 .halo_state = CS35L56_DSP1_HALO_STATE, 349 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 350 .prot_sts = CS35L56_PROTECTION_STATUS, 351 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 352 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 353 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 354 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 355 }; 356 357 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 358 .fw_ver = CS35L56_DSP1_FW_VER, 359 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 360 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 361 .prot_sts = CS35L56_PROTECTION_STATUS, 362 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 363 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 364 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 365 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 366 }; 367 368 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 369 .fw_ver = CS35L63_DSP1_FW_VER, 370 .halo_state = CS35L63_DSP1_HALO_STATE, 371 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 372 .prot_sts = CS35L63_PROTECTION_STATUS, 373 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 374 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 375 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 376 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 377 }; 378 379 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 380 { 381 switch (cs35l56_base->type) { 382 default: 383 switch (cs35l56_base->rev) { 384 case 0xb0: 385 cs35l56_base->fw_reg = &cs35l56_fw_reg; 386 break; 387 default: 388 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 389 break; 390 } 391 break; 392 case 0x63: 393 cs35l56_base->fw_reg = &cs35l63_fw_reg; 394 break; 395 } 396 } 397 398 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 399 { 400 unsigned int val; 401 int ret; 402 403 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 404 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 405 val, (val == 0), 406 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 407 if (ret) { 408 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 409 return ret; 410 } 411 412 return 0; 413 } 414 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 415 416 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 417 { 418 int ret; 419 unsigned int val; 420 421 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 422 if (ret) 423 return ret; 424 425 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 426 cs35l56_base->fw_reg->pm_cur_stat, 427 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 428 CS35L56_HALO_STATE_POLL_US, 429 CS35L56_HALO_STATE_TIMEOUT_US); 430 if (ret < 0) 431 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 432 val, ret); 433 return ret; 434 } 435 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 436 437 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 438 { 439 unsigned int val = 0; 440 int read_ret, poll_ret; 441 442 /* 443 * The regmap must remain in cache-only until the chip has 444 * booted, so use a bypassed read of the status register. 445 */ 446 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 447 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 448 CS35L56_HALO_STATE_POLL_US, 449 CS35L56_HALO_STATE_TIMEOUT_US, 450 false, 451 cs35l56_base->regmap, 452 cs35l56_base->fw_reg->halo_state, 453 &val); 454 455 if (poll_ret) { 456 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 457 read_ret, val); 458 return -EIO; 459 } 460 461 return 0; 462 } 463 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 464 465 void cs35l56_wait_control_port_ready(void) 466 { 467 /* Wait for control port to be ready (datasheet tIRS). */ 468 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 469 } 470 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 471 472 void cs35l56_wait_min_reset_pulse(void) 473 { 474 /* Satisfy minimum reset pulse width spec */ 475 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 476 } 477 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 478 479 static const struct { 480 u32 addr; 481 u32 value; 482 } cs35l56_spi_system_reset_stages[] = { 483 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 484 /* The next write is necessary to delimit the soft reset */ 485 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 486 }; 487 488 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 489 struct spi_device *spi) 490 { 491 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 492 struct spi_transfer t = { 493 .tx_buf = buf, 494 .len = sizeof(*buf), 495 }; 496 struct spi_message m; 497 int i, ret; 498 499 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 500 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 501 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 502 spi_message_init_with_transfers(&m, &t, 1); 503 ret = spi_sync_locked(spi, &m); 504 if (ret) 505 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 506 507 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 508 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 509 } 510 } 511 512 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 513 { 514 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 515 unsigned int val; 516 int read_ret, ret; 517 518 /* 519 * There must not be any other SPI bus activity while the amp is 520 * soft-resetting. 521 */ 522 ret = spi_bus_lock(spi->controller); 523 if (ret) { 524 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 525 return; 526 } 527 528 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 529 spi_bus_unlock(spi->controller); 530 531 /* 532 * Check firmware boot by testing for a response in MBOX_2. 533 * HALO_STATE cannot be trusted yet because the reset sequence 534 * can leave it with stale state. But MBOX is reset. 535 * The regmap must remain in cache-only until the chip has 536 * booted, so use a bypassed read. 537 */ 538 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 539 (val > 0) && (val < 0xffffffff), 540 CS35L56_HALO_STATE_POLL_US, 541 CS35L56_HALO_STATE_TIMEOUT_US, 542 false, 543 cs35l56_base->regmap, 544 CS35L56_DSP_VIRTUAL1_MBOX_2, 545 &val); 546 if (ret) { 547 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 548 read_ret, val); 549 } 550 } 551 552 static const struct reg_sequence cs35l56_system_reset_seq[] = { 553 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 554 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 555 }; 556 557 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 558 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 559 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 560 }; 561 562 static const struct reg_sequence cs35l63_system_reset_seq[] = { 563 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 564 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 565 }; 566 567 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 568 { 569 /* 570 * Must enter cache-only first so there can't be any more register 571 * accesses other than the controlled system reset sequence below. 572 */ 573 regcache_cache_only(cs35l56_base->regmap, true); 574 575 if (cs35l56_is_spi(cs35l56_base)) { 576 cs35l56_spi_system_reset(cs35l56_base); 577 return; 578 } 579 580 switch (cs35l56_base->type) { 581 case 0x54: 582 case 0x56: 583 case 0x57: 584 switch (cs35l56_base->rev) { 585 case 0xb0: 586 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 587 cs35l56_system_reset_seq, 588 ARRAY_SIZE(cs35l56_system_reset_seq)); 589 break; 590 default: 591 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 592 cs35l56_b2_system_reset_seq, 593 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 594 break; 595 } 596 break; 597 case 0x63: 598 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 599 cs35l63_system_reset_seq, 600 ARRAY_SIZE(cs35l63_system_reset_seq)); 601 break; 602 default: 603 break; 604 } 605 606 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 607 if (is_soundwire) 608 return; 609 610 cs35l56_wait_control_port_ready(); 611 612 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 613 } 614 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 615 616 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 617 { 618 int ret; 619 620 if (irq < 1) 621 return 0; 622 623 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 624 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 625 "cs35l56", cs35l56_base); 626 if (!ret) 627 cs35l56_base->irq = irq; 628 else 629 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 630 631 return ret; 632 } 633 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 634 635 irqreturn_t cs35l56_irq(int irq, void *data) 636 { 637 struct cs35l56_base *cs35l56_base = data; 638 unsigned int status1 = 0, status8 = 0, status20 = 0; 639 unsigned int mask1, mask8, mask20; 640 unsigned int val; 641 int rv; 642 643 irqreturn_t ret = IRQ_NONE; 644 645 if (!cs35l56_base->init_done) 646 return IRQ_NONE; 647 648 mutex_lock(&cs35l56_base->irq_lock); 649 650 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 651 if (rv < 0) { 652 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 653 goto err_unlock; 654 } 655 656 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 657 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 658 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 659 goto err; 660 } 661 662 /* Ack interrupts */ 663 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 664 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 665 status1 &= ~mask1; 666 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 667 668 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 669 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 670 status8 &= ~mask8; 671 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 672 673 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 674 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 675 status20 &= ~mask20; 676 /* We don't want EINT20 but they default to unmasked: force mask */ 677 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 678 679 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 680 681 /* Check to see if unmasked bits are active */ 682 if (!status1 && !status8 && !status20) 683 goto err; 684 685 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 686 dev_crit(cs35l56_base->dev, "Amp short error\n"); 687 688 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 689 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 690 691 ret = IRQ_HANDLED; 692 693 err: 694 pm_runtime_put(cs35l56_base->dev); 695 err_unlock: 696 mutex_unlock(&cs35l56_base->irq_lock); 697 698 return ret; 699 } 700 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 701 702 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 703 { 704 unsigned int val; 705 int ret; 706 707 /* 708 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 709 * can't be used here to test for memory retention. 710 * Assume that tuning must be re-loaded. 711 */ 712 if (cs35l56_base->secured) 713 return true; 714 715 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 716 if (ret) { 717 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 718 return ret; 719 } 720 721 ret = regmap_read(cs35l56_base->regmap, 722 cs35l56_base->fw_reg->prot_sts, 723 &val); 724 if (ret) 725 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 726 else 727 ret = !!(val & CS35L56_FIRMWARE_MISSING); 728 729 pm_runtime_put_autosuspend(cs35l56_base->dev); 730 731 return ret; 732 } 733 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 734 735 static const struct reg_sequence cs35l56_hibernate_seq[] = { 736 /* This must be the last register access */ 737 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 738 }; 739 740 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 741 { 742 unsigned int val; 743 744 /* 745 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 746 * transactions to meet the minimum required time from the rising edge 747 * to the last falling edge of wake. 748 * 749 * It uses bypassed read because we must wake the chip before 750 * disabling regmap cache-only. 751 */ 752 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 753 754 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 755 756 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 757 758 cs35l56_wait_control_port_ready(); 759 } 760 761 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 762 { 763 unsigned int val; 764 int ret; 765 766 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 767 cs35l56_base->fw_reg->transducer_actual_ps, 768 val, (val >= CS35L56_PS3), 769 CS35L56_PS3_POLL_US, 770 CS35L56_PS3_TIMEOUT_US); 771 if (ret) 772 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 773 774 return ret; 775 } 776 777 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 778 { 779 if (!cs35l56_base->init_done) 780 return 0; 781 782 /* Firmware must have entered a power-save state */ 783 cs35l56_wait_for_ps3(cs35l56_base); 784 785 /* Clear BOOT_DONE so it can be used to detect a reboot */ 786 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 787 788 if (!cs35l56_base->can_hibernate) { 789 regcache_cache_only(cs35l56_base->regmap, true); 790 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 791 792 return 0; 793 } 794 795 /* 796 * Must enter cache-only first so there can't be any more register 797 * accesses other than the controlled hibernate sequence below. 798 */ 799 regcache_cache_only(cs35l56_base->regmap, true); 800 801 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 802 cs35l56_hibernate_seq, 803 ARRAY_SIZE(cs35l56_hibernate_seq)); 804 805 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 806 807 return 0; 808 } 809 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 810 811 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 812 { 813 unsigned int val; 814 int ret; 815 816 if (!cs35l56_base->init_done) 817 return 0; 818 819 if (!cs35l56_base->can_hibernate) 820 goto out_sync; 821 822 /* Must be done before releasing cache-only */ 823 if (!is_soundwire) 824 cs35l56_issue_wake_event(cs35l56_base); 825 826 out_sync: 827 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 828 if (ret) { 829 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 830 goto err; 831 } 832 833 regcache_cache_only(cs35l56_base->regmap, false); 834 835 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 836 if (ret) 837 goto err; 838 839 /* BOOT_DONE will be 1 if the amp reset */ 840 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 841 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 842 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 843 regcache_mark_dirty(cs35l56_base->regmap); 844 } 845 846 regcache_sync(cs35l56_base->regmap); 847 848 dev_dbg(cs35l56_base->dev, "Resumed"); 849 850 return 0; 851 852 err: 853 regcache_cache_only(cs35l56_base->regmap, true); 854 855 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 856 cs35l56_hibernate_seq, 857 ARRAY_SIZE(cs35l56_hibernate_seq)); 858 859 return ret; 860 } 861 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 862 863 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 864 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 865 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 866 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 867 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 868 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 869 }; 870 871 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 872 { 873 cs_dsp->num = 1; 874 cs_dsp->type = WMFW_HALO; 875 cs_dsp->rev = 0; 876 cs_dsp->dev = cs35l56_base->dev; 877 cs_dsp->regmap = cs35l56_base->regmap; 878 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 879 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 880 cs_dsp->mem = cs35l56_dsp1_regions; 881 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 882 cs_dsp->no_core_startstop = true; 883 884 cs35l56_base->dsp = cs_dsp; 885 } 886 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 887 888 struct cs35l56_pte { 889 u8 x; 890 u8 wafer_id; 891 u8 pte[2]; 892 u8 lot[3]; 893 u8 y; 894 u8 unused[3]; 895 u8 dvs; 896 } __packed; 897 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 898 899 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 900 { 901 struct cs35l56_pte pte; 902 u64 unique_id; 903 int ret; 904 905 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 906 if (ret) { 907 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 908 return ret; 909 } 910 911 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 912 unique_id <<= 32; 913 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 914 ((u32)pte.dvs << 24); 915 916 cs35l56_base->silicon_uid = unique_id; 917 918 return 0; 919 } 920 921 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 922 { 923 u32 tmp[2]; 924 u64 unique_id; 925 int ret; 926 927 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 928 if (ret) { 929 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 930 return ret; 931 } 932 933 unique_id = tmp[1]; 934 unique_id <<= 32; 935 unique_id |= tmp[0]; 936 937 cs35l56_base->silicon_uid = unique_id; 938 939 return 0; 940 } 941 942 /* Firmware calibration controls */ 943 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 944 .alg_id = 0x9f210, 945 .mem_region = WMFW_ADSP2_YM, 946 .ambient = "CAL_AMBIENT", 947 .calr = "CAL_R", 948 .status = "CAL_STATUS", 949 .checksum = "CAL_CHECKSUM", 950 }; 951 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 952 953 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 954 .alg_id = 0xbf210, 955 .mem_region = WMFW_ADSP2_YM, 956 .ambient = "CAL_AMBIENT", 957 .calr = "CAL_R", 958 .status = "CAL_STATUS", 959 .checksum = "CAL_CHECKSUM", 960 }; 961 962 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 963 { 964 int ret; 965 966 /* Driver can't apply calibration to a secured part, so skip */ 967 if (cs35l56_base->secured) 968 return 0; 969 970 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 971 cs35l56_base->silicon_uid, 972 cs35l56_base->cal_index, 973 &cs35l56_base->cal_data); 974 975 /* Only return an error status if probe should be aborted */ 976 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 977 return 0; 978 979 if (ret < 0) 980 return ret; 981 982 cs35l56_base->cal_data_valid = true; 983 984 return 0; 985 } 986 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 987 988 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 989 const struct cirrus_amp_cal_data *data) 990 { 991 992 /* Ignore if it is empty */ 993 if (!data->calTime[0] && !data->calTime[1]) 994 return -ENODATA; 995 996 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 997 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 998 return -EINVAL; 999 } 1000 1001 cs35l56_base->cal_data = *data; 1002 cs35l56_base->cal_data_valid = true; 1003 1004 return 0; 1005 } 1006 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 1007 1008 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 1009 { 1010 const struct cirrus_amp_cal_controls *calibration_controls = 1011 cs35l56_base->calibration_controls; 1012 struct cs_dsp *dsp = cs35l56_base->dsp; 1013 struct cirrus_amp_cal_data cal_data; 1014 struct cs_dsp_coeff_ctl *ctl; 1015 bool ngate_ch1_was_enabled = false; 1016 bool ngate_ch2_was_enabled = false; 1017 int cali_norm_en_alg_id, cali_norm_en_mem; 1018 int ret; 1019 __be32 val; 1020 1021 if (cs35l56_base->silicon_uid == 0) { 1022 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1023 return -ENXIO; 1024 } 1025 1026 switch (cs35l56_base->type) { 1027 case 0x54: 1028 case 0x56: 1029 case 0x57: 1030 if (cs35l56_base->rev < 0xb2) { 1031 cali_norm_en_alg_id = 0x9f22f; 1032 cali_norm_en_mem = WMFW_ADSP2_YM; 1033 } else { 1034 cali_norm_en_alg_id = 0x9f210; 1035 cali_norm_en_mem = WMFW_ADSP2_XM; 1036 } 1037 break; 1038 default: 1039 cali_norm_en_alg_id = 0xbf210; 1040 cali_norm_en_mem = WMFW_ADSP2_XM; 1041 break; 1042 } 1043 1044 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1045 if (ret) 1046 return ret; 1047 1048 ret = cs35l56_wait_for_ps3(cs35l56_base); 1049 if (ret) { 1050 ret = -EBUSY; 1051 goto err_pm_put; 1052 } 1053 1054 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1055 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1056 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1057 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1058 1059 scoped_guard(mutex, &dsp->pwr_lock) { 1060 ctl = cs_dsp_get_ctl(dsp, 1061 calibration_controls->status, 1062 calibration_controls->mem_region, 1063 calibration_controls->alg_id); 1064 if (!ctl) { 1065 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1066 calibration_controls->status); 1067 ret = -EIO; 1068 goto err; 1069 } 1070 1071 val = cpu_to_be32(0); 1072 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1073 "CALI_NORM_EN", 1074 cali_norm_en_mem, 1075 cali_norm_en_alg_id), 1076 0, &val, sizeof(val)); 1077 if (ret < 0) { 1078 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1079 ret = -EIO; 1080 goto err; 1081 } 1082 1083 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1084 if (ret) { 1085 ret = -EIO; 1086 goto err; 1087 } 1088 1089 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1090 (val == cpu_to_be32(1)), 1091 CS35L56_CALIBRATION_POLL_US, 1092 CS35L56_CALIBRATION_TIMEOUT_US, 1093 true, 1094 ctl, 0, &val, sizeof(val))) { 1095 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1096 be32_to_cpu(val)); 1097 switch (be32_to_cpu(val)) { 1098 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1099 ret = -ERANGE; 1100 goto err; 1101 default: 1102 ret = -ETIMEDOUT; 1103 goto err; 1104 } 1105 } 1106 } 1107 1108 cs35l56_base->cal_data_valid = false; 1109 memset(&cal_data, 0, sizeof(cal_data)); 1110 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1111 if (ret) { 1112 ret = -EIO; 1113 goto err; 1114 } 1115 1116 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1117 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1118 1119 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1120 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1121 cs35l56_base->cal_data = cal_data; 1122 cs35l56_base->cal_data_valid = true; 1123 1124 ret = 0; 1125 1126 err: 1127 if (ngate_ch1_was_enabled) { 1128 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1129 CS35L56_AUX_NGATE_CHn_EN); 1130 } 1131 if (ngate_ch2_was_enabled) { 1132 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1133 CS35L56_AUX_NGATE_CHn_EN); 1134 } 1135 err_pm_put: 1136 pm_runtime_put(cs35l56_base->dev); 1137 1138 return ret; 1139 } 1140 1141 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1142 const char __user *from, size_t count, 1143 loff_t *ppos) 1144 { 1145 static const char * const options[] = { "factory", "store_uefi" }; 1146 char buf[11] = { 0 }; 1147 int num_amps, ret; 1148 1149 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1150 return -ENXIO; 1151 1152 if (*ppos) 1153 return -EINVAL; 1154 1155 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1156 if (ret < 0) 1157 return ret; 1158 1159 switch (sysfs_match_string(options, buf)) { 1160 case 0: 1161 ret = cs35l56_perform_calibration(cs35l56_base); 1162 if (ret < 0) 1163 return ret; 1164 break; 1165 case 1: 1166 if (!cs35l56_base->cal_data_valid) 1167 return -ENODATA; 1168 1169 num_amps = cs35l56_base->num_amps; 1170 if (num_amps == 0) 1171 num_amps = -1; 1172 1173 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1174 cs35l56_base->cal_index, 1175 num_amps, 1176 &cs35l56_base->cal_data); 1177 if (ret < 0) 1178 return ret; 1179 break; 1180 default: 1181 return -EOPNOTSUPP; 1182 } 1183 1184 return count; 1185 } 1186 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1187 1188 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1189 const char __user *from, size_t count, 1190 loff_t *ppos) 1191 { 1192 unsigned long val; 1193 int ret; 1194 1195 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1196 return -ENXIO; 1197 1198 if (*ppos) 1199 return -EINVAL; 1200 1201 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1202 if (ret) 1203 return ret; 1204 1205 ret = kstrtoul_from_user(from, count, 10, &val); 1206 if (ret < 0) 1207 goto out; 1208 1209 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1210 if (ret) 1211 ret = -EIO; 1212 out: 1213 pm_runtime_put(cs35l56_base->dev); 1214 1215 if (ret < 0) 1216 return ret; 1217 1218 return count; 1219 } 1220 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1221 1222 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1223 char __user *to, size_t count, 1224 loff_t *ppos) 1225 { 1226 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1227 return -ENXIO; 1228 1229 if (!cs35l56_base->cal_data_valid) 1230 return 0; 1231 1232 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1233 sizeof(cs35l56_base->cal_data)); 1234 } 1235 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1236 1237 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1238 const char __user *from, size_t count, 1239 loff_t *ppos) 1240 { 1241 struct cirrus_amp_cal_data cal_data; 1242 int ret; 1243 1244 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1245 return -ENXIO; 1246 1247 /* Only allow a full blob to be written */ 1248 if (*ppos || (count != sizeof(cal_data))) 1249 return -EMSGSIZE; 1250 1251 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1252 if (ret) 1253 return ret; 1254 1255 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1256 if (ret) 1257 return ret; 1258 1259 return count; 1260 } 1261 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1262 1263 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1264 const struct cs35l56_cal_debugfs_fops *fops) 1265 { 1266 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1267 return; 1268 1269 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1270 1271 debugfs_create_file("calibrate", 1272 0200, cs35l56_base->debugfs, cs35l56_base, 1273 &fops->calibrate); 1274 debugfs_create_file("cal_temperature", 1275 0200, cs35l56_base->debugfs, cs35l56_base, 1276 &fops->cal_temperature); 1277 debugfs_create_file("cal_data", 1278 0644, cs35l56_base->debugfs, cs35l56_base, 1279 &fops->cal_data); 1280 } 1281 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1282 1283 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1284 { 1285 debugfs_remove_recursive(cs35l56_base->debugfs); 1286 } 1287 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1288 1289 const char * const cs35l56_cal_set_status_text[] = { 1290 "Unknown", "Default", "Set", 1291 }; 1292 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1293 1294 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1295 struct snd_ctl_elem_value *uvalue) 1296 { 1297 struct cs_dsp *dsp = cs35l56_base->dsp; 1298 __be32 cal_set_status_be; 1299 int alg_id; 1300 int ret; 1301 1302 switch (cs35l56_base->type) { 1303 case 0x54: 1304 case 0x56: 1305 case 0x57: 1306 alg_id = 0x9f210; 1307 break; 1308 default: 1309 alg_id = 0xbf210; 1310 break; 1311 } 1312 1313 scoped_guard(mutex, &dsp->pwr_lock) { 1314 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1315 "CAL_SET_STATUS", 1316 WMFW_ADSP2_YM, alg_id), 1317 0, &cal_set_status_be, 1318 sizeof(cal_set_status_be)); 1319 } 1320 if (ret) { 1321 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1322 return 0; 1323 } 1324 1325 switch (be32_to_cpu(cal_set_status_be)) { 1326 case CS35L56_CAL_SET_STATUS_DEFAULT: 1327 case CS35L56_CAL_SET_STATUS_SET: 1328 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1329 return 0; 1330 default: 1331 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1332 return 0; 1333 } 1334 } 1335 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1336 1337 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1338 bool *fw_missing, unsigned int *fw_version) 1339 { 1340 unsigned int prot_status; 1341 int ret; 1342 1343 ret = regmap_read(cs35l56_base->regmap, 1344 cs35l56_base->fw_reg->prot_sts, &prot_status); 1345 if (ret) { 1346 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1347 return ret; 1348 } 1349 1350 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1351 1352 ret = regmap_read(cs35l56_base->regmap, 1353 cs35l56_base->fw_reg->fw_ver, fw_version); 1354 if (ret) { 1355 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1356 return ret; 1357 } 1358 1359 return 0; 1360 } 1361 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1362 1363 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1364 { 1365 unsigned int firmware_version; 1366 bool firmware_missing; 1367 int ret; 1368 1369 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1370 if (ret) 1371 return; 1372 1373 if (!firmware_missing) 1374 return; 1375 1376 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1377 } 1378 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1379 1380 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1381 { 1382 __be32 pid, sid, tid; 1383 unsigned int alg_id; 1384 int ret; 1385 1386 switch (cs35l56_base->type) { 1387 case 0x54: 1388 case 0x56: 1389 case 0x57: 1390 alg_id = 0x9f212; 1391 break; 1392 default: 1393 alg_id = 0xbf212; 1394 break; 1395 } 1396 1397 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1398 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1399 WMFW_ADSP2_XM, alg_id), 1400 0, &pid, sizeof(pid)); 1401 if (!ret) 1402 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1403 WMFW_ADSP2_XM, alg_id), 1404 0, &sid, sizeof(sid)); 1405 if (!ret) 1406 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1407 WMFW_ADSP2_XM, alg_id), 1408 0, &tid, sizeof(tid)); 1409 } 1410 1411 if (ret) 1412 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1413 else 1414 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1415 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1416 } 1417 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1418 1419 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1420 { 1421 int ret; 1422 unsigned int devid, revid, otpid, secured, fw_ver; 1423 bool fw_missing; 1424 1425 /* 1426 * When the system is not using a reset_gpio ensure the device is 1427 * awake, otherwise the device has just been released from reset and 1428 * the driver must wait for the control port to become usable. 1429 */ 1430 if (!cs35l56_base->reset_gpio) 1431 cs35l56_issue_wake_event(cs35l56_base); 1432 else 1433 cs35l56_wait_control_port_ready(); 1434 1435 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1436 if (ret < 0) { 1437 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1438 return ret; 1439 } 1440 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1441 cs35l56_set_fw_reg_table(cs35l56_base); 1442 1443 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1444 if (ret) 1445 return ret; 1446 1447 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1448 if (ret < 0) { 1449 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1450 return ret; 1451 } 1452 devid &= CS35L56_DEVID_MASK; 1453 1454 switch (devid) { 1455 case 0x35A54: 1456 case 0x35A56: 1457 case 0x35A57: 1458 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1459 break; 1460 case 0x35A630: 1461 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1462 devid = devid >> 4; 1463 break; 1464 default: 1465 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1466 return -ENODEV; 1467 } 1468 1469 cs35l56_base->type = devid & 0xFF; 1470 1471 /* Silicon is now identified and booted so exit cache-only */ 1472 regcache_cache_only(cs35l56_base->regmap, false); 1473 1474 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1475 if (ret) { 1476 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1477 return ret; 1478 } 1479 1480 /* When any bus is restricted treat the device as secured */ 1481 if (secured & CS35L56_RESTRICTED_MASK) 1482 cs35l56_base->secured = true; 1483 1484 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1485 if (ret < 0) { 1486 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1487 return ret; 1488 } 1489 1490 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1491 if (ret) 1492 return ret; 1493 1494 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1495 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1496 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1497 1498 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1499 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1500 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1501 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1502 0); 1503 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1504 CS35L56_TEMP_ERR_EINT1_MASK, 1505 0); 1506 1507 switch (cs35l56_base->type) { 1508 case 0x54: 1509 case 0x56: 1510 case 0x57: 1511 ret = cs35l56_read_silicon_uid(cs35l56_base); 1512 break; 1513 default: 1514 ret = cs35l63_read_silicon_uid(cs35l56_base); 1515 break; 1516 } 1517 if (ret) 1518 return ret; 1519 1520 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1521 1522 return 0; 1523 } 1524 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1525 1526 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1527 { 1528 struct gpio_descs *descs; 1529 u32 speaker_id; 1530 int i, ret; 1531 1532 /* Check for vendor-specific speaker ID method */ 1533 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1534 if (ret >= 0) { 1535 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1536 return ret; 1537 } else if (ret != -ENOENT) { 1538 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1539 return ret; 1540 } 1541 1542 /* Attempt to read the speaker type from a device property */ 1543 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1544 if (!ret) { 1545 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1546 return speaker_id; 1547 } 1548 1549 /* Read the speaker type qualifier from the motherboard GPIOs */ 1550 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1551 if (!descs) { 1552 return -ENOENT; 1553 } else if (IS_ERR(descs)) { 1554 ret = PTR_ERR(descs); 1555 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1556 } 1557 1558 speaker_id = 0; 1559 for (i = 0; i < descs->ndescs; i++) { 1560 ret = gpiod_get_value_cansleep(descs->desc[i]); 1561 if (ret < 0) { 1562 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1563 goto err; 1564 } 1565 1566 speaker_id |= (ret << i); 1567 } 1568 1569 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1570 ret = speaker_id; 1571 err: 1572 gpiod_put_array(descs); 1573 1574 return ret; 1575 } 1576 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1577 1578 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 1579 const u32 *gpios, int num_gpios, 1580 const u32 *pulls, int num_pulls) 1581 { 1582 int max_gpio; 1583 int ret = 0; 1584 int i; 1585 1586 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) || 1587 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls))) 1588 return -EOVERFLOW; 1589 1590 switch (cs35l56_base->type) { 1591 case 0x54: 1592 case 0x56: 1593 case 0x57: 1594 max_gpio = CS35L56_MAX_GPIO; 1595 break; 1596 default: 1597 max_gpio = CS35L63_MAX_GPIO; 1598 break; 1599 } 1600 1601 for (i = 0; i < num_gpios; i++) { 1602 if (gpios[i] < 1 || gpios[i] > max_gpio) { 1603 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]); 1604 /* Keep going so we log all bad values */ 1605 ret = -EINVAL; 1606 } 1607 1608 /* Change to zero-based */ 1609 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1; 1610 } 1611 1612 for (i = 0; i < num_pulls; i++) { 1613 switch (pulls[i]) { 1614 case 0: 1615 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE; 1616 break; 1617 case 1: 1618 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP; 1619 break; 1620 case 2: 1621 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN; 1622 break; 1623 default: 1624 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]); 1625 /* Keep going so we log all bad values */ 1626 ret = -EINVAL; 1627 break; 1628 } 1629 } 1630 if (ret) 1631 return ret; 1632 1633 cs35l56_base->num_onchip_spkid_gpios = num_gpios; 1634 cs35l56_base->num_onchip_spkid_pulls = num_pulls; 1635 1636 return 0; 1637 } 1638 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED"); 1639 1640 /* Caller must pm_runtime resume before calling this function */ 1641 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base) 1642 { 1643 struct regmap *regmap = cs35l56_base->regmap; 1644 unsigned int addr_offset, val; 1645 int num_gpios, num_pulls; 1646 int i, ret; 1647 1648 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base); 1649 1650 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1651 return 0; 1652 1653 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1654 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1655 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls, 1656 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)); 1657 1658 for (i = 0; i < num_gpios; i++) { 1659 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1660 1661 /* Set unspecified pulls to NONE */ 1662 if (i < num_pulls) { 1663 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, 1664 cs35l56_base->onchip_spkid_pulls[i]); 1665 } else { 1666 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE); 1667 } 1668 1669 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset, 1670 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE, 1671 val | CS35L56_PAD_GPIO_IE); 1672 if (ret) { 1673 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n", 1674 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1675 return ret; 1676 } 1677 } 1678 1679 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES); 1680 if (ret) { 1681 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret); 1682 return ret; 1683 } 1684 1685 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2); 1686 1687 return 0; 1688 } 1689 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED"); 1690 1691 /* Caller must pm_runtime resume before calling this function */ 1692 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base) 1693 { 1694 struct regmap *regmap = cs35l56_base->regmap; 1695 unsigned int addr_offset, val; 1696 int num_gpios; 1697 int speaker_id = 0; 1698 int i, ret; 1699 1700 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base); 1701 1702 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1703 return -ENOENT; 1704 1705 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1706 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1707 1708 for (i = 0; i < num_gpios; i++) { 1709 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1710 1711 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset, 1712 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK, 1713 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO); 1714 if (ret) { 1715 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n", 1716 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1717 return ret; 1718 } 1719 } 1720 1721 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val); 1722 if (ret) { 1723 dev_err(cs35l56_base->dev, "GPIO%d status read failed: %d\n", 1724 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1725 return ret; 1726 } 1727 1728 for (i = 0; i < num_gpios; i++) { 1729 speaker_id <<= 1; 1730 1731 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i])) 1732 speaker_id |= 1; 1733 } 1734 1735 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id); 1736 1737 return speaker_id; 1738 } 1739 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED"); 1740 1741 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1742 [0x0C] = 128000, 1743 [0x0F] = 256000, 1744 [0x11] = 384000, 1745 [0x12] = 512000, 1746 [0x15] = 768000, 1747 [0x17] = 1024000, 1748 [0x1A] = 1500000, 1749 [0x1B] = 1536000, 1750 [0x1C] = 2000000, 1751 [0x1D] = 2048000, 1752 [0x1E] = 2400000, 1753 [0x20] = 3000000, 1754 [0x21] = 3072000, 1755 [0x23] = 4000000, 1756 [0x24] = 4096000, 1757 [0x25] = 4800000, 1758 [0x27] = 6000000, 1759 [0x28] = 6144000, 1760 [0x29] = 6250000, 1761 [0x2A] = 6400000, 1762 [0x2E] = 8000000, 1763 [0x2F] = 8192000, 1764 [0x30] = 9600000, 1765 [0x32] = 12000000, 1766 [0x33] = 12288000, 1767 [0x37] = 13500000, 1768 [0x38] = 19200000, 1769 [0x39] = 22579200, 1770 [0x3B] = 24576000, 1771 }; 1772 1773 int cs35l56_get_bclk_freq_id(unsigned int freq) 1774 { 1775 int i; 1776 1777 if (freq == 0) 1778 return -EINVAL; 1779 1780 /* The BCLK frequency must be a valid PLL REFCLK */ 1781 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1782 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1783 return i; 1784 } 1785 1786 return -EINVAL; 1787 } 1788 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1789 1790 static const char * const cs35l56_supplies[/* auto-sized */] = { 1791 "VDD_P", 1792 "VDD_IO", 1793 "VDD_A", 1794 }; 1795 1796 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1797 { 1798 int i; 1799 1800 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1801 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1802 data[i].supply = cs35l56_supplies[i]; 1803 } 1804 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1805 1806 const char * const cs35l56_tx_input_texts[] = { 1807 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1808 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1809 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1810 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1811 }; 1812 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1813 1814 const unsigned int cs35l56_tx_input_values[] = { 1815 CS35L56_INPUT_SRC_NONE, 1816 CS35L56_INPUT_SRC_ASP1RX1, 1817 CS35L56_INPUT_SRC_ASP1RX2, 1818 CS35L56_INPUT_SRC_VMON, 1819 CS35L56_INPUT_SRC_IMON, 1820 CS35L56_INPUT_SRC_ERR_VOL, 1821 CS35L56_INPUT_SRC_CLASSH, 1822 CS35L56_INPUT_SRC_VDDBMON, 1823 CS35L56_INPUT_SRC_VBSTMON, 1824 CS35L56_INPUT_SRC_DSP1TX1, 1825 CS35L56_INPUT_SRC_DSP1TX2, 1826 CS35L56_INPUT_SRC_DSP1TX3, 1827 CS35L56_INPUT_SRC_DSP1TX4, 1828 CS35L56_INPUT_SRC_DSP1TX5, 1829 CS35L56_INPUT_SRC_DSP1TX6, 1830 CS35L56_INPUT_SRC_DSP1TX7, 1831 CS35L56_INPUT_SRC_DSP1TX8, 1832 CS35L56_INPUT_SRC_TEMPMON, 1833 CS35L56_INPUT_SRC_INTERPOLATOR, 1834 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1835 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1836 }; 1837 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1838 1839 const struct regmap_config cs35l56_regmap_i2c = { 1840 .reg_bits = 32, 1841 .val_bits = 32, 1842 .reg_stride = 4, 1843 .reg_format_endian = REGMAP_ENDIAN_BIG, 1844 .val_format_endian = REGMAP_ENDIAN_BIG, 1845 .max_register = CS35L56_DSP1_PMEM_5114, 1846 .reg_defaults = cs35l56_reg_defaults, 1847 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1848 .volatile_reg = cs35l56_volatile_reg, 1849 .readable_reg = cs35l56_readable_reg, 1850 .precious_reg = cs35l56_precious_reg, 1851 .cache_type = REGCACHE_MAPLE, 1852 }; 1853 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1854 1855 const struct regmap_config cs35l56_regmap_spi = { 1856 .reg_bits = 32, 1857 .val_bits = 32, 1858 .pad_bits = 16, 1859 .reg_stride = 4, 1860 .reg_format_endian = REGMAP_ENDIAN_BIG, 1861 .val_format_endian = REGMAP_ENDIAN_BIG, 1862 .max_register = CS35L56_DSP1_PMEM_5114, 1863 .reg_defaults = cs35l56_reg_defaults, 1864 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1865 .volatile_reg = cs35l56_volatile_reg, 1866 .readable_reg = cs35l56_readable_reg, 1867 .precious_reg = cs35l56_precious_reg, 1868 .cache_type = REGCACHE_MAPLE, 1869 }; 1870 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1871 1872 const struct regmap_config cs35l56_regmap_sdw = { 1873 .reg_bits = 32, 1874 .val_bits = 32, 1875 .reg_stride = 4, 1876 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1877 .val_format_endian = REGMAP_ENDIAN_BIG, 1878 .max_register = CS35L56_DSP1_PMEM_5114, 1879 .reg_defaults = cs35l56_reg_defaults, 1880 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1881 .volatile_reg = cs35l56_volatile_reg, 1882 .readable_reg = cs35l56_readable_reg, 1883 .precious_reg = cs35l56_precious_reg, 1884 .cache_type = REGCACHE_MAPLE, 1885 }; 1886 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1887 1888 const struct regmap_config cs35l63_regmap_i2c = { 1889 .reg_bits = 32, 1890 .val_bits = 32, 1891 .reg_stride = 4, 1892 .reg_base = 0x8000, 1893 .reg_format_endian = REGMAP_ENDIAN_BIG, 1894 .val_format_endian = REGMAP_ENDIAN_BIG, 1895 .max_register = CS35L56_DSP1_PMEM_5114, 1896 .reg_defaults = cs35l63_reg_defaults, 1897 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1898 .volatile_reg = cs35l63_volatile_reg, 1899 .readable_reg = cs35l56_readable_reg, 1900 .precious_reg = cs35l56_precious_reg, 1901 .cache_type = REGCACHE_MAPLE, 1902 }; 1903 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1904 1905 const struct regmap_config cs35l63_regmap_sdw = { 1906 .reg_bits = 32, 1907 .val_bits = 32, 1908 .reg_stride = 4, 1909 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1910 .val_format_endian = REGMAP_ENDIAN_BIG, 1911 .max_register = CS35L56_DSP1_PMEM_5114, 1912 .reg_defaults = cs35l63_reg_defaults, 1913 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1914 .volatile_reg = cs35l63_volatile_reg, 1915 .readable_reg = cs35l56_readable_reg, 1916 .precious_reg = cs35l56_precious_reg, 1917 .cache_type = REGCACHE_MAPLE, 1918 }; 1919 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1920 1921 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1922 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1923 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1924 MODULE_LICENSE("GPL"); 1925 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1926 MODULE_IMPORT_NS("FW_CS_DSP"); 1927