1 #ifndef QEMU_PCI_DEVICE_H
2 #define QEMU_PCI_DEVICE_H
3
4 #include "hw/pci/pci.h"
5 #include "hw/pci/pcie.h"
6 #include "hw/pci/pcie_doe.h"
7
8 #define TYPE_PCI_DEVICE "pci-device"
9 typedef struct PCIDeviceClass PCIDeviceClass;
10 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
11 PCI_DEVICE, TYPE_PCI_DEVICE)
12
13 /*
14 * Implemented by devices that can be plugged on CXL buses. In the spec, this is
15 * actually a "CXL Component, but we name it device to match the PCI naming.
16 */
17 #define INTERFACE_CXL_DEVICE "cxl-device"
18
19 /* Implemented by devices that can be plugged on PCI Express buses */
20 #define INTERFACE_PCIE_DEVICE "pci-express-device"
21
22 /* Implemented by devices that can be plugged on Conventional PCI buses */
23 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
24
25 struct PCIDeviceClass {
26 DeviceClass parent_class;
27
28 void (*realize)(PCIDevice *dev, Error **errp);
29 PCIUnregisterFunc *exit;
30 PCIConfigReadFunc *config_read;
31 PCIConfigWriteFunc *config_write;
32
33 uint16_t vendor_id;
34 uint16_t device_id;
35 uint8_t revision;
36 uint16_t class_id;
37 uint16_t subsystem_vendor_id; /* only for header type = 0 */
38 uint16_t subsystem_id; /* only for header type = 0 */
39
40 const char *romfile; /* rom bar */
41
42 bool sriov_vf_user_creatable;
43 };
44
45 enum PCIReqIDType {
46 PCI_REQ_ID_INVALID = 0,
47 PCI_REQ_ID_BDF,
48 PCI_REQ_ID_SECONDARY_BUS,
49 PCI_REQ_ID_MAX,
50 };
51 typedef enum PCIReqIDType PCIReqIDType;
52
53 struct PCIReqIDCache {
54 PCIDevice *dev;
55 PCIReqIDType type;
56 };
57 typedef struct PCIReqIDCache PCIReqIDCache;
58
59 struct PCIDevice {
60 DeviceState qdev;
61 bool partially_hotplugged;
62 bool enabled;
63
64 /* PCI config space */
65 uint8_t *config;
66
67 /*
68 * Used to enable config checks on load. Note that writable bits are
69 * never checked even if set in cmask.
70 */
71 uint8_t *cmask;
72
73 /* Used to implement R/W bytes */
74 uint8_t *wmask;
75
76 /* Used to implement RW1C(Write 1 to Clear) bytes */
77 uint8_t *w1cmask;
78
79 /* Used to allocate config space for capabilities. */
80 uint8_t *used;
81
82 /* the following fields are read only */
83 int32_t devfn;
84 /*
85 * Cached device to fetch requester ID from, to avoid the PCI tree
86 * walking every time we invoke PCI request (e.g., MSI). For
87 * conventional PCI root complex, this field is meaningless.
88 */
89 PCIReqIDCache requester_id_cache;
90 char name[64];
91 PCIIORegion io_regions[PCI_NUM_REGIONS];
92 AddressSpace bus_master_as;
93 bool is_master;
94 MemoryRegion bus_master_container_region;
95 MemoryRegion bus_master_enable_region;
96
97 /* do not access the following fields */
98 PCIConfigReadFunc *config_read;
99 PCIConfigWriteFunc *config_write;
100
101 /* Legacy PCI VGA regions */
102 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
103 bool has_vga;
104
105 /* Current IRQ levels. Used internally by the generic PCI code. */
106 uint8_t irq_state;
107
108 /* Capability bits */
109 uint32_t cap_present;
110
111 /* Offset of PM capability in config space */
112 uint8_t pm_cap;
113
114 /* Offset of MSI-X capability in config space */
115 uint8_t msix_cap;
116
117 /* MSI-X entries */
118 int msix_entries_nr;
119
120 /* Space to store MSIX table & pending bit array */
121 uint8_t *msix_table;
122 uint8_t *msix_pba;
123
124 /* May be used by INTx or MSI during interrupt notification */
125 void *irq_opaque;
126
127 MSITriggerFunc *msi_trigger;
128 MSIPrepareMessageFunc *msi_prepare_message;
129 MSIxPrepareMessageFunc *msix_prepare_message;
130
131 /* MemoryRegion container for msix exclusive BAR setup */
132 MemoryRegion msix_exclusive_bar;
133 /* Memory Regions for MSIX table and pending bit entries. */
134 MemoryRegion msix_table_mmio;
135 MemoryRegion msix_pba_mmio;
136 /* Reference-count for entries actually in use by driver. */
137 unsigned *msix_entry_used;
138 /* MSIX function mask set or MSIX disabled */
139 bool msix_function_masked;
140 /* Version id needed for VMState */
141 int32_t version_id;
142
143 /* Offset of MSI capability in config space */
144 uint8_t msi_cap;
145
146 /* PCI Express */
147 PCIExpressDevice exp;
148
149 /* SHPC */
150 SHPCDevice *shpc;
151
152 /* Location of option rom */
153 char *romfile;
154 uint32_t romsize;
155 bool has_rom;
156 MemoryRegion rom;
157 int32_t rom_bar;
158
159 /* INTx routing notifier */
160 PCIINTxRoutingNotifier intx_routing_notifier;
161
162 /* MSI-X notifiers */
163 MSIVectorUseNotifier msix_vector_use_notifier;
164 MSIVectorReleaseNotifier msix_vector_release_notifier;
165 MSIVectorPollNotifier msix_vector_poll_notifier;
166
167 /* SPDM */
168 uint16_t spdm_port;
169
170 /* DOE */
171 DOECap doe_spdm;
172
173 /* ID of standby device in net_failover pair */
174 char *failover_pair_id;
175 uint32_t acpi_index;
176
177 /*
178 * Indirect DMA region bounce buffer size as configured for the device. This
179 * is a configuration parameter that is reflected into bus_master_as when
180 * realizing the device.
181 */
182 uint32_t max_bounce_buffer_size;
183
184 char *sriov_pf;
185 };
186
pci_intx(PCIDevice * pci_dev)187 static inline int pci_intx(PCIDevice *pci_dev)
188 {
189 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
190 }
191
pci_is_cxl(const PCIDevice * d)192 static inline int pci_is_cxl(const PCIDevice *d)
193 {
194 return d->cap_present & QEMU_PCIE_CAP_CXL;
195 }
196
pci_is_express(const PCIDevice * d)197 static inline int pci_is_express(const PCIDevice *d)
198 {
199 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
200 }
201
pci_is_express_downstream_port(const PCIDevice * d)202 static inline int pci_is_express_downstream_port(const PCIDevice *d)
203 {
204 uint8_t type;
205
206 if (!pci_is_express(d) || !d->exp.exp_cap) {
207 return 0;
208 }
209
210 type = pcie_cap_get_type(d);
211
212 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
213 }
214
pci_is_vf(const PCIDevice * d)215 static inline int pci_is_vf(const PCIDevice *d)
216 {
217 return d->sriov_pf || d->exp.sriov_vf.pf != NULL;
218 }
219
pci_config_size(const PCIDevice * d)220 static inline uint32_t pci_config_size(const PCIDevice *d)
221 {
222 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
223 }
224
pci_get_bdf(PCIDevice * dev)225 static inline uint16_t pci_get_bdf(PCIDevice *dev)
226 {
227 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
228 }
229
230 uint16_t pci_requester_id(PCIDevice *dev);
231
232 /* DMA access functions */
pci_get_address_space(PCIDevice * dev)233 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
234 {
235 return &dev->bus_master_as;
236 }
237
238 /**
239 * pci_dma_rw: Read from or write to an address space from PCI device.
240 *
241 * Return a MemTxResult indicating whether the operation succeeded
242 * or failed (eg unassigned memory, device rejected the transaction,
243 * IOMMU fault).
244 *
245 * @dev: #PCIDevice doing the memory access
246 * @addr: address within the #PCIDevice address space
247 * @buf: buffer with the data transferred
248 * @len: the number of bytes to read or write
249 * @dir: indicates the transfer direction
250 */
pci_dma_rw(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len,DMADirection dir,MemTxAttrs attrs)251 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
252 void *buf, dma_addr_t len,
253 DMADirection dir, MemTxAttrs attrs)
254 {
255 return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
256 dir, attrs);
257 }
258
259 /**
260 * pci_dma_read: Read from an address space from PCI device.
261 *
262 * Return a MemTxResult indicating whether the operation succeeded
263 * or failed (eg unassigned memory, device rejected the transaction,
264 * IOMMU fault). Called within RCU critical section.
265 *
266 * @dev: #PCIDevice doing the memory access
267 * @addr: address within the #PCIDevice address space
268 * @buf: buffer with the data transferred
269 * @len: length of the data transferred
270 */
pci_dma_read(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len)271 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
272 void *buf, dma_addr_t len)
273 {
274 return pci_dma_rw(dev, addr, buf, len,
275 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
276 }
277
278 /**
279 * pci_dma_write: Write to address space from PCI device.
280 *
281 * Return a MemTxResult indicating whether the operation succeeded
282 * or failed (eg unassigned memory, device rejected the transaction,
283 * IOMMU fault).
284 *
285 * @dev: #PCIDevice doing the memory access
286 * @addr: address within the #PCIDevice address space
287 * @buf: buffer with the data transferred
288 * @len: the number of bytes to write
289 */
pci_dma_write(PCIDevice * dev,dma_addr_t addr,const void * buf,dma_addr_t len)290 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
291 const void *buf, dma_addr_t len)
292 {
293 return pci_dma_rw(dev, addr, (void *) buf, len,
294 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
295 }
296
297 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
298 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
299 dma_addr_t addr, \
300 uint##_bits##_t *val, \
301 MemTxAttrs attrs) \
302 { \
303 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
304 } \
305 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
306 dma_addr_t addr, \
307 uint##_bits##_t val, \
308 MemTxAttrs attrs) \
309 { \
310 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
311 }
312
313 PCI_DMA_DEFINE_LDST(ub, b, 8);
314 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
315 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
316 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
317 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
318 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
319 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
320
321 #undef PCI_DMA_DEFINE_LDST
322
323 /**
324 * pci_dma_map: Map device PCI address space range into host virtual address
325 * @dev: #PCIDevice to be accessed
326 * @addr: address within that device's address space
327 * @plen: pointer to length of buffer; updated on return to indicate
328 * if only a subset of the requested range has been mapped
329 * @dir: indicates the transfer direction
330 *
331 * Return: A host pointer, or %NULL if the resources needed to
332 * perform the mapping are exhausted (in that case *@plen
333 * is set to zero).
334 */
pci_dma_map(PCIDevice * dev,dma_addr_t addr,dma_addr_t * plen,DMADirection dir)335 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
336 dma_addr_t *plen, DMADirection dir)
337 {
338 return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
339 MEMTXATTRS_UNSPECIFIED);
340 }
341
pci_dma_unmap(PCIDevice * dev,void * buffer,dma_addr_t len,DMADirection dir,dma_addr_t access_len)342 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
343 DMADirection dir, dma_addr_t access_len)
344 {
345 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
346 }
347
pci_dma_sglist_init(QEMUSGList * qsg,PCIDevice * dev,int alloc_hint)348 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
349 int alloc_hint)
350 {
351 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
352 }
353
354 extern const VMStateDescription vmstate_pci_device;
355
356 #define VMSTATE_PCI_DEVICE(_field, _state) { \
357 .name = (stringify(_field)), \
358 .size = sizeof(PCIDevice), \
359 .vmsd = &vmstate_pci_device, \
360 .flags = VMS_STRUCT, \
361 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
362 }
363
364 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
365 .name = (stringify(_field)), \
366 .size = sizeof(PCIDevice), \
367 .vmsd = &vmstate_pci_device, \
368 .flags = VMS_STRUCT | VMS_POINTER, \
369 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
370 }
371
372 #endif
373