xref: /qemu/include/hw/ppc/spapr_nested.h (revision 71569cd8aba31fcb3a326c56c307d2b811417c0b)
1 #ifndef HW_SPAPR_NESTED_H
2 #define HW_SPAPR_NESTED_H
3 
4 #include "target/ppc/cpu.h"
5 
6 /* Guest State Buffer Element IDs */
7 #define GSB_HV_VCPU_IGNORED_ID  0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE  0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR           0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET           0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL         0x0006 /* Process Table */
14                     /* RESERVED 0x0007 - 0x07FF */
15 #define GSB_L0_GUEST_HEAP_INUSE 0x0800 /* Guest Management Heap Size */
16 #define GSB_L0_GUEST_HEAP_MAX   0x0801 /* Guest Management Heap Max Size */
17 #define GSB_L0_GUEST_PGTABLE_SIZE_INUSE  0x0802 /* Guest Pagetable Size */
18 #define GSB_L0_GUEST_PGTABLE_SIZE_MAX    0x0803 /* Guest Pagetable Max Size */
19 #define GSB_L0_GUEST_PGTABLE_RECLAIMED   0x0804 /* Pagetable Reclaim in bytes */
20                     /* RESERVED 0x0805 - 0xBFF */
21 #define GSB_VCPU_IN_BUFFER      0x0C00 /* Run VCPU Input Buffer */
22 #define GSB_VCPU_OUT_BUFFER     0x0C01 /* Run VCPU Out Buffer */
23 #define GSB_VCPU_VPA            0x0C02 /* HRA to Guest VCPU VPA */
24                     /* RESERVED 0x0C03 - 0x0FFF */
25 #define GSB_VCPU_GPR0           0x1000
26 #define GSB_VCPU_GPR1           0x1001
27 #define GSB_VCPU_GPR2           0x1002
28 #define GSB_VCPU_GPR3           0x1003
29 #define GSB_VCPU_GPR4           0x1004
30 #define GSB_VCPU_GPR5           0x1005
31 #define GSB_VCPU_GPR6           0x1006
32 #define GSB_VCPU_GPR7           0x1007
33 #define GSB_VCPU_GPR8           0x1008
34 #define GSB_VCPU_GPR9           0x1009
35 #define GSB_VCPU_GPR10          0x100A
36 #define GSB_VCPU_GPR11          0x100B
37 #define GSB_VCPU_GPR12          0x100C
38 #define GSB_VCPU_GPR13          0x100D
39 #define GSB_VCPU_GPR14          0x100E
40 #define GSB_VCPU_GPR15          0x100F
41 #define GSB_VCPU_GPR16          0x1010
42 #define GSB_VCPU_GPR17          0x1011
43 #define GSB_VCPU_GPR18          0x1012
44 #define GSB_VCPU_GPR19          0x1013
45 #define GSB_VCPU_GPR20          0x1014
46 #define GSB_VCPU_GPR21          0x1015
47 #define GSB_VCPU_GPR22          0x1016
48 #define GSB_VCPU_GPR23          0x1017
49 #define GSB_VCPU_GPR24          0x1018
50 #define GSB_VCPU_GPR25          0x1019
51 #define GSB_VCPU_GPR26          0x101A
52 #define GSB_VCPU_GPR27          0x101B
53 #define GSB_VCPU_GPR28          0x101C
54 #define GSB_VCPU_GPR29          0x101D
55 #define GSB_VCPU_GPR30          0x101E
56 #define GSB_VCPU_GPR31          0x101F
57 #define GSB_VCPU_HDEC_EXPIRY_TB 0x1020
58 #define GSB_VCPU_SPR_NIA        0x1021
59 #define GSB_VCPU_SPR_MSR        0x1022
60 #define GSB_VCPU_SPR_LR         0x1023
61 #define GSB_VCPU_SPR_XER        0x1024
62 #define GSB_VCPU_SPR_CTR        0x1025
63 #define GSB_VCPU_SPR_CFAR       0x1026
64 #define GSB_VCPU_SPR_SRR0       0x1027
65 #define GSB_VCPU_SPR_SRR1       0x1028
66 #define GSB_VCPU_SPR_DAR        0x1029
67 #define GSB_VCPU_DEC_EXPIRE_TB  0x102A
68 #define GSB_VCPU_SPR_VTB        0x102B
69 #define GSB_VCPU_SPR_LPCR       0x102C
70 #define GSB_VCPU_SPR_HFSCR      0x102D
71 #define GSB_VCPU_SPR_FSCR       0x102E
72 #define GSB_VCPU_SPR_FPSCR      0x102F
73 #define GSB_VCPU_SPR_DAWR0      0x1030
74 #define GSB_VCPU_SPR_DAWR1      0x1031
75 #define GSB_VCPU_SPR_CIABR      0x1032
76 #define GSB_VCPU_SPR_PURR       0x1033
77 #define GSB_VCPU_SPR_SPURR      0x1034
78 #define GSB_VCPU_SPR_IC         0x1035
79 #define GSB_VCPU_SPR_SPRG0      0x1036
80 #define GSB_VCPU_SPR_SPRG1      0x1037
81 #define GSB_VCPU_SPR_SPRG2      0x1038
82 #define GSB_VCPU_SPR_SPRG3      0x1039
83 #define GSB_VCPU_SPR_PPR        0x103A
84 #define GSB_VCPU_SPR_MMCR0      0x103B
85 #define GSB_VCPU_SPR_MMCR1      0x103C
86 #define GSB_VCPU_SPR_MMCR2      0x103D
87 #define GSB_VCPU_SPR_MMCR3      0x103E
88 #define GSB_VCPU_SPR_MMCRA      0x103F
89 #define GSB_VCPU_SPR_SIER       0x1040
90 #define GSB_VCPU_SPR_SIER2      0x1041
91 #define GSB_VCPU_SPR_SIER3      0x1042
92 #define GSB_VCPU_SPR_BESCR      0x1043
93 #define GSB_VCPU_SPR_EBBHR      0x1044
94 #define GSB_VCPU_SPR_EBBRR      0x1045
95 #define GSB_VCPU_SPR_AMR        0x1046
96 #define GSB_VCPU_SPR_IAMR       0x1047
97 #define GSB_VCPU_SPR_AMOR       0x1048
98 #define GSB_VCPU_SPR_UAMOR      0x1049
99 #define GSB_VCPU_SPR_SDAR       0x104A
100 #define GSB_VCPU_SPR_SIAR       0x104B
101 #define GSB_VCPU_SPR_DSCR       0x104C
102 #define GSB_VCPU_SPR_TAR        0x104D
103 #define GSB_VCPU_SPR_DEXCR      0x104E
104 #define GSB_VCPU_SPR_HDEXCR     0x104F
105 #define GSB_VCPU_SPR_HASHKEYR   0x1050
106 #define GSB_VCPU_SPR_HASHPKEYR  0x1051
107 #define GSB_VCPU_SPR_CTRL       0x1052
108 #define GSB_VCPU_SPR_DPDES      0x1053
109                     /* RESERVED 0x1054 - 0x1FFF */
110 #define GSB_VCPU_SPR_CR         0x2000
111 #define GSB_VCPU_SPR_PIDR       0x2001
112 #define GSB_VCPU_SPR_DSISR      0x2002
113 #define GSB_VCPU_SPR_VSCR       0x2003
114 #define GSB_VCPU_SPR_VRSAVE     0x2004
115 #define GSB_VCPU_SPR_DAWRX0     0x2005
116 #define GSB_VCPU_SPR_DAWRX1     0x2006
117 #define GSB_VCPU_SPR_PMC1       0x2007
118 #define GSB_VCPU_SPR_PMC2       0x2008
119 #define GSB_VCPU_SPR_PMC3       0x2009
120 #define GSB_VCPU_SPR_PMC4       0x200A
121 #define GSB_VCPU_SPR_PMC5       0x200B
122 #define GSB_VCPU_SPR_PMC6       0x200C
123 #define GSB_VCPU_SPR_WORT       0x200D
124 #define GSB_VCPU_SPR_PSPB       0x200E
125                     /* RESERVED 0x200F - 0x2FFF */
126 #define GSB_VCPU_SPR_VSR0       0x3000
127 #define GSB_VCPU_SPR_VSR1       0x3001
128 #define GSB_VCPU_SPR_VSR2       0x3002
129 #define GSB_VCPU_SPR_VSR3       0x3003
130 #define GSB_VCPU_SPR_VSR4       0x3004
131 #define GSB_VCPU_SPR_VSR5       0x3005
132 #define GSB_VCPU_SPR_VSR6       0x3006
133 #define GSB_VCPU_SPR_VSR7       0x3007
134 #define GSB_VCPU_SPR_VSR8       0x3008
135 #define GSB_VCPU_SPR_VSR9       0x3009
136 #define GSB_VCPU_SPR_VSR10      0x300A
137 #define GSB_VCPU_SPR_VSR11      0x300B
138 #define GSB_VCPU_SPR_VSR12      0x300C
139 #define GSB_VCPU_SPR_VSR13      0x300D
140 #define GSB_VCPU_SPR_VSR14      0x300E
141 #define GSB_VCPU_SPR_VSR15      0x300F
142 #define GSB_VCPU_SPR_VSR16      0x3010
143 #define GSB_VCPU_SPR_VSR17      0x3011
144 #define GSB_VCPU_SPR_VSR18      0x3012
145 #define GSB_VCPU_SPR_VSR19      0x3013
146 #define GSB_VCPU_SPR_VSR20      0x3014
147 #define GSB_VCPU_SPR_VSR21      0x3015
148 #define GSB_VCPU_SPR_VSR22      0x3016
149 #define GSB_VCPU_SPR_VSR23      0x3017
150 #define GSB_VCPU_SPR_VSR24      0x3018
151 #define GSB_VCPU_SPR_VSR25      0x3019
152 #define GSB_VCPU_SPR_VSR26      0x301A
153 #define GSB_VCPU_SPR_VSR27      0x301B
154 #define GSB_VCPU_SPR_VSR28      0x301C
155 #define GSB_VCPU_SPR_VSR29      0x301D
156 #define GSB_VCPU_SPR_VSR30      0x301E
157 #define GSB_VCPU_SPR_VSR31      0x301F
158 #define GSB_VCPU_SPR_VSR32      0x3020
159 #define GSB_VCPU_SPR_VSR33      0x3021
160 #define GSB_VCPU_SPR_VSR34      0x3022
161 #define GSB_VCPU_SPR_VSR35      0x3023
162 #define GSB_VCPU_SPR_VSR36      0x3024
163 #define GSB_VCPU_SPR_VSR37      0x3025
164 #define GSB_VCPU_SPR_VSR38      0x3026
165 #define GSB_VCPU_SPR_VSR39      0x3027
166 #define GSB_VCPU_SPR_VSR40      0x3028
167 #define GSB_VCPU_SPR_VSR41      0x3029
168 #define GSB_VCPU_SPR_VSR42      0x302A
169 #define GSB_VCPU_SPR_VSR43      0x302B
170 #define GSB_VCPU_SPR_VSR44      0x302C
171 #define GSB_VCPU_SPR_VSR45      0x302D
172 #define GSB_VCPU_SPR_VSR46      0x302E
173 #define GSB_VCPU_SPR_VSR47      0x302F
174 #define GSB_VCPU_SPR_VSR48      0x3030
175 #define GSB_VCPU_SPR_VSR49      0x3031
176 #define GSB_VCPU_SPR_VSR50      0x3032
177 #define GSB_VCPU_SPR_VSR51      0x3033
178 #define GSB_VCPU_SPR_VSR52      0x3034
179 #define GSB_VCPU_SPR_VSR53      0x3035
180 #define GSB_VCPU_SPR_VSR54      0x3036
181 #define GSB_VCPU_SPR_VSR55      0x3037
182 #define GSB_VCPU_SPR_VSR56      0x3038
183 #define GSB_VCPU_SPR_VSR57      0x3039
184 #define GSB_VCPU_SPR_VSR58      0x303A
185 #define GSB_VCPU_SPR_VSR59      0x303B
186 #define GSB_VCPU_SPR_VSR60      0x303C
187 #define GSB_VCPU_SPR_VSR61      0x303D
188 #define GSB_VCPU_SPR_VSR62      0x303E
189 #define GSB_VCPU_SPR_VSR63      0x303F
190                     /* RESERVED 0x3040 - 0xEFFF */
191 #define GSB_VCPU_SPR_HDAR       0xF000
192 #define GSB_VCPU_SPR_HDSISR     0xF001
193 #define GSB_VCPU_SPR_HEIR       0xF002
194 #define GSB_VCPU_SPR_ASDR       0xF003
195 /* End of list of Guest State Buffer Element IDs */
196 #define GSB_LAST                GSB_VCPU_SPR_ASDR
197 
198 typedef struct SpaprMachineStateNested {
199     uint64_t ptcr;
200     uint8_t api;
201 #define NESTED_API_KVM_HV  1
202 #define NESTED_API_PAPR    2
203     bool capabilities_set;
204     uint32_t pvr_base;
205 
206     /**
207      * l0_guest_heap_inuse: The currently used bytes in the Hypervisor's Guest
208      * Management Space associated with the Host Partition.
209      **/
210     uint64_t l0_guest_heap_inuse;
211 
212     /**
213      * host_heap_max: The maximum bytes available in the Hypervisor's Guest
214      * Management Space associated with the Host Partition.
215      **/
216     uint64_t l0_guest_heap_max;
217 
218     /**
219      * host_pagetable: The currently used bytes in the Hypervisor's Guest
220      * Page Table Management Space associated with the Host Partition.
221      **/
222     uint64_t l0_guest_pgtable_size_inuse;
223 
224     /**
225      * host_pagetable_max: The maximum bytes available in the Hypervisor's Guest
226      * Page Table Management Space associated with the Host Partition.
227      **/
228     uint64_t l0_guest_pgtable_size_max;
229 
230     /**
231      * host_pagetable_reclaim: The amount of space in bytes that has been
232      * reclaimed due to overcommit in the  Hypervisor's Guest Page Table
233      * Management Space associated with the Host Partition.
234      **/
235     uint64_t l0_guest_pgtable_reclaimed;
236 
237     GHashTable *guests;
238 } SpaprMachineStateNested;
239 
240 typedef struct SpaprMachineStateNestedGuest {
241     uint32_t pvr_logical;
242     unsigned long nr_vcpus;
243     uint64_t parttbl[2];
244     uint64_t tb_offset;
245     struct SpaprMachineStateNestedGuestVcpu *vcpus;
246 } SpaprMachineStateNestedGuest;
247 
248 /* Nested PAPR API related macros */
249 #define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
250 #define H_GUEST_CAPABILITIES_P9_MODE  0x4000000000000000
251 #define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000
252 #define H_GUEST_CAPABILITIES_P11_MODE 0x1000000000000000
253 #define H_GUEST_CAP_VALID_MASK        (H_GUEST_CAPABILITIES_P11_MODE | \
254                                        H_GUEST_CAPABILITIES_P10_MODE | \
255                                        H_GUEST_CAPABILITIES_P9_MODE)
256 #define H_GUEST_CAP_COPY_MEM_BMAP     0
257 #define H_GUEST_CAP_P9_MODE_BMAP      1
258 #define H_GUEST_CAP_P10_MODE_BMAP     2
259 #define H_GUEST_CAP_P11_MODE_BMAP     3
260 #define PAPR_NESTED_GUEST_MAX         4096
261 #define H_GUEST_DELETE_ALL_FLAG       0x8000000000000000ULL
262 #define PAPR_NESTED_GUEST_VCPU_MAX    2048
263 #define VCPU_OUT_BUF_MIN_SZ           0x80ULL
264 #define HVMASK_DEFAULT                0xffffffffffffffff
265 #define HVMASK_LPCR                   0x0070000003820800
266 #define HVMASK_MSR                    0xEBFFFFFFFFBFEFFF
267 #define HVMASK_HDEXCR                 0x00000000FFFFFFFF
268 #define HVMASK_TB_OFFSET              0x000000FFFFFFFFFF
269 #define GSB_MAX_BUF_SIZE              (1024 * 1024)
270 #define H_GUEST_GET_STATE_FLAGS_MASK   0xC000000000000000ULL
271 #define H_GUEST_SET_STATE_FLAGS_MASK   0x8000000000000000ULL
272 #define H_GUEST_SET_STATE_FLAGS_GUEST_WIDE 0x8000000000000000ULL
273 #define H_GUEST_GET_STATE_FLAGS_GUEST_WIDE 0x8000000000000000ULL
274 #define H_GUEST_GET_STATE_FLAGS_HOST_WIDE  0x4000000000000000ULL
275 
276 #define GUEST_STATE_REQUEST_GUEST_WIDE     0x1
277 #define GUEST_STATE_REQUEST_HOST_WIDE      0x2
278 #define GUEST_STATE_REQUEST_SET            0x4
279 
280 /*
281  * As per ISA v3.1B, following bits are reserved:
282  *      0:2
283  *      4:57  (ISA mentions bit 58 as well but it should be used for P10)
284  *      61:63 (hence, haven't included PCR bits for v2.06 and v2.05
285  *             in LOW BITS)
286  */
287 #define PCR_LOW_BITS   (PCR_COMPAT_3_10 | PCR_COMPAT_3_00)
288 #define HVMASK_PCR     (~PCR_LOW_BITS)
289 
290 #define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \
291     .id = (i),                                     \
292     .size = (sz),                                  \
293     .location = ptr,                               \
294     .offset = offsetof(struct s, f),               \
295     .copy = (c)                                    \
296 }
297 
298 #define GSBE_NESTED_MACHINE_DW(i, f)  {                             \
299         .id = (i),                                                  \
300         .size = 8,                                                  \
301         .location = get_machine_ptr,                                \
302         .offset = offsetof(struct SpaprMachineStateNested, f),     \
303         .copy = copy_state_8to8,                                    \
304         .mask = HVMASK_DEFAULT                                      \
305 }
306 
307 #define GSBE_NESTED(i, sz, f, c) {                             \
308     .id = (i),                                                 \
309     .size = (sz),                                              \
310     .location = get_guest_ptr,                                 \
311     .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\
312     .copy = (c),                                               \
313     .mask = HVMASK_DEFAULT                                     \
314 }
315 
316 #define GSBE_NESTED_MSK(i, sz, f, c, m) {                      \
317     .id = (i),                                                 \
318     .size = (sz),                                              \
319     .location = get_guest_ptr,                                 \
320     .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\
321     .copy = (c),                                               \
322     .mask = (m)                                                \
323 }
324 
325 #define GSBE_NESTED_VCPU(i, sz, f, c) {                            \
326     .id = (i),                                                     \
327     .size = (sz),                                                  \
328     .location = get_vcpu_ptr,                                      \
329     .offset = offsetof(struct SpaprMachineStateNestedGuestVcpu, f),\
330     .copy = (c),                                                   \
331     .mask = HVMASK_DEFAULT                                         \
332 }
333 
334 #define GUEST_STATE_ELEMENT_NOP(i, sz) { \
335     .id = (i),                             \
336     .size = (sz),                          \
337     .location = NULL,                      \
338     .offset = 0,                           \
339     .copy = NULL,                          \
340     .mask = HVMASK_DEFAULT                 \
341 }
342 
343 #define GUEST_STATE_ELEMENT_NOP_DW(i)   \
344         GUEST_STATE_ELEMENT_NOP(i, 8)
345 #define GUEST_STATE_ELEMENT_NOP_W(i) \
346         GUEST_STATE_ELEMENT_NOP(i, 4)
347 
348 #define GUEST_STATE_ELEMENT_BASE(i, s, c) {  \
349             .id = (i),                           \
350             .size = (s),                         \
351             .location = get_vcpu_state_ptr,      \
352             .offset = 0,                         \
353             .copy = (c),                         \
354             .mask = HVMASK_DEFAULT               \
355     }
356 
357 #define GUEST_STATE_ELEMENT_OFF(i, s, f, c) {    \
358             .id = (i),                           \
359             .size = (s),                         \
360             .location = get_vcpu_state_ptr,      \
361             .offset = offsetof(struct nested_ppc_state, f),  \
362             .copy = (c),                         \
363             .mask = HVMASK_DEFAULT               \
364     }
365 
366 #define GUEST_STATE_ELEMENT_MSK(i, s, f, c, m) { \
367             .id = (i),                           \
368             .size = (s),                         \
369             .location = get_vcpu_state_ptr,      \
370             .offset = offsetof(struct nested_ppc_state, f),  \
371             .copy = (c),                         \
372             .mask = (m)                          \
373     }
374 
375 #define GUEST_STATE_ELEMENT_ENV_QW(i, f) \
376     GUEST_STATE_ELEMENT_OFF(i, 16, f, copy_state_16to16)
377 #define GUEST_STATE_ELEMENT_ENV_DW(i, f) \
378     GUEST_STATE_ELEMENT_OFF(i, 8, f, copy_state_8to8)
379 #define GUEST_STATE_ELEMENT_ENV_W(i, f) \
380     GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to8)
381 #define GUEST_STATE_ELEMENT_ENV_WW(i, f) \
382     GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to4)
383 #define GSE_ENV_DWM(i, f, m) \
384     GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m)
385 
386 struct guest_state_element {
387     uint16_t id;
388     uint16_t size;
389     uint8_t value[];
390 } QEMU_PACKED;
391 
392 struct guest_state_buffer {
393     uint32_t num_elements;
394     struct guest_state_element elements[];
395 } QEMU_PACKED;
396 
397 /* Actual buffer plus some metadata about the request */
398 struct guest_state_request {
399     struct guest_state_buffer *gsb;
400     int64_t buf;
401     int64_t len;
402     uint16_t flags;
403 };
404 
405 /*
406  * Register state for entering a nested guest with H_ENTER_NESTED.
407  * New member must be added at the end.
408  */
409 struct kvmppc_hv_guest_state {
410     uint64_t version;      /* version of this structure layout, must be first */
411     uint32_t lpid;
412     uint32_t vcpu_token;
413     /* These registers are hypervisor privileged (at least for writing) */
414     uint64_t lpcr;
415     uint64_t pcr;
416     uint64_t amor;
417     uint64_t dpdes;
418     uint64_t hfscr;
419     int64_t tb_offset;
420     uint64_t dawr0;
421     uint64_t dawrx0;
422     uint64_t ciabr;
423     uint64_t hdec_expiry;
424     uint64_t purr;
425     uint64_t spurr;
426     uint64_t ic;
427     uint64_t vtb;
428     uint64_t hdar;
429     uint64_t hdsisr;
430     uint64_t heir;
431     uint64_t asdr;
432     /* These are OS privileged but need to be set late in guest entry */
433     uint64_t srr0;
434     uint64_t srr1;
435     uint64_t sprg[4];
436     uint64_t pidr;
437     uint64_t cfar;
438     uint64_t ppr;
439     /* Version 1 ends here */
440     uint64_t dawr1;
441     uint64_t dawrx1;
442     /* Version 2 ends here */
443 };
444 
445 /* Latest version of hv_guest_state structure */
446 #define HV_GUEST_STATE_VERSION  2
447 
448 /* Linux 64-bit powerpc pt_regs struct, used by nested HV */
449 struct kvmppc_pt_regs {
450     uint64_t gpr[32];
451     uint64_t nip;
452     uint64_t msr;
453     uint64_t orig_gpr3;    /* Used for restarting system calls */
454     uint64_t ctr;
455     uint64_t link;
456     uint64_t xer;
457     uint64_t ccr;
458     uint64_t softe;        /* Soft enabled/disabled */
459     uint64_t trap;         /* Reason for being here */
460     uint64_t dar;          /* Fault registers */
461     uint64_t dsisr;        /* on 4xx/Book-E used for ESR */
462     uint64_t result;       /* Result of a system call */
463 };
464 
465 /*
466  * nested_ppc_state is used to save the host CPU state before switching it to
467  * the guest CPU state, to be restored on H_ENTER_NESTED exit.
468  */
469 struct nested_ppc_state {
470     uint64_t gpr[32];
471     uint64_t lr;
472     uint64_t ctr;
473     uint64_t cfar;
474     uint64_t msr;
475     uint64_t nip;
476     uint32_t cr;
477 
478     uint64_t xer;
479 
480     uint64_t lpcr;
481     uint64_t lpidr;
482     uint64_t pidr;
483     uint64_t pcr;
484     uint64_t dpdes;
485     uint64_t hfscr;
486     uint64_t srr0;
487     uint64_t srr1;
488     uint64_t sprg0;
489     uint64_t sprg1;
490     uint64_t sprg2;
491     uint64_t sprg3;
492     uint64_t ppr;
493 
494     int64_t tb_offset;
495     /* Nested PAPR API */
496     uint64_t amor;
497     uint64_t dawr0;
498     uint64_t dawrx0;
499     uint64_t ciabr;
500     uint64_t purr;
501     uint64_t spurr;
502     uint64_t ic;
503     uint64_t vtb;
504     uint64_t hdar;
505     uint64_t hdsisr;
506     uint64_t heir;
507     uint64_t asdr;
508     uint64_t dawr1;
509     uint64_t dawrx1;
510     uint64_t dexcr;
511     uint64_t hdexcr;
512     uint64_t hashkeyr;
513     uint64_t hashpkeyr;
514     ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
515     uint64_t ebbhr;
516     uint64_t tar;
517     uint64_t ebbrr;
518     uint64_t bescr;
519     uint64_t iamr;
520     uint64_t amr;
521     uint64_t uamor;
522     uint64_t dscr;
523     uint64_t fscr;
524     uint64_t pspb;
525     uint64_t ctrl;
526     uint64_t vrsave;
527     uint64_t dar;
528     uint64_t dsisr;
529     uint64_t pmc1;
530     uint64_t pmc2;
531     uint64_t pmc3;
532     uint64_t pmc4;
533     uint64_t pmc5;
534     uint64_t pmc6;
535     uint64_t mmcr0;
536     uint64_t mmcr1;
537     uint64_t mmcr2;
538     uint64_t mmcra;
539     uint64_t sdar;
540     uint64_t siar;
541     uint64_t sier;
542     uint32_t vscr;
543     uint64_t fpscr;
544     int64_t dec_expiry_tb;
545 };
546 
547 struct SpaprMachineStateNestedGuestVcpuRunBuf {
548     uint64_t addr;
549     uint64_t size;
550 };
551 
552 typedef struct SpaprMachineStateNestedGuestVcpu {
553     bool enabled;
554     struct nested_ppc_state state;
555     struct SpaprMachineStateNestedGuestVcpuRunBuf runbufin;
556     struct SpaprMachineStateNestedGuestVcpuRunBuf runbufout;
557     int64_t tb_offset;
558     uint64_t hdecr_expiry_tb;
559 } SpaprMachineStateNestedGuestVcpu;
560 
561 struct guest_state_element_type {
562     uint16_t id;
563     int size;
564 #define GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE 0x1
565 #define GUEST_STATE_ELEMENT_TYPE_FLAG_HOST_WIDE 0x2
566 #define GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY 0x4
567    uint16_t flags;
568    void *(*location)(struct SpaprMachineState *, SpaprMachineStateNestedGuest *,
569                      target_ulong);
570     size_t offset;
571     void (*copy)(void *, void *, bool);
572     uint64_t mask;
573 };
574 
575 void spapr_exit_nested(PowerPCCPU *cpu, int excp);
576 typedef struct SpaprMachineState SpaprMachineState;
577 bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
578                               target_ulong lpid, ppc_v3_pate_t *entry);
579 uint8_t spapr_nested_api(SpaprMachineState *spapr);
580 void spapr_nested_gsb_init(void);
581 bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu,
582                                 target_ulong lpid, ppc_v3_pate_t *entry);
583 #endif /* HW_SPAPR_NESTED_H */
584