1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H
10
11 #include <linux/mutex.h>
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
18
19 /**
20 * Standard SPI NAND flash operations
21 */
22
23 #define SPINAND_RESET_1S_0_0_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29 #define SPINAND_WR_EN_1S_0_0_OP \
30 SPI_MEM_OP(SPI_MEM_OP_CMD(0x06, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35 #define SPINAND_WR_DIS_1S_0_0_OP \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x04, 1), \
37 SPI_MEM_OP_NO_ADDR, \
38 SPI_MEM_OP_NO_DUMMY, \
39 SPI_MEM_OP_NO_DATA)
40
41 #define SPINAND_READID_1S_1S_1S_OP(naddr, ndummy, buf, len) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
43 SPI_MEM_OP_ADDR(naddr, 0, 1), \
44 SPI_MEM_OP_DUMMY(ndummy, 1), \
45 SPI_MEM_OP_DATA_IN(len, buf, 1))
46
47 #define SPINAND_SET_FEATURE_1S_1S_1S_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
52
53 #define SPINAND_GET_FEATURE_1S_1S_1S_OP(reg, valptr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
55 SPI_MEM_OP_ADDR(1, reg, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_DATA_IN(1, valptr, 1))
58
59 #define SPINAND_BLK_ERASE_1S_1S_0_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65 #define SPINAND_PAGE_READ_1S_1S_0_OP(addr) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
67 SPI_MEM_OP_ADDR(3, addr, 1), \
68 SPI_MEM_OP_NO_DUMMY, \
69 SPI_MEM_OP_NO_DATA)
70
71 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
72 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
73 SPI_MEM_OP_ADDR(2, addr, 1), \
74 SPI_MEM_OP_DUMMY(ndummy, 1), \
75 SPI_MEM_OP_DATA_IN(len, buf, 1), \
76 SPI_MEM_OP_MAX_FREQ(freq))
77
78 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
80 SPI_MEM_OP_ADDR(2, addr, 1), \
81 SPI_MEM_OP_DUMMY(ndummy, 1), \
82 SPI_MEM_OP_DATA_IN(len, buf, 1), \
83 SPI_MEM_OP_MAX_FREQ(freq))
84
85 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
86 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
87 SPI_MEM_OP_ADDR(3, addr, 1), \
88 SPI_MEM_OP_DUMMY(ndummy, 1), \
89 SPI_MEM_OP_DATA_IN(len, buf, 1), \
90 SPI_MEM_OP_MAX_FREQ(freq))
91
92 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_3A_1S_1S_1S_OP(addr, ndummy, buf, len, freq) \
93 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
94 SPI_MEM_OP_ADDR(3, addr, 1), \
95 SPI_MEM_OP_DUMMY(ndummy, 1), \
96 SPI_MEM_OP_DATA_IN(len, buf, 1), \
97 SPI_MEM_OP_MAX_FREQ(freq))
98
99 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(addr, ndummy, buf, len, freq) \
100 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
101 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
102 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
103 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
104 SPI_MEM_OP_MAX_FREQ(freq))
105
106 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \
107 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
108 SPI_MEM_OP_ADDR(2, addr, 1), \
109 SPI_MEM_OP_DUMMY(ndummy, 1), \
110 SPI_MEM_OP_DATA_IN(len, buf, 2), \
111 SPI_MEM_OP_MAX_FREQ(freq))
112
113 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_2S_OP(addr, ndummy, buf, len, freq) \
114 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
115 SPI_MEM_OP_ADDR(3, addr, 1), \
116 SPI_MEM_OP_DUMMY(ndummy, 1), \
117 SPI_MEM_OP_DATA_IN(len, buf, 2), \
118 SPI_MEM_OP_MAX_FREQ(freq))
119
120 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(addr, ndummy, buf, len, freq) \
121 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
122 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
123 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
124 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
125 SPI_MEM_OP_MAX_FREQ(freq))
126
127 #define SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \
128 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
129 SPI_MEM_OP_ADDR(2, addr, 2), \
130 SPI_MEM_OP_DUMMY(ndummy, 2), \
131 SPI_MEM_OP_DATA_IN(len, buf, 2), \
132 SPI_MEM_OP_MAX_FREQ(freq))
133
134 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_2S_2S_OP(addr, ndummy, buf, len, freq) \
135 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
136 SPI_MEM_OP_ADDR(3, addr, 2), \
137 SPI_MEM_OP_DUMMY(ndummy, 2), \
138 SPI_MEM_OP_DATA_IN(len, buf, 2), \
139 SPI_MEM_OP_MAX_FREQ(freq))
140
141 #define SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(addr, ndummy, buf, len, freq) \
142 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
143 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
144 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
145 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
146 SPI_MEM_OP_MAX_FREQ(freq))
147
148 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \
149 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
150 SPI_MEM_OP_ADDR(2, addr, 1), \
151 SPI_MEM_OP_DUMMY(ndummy, 1), \
152 SPI_MEM_OP_DATA_IN(len, buf, 4), \
153 SPI_MEM_OP_MAX_FREQ(freq))
154
155 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_1S_4S_OP(addr, ndummy, buf, len, freq) \
156 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
157 SPI_MEM_OP_ADDR(3, addr, 1), \
158 SPI_MEM_OP_DUMMY(ndummy, 1), \
159 SPI_MEM_OP_DATA_IN(len, buf, 4), \
160 SPI_MEM_OP_MAX_FREQ(freq))
161
162 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(addr, ndummy, buf, len, freq) \
163 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
164 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
165 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
166 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
167 SPI_MEM_OP_MAX_FREQ(freq))
168
169 #define SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \
170 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
171 SPI_MEM_OP_ADDR(2, addr, 4), \
172 SPI_MEM_OP_DUMMY(ndummy, 4), \
173 SPI_MEM_OP_DATA_IN(len, buf, 4), \
174 SPI_MEM_OP_MAX_FREQ(freq))
175
176 #define SPINAND_PAGE_READ_FROM_CACHE_3A_1S_4S_4S_OP(addr, ndummy, buf, len, freq) \
177 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
178 SPI_MEM_OP_ADDR(3, addr, 4), \
179 SPI_MEM_OP_DUMMY(ndummy, 4), \
180 SPI_MEM_OP_DATA_IN(len, buf, 4), \
181 SPI_MEM_OP_MAX_FREQ(freq))
182
183 #define SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(addr, ndummy, buf, len, freq) \
184 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
185 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
186 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
187 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
188 SPI_MEM_OP_MAX_FREQ(freq))
189
190 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(addr, ndummy, buf, len, freq) \
191 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
192 SPI_MEM_OP_ADDR(2, addr, 1), \
193 SPI_MEM_OP_DUMMY(ndummy, 1), \
194 SPI_MEM_OP_DATA_IN(len, buf, 8), \
195 SPI_MEM_OP_MAX_FREQ(freq))
196
197 #define SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(addr, ndummy, buf, len, freq) \
198 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \
199 SPI_MEM_OP_ADDR(2, addr, 8), \
200 SPI_MEM_OP_DUMMY(ndummy, 8), \
201 SPI_MEM_OP_DATA_IN(len, buf, 8), \
202 SPI_MEM_OP_MAX_FREQ(freq))
203
204 #define SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(addr, ndummy, buf, len, freq) \
205 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \
206 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
207 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
208 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
209 SPI_MEM_OP_MAX_FREQ(freq))
210
211 #define SPINAND_PROG_EXEC_1S_1S_0_OP(addr) \
212 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
213 SPI_MEM_OP_ADDR(3, addr, 1), \
214 SPI_MEM_OP_NO_DUMMY, \
215 SPI_MEM_OP_NO_DATA)
216
217 #define SPINAND_PROG_LOAD_1S_1S_1S_OP(reset, addr, buf, len) \
218 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
219 SPI_MEM_OP_ADDR(2, addr, 1), \
220 SPI_MEM_OP_NO_DUMMY, \
221 SPI_MEM_OP_DATA_OUT(len, buf, 1))
222
223 #define SPINAND_PROG_LOAD_1S_1S_4S_OP(reset, addr, buf, len) \
224 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
225 SPI_MEM_OP_ADDR(2, addr, 1), \
226 SPI_MEM_OP_NO_DUMMY, \
227 SPI_MEM_OP_DATA_OUT(len, buf, 4))
228
229 #define SPINAND_PROG_LOAD_1S_1S_8S_OP(addr, buf, len) \
230 SPI_MEM_OP(SPI_MEM_OP_CMD(0x82, 1), \
231 SPI_MEM_OP_ADDR(2, addr, 1), \
232 SPI_MEM_OP_NO_DUMMY, \
233 SPI_MEM_OP_DATA_OUT(len, buf, 8))
234
235 #define SPINAND_PROG_LOAD_1S_8S_8S_OP(reset, addr, buf, len) \
236 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0xc2 : 0xc4, 1), \
237 SPI_MEM_OP_ADDR(2, addr, 8), \
238 SPI_MEM_OP_NO_DUMMY, \
239 SPI_MEM_OP_DATA_OUT(len, buf, 8))
240
241 /**
242 * Octal DDR SPI NAND flash operations
243 */
244
245 #define SPINAND_RESET_8D_0_0_OP \
246 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xff, 8), \
247 SPI_MEM_OP_NO_ADDR, \
248 SPI_MEM_OP_NO_DUMMY, \
249 SPI_MEM_OP_NO_DATA)
250
251 #define SPINAND_READID_8D_8D_8D_OP(naddr, ndummy, buf, len) \
252 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9f, 8), \
253 SPI_MEM_DTR_OP_ADDR(naddr, 0, 8), \
254 SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \
255 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8))
256
257 #define SPINAND_WR_EN_8D_0_0_OP \
258 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x06, 8), \
259 SPI_MEM_OP_NO_ADDR, \
260 SPI_MEM_OP_NO_DUMMY, \
261 SPI_MEM_OP_NO_DATA)
262
263 #define SPINAND_WR_DIS_8D_0_0_OP \
264 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x04, 8), \
265 SPI_MEM_OP_NO_ADDR, \
266 SPI_MEM_OP_NO_DUMMY, \
267 SPI_MEM_OP_NO_DATA)
268
269 #define SPINAND_SET_FEATURE_8D_8D_8D_OP(reg, valptr) \
270 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x1f, 8), \
271 SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \
272 SPI_MEM_OP_NO_DUMMY, \
273 SPI_MEM_DTR_OP_DATA_OUT(2, valptr, 8))
274
275 #define SPINAND_GET_FEATURE_8D_8D_8D_OP(reg, valptr) \
276 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x0f, 8), \
277 SPI_MEM_DTR_OP_RPT_ADDR(reg, 8), \
278 SPI_MEM_DTR_OP_DUMMY(14, 8), \
279 SPI_MEM_DTR_OP_DATA_IN(2, valptr, 8))
280
281 #define SPINAND_BLK_ERASE_8D_8D_0_OP(addr) \
282 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0xd8, 8), \
283 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \
284 SPI_MEM_OP_NO_DUMMY, \
285 SPI_MEM_OP_NO_DATA)
286
287 #define SPINAND_PAGE_READ_8D_8D_0_OP(addr) \
288 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x13, 8), \
289 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \
290 SPI_MEM_OP_NO_DUMMY, \
291 SPI_MEM_OP_NO_DATA)
292
293 #define SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(addr, ndummy, buf, len, freq) \
294 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \
295 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \
296 SPI_MEM_DTR_OP_DUMMY(ndummy, 8), \
297 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
298 SPI_MEM_OP_MAX_FREQ(freq))
299
300 #define SPINAND_PROG_EXEC_8D_8D_0_OP(addr) \
301 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x10, 8), \
302 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \
303 SPI_MEM_OP_NO_DUMMY, \
304 SPI_MEM_OP_NO_DATA)
305
306 #define SPINAND_PROG_LOAD_8D_8D_8D_OP(reset, addr, buf, len) \
307 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD((reset ? 0xc2 : 0xc4), 8), \
308 SPI_MEM_DTR_OP_ADDR(2, addr, 8), \
309 SPI_MEM_OP_NO_DUMMY, \
310 SPI_MEM_DTR_OP_DATA_OUT(len, buf, 8))
311
312 /* feature register */
313 #define REG_BLOCK_LOCK 0xa0
314 #define BL_ALL_UNLOCKED 0x00
315
316 /* configuration register */
317 #define REG_CFG 0xb0
318 #define CFG_OTP_ENABLE BIT(6)
319 #define CFG_ECC_ENABLE BIT(4)
320 #define CFG_QUAD_ENABLE BIT(0)
321
322 /* status register */
323 #define REG_STATUS 0xc0
324 #define STATUS_BUSY BIT(0)
325 #define STATUS_ERASE_FAILED BIT(2)
326 #define STATUS_PROG_FAILED BIT(3)
327 #define STATUS_ECC_MASK GENMASK(5, 4)
328 #define STATUS_ECC_NO_BITFLIPS (0 << 4)
329 #define STATUS_ECC_HAS_BITFLIPS (1 << 4)
330 #define STATUS_ECC_UNCOR_ERROR (2 << 4)
331
332 struct spinand_op;
333 struct spinand_device;
334
335 #define SPINAND_MAX_ID_LEN 6
336 /*
337 * For erase, write and read operation, we got the following timings :
338 * tBERS (erase) 1ms to 4ms
339 * tPROG 300us to 400us
340 * tREAD 25us to 100us
341 * In order to minimize latency, the min value is divided by 4 for the
342 * initial delay, and dividing by 20 for the poll delay.
343 * For reset, 5us/10us/500us if the device is respectively
344 * reading/programming/erasing when the RESET occurs. Since we always
345 * issue a RESET when the device is IDLE, 5us is selected for both initial
346 * and poll delay.
347 */
348 #define SPINAND_READ_INITIAL_DELAY_US 6
349 #define SPINAND_READ_POLL_DELAY_US 5
350 #define SPINAND_RESET_INITIAL_DELAY_US 5
351 #define SPINAND_RESET_POLL_DELAY_US 5
352 #define SPINAND_WRITE_INITIAL_DELAY_US 75
353 #define SPINAND_WRITE_POLL_DELAY_US 15
354 #define SPINAND_ERASE_INITIAL_DELAY_US 250
355 #define SPINAND_ERASE_POLL_DELAY_US 50
356
357 #define SPINAND_WAITRDY_TIMEOUT_MS 400
358
359 /**
360 * struct spinand_id - SPI NAND id structure
361 * @data: buffer containing the id bytes. Currently 6 bytes large, but can
362 * be extended if required
363 * @len: ID length
364 */
365 struct spinand_id {
366 u8 data[SPINAND_MAX_ID_LEN];
367 int len;
368 };
369
370 enum spinand_readid_method {
371 SPINAND_READID_METHOD_OPCODE,
372 SPINAND_READID_METHOD_OPCODE_ADDR,
373 SPINAND_READID_METHOD_OPCODE_DUMMY,
374 };
375
376 /**
377 * struct spinand_devid - SPI NAND device id structure
378 * @id: device id of current chip
379 * @len: number of bytes in device id
380 * @method: method to read chip id
381 * There are 3 possible variants:
382 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
383 * after read_id opcode.
384 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
385 * read_id opcode + 1-byte address.
386 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
387 * read_id opcode + 1 dummy byte.
388 */
389 struct spinand_devid {
390 const u8 *id;
391 const u8 len;
392 const enum spinand_readid_method method;
393 };
394
395 /**
396 * struct manufacurer_ops - SPI NAND manufacturer specific operations
397 * @init: initialize a SPI NAND device
398 * @cleanup: cleanup a SPI NAND device
399 *
400 * Each SPI NAND manufacturer driver should implement this interface so that
401 * NAND chips coming from this vendor can be initialized properly.
402 */
403 struct spinand_manufacturer_ops {
404 int (*init)(struct spinand_device *spinand);
405 void (*cleanup)(struct spinand_device *spinand);
406 };
407
408 /**
409 * struct spinand_manufacturer - SPI NAND manufacturer instance
410 * @id: manufacturer ID
411 * @name: manufacturer name
412 * @devid_len: number of bytes in device ID
413 * @chips: supported SPI NANDs under current manufacturer
414 * @nchips: number of SPI NANDs available in chips array
415 * @ops: manufacturer operations
416 */
417 struct spinand_manufacturer {
418 u8 id;
419 char *name;
420 const struct spinand_info *chips;
421 const size_t nchips;
422 const struct spinand_manufacturer_ops *ops;
423 };
424
425 /* SPI NAND manufacturers */
426 extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
427 extern const struct spinand_manufacturer ato_spinand_manufacturer;
428 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
429 extern const struct spinand_manufacturer esmt_8c_spinand_manufacturer;
430 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
431 extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
432 extern const struct spinand_manufacturer foresee_spinand_manufacturer;
433 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
434 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
435 extern const struct spinand_manufacturer micron_spinand_manufacturer;
436 extern const struct spinand_manufacturer paragon_spinand_manufacturer;
437 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
438 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
439 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
440 extern const struct spinand_manufacturer xtx_spinand_manufacturer;
441
442 /**
443 * struct spinand_op_variants - SPI NAND operation variants
444 * @ops: the list of variants for a given operation
445 * @nops: the number of variants
446 *
447 * Some operations like read-from-cache/write-to-cache have several variants
448 * depending on the number of IO lines you use to transfer data or address
449 * cycles. This structure is a way to describe the different variants supported
450 * by a chip and let the core pick the best one based on the SPI mem controller
451 * capabilities.
452 */
453 struct spinand_op_variants {
454 const struct spi_mem_op *ops;
455 unsigned int nops;
456 };
457
458 #define SPINAND_OP_VARIANTS(name, ...) \
459 const struct spinand_op_variants name = { \
460 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
461 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
462 sizeof(struct spi_mem_op), \
463 }
464
465 /**
466 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
467 * chip
468 * @get_status: get the ECC status. Should return a positive number encoding
469 * the number of corrected bitflips if correction was possible or
470 * -EBADMSG if there are uncorrectable errors. I can also return
471 * other negative error codes if the error is not caused by
472 * uncorrectable bitflips
473 * @ooblayout: the OOB layout used by the on-die ECC implementation
474 */
475 struct spinand_ecc_info {
476 int (*get_status)(struct spinand_device *spinand, u8 status);
477 const struct mtd_ooblayout_ops *ooblayout;
478 };
479
480 #define SPINAND_HAS_QE_BIT BIT(0)
481 #define SPINAND_HAS_CR_FEAT_BIT BIT(1)
482 #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
483 #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
484 #define SPINAND_NO_RAW_ACCESS BIT(4)
485
486 /**
487 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
488 * @status: status of the last wait operation that will be used in case
489 * ->get_status() is not populated by the spinand device.
490 */
491 struct spinand_ondie_ecc_conf {
492 u8 status;
493 };
494
495 /**
496 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area
497 * @npages: number of pages in the OTP
498 * @start_page: start page of the user/factory OTP area.
499 */
500 struct spinand_otp_layout {
501 unsigned int npages;
502 unsigned int start_page;
503 };
504
505 /**
506 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area
507 * @info: get the OTP area information
508 * @read: read from the SPI NAND OTP area
509 */
510 struct spinand_fact_otp_ops {
511 int (*info)(struct spinand_device *spinand, size_t len,
512 struct otp_info *buf, size_t *retlen);
513 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
514 size_t *retlen, u8 *buf);
515 };
516
517 /**
518 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area
519 * @info: get the OTP area information
520 * @lock: lock an OTP region
521 * @erase: erase an OTP region
522 * @read: read from the SPI NAND OTP area
523 * @write: write to the SPI NAND OTP area
524 */
525 struct spinand_user_otp_ops {
526 int (*info)(struct spinand_device *spinand, size_t len,
527 struct otp_info *buf, size_t *retlen);
528 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len);
529 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len);
530 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
531 size_t *retlen, u8 *buf);
532 int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
533 size_t *retlen, const u8 *buf);
534 };
535
536 /**
537 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area
538 * @layout: OTP region layout
539 * @ops: OTP access ops
540 */
541 struct spinand_fact_otp {
542 const struct spinand_otp_layout layout;
543 const struct spinand_fact_otp_ops *ops;
544 };
545
546 /**
547 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area
548 * @layout: OTP region layout
549 * @ops: OTP access ops
550 */
551 struct spinand_user_otp {
552 const struct spinand_otp_layout layout;
553 const struct spinand_user_otp_ops *ops;
554 };
555
556 /**
557 * enum spinand_bus_interface - SPI NAND bus interface types
558 * @SSDR: Bus configuration supporting all 1S-XX-XX operations, including dual and quad
559 * @ODTR: Bus configuration supporting only 8D-8D-8D operations
560 */
561 enum spinand_bus_interface {
562 SSDR,
563 ODTR,
564 };
565
566 /**
567 * struct spinand_info - Structure used to describe SPI NAND chips
568 * @model: model name
569 * @devid: device ID
570 * @flags: OR-ing of the SPINAND_XXX flags
571 * @memorg: memory organization
572 * @eccreq: ECC requirements
573 * @eccinfo: on-die ECC info
574 * @op_variants: operations variants
575 * @op_variants.read_cache: variants of the read-cache operation
576 * @op_variants.write_cache: variants of the write-cache operation
577 * @op_variants.update_cache: variants of the update-cache operation
578 * @vendor_ops: vendor specific operations
579 * @select_target: function used to select a target/die. Required only for
580 * multi-die chips
581 * @configure_chip: Align the chip configuration with the core settings
582 * @set_cont_read: enable/disable continuous cached reads
583 * @fact_otp: SPI NAND factory OTP info.
584 * @user_otp: SPI NAND user OTP info.
585 * @read_retries: the number of read retry modes supported
586 * @set_read_retry: enable/disable read retry for data recovery
587 *
588 * Each SPI NAND manufacturer driver should have a spinand_info table
589 * describing all the chips supported by the driver.
590 */
591 struct spinand_info {
592 const char *model;
593 struct spinand_devid devid;
594 u32 flags;
595 struct nand_memory_organization memorg;
596 struct nand_ecc_props eccreq;
597 struct spinand_ecc_info eccinfo;
598 struct {
599 const struct spinand_op_variants *read_cache;
600 const struct spinand_op_variants *write_cache;
601 const struct spinand_op_variants *update_cache;
602 } op_variants;
603 const struct spinand_op_variants *vendor_ops;
604 int (*select_target)(struct spinand_device *spinand,
605 unsigned int target);
606 int (*configure_chip)(struct spinand_device *spinand,
607 enum spinand_bus_interface iface);
608 int (*set_cont_read)(struct spinand_device *spinand,
609 bool enable);
610 struct spinand_fact_otp fact_otp;
611 struct spinand_user_otp user_otp;
612 unsigned int read_retries;
613 int (*set_read_retry)(struct spinand_device *spinand,
614 unsigned int read_retry);
615 };
616
617 #define SPINAND_ID(__method, ...) \
618 { \
619 .id = (const u8[]){ __VA_ARGS__ }, \
620 .len = sizeof((u8[]){ __VA_ARGS__ }), \
621 .method = __method, \
622 }
623
624 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
625 { \
626 .read_cache = __read, \
627 .write_cache = __write, \
628 .update_cache = __update, \
629 }
630
631 #define SPINAND_INFO_VENDOR_OPS(__ops) \
632 .vendor_ops = __ops
633
634 #define SPINAND_ECCINFO(__ooblayout, __get_status) \
635 .eccinfo = { \
636 .ooblayout = __ooblayout, \
637 .get_status = __get_status, \
638 }
639
640 #define SPINAND_SELECT_TARGET(__func) \
641 .select_target = __func
642
643 #define SPINAND_CONFIGURE_CHIP(__configure_chip) \
644 .configure_chip = __configure_chip
645
646 #define SPINAND_CONT_READ(__set_cont_read) \
647 .set_cont_read = __set_cont_read
648
649 #define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \
650 .fact_otp = { \
651 .layout = { \
652 .npages = __npages, \
653 .start_page = __start_page, \
654 }, \
655 .ops = __ops, \
656 }
657
658 #define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \
659 .user_otp = { \
660 .layout = { \
661 .npages = __npages, \
662 .start_page = __start_page, \
663 }, \
664 .ops = __ops, \
665 }
666
667 #define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \
668 .read_retries = __read_retries, \
669 .set_read_retry = __set_read_retry
670
671 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
672 __flags, ...) \
673 { \
674 .model = __model, \
675 .devid = __id, \
676 .memorg = __memorg, \
677 .eccreq = __eccreq, \
678 .op_variants = __op_variants, \
679 .flags = __flags, \
680 __VA_ARGS__ \
681 }
682
683 struct spinand_dirmap {
684 struct spi_mem_dirmap_desc *wdesc;
685 struct spi_mem_dirmap_desc *rdesc;
686 struct spi_mem_dirmap_desc *wdesc_ecc;
687 struct spi_mem_dirmap_desc *rdesc_ecc;
688 };
689
690 /**
691 * struct spinand_mem_ops - SPI NAND memory operations
692 * @reset: reset op template
693 * @readid: read ID op template
694 * @wr_en: write enable op template
695 * @wr_dis: write disable op template
696 * @set_feature: set feature op template
697 * @get_feature: get feature op template
698 * @blk_erase: blk erase op template
699 * @page_read: page read op template
700 * @prog_exec: prog exec op template
701 * @read_cache: read cache op template
702 * @write_cache: write cache op template
703 * @update_cache: update cache op template
704 */
705 struct spinand_mem_ops {
706 struct spi_mem_op reset;
707 struct spi_mem_op readid;
708 struct spi_mem_op wr_en;
709 struct spi_mem_op wr_dis;
710 struct spi_mem_op set_feature;
711 struct spi_mem_op get_feature;
712 struct spi_mem_op blk_erase;
713 struct spi_mem_op page_read;
714 struct spi_mem_op prog_exec;
715 const struct spi_mem_op *read_cache;
716 const struct spi_mem_op *write_cache;
717 const struct spi_mem_op *update_cache;
718 };
719
720 /**
721 * struct spinand_device - SPI NAND device instance
722 * @base: NAND device instance
723 * @spimem: pointer to the SPI mem object
724 * @lock: lock used to serialize accesses to the NAND
725 * @id: NAND ID as returned by READ_ID
726 * @flags: NAND flags
727 * @ssdr_op_templates: Templates for all single SDR SPI mem operations
728 * @odtr_op_templates: Templates for all octal DTR SPI mem operations
729 * @op_templates: Templates for all SPI mem operations
730 * @bus_iface: Current bus interface
731 * @select_target: select a specific target/die. Usually called before sending
732 * a command addressing a page or an eraseblock embedded in
733 * this die. Only required if your chip exposes several dies
734 * @cur_target: currently selected target/die
735 * @eccinfo: on-die ECC information
736 * @cfg_cache: config register cache. One entry per die
737 * @databuf: bounce buffer for data
738 * @oobbuf: bounce buffer for OOB data
739 * @scratchbuf: buffer used for everything but page accesses. This is needed
740 * because the spi-mem interface explicitly requests that buffers
741 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
742 * the stack
743 * @manufacturer: SPI NAND manufacturer information
744 * @configure_chip: Align the chip configuration with the core settings
745 * @cont_read_possible: Field filled by the core once the whole system
746 * configuration is known to tell whether continuous reads are
747 * suitable to use or not in general with this chip/configuration.
748 * A per-transfer check must of course be done to ensure it is
749 * actually relevant to enable this feature.
750 * @set_cont_read: Enable/disable the continuous read feature
751 * @priv: manufacturer private data
752 * @fact_otp: SPI NAND factory OTP info.
753 * @user_otp: SPI NAND user OTP info.
754 * @read_retries: the number of read retry modes supported
755 * @set_read_retry: Enable/disable the read retry feature
756 */
757 struct spinand_device {
758 struct nand_device base;
759 struct spi_mem *spimem;
760 struct mutex lock;
761 struct spinand_id id;
762 u32 flags;
763
764 struct spinand_mem_ops ssdr_op_templates;
765 struct spinand_mem_ops odtr_op_templates;
766 struct spinand_mem_ops *op_templates;
767 enum spinand_bus_interface bus_iface;
768
769 struct spinand_dirmap *dirmaps;
770
771 int (*select_target)(struct spinand_device *spinand,
772 unsigned int target);
773 unsigned int cur_target;
774
775 struct spinand_ecc_info eccinfo;
776
777 u8 *cfg_cache;
778 u8 *databuf;
779 u8 *oobbuf;
780 u8 *scratchbuf;
781 const struct spinand_manufacturer *manufacturer;
782 void *priv;
783
784 int (*configure_chip)(struct spinand_device *spinand,
785 enum spinand_bus_interface iface);
786 bool cont_read_possible;
787 int (*set_cont_read)(struct spinand_device *spinand,
788 bool enable);
789
790 const struct spinand_fact_otp *fact_otp;
791 const struct spinand_user_otp *user_otp;
792
793 unsigned int read_retries;
794 int (*set_read_retry)(struct spinand_device *spinand,
795 unsigned int retry_mode);
796 };
797
798 struct spi_mem_op spinand_fill_wr_en_op(struct spinand_device *spinand);
799 struct spi_mem_op spinand_fill_set_feature_op(struct spinand_device *spinand, u64 reg, const void *valptr);
800 struct spi_mem_op spinand_fill_get_feature_op(struct spinand_device *spinand, u64 reg, void *valptr);
801 struct spi_mem_op spinand_fill_prog_exec_op(struct spinand_device *spinand, u64 addr);
802
803 #define SPINAND_OP(spinand, op_name, ...) \
804 spinand_fill_ ## op_name ## _op(spinand, ##__VA_ARGS__)
805
806 /**
807 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
808 * @mtd: MTD instance
809 *
810 * Return: the SPI NAND device attached to @mtd.
811 */
mtd_to_spinand(struct mtd_info * mtd)812 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
813 {
814 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
815 }
816
817 /**
818 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
819 * @spinand: SPI NAND device
820 *
821 * Return: the MTD device embedded in @spinand.
822 */
spinand_to_mtd(struct spinand_device * spinand)823 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
824 {
825 return nanddev_to_mtd(&spinand->base);
826 }
827
828 /**
829 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
830 * @nand: NAND object
831 *
832 * Return: the SPI NAND device embedding @nand.
833 */
nand_to_spinand(struct nand_device * nand)834 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
835 {
836 return container_of(nand, struct spinand_device, base);
837 }
838
839 /**
840 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
841 * @spinand: SPI NAND device
842 *
843 * Return: the NAND device embedded in @spinand.
844 */
845 static inline struct nand_device *
spinand_to_nand(struct spinand_device * spinand)846 spinand_to_nand(struct spinand_device *spinand)
847 {
848 return &spinand->base;
849 }
850
851 /**
852 * spinand_set_of_node - Attach a DT node to a SPI NAND device
853 * @spinand: SPI NAND device
854 * @np: DT node
855 *
856 * Attach a DT node to a SPI NAND device.
857 */
spinand_set_of_node(struct spinand_device * spinand,struct device_node * np)858 static inline void spinand_set_of_node(struct spinand_device *spinand,
859 struct device_node *np)
860 {
861 nanddev_set_of_node(&spinand->base, np);
862 }
863
864 int spinand_match_and_init(struct spinand_device *spinand,
865 const struct spinand_info *table,
866 unsigned int table_size,
867 enum spinand_readid_method rdid_method);
868
869 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
870 int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val);
871 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
872 int spinand_write_enable_op(struct spinand_device *spinand);
873 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
874
875 int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us,
876 unsigned long poll_delay_us, u8 *s);
877
878 int spinand_read_page(struct spinand_device *spinand,
879 const struct nand_page_io_req *req);
880
881 int spinand_write_page(struct spinand_device *spinand,
882 const struct nand_page_io_req *req);
883
884 size_t spinand_otp_page_size(struct spinand_device *spinand);
885 size_t spinand_fact_otp_size(struct spinand_device *spinand);
886 size_t spinand_user_otp_size(struct spinand_device *spinand);
887
888 int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs,
889 size_t len, size_t *retlen, u8 *buf);
890 int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs,
891 size_t len, size_t *retlen, u8 *buf);
892 int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs,
893 size_t len, size_t *retlen, const u8 *buf);
894
895 int spinand_set_mtd_otp_ops(struct spinand_device *spinand);
896
897 #endif /* __LINUX_MTD_SPINAND_H */
898