1 /*
2 * Sparc CPU init helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu/module.h"
24 #include "qemu/qemu-print.h"
25 #include "accel/tcg/cpu-mmu-index.h"
26 #include "exec/translation-block.h"
27 #include "hw/qdev-properties.h"
28 #include "qapi/visitor.h"
29 #include "tcg/tcg.h"
30 #include "fpu/softfloat.h"
31 #include "target/sparc/translate.h"
32
33 //#define DEBUG_FEATURES
34
sparc_cpu_reset_hold(Object * obj,ResetType type)35 static void sparc_cpu_reset_hold(Object *obj, ResetType type)
36 {
37 CPUState *cs = CPU(obj);
38 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
39 CPUSPARCState *env = cpu_env(cs);
40
41 if (scc->parent_phases.hold) {
42 scc->parent_phases.hold(obj, type);
43 }
44
45 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
46 env->cwp = 0;
47 #ifndef TARGET_SPARC64
48 env->wim = 1;
49 #endif
50 env->regwptr = env->regbase + (env->cwp * 16);
51 #if defined(CONFIG_USER_ONLY)
52 #ifdef TARGET_SPARC64
53 env->cleanwin = env->nwindows - 2;
54 env->cansave = env->nwindows - 2;
55 env->pstate = PS_RMO | PS_PEF | PS_IE;
56 env->asi = 0x82; /* Primary no-fault */
57 #endif
58 #else
59 #if !defined(TARGET_SPARC64)
60 env->psret = 0;
61 env->psrs = 1;
62 env->psrps = 1;
63 #endif
64 #ifdef TARGET_SPARC64
65 env->pstate = PS_PRIV | PS_RED | PS_PEF;
66 if (!cpu_has_hypervisor(env)) {
67 env->pstate |= PS_AG;
68 }
69 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
70 env->tl = env->maxtl;
71 env->gl = 2;
72 cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
73 env->lsu = 0;
74 #else
75 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
76 env->mmuregs[0] |= env->def.mmu_bm;
77 #endif
78 env->pc = 0;
79 env->npc = env->pc + 4;
80 #endif
81 env->cache_control = 0;
82 cpu_put_fsr(env, 0);
83 }
84
85 #ifndef CONFIG_USER_ONLY
sparc_cpu_exec_interrupt(CPUState * cs,int interrupt_request)86 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
87 {
88 if (interrupt_request & CPU_INTERRUPT_HARD) {
89 CPUSPARCState *env = cpu_env(cs);
90
91 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
92 int pil = env->interrupt_index & 0xf;
93 int type = env->interrupt_index & 0xf0;
94
95 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
96 cs->exception_index = env->interrupt_index;
97 sparc_cpu_do_interrupt(cs);
98 return true;
99 }
100 }
101 }
102 return false;
103 }
104 #endif /* !CONFIG_USER_ONLY */
105
cpu_sparc_disas_set_info(CPUState * cpu,disassemble_info * info)106 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
107 {
108 info->print_insn = print_insn_sparc;
109 info->endian = BFD_ENDIAN_BIG;
110 #ifdef TARGET_SPARC64
111 info->mach = bfd_mach_sparc_v9b;
112 #endif
113 }
114
115 static void
cpu_add_feat_as_prop(const char * typename,const char * name,const char * val)116 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
117 {
118 GlobalProperty *prop = g_new0(typeof(*prop), 1);
119 prop->driver = typename;
120 prop->property = g_strdup(name);
121 prop->value = g_strdup(val);
122 qdev_prop_register_global(prop);
123 }
124
125 /* Parse "+feature,-feature,feature=foo" CPU feature string */
sparc_cpu_parse_features(const char * typename,char * features,Error ** errp)126 static void sparc_cpu_parse_features(const char *typename, char *features,
127 Error **errp)
128 {
129 GList *l, *plus_features = NULL, *minus_features = NULL;
130 char *featurestr; /* Single 'key=value" string being parsed */
131 static bool cpu_globals_initialized;
132
133 if (cpu_globals_initialized) {
134 return;
135 }
136 cpu_globals_initialized = true;
137
138 if (!features) {
139 return;
140 }
141
142 for (featurestr = strtok(features, ",");
143 featurestr;
144 featurestr = strtok(NULL, ",")) {
145 const char *name;
146 const char *val = NULL;
147 char *eq = NULL;
148
149 /* Compatibility syntax: */
150 if (featurestr[0] == '+') {
151 plus_features = g_list_append(plus_features,
152 g_strdup(featurestr + 1));
153 continue;
154 } else if (featurestr[0] == '-') {
155 minus_features = g_list_append(minus_features,
156 g_strdup(featurestr + 1));
157 continue;
158 }
159
160 eq = strchr(featurestr, '=');
161 name = featurestr;
162 if (eq) {
163 *eq++ = 0;
164 val = eq;
165
166 /*
167 * Temporarily, only +feat/-feat will be supported
168 * for boolean properties until we remove the
169 * minus-overrides-plus semantics and just follow
170 * the order options appear on the command-line.
171 *
172 * TODO: warn if user is relying on minus-override-plus semantics
173 * TODO: remove minus-override-plus semantics after
174 * warning for a few releases
175 */
176 if (!strcasecmp(val, "on") ||
177 !strcasecmp(val, "off") ||
178 !strcasecmp(val, "true") ||
179 !strcasecmp(val, "false")) {
180 error_setg(errp, "Boolean properties in format %s=%s"
181 " are not supported", name, val);
182 return;
183 }
184 } else {
185 error_setg(errp, "Unsupported property format: %s", name);
186 return;
187 }
188 cpu_add_feat_as_prop(typename, name, val);
189 }
190
191 for (l = plus_features; l; l = l->next) {
192 const char *name = l->data;
193 cpu_add_feat_as_prop(typename, name, "on");
194 }
195 g_list_free_full(plus_features, g_free);
196
197 for (l = minus_features; l; l = l->next) {
198 const char *name = l->data;
199 cpu_add_feat_as_prop(typename, name, "off");
200 }
201 g_list_free_full(minus_features, g_free);
202 }
203
cpu_sparc_set_id(CPUSPARCState * env,unsigned int cpu)204 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
205 {
206 #if !defined(TARGET_SPARC64)
207 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
208 #endif
209 }
210
211 static const sparc_def_t sparc_defs[] = {
212 #ifdef TARGET_SPARC64
213 {
214 .name = "Fujitsu-Sparc64",
215 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
216 .fpu_version = 0x00000000,
217 .mmu_version = mmu_us_12,
218 .nwindows = 4,
219 .maxtl = 4,
220 .features = CPU_DEFAULT_FEATURES,
221 },
222 {
223 .name = "Fujitsu-Sparc64-III",
224 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
225 .fpu_version = 0x00000000,
226 .mmu_version = mmu_us_12,
227 .nwindows = 5,
228 .maxtl = 4,
229 .features = CPU_DEFAULT_FEATURES,
230 },
231 {
232 .name = "Fujitsu-Sparc64-IV",
233 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
234 .fpu_version = 0x00000000,
235 .mmu_version = mmu_us_12,
236 .nwindows = 8,
237 .maxtl = 5,
238 .features = CPU_DEFAULT_FEATURES,
239 },
240 {
241 .name = "Fujitsu-Sparc64-V",
242 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
243 .fpu_version = 0x00000000,
244 .mmu_version = mmu_us_12,
245 .nwindows = 8,
246 .maxtl = 5,
247 .features = CPU_DEFAULT_FEATURES,
248 },
249 {
250 .name = "TI-UltraSparc-I",
251 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
252 .fpu_version = 0x00000000,
253 .mmu_version = mmu_us_12,
254 .nwindows = 8,
255 .maxtl = 5,
256 .features = CPU_DEFAULT_FEATURES,
257 },
258 {
259 .name = "TI-UltraSparc-II",
260 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
261 .fpu_version = 0x00000000,
262 .mmu_version = mmu_us_12,
263 .nwindows = 8,
264 .maxtl = 5,
265 .features = CPU_DEFAULT_FEATURES,
266 },
267 {
268 .name = "TI-UltraSparc-IIi",
269 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
270 .fpu_version = 0x00000000,
271 .mmu_version = mmu_us_12,
272 .nwindows = 8,
273 .maxtl = 5,
274 .features = CPU_DEFAULT_FEATURES,
275 },
276 {
277 .name = "TI-UltraSparc-IIe",
278 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
279 .fpu_version = 0x00000000,
280 .mmu_version = mmu_us_12,
281 .nwindows = 8,
282 .maxtl = 5,
283 .features = CPU_DEFAULT_FEATURES,
284 },
285 {
286 .name = "Sun-UltraSparc-III",
287 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
288 .fpu_version = 0x00000000,
289 .mmu_version = mmu_us_12,
290 .nwindows = 8,
291 .maxtl = 5,
292 .features = CPU_DEFAULT_FEATURES,
293 },
294 {
295 .name = "Sun-UltraSparc-III-Cu",
296 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
297 .fpu_version = 0x00000000,
298 .mmu_version = mmu_us_3,
299 .nwindows = 8,
300 .maxtl = 5,
301 .features = CPU_DEFAULT_FEATURES,
302 },
303 {
304 .name = "Sun-UltraSparc-IIIi",
305 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
306 .fpu_version = 0x00000000,
307 .mmu_version = mmu_us_12,
308 .nwindows = 8,
309 .maxtl = 5,
310 .features = CPU_DEFAULT_FEATURES,
311 },
312 {
313 .name = "Sun-UltraSparc-IV",
314 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
315 .fpu_version = 0x00000000,
316 .mmu_version = mmu_us_4,
317 .nwindows = 8,
318 .maxtl = 5,
319 .features = CPU_DEFAULT_FEATURES,
320 },
321 {
322 .name = "Sun-UltraSparc-IV-plus",
323 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
324 .fpu_version = 0x00000000,
325 .mmu_version = mmu_us_12,
326 .nwindows = 8,
327 .maxtl = 5,
328 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
329 },
330 {
331 .name = "Sun-UltraSparc-IIIi-plus",
332 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
333 .fpu_version = 0x00000000,
334 .mmu_version = mmu_us_3,
335 .nwindows = 8,
336 .maxtl = 5,
337 .features = CPU_DEFAULT_FEATURES,
338 },
339 {
340 .name = "Sun-UltraSparc-T1",
341 /* defined in sparc_ifu_fdp.v and ctu.h */
342 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
343 .fpu_version = 0x00000000,
344 .mmu_version = mmu_sun4v,
345 .nwindows = 8,
346 .maxtl = 6,
347 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
348 | CPU_FEATURE_GL,
349 },
350 {
351 .name = "Sun-UltraSparc-T2",
352 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
353 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
354 .fpu_version = 0x00000000,
355 .mmu_version = mmu_sun4v,
356 .nwindows = 8,
357 .maxtl = 6,
358 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
359 | CPU_FEATURE_GL,
360 },
361 {
362 .name = "NEC-UltraSparc-I",
363 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
364 .fpu_version = 0x00000000,
365 .mmu_version = mmu_us_12,
366 .nwindows = 8,
367 .maxtl = 5,
368 .features = CPU_DEFAULT_FEATURES,
369 },
370 #else
371 {
372 .name = "Fujitsu-MB86904",
373 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
374 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
375 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
376 .mmu_bm = 0x00004000,
377 .mmu_ctpr_mask = 0x00ffffc0,
378 .mmu_cxr_mask = 0x000000ff,
379 .mmu_sfsr_mask = 0x00016fff,
380 .mmu_trcr_mask = 0x00ffffff,
381 .nwindows = 8,
382 .features = CPU_DEFAULT_FEATURES,
383 },
384 {
385 .name = "Fujitsu-MB86907",
386 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
387 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
388 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
389 .mmu_bm = 0x00004000,
390 .mmu_ctpr_mask = 0xffffffc0,
391 .mmu_cxr_mask = 0x000000ff,
392 .mmu_sfsr_mask = 0x00016fff,
393 .mmu_trcr_mask = 0xffffffff,
394 .nwindows = 8,
395 .features = CPU_DEFAULT_FEATURES,
396 },
397 {
398 .name = "TI-MicroSparc-I",
399 .iu_version = 0x41000000,
400 .fpu_version = 4 << FSR_VER_SHIFT,
401 .mmu_version = 0x41000000,
402 .mmu_bm = 0x00004000,
403 .mmu_ctpr_mask = 0x007ffff0,
404 .mmu_cxr_mask = 0x0000003f,
405 .mmu_sfsr_mask = 0x00016fff,
406 .mmu_trcr_mask = 0x0000003f,
407 .nwindows = 7,
408 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
409 },
410 {
411 .name = "TI-MicroSparc-II",
412 .iu_version = 0x42000000,
413 .fpu_version = 4 << FSR_VER_SHIFT,
414 .mmu_version = 0x02000000,
415 .mmu_bm = 0x00004000,
416 .mmu_ctpr_mask = 0x00ffffc0,
417 .mmu_cxr_mask = 0x000000ff,
418 .mmu_sfsr_mask = 0x00016fff,
419 .mmu_trcr_mask = 0x00ffffff,
420 .nwindows = 8,
421 .features = CPU_DEFAULT_FEATURES,
422 },
423 {
424 .name = "TI-MicroSparc-IIep",
425 .iu_version = 0x42000000,
426 .fpu_version = 4 << FSR_VER_SHIFT,
427 .mmu_version = 0x04000000,
428 .mmu_bm = 0x00004000,
429 .mmu_ctpr_mask = 0x00ffffc0,
430 .mmu_cxr_mask = 0x000000ff,
431 .mmu_sfsr_mask = 0x00016bff,
432 .mmu_trcr_mask = 0x00ffffff,
433 .nwindows = 8,
434 .features = CPU_DEFAULT_FEATURES,
435 },
436 {
437 .name = "TI-SuperSparc-40", /* STP1020NPGA */
438 .iu_version = 0x41000000, /* SuperSPARC 2.x */
439 .fpu_version = 0 << FSR_VER_SHIFT,
440 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
441 .mmu_bm = 0x00002000,
442 .mmu_ctpr_mask = 0xffffffc0,
443 .mmu_cxr_mask = 0x0000ffff,
444 .mmu_sfsr_mask = 0xffffffff,
445 .mmu_trcr_mask = 0xffffffff,
446 .nwindows = 8,
447 .features = CPU_DEFAULT_FEATURES,
448 },
449 {
450 .name = "TI-SuperSparc-50", /* STP1020PGA */
451 .iu_version = 0x40000000, /* SuperSPARC 3.x */
452 .fpu_version = 0 << FSR_VER_SHIFT,
453 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
454 .mmu_bm = 0x00002000,
455 .mmu_ctpr_mask = 0xffffffc0,
456 .mmu_cxr_mask = 0x0000ffff,
457 .mmu_sfsr_mask = 0xffffffff,
458 .mmu_trcr_mask = 0xffffffff,
459 .nwindows = 8,
460 .features = CPU_DEFAULT_FEATURES,
461 },
462 {
463 .name = "TI-SuperSparc-51",
464 .iu_version = 0x40000000, /* SuperSPARC 3.x */
465 .fpu_version = 0 << FSR_VER_SHIFT,
466 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
467 .mmu_bm = 0x00002000,
468 .mmu_ctpr_mask = 0xffffffc0,
469 .mmu_cxr_mask = 0x0000ffff,
470 .mmu_sfsr_mask = 0xffffffff,
471 .mmu_trcr_mask = 0xffffffff,
472 .mxcc_version = 0x00000104,
473 .nwindows = 8,
474 .features = CPU_DEFAULT_FEATURES,
475 },
476 {
477 .name = "TI-SuperSparc-60", /* STP1020APGA */
478 .iu_version = 0x40000000, /* SuperSPARC 3.x */
479 .fpu_version = 0 << FSR_VER_SHIFT,
480 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
481 .mmu_bm = 0x00002000,
482 .mmu_ctpr_mask = 0xffffffc0,
483 .mmu_cxr_mask = 0x0000ffff,
484 .mmu_sfsr_mask = 0xffffffff,
485 .mmu_trcr_mask = 0xffffffff,
486 .nwindows = 8,
487 .features = CPU_DEFAULT_FEATURES,
488 },
489 {
490 .name = "TI-SuperSparc-61",
491 .iu_version = 0x44000000, /* SuperSPARC 3.x */
492 .fpu_version = 0 << FSR_VER_SHIFT,
493 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
494 .mmu_bm = 0x00002000,
495 .mmu_ctpr_mask = 0xffffffc0,
496 .mmu_cxr_mask = 0x0000ffff,
497 .mmu_sfsr_mask = 0xffffffff,
498 .mmu_trcr_mask = 0xffffffff,
499 .mxcc_version = 0x00000104,
500 .nwindows = 8,
501 .features = CPU_DEFAULT_FEATURES,
502 },
503 {
504 .name = "TI-SuperSparc-II",
505 .iu_version = 0x40000000, /* SuperSPARC II 1.x */
506 .fpu_version = 0 << FSR_VER_SHIFT,
507 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
508 .mmu_bm = 0x00002000,
509 .mmu_ctpr_mask = 0xffffffc0,
510 .mmu_cxr_mask = 0x0000ffff,
511 .mmu_sfsr_mask = 0xffffffff,
512 .mmu_trcr_mask = 0xffffffff,
513 .mxcc_version = 0x00000104,
514 .nwindows = 8,
515 .features = CPU_DEFAULT_FEATURES,
516 },
517 {
518 .name = "LEON2",
519 .iu_version = 0xf2000000,
520 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
521 .mmu_version = 0xf2000000,
522 .mmu_bm = 0x00004000,
523 .mmu_ctpr_mask = 0x007ffff0,
524 .mmu_cxr_mask = 0x0000003f,
525 .mmu_sfsr_mask = 0xffffffff,
526 .mmu_trcr_mask = 0xffffffff,
527 .nwindows = 8,
528 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
529 },
530 {
531 .name = "LEON3",
532 .iu_version = 0xf3000000,
533 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
534 .mmu_version = 0xf3000000,
535 .mmu_bm = 0x00000000,
536 .mmu_ctpr_mask = 0xfffffffc,
537 .mmu_cxr_mask = 0x000000ff,
538 .mmu_sfsr_mask = 0xffffffff,
539 .mmu_trcr_mask = 0xffffffff,
540 .nwindows = 8,
541 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
542 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
543 CPU_FEATURE_CASA,
544 },
545 #endif
546 };
547
548 /* This must match sparc_cpu_properties[]. */
549 static const char * const feature_name[] = {
550 [CPU_FEATURE_BIT_FLOAT128] = "float128",
551 #ifdef TARGET_SPARC64
552 [CPU_FEATURE_BIT_CMT] = "cmt",
553 [CPU_FEATURE_BIT_GL] = "gl",
554 [CPU_FEATURE_BIT_HYPV] = "hypv",
555 [CPU_FEATURE_BIT_VIS1] = "vis1",
556 [CPU_FEATURE_BIT_VIS2] = "vis2",
557 [CPU_FEATURE_BIT_FMAF] = "fmaf",
558 [CPU_FEATURE_BIT_VIS3] = "vis3",
559 [CPU_FEATURE_BIT_IMA] = "ima",
560 [CPU_FEATURE_BIT_VIS4] = "vis4",
561 #else
562 [CPU_FEATURE_BIT_MUL] = "mul",
563 [CPU_FEATURE_BIT_DIV] = "div",
564 [CPU_FEATURE_BIT_FSMULD] = "fsmuld",
565 #endif
566 };
567
print_features(uint32_t features,const char * prefix)568 static void print_features(uint32_t features, const char *prefix)
569 {
570 unsigned int i;
571
572 for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
573 if (feature_name[i] && (features & (1 << i))) {
574 if (prefix) {
575 qemu_printf("%s", prefix);
576 }
577 qemu_printf("%s ", feature_name[i]);
578 }
579 }
580 }
581
sparc_cpu_list(void)582 static void sparc_cpu_list(void)
583 {
584 unsigned int i;
585
586 qemu_printf("Available CPU types:\n");
587 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
588 qemu_printf(" %-20s (IU " TARGET_FMT_lx
589 " FPU %08x MMU %08x NWINS %d) ",
590 sparc_defs[i].name,
591 sparc_defs[i].iu_version,
592 sparc_defs[i].fpu_version,
593 sparc_defs[i].mmu_version,
594 sparc_defs[i].nwindows);
595 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
596 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
597 qemu_printf("\n");
598 }
599 qemu_printf("Default CPU feature flags (use '-' to remove): ");
600 print_features(CPU_DEFAULT_FEATURES, NULL);
601 qemu_printf("\n");
602 qemu_printf("Available CPU feature flags (use '+' to add): ");
603 print_features(~CPU_DEFAULT_FEATURES, NULL);
604 qemu_printf("\n");
605 qemu_printf("Numerical features (use '=' to set): iu_version "
606 "fpu_version mmu_version nwindows\n");
607 }
608
cpu_print_cc(FILE * f,uint32_t cc)609 static void cpu_print_cc(FILE *f, uint32_t cc)
610 {
611 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
612 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
613 cc & PSR_CARRY ? 'C' : '-');
614 }
615
616 #ifdef TARGET_SPARC64
617 #define REGS_PER_LINE 4
618 #else
619 #define REGS_PER_LINE 8
620 #endif
621
sparc_cpu_dump_state(CPUState * cs,FILE * f,int flags)622 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
623 {
624 CPUSPARCState *env = cpu_env(cs);
625 int i, x;
626
627 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
628 env->npc);
629
630 for (i = 0; i < 8; i++) {
631 if (i % REGS_PER_LINE == 0) {
632 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
633 }
634 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
635 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
636 qemu_fprintf(f, "\n");
637 }
638 }
639 for (x = 0; x < 3; x++) {
640 for (i = 0; i < 8; i++) {
641 if (i % REGS_PER_LINE == 0) {
642 qemu_fprintf(f, "%%%c%d-%d: ",
643 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
644 i, i + REGS_PER_LINE - 1);
645 }
646 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
647 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
648 qemu_fprintf(f, "\n");
649 }
650 }
651 }
652
653 if (flags & CPU_DUMP_FPU) {
654 for (i = 0; i < TARGET_DPREGS; i++) {
655 if ((i & 3) == 0) {
656 qemu_fprintf(f, "%%f%02d: ", i * 2);
657 }
658 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
659 if ((i & 3) == 3) {
660 qemu_fprintf(f, "\n");
661 }
662 }
663 }
664
665 #ifdef TARGET_SPARC64
666 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
667 (unsigned)cpu_get_ccr(env));
668 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
669 qemu_fprintf(f, " xcc: ");
670 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
671 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
672 env->psrpil, env->gl);
673 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
674 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
675 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
676 "cleanwin: %d cwp: %d\n",
677 env->cansave, env->canrestore, env->otherwin, env->wstate,
678 env->cleanwin, env->nwindows - 1 - env->cwp);
679 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n",
680 cpu_get_fsr(env), env->y, env->fprs);
681
682 #else
683 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
684 cpu_print_cc(f, cpu_get_psr(env));
685 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
686 env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
687 env->wim);
688 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
689 cpu_get_fsr(env), env->y);
690 #endif
691 qemu_fprintf(f, "\n");
692 }
693
sparc_cpu_set_pc(CPUState * cs,vaddr value)694 static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
695 {
696 SPARCCPU *cpu = SPARC_CPU(cs);
697
698 cpu->env.pc = value;
699 cpu->env.npc = value + 4;
700 }
701
sparc_cpu_get_pc(CPUState * cs)702 static vaddr sparc_cpu_get_pc(CPUState *cs)
703 {
704 SPARCCPU *cpu = SPARC_CPU(cs);
705
706 return cpu->env.pc;
707 }
708
sparc_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)709 static void sparc_cpu_synchronize_from_tb(CPUState *cs,
710 const TranslationBlock *tb)
711 {
712 SPARCCPU *cpu = SPARC_CPU(cs);
713
714 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
715 cpu->env.pc = tb->pc;
716 cpu->env.npc = tb->cs_base;
717 }
718
sparc_get_tb_cpu_state(CPUState * cs)719 static TCGTBCPUState sparc_get_tb_cpu_state(CPUState *cs)
720 {
721 CPUSPARCState *env = cpu_env(cs);
722 uint32_t flags = cpu_mmu_index(cs, false);
723
724 #ifndef CONFIG_USER_ONLY
725 if (cpu_supervisor_mode(env)) {
726 flags |= TB_FLAG_SUPER;
727 }
728 #endif
729 #ifdef TARGET_SPARC64
730 #ifndef CONFIG_USER_ONLY
731 if (cpu_hypervisor_mode(env)) {
732 flags |= TB_FLAG_HYPER;
733 }
734 #endif
735 if (env->pstate & PS_AM) {
736 flags |= TB_FLAG_AM_ENABLED;
737 }
738 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) {
739 flags |= TB_FLAG_FPU_ENABLED;
740 }
741 flags |= env->asi << TB_FLAG_ASI_SHIFT;
742 #else
743 if (env->psref) {
744 flags |= TB_FLAG_FPU_ENABLED;
745 }
746 #ifndef CONFIG_USER_ONLY
747 if (env->fsr_qne) {
748 flags |= TB_FLAG_FSR_QNE;
749 }
750 #endif /* !CONFIG_USER_ONLY */
751 #endif /* TARGET_SPARC64 */
752
753 return (TCGTBCPUState){
754 .pc = env->pc,
755 .flags = flags,
756 .cs_base = env->npc,
757 };
758 }
759
sparc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)760 static void sparc_restore_state_to_opc(CPUState *cs,
761 const TranslationBlock *tb,
762 const uint64_t *data)
763 {
764 CPUSPARCState *env = cpu_env(cs);
765 target_ulong pc = data[0];
766 target_ulong npc = data[1];
767
768 env->pc = pc;
769 if (npc == DYNAMIC_PC) {
770 /* dynamic NPC: already stored */
771 } else if (npc & JUMP_PC) {
772 /* jump PC: use 'cond' and the jump targets of the translation */
773 if (env->cond) {
774 env->npc = npc & ~3;
775 } else {
776 env->npc = pc + 4;
777 }
778 } else {
779 env->npc = npc;
780 }
781 }
782
783 #ifndef CONFIG_USER_ONLY
sparc_cpu_has_work(CPUState * cs)784 static bool sparc_cpu_has_work(CPUState *cs)
785 {
786 return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
787 cpu_interrupts_enabled(cpu_env(cs));
788 }
789 #endif /* !CONFIG_USER_ONLY */
790
sparc_cpu_mmu_index(CPUState * cs,bool ifetch)791 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
792 {
793 CPUSPARCState *env = cpu_env(cs);
794
795 #ifndef TARGET_SPARC64
796 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
797 return MMU_PHYS_IDX;
798 } else {
799 return env->psrs;
800 }
801 #else
802 /* IMMU or DMMU disabled. */
803 if (ifetch
804 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
805 : (env->lsu & DMMU_E) == 0) {
806 return MMU_PHYS_IDX;
807 } else if (cpu_hypervisor_mode(env)) {
808 return MMU_PHYS_IDX;
809 } else if (env->tl > 0) {
810 return MMU_NUCLEUS_IDX;
811 } else if (cpu_supervisor_mode(env)) {
812 return MMU_KERNEL_IDX;
813 } else {
814 return MMU_USER_IDX;
815 }
816 #endif
817 }
818
sparc_cpu_type_name(const char * cpu_model)819 static char *sparc_cpu_type_name(const char *cpu_model)
820 {
821 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
822 char *s = name;
823
824 /* SPARC cpu model names happen to have whitespaces,
825 * as type names shouldn't have spaces replace them with '-'
826 */
827 while ((s = strchr(s, ' '))) {
828 *s = '-';
829 }
830
831 return name;
832 }
833
sparc_cpu_class_by_name(const char * cpu_model)834 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
835 {
836 ObjectClass *oc;
837 char *typename;
838
839 typename = sparc_cpu_type_name(cpu_model);
840
841 /* Fix up legacy names with '+' in it */
842 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) {
843 g_free(typename);
844 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus"));
845 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) {
846 g_free(typename);
847 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus"));
848 }
849
850 oc = object_class_by_name(typename);
851 g_free(typename);
852 return oc;
853 }
854
sparc_cpu_realizefn(DeviceState * dev,Error ** errp)855 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
856 {
857 CPUState *cs = CPU(dev);
858 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
859 Error *local_err = NULL;
860 CPUSPARCState *env = cpu_env(cs);
861
862 #if defined(CONFIG_USER_ONLY)
863 /* We are emulating the kernel, which will trap and emulate float128. */
864 env->def.features |= CPU_FEATURE_FLOAT128;
865 #endif
866
867 env->version = env->def.iu_version;
868 env->nwindows = env->def.nwindows;
869 #if !defined(TARGET_SPARC64)
870 env->mmuregs[0] |= env->def.mmu_version;
871 cpu_sparc_set_id(env, 0);
872 env->mxccregs[7] |= env->def.mxcc_version;
873 #else
874 env->mmu_version = env->def.mmu_version;
875 env->maxtl = env->def.maxtl;
876 env->version |= env->def.maxtl << 8;
877 env->version |= env->def.nwindows - 1;
878 #endif
879
880 /*
881 * Prefer SNaN over QNaN, order B then A. It's OK to do this in realize
882 * rather than reset, because fp_status is after 'end_reset_fields' in
883 * the CPU state struct so it won't get zeroed on reset.
884 */
885 set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
886 /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
887 set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
888 /* For inf * 0 + NaN, return the input NaN */
889 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
890 /* Default NaN value: sign bit clear, all frac bits set */
891 set_float_default_nan_pattern(0b01111111, &env->fp_status);
892
893 cpu_exec_realizefn(cs, &local_err);
894 if (local_err != NULL) {
895 error_propagate(errp, local_err);
896 return;
897 }
898
899 qemu_init_vcpu(cs);
900
901 scc->parent_realize(dev, errp);
902 }
903
sparc_cpu_initfn(Object * obj)904 static void sparc_cpu_initfn(Object *obj)
905 {
906 SPARCCPU *cpu = SPARC_CPU(obj);
907 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
908 CPUSPARCState *env = &cpu->env;
909
910 if (scc->cpu_def) {
911 env->def = *scc->cpu_def;
912 }
913 }
914
sparc_get_nwindows(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)915 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
916 void *opaque, Error **errp)
917 {
918 SPARCCPU *cpu = SPARC_CPU(obj);
919 int64_t value = cpu->env.def.nwindows;
920
921 visit_type_int(v, name, &value, errp);
922 }
923
sparc_set_nwindows(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)924 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
925 void *opaque, Error **errp)
926 {
927 const int64_t min = MIN_NWINDOWS;
928 const int64_t max = MAX_NWINDOWS;
929 SPARCCPU *cpu = SPARC_CPU(obj);
930 int64_t value;
931
932 if (!visit_type_int(v, name, &value, errp)) {
933 return;
934 }
935
936 if (value < min || value > max) {
937 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
938 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
939 object_get_typename(obj), name ? name : "null",
940 value, min, max);
941 return;
942 }
943 cpu->env.def.nwindows = value;
944 }
945
946 static const PropertyInfo qdev_prop_nwindows = {
947 .type = "int",
948 .description = "Number of register windows",
949 .get = sparc_get_nwindows,
950 .set = sparc_set_nwindows,
951 };
952
953 /* This must match feature_name[]. */
954 static const Property sparc_cpu_properties[] = {
955 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
956 CPU_FEATURE_BIT_FLOAT128, false),
957 #ifdef TARGET_SPARC64
958 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features,
959 CPU_FEATURE_BIT_CMT, false),
960 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features,
961 CPU_FEATURE_BIT_GL, false),
962 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features,
963 CPU_FEATURE_BIT_HYPV, false),
964 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
965 CPU_FEATURE_BIT_VIS1, false),
966 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
967 CPU_FEATURE_BIT_VIS2, false),
968 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features,
969 CPU_FEATURE_BIT_FMAF, false),
970 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features,
971 CPU_FEATURE_BIT_VIS3, false),
972 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features,
973 CPU_FEATURE_BIT_IMA, false),
974 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features,
975 CPU_FEATURE_BIT_VIS4, false),
976 #else
977 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
978 CPU_FEATURE_BIT_MUL, false),
979 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
980 CPU_FEATURE_BIT_DIV, false),
981 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features,
982 CPU_FEATURE_BIT_FSMULD, false),
983 #endif
984 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
985 qdev_prop_uint64, target_ulong),
986 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
987 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
988 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
989 qdev_prop_nwindows, uint32_t),
990 };
991
992 #ifndef CONFIG_USER_ONLY
993 #include "hw/core/sysemu-cpu-ops.h"
994
995 static const struct SysemuCPUOps sparc_sysemu_ops = {
996 .has_work = sparc_cpu_has_work,
997 .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
998 .legacy_vmsd = &vmstate_sparc_cpu,
999 };
1000 #endif
1001
1002 #ifdef CONFIG_TCG
1003 #include "accel/tcg/cpu-ops.h"
1004
1005 #ifndef CONFIG_USER_ONLY
sparc_pointer_wrap(CPUState * cs,int mmu_idx,vaddr result,vaddr base)1006 static vaddr sparc_pointer_wrap(CPUState *cs, int mmu_idx,
1007 vaddr result, vaddr base)
1008 {
1009 #ifdef TARGET_SPARC64
1010 return cpu_env(cs)->pstate & PS_AM ? (uint32_t)result : result;
1011 #else
1012 return (uint32_t)result;
1013 #endif
1014 }
1015 #endif
1016
1017 static const TCGCPUOps sparc_tcg_ops = {
1018 /*
1019 * From Oracle SPARC Architecture 2015:
1020 *
1021 * Compatibility notes: The PSO memory model described in SPARC V8 and
1022 * SPARC V9 compatibility architecture specifications was never
1023 * implemented in a SPARC V9 implementation and is not included in the
1024 * Oracle SPARC Architecture specification.
1025 *
1026 * The RMO memory model described in the SPARC V9 specification was
1027 * implemented in some non-Sun SPARC V9 implementations, but is not
1028 * directly supported in Oracle SPARC Architecture 2015 implementations.
1029 *
1030 * Therefore always use TSO in QEMU.
1031 *
1032 * D.5 Specification of Partial Store Order (PSO)
1033 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
1034 *
1035 * D.6 Specification of Total Store Order (TSO)
1036 * ... PSO with the additional requirement that all [stores] are followed
1037 * by an implied MEMBAR #StoreStore.
1038 */
1039 .guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST,
1040 .mttcg_supported = true,
1041
1042 .initialize = sparc_tcg_init,
1043 .translate_code = sparc_translate_code,
1044 .get_tb_cpu_state = sparc_get_tb_cpu_state,
1045 .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
1046 .restore_state_to_opc = sparc_restore_state_to_opc,
1047 .mmu_index = sparc_cpu_mmu_index,
1048
1049 #ifndef CONFIG_USER_ONLY
1050 .tlb_fill = sparc_cpu_tlb_fill,
1051 .pointer_wrap = sparc_pointer_wrap,
1052 .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
1053 .cpu_exec_halt = sparc_cpu_has_work,
1054 .cpu_exec_reset = cpu_reset,
1055 .do_interrupt = sparc_cpu_do_interrupt,
1056 .do_transaction_failed = sparc_cpu_do_transaction_failed,
1057 .do_unaligned_access = sparc_cpu_do_unaligned_access,
1058 #endif /* !CONFIG_USER_ONLY */
1059 };
1060 #endif /* CONFIG_TCG */
1061
sparc_cpu_class_init(ObjectClass * oc,const void * data)1062 static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
1063 {
1064 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
1065 CPUClass *cc = CPU_CLASS(oc);
1066 DeviceClass *dc = DEVICE_CLASS(oc);
1067 ResettableClass *rc = RESETTABLE_CLASS(oc);
1068
1069 device_class_set_parent_realize(dc, sparc_cpu_realizefn,
1070 &scc->parent_realize);
1071 device_class_set_props(dc, sparc_cpu_properties);
1072
1073 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
1074 &scc->parent_phases);
1075
1076 cc->class_by_name = sparc_cpu_class_by_name;
1077 cc->list_cpus = sparc_cpu_list,
1078 cc->parse_features = sparc_cpu_parse_features;
1079 cc->dump_state = sparc_cpu_dump_state;
1080 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
1081 cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
1082 #endif
1083 cc->set_pc = sparc_cpu_set_pc;
1084 cc->get_pc = sparc_cpu_get_pc;
1085 cc->gdb_read_register = sparc_cpu_gdb_read_register;
1086 cc->gdb_write_register = sparc_cpu_gdb_write_register;
1087 #ifndef CONFIG_USER_ONLY
1088 cc->sysemu_ops = &sparc_sysemu_ops;
1089 #endif
1090 cc->disas_set_info = cpu_sparc_disas_set_info;
1091
1092 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1093 cc->gdb_num_core_regs = 86;
1094 #else
1095 cc->gdb_num_core_regs = 72;
1096 #endif
1097 cc->tcg_ops = &sparc_tcg_ops;
1098 }
1099
1100 static const TypeInfo sparc_cpu_type_info = {
1101 .name = TYPE_SPARC_CPU,
1102 .parent = TYPE_CPU,
1103 .instance_size = sizeof(SPARCCPU),
1104 .instance_align = __alignof(SPARCCPU),
1105 .instance_init = sparc_cpu_initfn,
1106 .abstract = true,
1107 .class_size = sizeof(SPARCCPUClass),
1108 .class_init = sparc_cpu_class_init,
1109 };
1110
sparc_cpu_cpudef_class_init(ObjectClass * oc,const void * data)1111 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, const void *data)
1112 {
1113 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
1114 scc->cpu_def = data;
1115 }
1116
sparc_register_cpudef_type(const struct sparc_def_t * def)1117 static void sparc_register_cpudef_type(const struct sparc_def_t *def)
1118 {
1119 char *typename = sparc_cpu_type_name(def->name);
1120 TypeInfo ti = {
1121 .name = typename,
1122 .parent = TYPE_SPARC_CPU,
1123 .class_init = sparc_cpu_cpudef_class_init,
1124 .class_data = def,
1125 };
1126
1127 type_register_static(&ti);
1128 g_free(typename);
1129 }
1130
sparc_cpu_register_types(void)1131 static void sparc_cpu_register_types(void)
1132 {
1133 int i;
1134
1135 type_register_static(&sparc_cpu_type_info);
1136 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1137 sparc_register_cpudef_type(&sparc_defs[i]);
1138 }
1139 }
1140
1141 type_init(sparc_cpu_register_types)
1142