1 /*
2 * sPAPR CPU core device, acts as container of CPU thread devices.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "hw/cpu/core.h"
12 #include "hw/ppc/spapr_cpu_core.h"
13 #include "hw/qdev-properties.h"
14 #include "migration/vmstate.h"
15 #include "target/ppc/cpu.h"
16 #include "hw/ppc/spapr.h"
17 #include "qapi/error.h"
18 #include "system/cpus.h"
19 #include "system/kvm.h"
20 #include "target/ppc/kvm_ppc.h"
21 #include "hw/ppc/ppc.h"
22 #include "target/ppc/mmu-hash64.h"
23 #include "target/ppc/power8-pmu.h"
24 #include "system/numa.h"
25 #include "system/reset.h"
26 #include "system/hw_accel.h"
27 #include "qemu/error-report.h"
28
spapr_reset_vcpu(PowerPCCPU * cpu)29 static void spapr_reset_vcpu(PowerPCCPU *cpu)
30 {
31 CPUState *cs = CPU(cpu);
32 CPUPPCState *env = &cpu->env;
33 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
34 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
35 target_ulong lpcr;
36 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
37
38 cpu_reset(cs);
39
40 env->quiesced = true; /* set "RTAS stopped" state. */
41 ppc_maybe_interrupt(env);
42
43 /*
44 * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
45 * as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial
46 * Register Values". This can also be found in "LoPAPR 1.1" "C.9.2.1
47 * Initial Register Values".
48 */
49 env->msr &= ~(1ULL << MSR_SF);
50 env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
51
52 env->spr[SPR_HIOR] = 0;
53
54 lpcr = env->spr[SPR_LPCR];
55
56 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
57 * under KVM, the actual HW LPCR will be set differently by KVM itself,
58 * the settings below ensure proper operations with TCG in absence of
59 * a real hypervisor.
60 *
61 * Disable Power-saving mode Exit Cause exceptions for the CPU, so
62 * we don't get spurious wakups before an RTAS start-cpu call.
63 * For the same reason, set PSSCR_EC.
64 */
65 lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
66 lpcr |= LPCR_LPES0 | LPCR_LPES1;
67 env->spr[SPR_PSSCR] |= PSSCR_EC;
68
69 ppc_store_lpcr(cpu, lpcr);
70
71 /* Set a full AMOR so guest can use the AMR as it sees fit */
72 env->spr[SPR_AMOR] = 0xffffffffffffffffull;
73
74 spapr_cpu->vpa_addr = 0;
75 spapr_cpu->slb_shadow_addr = 0;
76 spapr_cpu->slb_shadow_size = 0;
77 spapr_cpu->dtl_addr = 0;
78 spapr_cpu->dtl_size = 0;
79
80 spapr_caps_cpu_apply(spapr, cpu);
81
82 kvm_check_mmu(cpu, &error_fatal);
83
84 cpu_ppc_tb_reset(env);
85
86 spapr_irq_cpu_intc_reset(spapr, cpu);
87 }
88
spapr_cpu_set_entry_state(PowerPCCPU * cpu,target_ulong nip,target_ulong r1,target_ulong r3,target_ulong r4)89 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
90 target_ulong r1, target_ulong r3,
91 target_ulong r4)
92 {
93 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
94 CPUPPCState *env = &cpu->env;
95
96 env->nip = nip;
97 env->gpr[1] = r1;
98 env->gpr[3] = r3;
99 env->gpr[4] = r4;
100 kvmppc_set_reg_ppc_online(cpu, 1);
101 CPU(cpu)->halted = 0;
102 /* Enable Power-saving mode Exit Cause exceptions */
103 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
104
105 env->quiesced = false; /* clear "RTAS stopped" state. */
106 ppc_maybe_interrupt(env);
107 }
108
109 /*
110 * Return the sPAPR CPU core type for @model which essentially is the CPU
111 * model specified with -cpu cmdline option.
112 */
spapr_get_cpu_core_type(const char * cpu_type)113 const char *spapr_get_cpu_core_type(const char *cpu_type)
114 {
115 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
116 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
117 len, cpu_type);
118 ObjectClass *oc = object_class_by_name(core_type);
119
120 g_free(core_type);
121 if (!oc) {
122 return NULL;
123 }
124
125 return object_class_get_name(oc);
126 }
127
slb_shadow_needed(void * opaque)128 static bool slb_shadow_needed(void *opaque)
129 {
130 SpaprCpuState *spapr_cpu = opaque;
131
132 return spapr_cpu->slb_shadow_addr != 0;
133 }
134
135 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
136 .name = "spapr_cpu/vpa/slb_shadow",
137 .version_id = 1,
138 .minimum_version_id = 1,
139 .needed = slb_shadow_needed,
140 .fields = (const VMStateField[]) {
141 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
142 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
143 VMSTATE_END_OF_LIST()
144 }
145 };
146
dtl_needed(void * opaque)147 static bool dtl_needed(void *opaque)
148 {
149 SpaprCpuState *spapr_cpu = opaque;
150
151 return spapr_cpu->dtl_addr != 0;
152 }
153
154 static const VMStateDescription vmstate_spapr_cpu_dtl = {
155 .name = "spapr_cpu/vpa/dtl",
156 .version_id = 1,
157 .minimum_version_id = 1,
158 .needed = dtl_needed,
159 .fields = (const VMStateField[]) {
160 VMSTATE_UINT64(dtl_addr, SpaprCpuState),
161 VMSTATE_UINT64(dtl_size, SpaprCpuState),
162 VMSTATE_END_OF_LIST()
163 }
164 };
165
vpa_needed(void * opaque)166 static bool vpa_needed(void *opaque)
167 {
168 SpaprCpuState *spapr_cpu = opaque;
169
170 return spapr_cpu->vpa_addr != 0;
171 }
172
173 static const VMStateDescription vmstate_spapr_cpu_vpa = {
174 .name = "spapr_cpu/vpa",
175 .version_id = 1,
176 .minimum_version_id = 1,
177 .needed = vpa_needed,
178 .fields = (const VMStateField[]) {
179 VMSTATE_UINT64(vpa_addr, SpaprCpuState),
180 VMSTATE_END_OF_LIST()
181 },
182 .subsections = (const VMStateDescription * const []) {
183 &vmstate_spapr_cpu_slb_shadow,
184 &vmstate_spapr_cpu_dtl,
185 NULL
186 }
187 };
188
189 static const VMStateDescription vmstate_spapr_cpu_state = {
190 .name = "spapr_cpu",
191 .version_id = 1,
192 .minimum_version_id = 1,
193 .fields = (const VMStateField[]) {
194 VMSTATE_END_OF_LIST()
195 },
196 .subsections = (const VMStateDescription * const []) {
197 &vmstate_spapr_cpu_vpa,
198 NULL
199 }
200 };
201
spapr_unrealize_vcpu(PowerPCCPU * cpu,SpaprCpuCore * sc)202 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
203 {
204 CPUPPCState *env = &cpu->env;
205
206 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
207 spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
208 cpu_ppc_tb_free(env);
209 qdev_unrealize(DEVICE(cpu));
210 }
211
212 /*
213 * Called when CPUs are hot-plugged.
214 */
spapr_cpu_core_reset(DeviceState * dev)215 static void spapr_cpu_core_reset(DeviceState *dev)
216 {
217 CPUCore *cc = CPU_CORE(dev);
218 SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
219 int i;
220
221 for (i = 0; i < cc->nr_threads; i++) {
222 spapr_reset_vcpu(sc->threads[i]);
223 }
224 }
225
226 /*
227 * Called by the machine reset.
228 */
spapr_cpu_core_reset_handler(void * opaque)229 static void spapr_cpu_core_reset_handler(void *opaque)
230 {
231 spapr_cpu_core_reset(opaque);
232 }
233
spapr_delete_vcpu(PowerPCCPU * cpu)234 static void spapr_delete_vcpu(PowerPCCPU *cpu)
235 {
236 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
237
238 cpu->machine_data = NULL;
239 g_free(spapr_cpu);
240 object_unparent(OBJECT(cpu));
241 }
242
spapr_cpu_core_unrealize(DeviceState * dev)243 static void spapr_cpu_core_unrealize(DeviceState *dev)
244 {
245 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
246 CPUCore *cc = CPU_CORE(dev);
247 int i;
248
249 for (i = 0; i < cc->nr_threads; i++) {
250 if (sc->threads[i]) {
251 /*
252 * Since this we can get here from the error path of
253 * spapr_cpu_core_realize(), make sure we only unrealize
254 * vCPUs that have already been realized.
255 */
256 if (qdev_is_realized(DEVICE(sc->threads[i]))) {
257 spapr_unrealize_vcpu(sc->threads[i], sc);
258 }
259 spapr_delete_vcpu(sc->threads[i]);
260 }
261 }
262 g_free(sc->threads);
263 qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
264 }
265
spapr_realize_vcpu(PowerPCCPU * cpu,SpaprMachineState * spapr,SpaprCpuCore * sc,int thread_index,Error ** errp)266 static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
267 SpaprCpuCore *sc, int thread_index, Error **errp)
268 {
269 CPUPPCState *env = &cpu->env;
270 CPUState *cs = CPU(cpu);
271
272 if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
273 return false;
274 }
275
276 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
277 kvmppc_set_papr(cpu);
278
279 env->spr_cb[SPR_PIR].default_value = cs->cpu_index;
280 env->spr_cb[SPR_TIR].default_value = thread_index;
281
282 env->spr_cb[SPR_HASHPKEYR].default_value = spapr->hashpkey_val;
283
284 cpu_ppc_set_1lpar(cpu);
285
286 /* Set time-base frequency to 512 MHz. vhyp must be set first. */
287 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
288
289 if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
290 qdev_unrealize(DEVICE(cpu));
291 return false;
292 }
293
294 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
295 cpu->machine_data);
296 return true;
297 }
298
spapr_create_vcpu(SpaprCpuCore * sc,int i,Error ** errp)299 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
300 {
301 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
302 CPUCore *cc = CPU_CORE(sc);
303 g_autoptr(Object) obj = NULL;
304 g_autofree char *id = NULL;
305 CPUState *cs;
306 PowerPCCPU *cpu;
307 CPUPPCState *env;
308
309 obj = object_new(scc->cpu_type);
310
311 cs = CPU(obj);
312 cpu = POWERPC_CPU(obj);
313 env = &cpu->env;
314 /*
315 * All CPUs start halted. CPU0 is unhalted from the machine level reset code
316 * and the rest are explicitly started up by the guest using an RTAS call.
317 */
318 qdev_prop_set_bit(DEVICE(obj), "start-powered-off", true);
319 cs->cpu_index = cc->core_id + i;
320 if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
321 return NULL;
322 }
323
324 env->chip_index = sc->node_id;
325 env->core_index = cc->core_id;
326
327 cpu->node_id = sc->node_id;
328
329 id = g_strdup_printf("thread[%d]", i);
330 object_property_add_child(OBJECT(sc), id, obj);
331
332 cpu->machine_data = g_new0(SpaprCpuState, 1);
333
334 return cpu;
335 }
336
spapr_cpu_core_realize(DeviceState * dev,Error ** errp)337 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
338 {
339 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
340 * tries to add a sPAPR CPU core to a non-pseries machine.
341 */
342 SpaprMachineState *spapr =
343 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
344 TYPE_SPAPR_MACHINE);
345 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
346 CPUCore *cc = CPU_CORE(OBJECT(dev));
347 int i;
348
349 if (!spapr) {
350 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
351 return;
352 }
353
354 qemu_register_reset(spapr_cpu_core_reset_handler, sc);
355 sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
356 for (i = 0; i < cc->nr_threads; i++) {
357 PowerPCCPU *cpu;
358
359 cpu = spapr_create_vcpu(sc, i, errp);
360 sc->threads[i] = cpu;
361 if (cpu && cc->nr_threads > 1) {
362 cpu->env.has_smt_siblings = true;
363 }
364
365 if (!cpu || !spapr_realize_vcpu(cpu, spapr, sc, i, errp)) {
366 spapr_cpu_core_unrealize(dev);
367 return;
368 }
369 }
370 }
371
372 static const Property spapr_cpu_core_properties[] = {
373 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
374 };
375
spapr_cpu_core_class_init(ObjectClass * oc,const void * data)376 static void spapr_cpu_core_class_init(ObjectClass *oc, const void *data)
377 {
378 DeviceClass *dc = DEVICE_CLASS(oc);
379 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
380
381 dc->realize = spapr_cpu_core_realize;
382 dc->unrealize = spapr_cpu_core_unrealize;
383 device_class_set_legacy_reset(dc, spapr_cpu_core_reset);
384 device_class_set_props(dc, spapr_cpu_core_properties);
385 scc->cpu_type = data;
386 }
387
388 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
389 { \
390 .parent = TYPE_SPAPR_CPU_CORE, \
391 .class_data = POWERPC_CPU_TYPE_NAME(cpu_model), \
392 .class_init = spapr_cpu_core_class_init, \
393 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
394 }
395
396 static const TypeInfo spapr_cpu_core_type_infos[] = {
397 {
398 .name = TYPE_SPAPR_CPU_CORE,
399 .parent = TYPE_CPU_CORE,
400 .abstract = true,
401 .instance_size = sizeof(SpaprCpuCore),
402 .class_size = sizeof(SpaprCpuCoreClass),
403 },
404 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
405 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
406 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
407 DEFINE_SPAPR_CPU_CORE_TYPE("power5p_v2.1"),
408 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
409 DEFINE_SPAPR_CPU_CORE_TYPE("power7p_v2.1"),
410 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
411 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
412 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
413 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
414 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
415 DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
416 DEFINE_SPAPR_CPU_CORE_TYPE("power11_v2.0"),
417 #ifdef CONFIG_KVM
418 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
419 #endif
420 };
421
422 DEFINE_TYPES(spapr_cpu_core_type_infos)
423