1 /* 2 * OpenPOWER Palmetto BMC 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/arm/boot.h" 15 #include "hw/arm/aspeed.h" 16 #include "hw/arm/aspeed_soc.h" 17 #include "hw/arm/aspeed_eeprom.h" 18 #include "hw/block/flash.h" 19 #include "hw/i2c/i2c_mux_pca954x.h" 20 #include "hw/i2c/smbus_eeprom.h" 21 #include "hw/gpio/pca9552.h" 22 #include "hw/nvram/eeprom_at24c.h" 23 #include "hw/sensor/tmp105.h" 24 #include "hw/misc/led.h" 25 #include "hw/qdev-properties.h" 26 #include "system/block-backend.h" 27 #include "system/reset.h" 28 #include "hw/loader.h" 29 #include "qemu/error-report.h" 30 #include "qemu/datadir.h" 31 #include "qemu/units.h" 32 #include "hw/qdev-clock.h" 33 #include "system/system.h" 34 35 static struct arm_boot_info aspeed_board_binfo = { 36 .board_id = -1, /* device-tree-only board */ 37 }; 38 39 struct AspeedMachineState { 40 /* Private */ 41 MachineState parent_obj; 42 /* Public */ 43 44 AspeedSoCState *soc; 45 MemoryRegion boot_rom; 46 bool mmio_exec; 47 uint32_t uart_chosen; 48 char *fmc_model; 49 char *spi_model; 50 uint32_t hw_strap1; 51 }; 52 53 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ 54 #if HOST_LONG_BITS == 32 55 #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) 56 #else 57 #define ASPEED_RAM_SIZE(sz) (sz) 58 #endif 59 60 /* Palmetto hardware value: 0x120CE416 */ 61 #define PALMETTO_BMC_HW_STRAP1 ( \ 62 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ 63 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ 64 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 65 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 66 SCU_HW_STRAP_VGA_CLASS_CODE | \ 67 SCU_HW_STRAP_LPC_RESET_PIN | \ 68 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 69 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 70 SCU_HW_STRAP_SPI_WIDTH | \ 71 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 72 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 73 74 /* TODO: Find the actual hardware value */ 75 #define SUPERMICROX11_BMC_HW_STRAP1 ( \ 76 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 77 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ 78 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 79 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ 80 SCU_HW_STRAP_VGA_CLASS_CODE | \ 81 SCU_HW_STRAP_LPC_RESET_PIN | \ 82 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ 83 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 84 SCU_HW_STRAP_SPI_WIDTH | \ 85 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 86 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 87 88 /* TODO: Find the actual hardware value */ 89 #define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ 90 AST2500_HW_STRAP1_DEFAULTS | \ 91 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 92 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 93 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 94 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 95 SCU_HW_STRAP_SPI_WIDTH | \ 96 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) 97 98 /* AST2500 evb hardware value: 0xF100C2E6 */ 99 #define AST2500_EVB_HW_STRAP1 (( \ 100 AST2500_HW_STRAP1_DEFAULTS | \ 101 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 102 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 103 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 104 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 105 SCU_HW_STRAP_MAC1_RGMII | \ 106 SCU_HW_STRAP_MAC0_RGMII) & \ 107 ~SCU_HW_STRAP_2ND_BOOT_WDT) 108 109 /* Romulus hardware value: 0xF10AD206 */ 110 #define ROMULUS_BMC_HW_STRAP1 ( \ 111 AST2500_HW_STRAP1_DEFAULTS | \ 112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 114 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 116 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ 117 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) 118 119 /* Sonorapass hardware value: 0xF100D216 */ 120 #define SONORAPASS_BMC_HW_STRAP1 ( \ 121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 123 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 124 SCU_AST2500_HW_STRAP_RESERVED28 | \ 125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 126 SCU_HW_STRAP_VGA_CLASS_CODE | \ 127 SCU_HW_STRAP_LPC_RESET_PIN | \ 128 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 129 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 130 SCU_HW_STRAP_VGA_BIOS_ROM | \ 131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 132 SCU_AST2500_HW_STRAP_RESERVED1) 133 134 #define G220A_BMC_HW_STRAP1 ( \ 135 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 136 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 137 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 138 SCU_AST2500_HW_STRAP_RESERVED28 | \ 139 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 140 SCU_HW_STRAP_2ND_BOOT_WDT | \ 141 SCU_HW_STRAP_VGA_CLASS_CODE | \ 142 SCU_HW_STRAP_LPC_RESET_PIN | \ 143 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 144 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 145 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \ 146 SCU_AST2500_HW_STRAP_RESERVED1) 147 148 /* FP5280G2 hardware value: 0XF100D286 */ 149 #define FP5280G2_BMC_HW_STRAP1 ( \ 150 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ 151 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ 152 SCU_AST2500_HW_STRAP_UART_DEBUG | \ 153 SCU_AST2500_HW_STRAP_RESERVED28 | \ 154 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ 155 SCU_HW_STRAP_VGA_CLASS_CODE | \ 156 SCU_HW_STRAP_LPC_RESET_PIN | \ 157 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ 158 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 159 SCU_HW_STRAP_MAC1_RGMII | \ 160 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 161 SCU_AST2500_HW_STRAP_RESERVED1) 162 163 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ 164 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 165 166 /* Quanta-Q71l hardware value */ 167 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \ 168 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ 169 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ 170 SCU_AST2400_HW_STRAP_ACPI_DIS | \ 171 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ 172 SCU_HW_STRAP_VGA_CLASS_CODE | \ 173 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ 174 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ 175 SCU_HW_STRAP_SPI_WIDTH | \ 176 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ 177 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) 178 179 /* AST2600 evb hardware value */ 180 #define AST2600_EVB_HW_STRAP1 0x000000C0 181 #define AST2600_EVB_HW_STRAP2 0x00000003 182 183 #ifdef TARGET_AARCH64 184 /* AST2700 evb hardware value */ 185 /* SCU HW Strap1 */ 186 #define AST2700_EVB_HW_STRAP1 0x00000800 187 /* SCUIO HW Strap1 */ 188 #define AST2700_EVB_HW_STRAP2 0x00000700 189 #endif 190 191 /* Rainier hardware value: (QEMU prototype) */ 192 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) 193 #define RAINIER_BMC_HW_STRAP2 0x80000848 194 195 /* Fuji hardware value */ 196 #define FUJI_BMC_HW_STRAP1 0x00000000 197 #define FUJI_BMC_HW_STRAP2 0x00000000 198 199 /* Bletchley hardware value */ 200 /* TODO: Leave same as EVB for now. */ 201 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1 202 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2 203 204 /* Qualcomm DC-SCM hardware value */ 205 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000 206 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041 207 208 #define AST_SMP_MAILBOX_BASE 0x1e6e2180 209 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 210 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 211 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 212 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 213 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) 214 #define AST_SMP_MBOX_GOSIGN 0xabbaab00 215 aspeed_write_smpboot(ARMCPU * cpu,const struct arm_boot_info * info)216 static void aspeed_write_smpboot(ARMCPU *cpu, 217 const struct arm_boot_info *info) 218 { 219 AddressSpace *as = arm_boot_address_space(cpu, info); 220 static const ARMInsnFixup poll_mailbox_ready[] = { 221 /* 222 * r2 = per-cpu go sign value 223 * r1 = AST_SMP_MBOX_FIELD_ENTRY 224 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 225 */ 226 { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ 227 { 0xe21000ff }, /* ands r0, r0, #255 */ 228 { 0xe59f201c }, /* ldr r2, [pc, #28] */ 229 { 0xe1822000 }, /* orr r2, r2, r0 */ 230 231 { 0xe59f1018 }, /* ldr r1, [pc, #24] */ 232 { 0xe59f0018 }, /* ldr r0, [pc, #24] */ 233 234 { 0xe320f002 }, /* wfe */ 235 { 0xe5904000 }, /* ldr r4, [r0] */ 236 { 0xe1520004 }, /* cmp r2, r4 */ 237 { 0x1afffffb }, /* bne <wfe> */ 238 { 0xe591f000 }, /* ldr pc, [r1] */ 239 { AST_SMP_MBOX_GOSIGN }, 240 { AST_SMP_MBOX_FIELD_ENTRY }, 241 { AST_SMP_MBOX_FIELD_GOSIGN }, 242 { 0, FIXUP_TERMINATOR } 243 }; 244 static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; 245 246 arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, 247 poll_mailbox_ready, fixupcontext); 248 } 249 aspeed_reset_secondary(ARMCPU * cpu,const struct arm_boot_info * info)250 static void aspeed_reset_secondary(ARMCPU *cpu, 251 const struct arm_boot_info *info) 252 { 253 AddressSpace *as = arm_boot_address_space(cpu, info); 254 CPUState *cs = CPU(cpu); 255 256 /* info->smp_bootreg_addr */ 257 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, 258 MEMTXATTRS_UNSPECIFIED, NULL); 259 cpu_set_pc(cs, info->smp_loader_start); 260 } 261 write_boot_rom(BlockBackend * blk,hwaddr addr,size_t rom_size,Error ** errp)262 static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size, 263 Error **errp) 264 { 265 g_autofree void *storage = NULL; 266 int64_t size; 267 268 /* 269 * The block backend size should have already been 'validated' by 270 * the creation of the m25p80 object. 271 */ 272 size = blk_getlength(blk); 273 if (size <= 0) { 274 error_setg(errp, "failed to get flash size"); 275 return; 276 } 277 278 if (rom_size > size) { 279 rom_size = size; 280 } 281 282 storage = g_malloc0(rom_size); 283 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { 284 error_setg(errp, "failed to read the initial flash content"); 285 return; 286 } 287 288 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); 289 } 290 291 /* 292 * Create a ROM and copy the flash contents at the expected address 293 * (0x0). Boots faster than execute-in-place. 294 */ aspeed_install_boot_rom(AspeedMachineState * bmc,BlockBackend * blk,uint64_t rom_size)295 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, 296 uint64_t rom_size) 297 { 298 AspeedSoCState *soc = bmc->soc; 299 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); 300 301 memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, 302 &error_abort); 303 memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, 304 &bmc->boot_rom, 1); 305 write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], 306 rom_size, &error_abort); 307 } 308 309 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" 310 311 /* 312 * This function locates the vbootrom image file specified via the command line 313 * using the -bios option. It loads the specified image into the vbootrom 314 * memory region and handles errors if the file cannot be found or loaded. 315 */ aspeed_load_vbootrom(AspeedMachineState * bmc,const char * bios_name,Error ** errp)316 static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name, 317 Error **errp) 318 { 319 g_autofree char *filename = NULL; 320 AspeedSoCState *soc = bmc->soc; 321 int ret; 322 323 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 324 if (!filename) { 325 error_setg(errp, "Could not find vbootrom image '%s'", bios_name); 326 return; 327 } 328 329 ret = load_image_mr(filename, &soc->vbootrom); 330 if (ret < 0) { 331 error_setg(errp, "Failed to load vbootrom image '%s'", bios_name); 332 return; 333 } 334 } 335 aspeed_board_init_flashes(AspeedSMCState * s,const char * flashtype,unsigned int count,int unit0)336 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 337 unsigned int count, int unit0) 338 { 339 int i; 340 341 if (!flashtype) { 342 return; 343 } 344 345 for (i = 0; i < count; ++i) { 346 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); 347 DeviceState *dev; 348 349 dev = qdev_new(flashtype); 350 if (dinfo) { 351 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 352 } 353 qdev_prop_set_uint8(dev, "cs", i); 354 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); 355 } 356 } 357 sdhci_attach_drive(SDHCIState * sdhci,DriveInfo * dinfo,bool emmc,bool boot_emmc)358 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, 359 bool boot_emmc) 360 { 361 DeviceState *card; 362 363 if (!dinfo) { 364 return; 365 } 366 card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); 367 368 /* 369 * Force the boot properties of the eMMC device only when the 370 * machine is strapped to boot from eMMC. Without these 371 * settings, the machine would not boot. 372 * 373 * This also allows the machine to use an eMMC device without 374 * boot areas when booting from the flash device (or -kernel) 375 * Ideally, the device and its properties should be defined on 376 * the command line. 377 */ 378 if (emmc && boot_emmc) { 379 qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); 380 qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); 381 } 382 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 383 &error_fatal); 384 qdev_realize_and_unref(card, 385 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), 386 &error_fatal); 387 } 388 connect_serial_hds_to_uarts(AspeedMachineState * bmc)389 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) 390 { 391 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 392 AspeedSoCState *s = bmc->soc; 393 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); 394 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 395 396 aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); 397 for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { 398 if (uart == uart_chosen) { 399 continue; 400 } 401 aspeed_soc_uart_set_chr(s, uart, serial_hd(i++)); 402 } 403 } 404 aspeed_machine_init(MachineState * machine)405 static void aspeed_machine_init(MachineState *machine) 406 { 407 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 408 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 409 AspeedSoCClass *sc; 410 int i; 411 const char *bios_name = NULL; 412 DriveInfo *emmc0 = NULL; 413 bool boot_emmc; 414 415 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 416 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 417 object_unref(OBJECT(bmc->soc)); 418 sc = ASPEED_SOC_GET_CLASS(bmc->soc); 419 420 /* 421 * This will error out if the RAM size is not supported by the 422 * memory controller of the SoC. 423 */ 424 object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, 425 &error_fatal); 426 427 for (i = 0; i < sc->macs_num; i++) { 428 if ((amc->macs_mask & (1 << i)) && 429 !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), 430 true, NULL)) { 431 break; /* No configs left; stop asking */ 432 } 433 } 434 435 object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, 436 &error_abort); 437 object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, 438 &error_abort); 439 object_property_set_link(OBJECT(bmc->soc), "memory", 440 OBJECT(get_system_memory()), &error_abort); 441 object_property_set_link(OBJECT(bmc->soc), "dram", 442 OBJECT(machine->ram), &error_abort); 443 if (amc->sdhci_wp_inverted) { 444 for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { 445 object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), 446 "wp-inverted", true, &error_abort); 447 } 448 } 449 if (machine->kernel_filename) { 450 /* 451 * When booting with a -kernel command line there is no u-boot 452 * that runs to unlock the SCU. In this case set the default to 453 * be unlocked as the kernel expects 454 */ 455 object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", 456 ASPEED_SCU_PROT_KEY, &error_abort); 457 } 458 connect_serial_hds_to_uarts(bmc); 459 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 460 461 if (defaults_enabled()) { 462 aspeed_board_init_flashes(&bmc->soc->fmc, 463 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 464 amc->num_cs, 0); 465 aspeed_board_init_flashes(&bmc->soc->spi[0], 466 bmc->spi_model ? bmc->spi_model : amc->spi_model, 467 1, amc->num_cs); 468 } 469 470 if (machine->kernel_filename && sc->num_cpus > 1) { 471 /* With no u-boot we must set up a boot stub for the secondary CPU */ 472 MemoryRegion *smpboot = g_new(MemoryRegion, 1); 473 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", 474 0x80, &error_abort); 475 memory_region_add_subregion(get_system_memory(), 476 AST_SMP_MAILBOX_BASE, smpboot); 477 478 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; 479 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; 480 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; 481 } 482 483 aspeed_board_binfo.ram_size = machine->ram_size; 484 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; 485 486 if (amc->i2c_init) { 487 amc->i2c_init(bmc); 488 } 489 490 for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { 491 sdhci_attach_drive(&bmc->soc->sdhci.slots[i], 492 drive_get(IF_SD, 0, i), false, false); 493 } 494 495 boot_emmc = sc->boot_from_emmc(bmc->soc); 496 497 if (bmc->soc->emmc.num_slots && defaults_enabled()) { 498 emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); 499 sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); 500 } 501 502 if (!bmc->mmio_exec) { 503 DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); 504 BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; 505 506 if (fmc0 && !boot_emmc) { 507 uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); 508 aspeed_install_boot_rom(bmc, fmc0, rom_size); 509 } else if (emmc0) { 510 aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(emmc0), 64 * KiB); 511 } 512 } 513 514 if (amc->vbootrom) { 515 bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; 516 aspeed_load_vbootrom(bmc, bios_name, &error_abort); 517 } 518 519 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); 520 } 521 palmetto_bmc_i2c_init(AspeedMachineState * bmc)522 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) 523 { 524 AspeedSoCState *soc = bmc->soc; 525 DeviceState *dev; 526 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 527 528 /* 529 * The palmetto platform expects a ds3231 RTC but a ds1338 is 530 * enough to provide basic RTC features. Alarms will be missing 531 */ 532 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); 533 534 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, 535 eeprom_buf); 536 537 /* add a TMP423 temperature sensor */ 538 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 539 "tmp423", 0x4c)); 540 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 541 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 542 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 543 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); 544 } 545 quanta_q71l_bmc_i2c_init(AspeedMachineState * bmc)546 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) 547 { 548 AspeedSoCState *soc = bmc->soc; 549 550 /* 551 * The quanta-q71l platform expects tmp75s which are compatible with 552 * tmp105s. 553 */ 554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); 555 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); 556 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); 557 558 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ 559 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ 560 /* TODO: Add Memory Riser i2c mux and eeproms. */ 561 562 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74); 563 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77); 564 565 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ 566 567 /* i2c-7 */ 568 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70); 569 /* - i2c@0: pmbus@59 */ 570 /* - i2c@1: pmbus@58 */ 571 /* - i2c@2: pmbus@58 */ 572 /* - i2c@3: pmbus@59 */ 573 574 /* TODO: i2c-7: Add PDB FRU eeprom@52 */ 575 /* TODO: i2c-8: Add BMC FRU eeprom@50 */ 576 } 577 ast2500_evb_i2c_init(AspeedMachineState * bmc)578 static void ast2500_evb_i2c_init(AspeedMachineState *bmc) 579 { 580 AspeedSoCState *soc = bmc->soc; 581 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 582 583 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, 584 eeprom_buf); 585 586 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ 587 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 588 TYPE_TMP105, 0x4d); 589 } 590 ast2600_evb_i2c_init(AspeedMachineState * bmc)591 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) 592 { 593 AspeedSoCState *soc = bmc->soc; 594 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 595 596 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 597 eeprom_buf); 598 599 /* LM75 is compatible with TMP105 driver */ 600 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 601 TYPE_TMP105, 0x4d); 602 } 603 yosemitev2_bmc_i2c_init(AspeedMachineState * bmc)604 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc) 605 { 606 AspeedSoCState *soc = bmc->soc; 607 608 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB); 609 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB, 610 yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len); 611 /* TMP421 */ 612 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "tmp421", 0x1f); 613 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4e); 614 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp421", 0x4f); 615 616 } 617 romulus_bmc_i2c_init(AspeedMachineState * bmc)618 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) 619 { 620 AspeedSoCState *soc = bmc->soc; 621 622 /* 623 * The romulus board expects Epson RX8900 I2C RTC but a ds1338 is 624 * good enough 625 */ 626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 627 } 628 tiogapass_bmc_i2c_init(AspeedMachineState * bmc)629 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc) 630 { 631 AspeedSoCState *soc = bmc->soc; 632 633 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB); 634 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB, 635 tiogapass_bmc_fruid, tiogapass_bmc_fruid_len); 636 /* TMP421 */ 637 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "tmp421", 0x1f); 638 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4f); 639 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp421", 0x4e); 640 } 641 create_pca9552(AspeedSoCState * soc,int bus_id,int addr)642 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr) 643 { 644 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), 645 TYPE_PCA9552, addr); 646 } 647 sonorapass_bmc_i2c_init(AspeedMachineState * bmc)648 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) 649 { 650 AspeedSoCState *soc = bmc->soc; 651 652 /* bus 2 : */ 653 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); 654 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); 655 /* bus 2 : pca9546 @ 0x73 */ 656 657 /* bus 3 : pca9548 @ 0x70 */ 658 659 /* bus 4 : */ 660 uint8_t *eeprom4_54 = g_malloc0(8 * 1024); 661 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 662 eeprom4_54); 663 /* PCA9539 @ 0x76, but PCA9552 is compatible */ 664 create_pca9552(soc, 4, 0x76); 665 /* PCA9539 @ 0x77, but PCA9552 is compatible */ 666 create_pca9552(soc, 4, 0x77); 667 668 /* bus 6 : */ 669 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); 670 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); 671 /* bus 6 : pca9546 @ 0x73 */ 672 673 /* bus 8 : */ 674 uint8_t *eeprom8_56 = g_malloc0(8 * 1024); 675 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, 676 eeprom8_56); 677 create_pca9552(soc, 8, 0x60); 678 create_pca9552(soc, 8, 0x61); 679 /* bus 8 : adc128d818 @ 0x1d */ 680 /* bus 8 : adc128d818 @ 0x1f */ 681 682 /* 683 * bus 13 : pca9548 @ 0x71 684 * - channel 3: 685 * - tmm421 @ 0x4c 686 * - tmp421 @ 0x4e 687 * - tmp421 @ 0x4f 688 */ 689 690 } 691 witherspoon_bmc_i2c_init(AspeedMachineState * bmc)692 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) 693 { 694 static const struct { 695 unsigned gpio_id; 696 LEDColor color; 697 const char *description; 698 bool gpio_polarity; 699 } pca1_leds[] = { 700 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW}, 701 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW}, 702 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW}, 703 }; 704 AspeedSoCState *soc = bmc->soc; 705 uint8_t *eeprom_buf = g_malloc0(8 * 1024); 706 DeviceState *dev; 707 LEDState *led; 708 709 /* Bus 3: TODO bmp280@77 */ 710 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 711 qdev_prop_set_string(dev, "description", "pca1"); 712 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 713 aspeed_i2c_get_bus(&soc->i2c, 3), 714 &error_fatal); 715 716 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) { 717 led = led_create_simple(OBJECT(bmc), 718 pca1_leds[i].gpio_polarity, 719 pca1_leds[i].color, 720 pca1_leds[i].description); 721 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id, 722 qdev_get_gpio_in(DEVICE(led), 0)); 723 } 724 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76); 725 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52); 726 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); 727 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); 728 729 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ 730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, 731 0x4a); 732 733 /* 734 * The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is 735 * good enough 736 */ 737 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); 738 739 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, 740 eeprom_buf); 741 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); 742 qdev_prop_set_string(dev, "description", "pca0"); 743 i2c_slave_realize_and_unref(I2C_SLAVE(dev), 744 aspeed_i2c_get_bus(&soc->i2c, 11), 745 &error_fatal); 746 /* Bus 11: TODO ucd90160@64 */ 747 } 748 g220a_bmc_i2c_init(AspeedMachineState * bmc)749 static void g220a_bmc_i2c_init(AspeedMachineState *bmc) 750 { 751 AspeedSoCState *soc = bmc->soc; 752 DeviceState *dev; 753 754 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), 755 "emc1413", 0x4c)); 756 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 757 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 758 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 759 760 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), 761 "emc1413", 0x4c)); 762 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 763 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 764 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 765 766 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13), 767 "emc1413", 0x4c)); 768 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); 769 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); 770 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); 771 772 static uint8_t eeprom_buf[2 * 1024] = { 773 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe, 774 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65, 775 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32, 776 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42, 777 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45, 778 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1, 779 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 780 }; 781 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57, 782 eeprom_buf); 783 } 784 fp5280g2_bmc_i2c_init(AspeedMachineState * bmc)785 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc) 786 { 787 AspeedSoCState *soc = bmc->soc; 788 I2CSlave *i2c_mux; 789 790 /* The at24c256 */ 791 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768); 792 793 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */ 794 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 795 0x48); 796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105, 797 0x49); 798 799 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), 800 "pca9546", 0x70); 801 /* It expects a TMP112 but a TMP105 is compatible */ 802 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105, 803 0x4a); 804 805 /* It expects a ds3232 but a ds1338 is good enough */ 806 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68); 807 808 /* It expects a pca9555 but a pca9552 is compatible */ 809 create_pca9552(soc, 8, 0x30); 810 } 811 rainier_bmc_i2c_init(AspeedMachineState * bmc)812 static void rainier_bmc_i2c_init(AspeedMachineState *bmc) 813 { 814 AspeedSoCState *soc = bmc->soc; 815 I2CSlave *i2c_mux; 816 817 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); 818 819 create_pca9552(soc, 3, 0x61); 820 821 /* The rainier expects a TMP275 but a TMP105 is compatible */ 822 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 823 0x48); 824 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 825 0x49); 826 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, 827 0x4a); 828 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), 829 "pca9546", 0x70); 830 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 831 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 832 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); 833 create_pca9552(soc, 4, 0x60); 834 835 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 836 0x48); 837 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, 838 0x49); 839 create_pca9552(soc, 5, 0x60); 840 create_pca9552(soc, 5, 0x61); 841 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), 842 "pca9546", 0x70); 843 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 844 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 845 846 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 847 0x48); 848 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 849 0x4a); 850 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, 851 0x4b); 852 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), 853 "pca9546", 0x70); 854 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 855 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 856 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); 857 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); 858 859 create_pca9552(soc, 7, 0x30); 860 create_pca9552(soc, 7, 0x31); 861 create_pca9552(soc, 7, 0x32); 862 create_pca9552(soc, 7, 0x33); 863 create_pca9552(soc, 7, 0x60); 864 create_pca9552(soc, 7, 0x61); 865 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); 866 /* Bus 7: TODO si7021-a20@20 */ 867 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, 868 0x48); 869 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); 870 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); 871 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); 872 873 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 874 0x48); 875 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 876 0x4a); 877 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 878 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); 879 at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 880 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); 881 create_pca9552(soc, 8, 0x60); 882 create_pca9552(soc, 8, 0x61); 883 /* Bus 8: ucd90320@11 */ 884 /* Bus 8: ucd90320@b */ 885 /* Bus 8: ucd90320@c */ 886 887 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); 888 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); 889 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); 890 891 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); 892 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); 893 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); 894 895 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 896 0x48); 897 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, 898 0x49); 899 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), 900 "pca9546", 0x70); 901 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); 902 at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); 903 create_pca9552(soc, 11, 0x60); 904 905 906 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); 907 create_pca9552(soc, 13, 0x60); 908 909 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); 910 create_pca9552(soc, 14, 0x60); 911 912 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); 913 create_pca9552(soc, 15, 0x60); 914 } 915 get_pca9548_channels(I2CBus * bus,uint8_t mux_addr,I2CBus ** channels)916 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr, 917 I2CBus **channels) 918 { 919 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr); 920 for (int i = 0; i < 8; i++) { 921 channels[i] = pca954x_i2c_get_bus(mux, i); 922 } 923 } 924 925 #define TYPE_LM75 TYPE_TMP105 926 #define TYPE_TMP75 TYPE_TMP105 927 #define TYPE_TMP422 "tmp422" 928 fuji_bmc_i2c_init(AspeedMachineState * bmc)929 static void fuji_bmc_i2c_init(AspeedMachineState *bmc) 930 { 931 AspeedSoCState *soc = bmc->soc; 932 I2CBus *i2c[144] = {}; 933 934 for (int i = 0; i < 16; i++) { 935 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 936 } 937 I2CBus *i2c180 = i2c[2]; 938 I2CBus *i2c480 = i2c[8]; 939 I2CBus *i2c600 = i2c[11]; 940 941 get_pca9548_channels(i2c180, 0x70, &i2c[16]); 942 get_pca9548_channels(i2c480, 0x70, &i2c[24]); 943 /* NOTE: The device tree skips [32, 40) in the alias numbering */ 944 get_pca9548_channels(i2c600, 0x77, &i2c[40]); 945 get_pca9548_channels(i2c[24], 0x71, &i2c[48]); 946 get_pca9548_channels(i2c[25], 0x72, &i2c[56]); 947 get_pca9548_channels(i2c[26], 0x76, &i2c[64]); 948 get_pca9548_channels(i2c[27], 0x76, &i2c[72]); 949 for (int i = 0; i < 8; i++) { 950 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]); 951 } 952 953 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c); 954 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d); 955 956 /* 957 * EEPROM 24c64 size is 64Kbits or 8 Kbytes 958 * 24c02 size is 2Kbits or 256 bytes 959 */ 960 at24c_eeprom_init(i2c[19], 0x52, 8 * KiB); 961 at24c_eeprom_init(i2c[20], 0x50, 256); 962 at24c_eeprom_init(i2c[22], 0x52, 256); 963 964 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48); 965 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49); 966 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a); 967 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c); 968 969 at24c_eeprom_init(i2c[8], 0x51, 8 * KiB); 970 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a); 971 972 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c); 973 at24c_eeprom_init(i2c[50], 0x52, 8 * KiB); 974 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48); 975 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49); 976 977 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48); 978 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49); 979 980 at24c_eeprom_init(i2c[65], 0x53, 8 * KiB); 981 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49); 982 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48); 983 at24c_eeprom_init(i2c[68], 0x52, 8 * KiB); 984 at24c_eeprom_init(i2c[69], 0x52, 8 * KiB); 985 at24c_eeprom_init(i2c[70], 0x52, 8 * KiB); 986 at24c_eeprom_init(i2c[71], 0x52, 8 * KiB); 987 988 at24c_eeprom_init(i2c[73], 0x53, 8 * KiB); 989 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49); 990 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48); 991 at24c_eeprom_init(i2c[76], 0x52, 8 * KiB); 992 at24c_eeprom_init(i2c[77], 0x52, 8 * KiB); 993 at24c_eeprom_init(i2c[78], 0x52, 8 * KiB); 994 at24c_eeprom_init(i2c[79], 0x52, 8 * KiB); 995 at24c_eeprom_init(i2c[28], 0x50, 256); 996 997 for (int i = 0; i < 8; i++) { 998 at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB); 999 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48); 1000 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b); 1001 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a); 1002 } 1003 } 1004 1005 #define TYPE_TMP421 "tmp421" 1006 bletchley_bmc_i2c_init(AspeedMachineState * bmc)1007 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc) 1008 { 1009 AspeedSoCState *soc = bmc->soc; 1010 I2CBus *i2c[13] = {}; 1011 for (int i = 0; i < 13; i++) { 1012 if ((i == 8) || (i == 11)) { 1013 continue; 1014 } 1015 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1016 } 1017 1018 /* Bus 0 - 5 all have the same config. */ 1019 for (int i = 0; i < 6; i++) { 1020 /* Missing model: ti,ina230 @ 0x45 */ 1021 /* Missing model: mps,mp5023 @ 0x40 */ 1022 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f); 1023 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */ 1024 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76); 1025 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67); 1026 /* Missing model: fsc,fusb302 @ 0x22 */ 1027 } 1028 1029 /* Bus 6 */ 1030 at24c_eeprom_init(i2c[6], 0x56, 65536); 1031 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */ 1032 i2c_slave_create_simple(i2c[6], "ds1338", 0x51); 1033 1034 1035 /* Bus 7 */ 1036 at24c_eeprom_init(i2c[7], 0x54, 65536); 1037 1038 /* Bus 9 */ 1039 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f); 1040 1041 /* Bus 10 */ 1042 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f); 1043 /* Missing model: ti,hdc1080 @ 0x40 */ 1044 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67); 1045 1046 /* Bus 12 */ 1047 /* Missing model: adi,adm1278 @ 0x11 */ 1048 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c); 1049 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d); 1050 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); 1051 } 1052 fby35_i2c_init(AspeedMachineState * bmc)1053 static void fby35_i2c_init(AspeedMachineState *bmc) 1054 { 1055 AspeedSoCState *soc = bmc->soc; 1056 I2CBus *i2c[16]; 1057 1058 for (int i = 0; i < 16; i++) { 1059 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); 1060 } 1061 1062 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); 1063 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); 1064 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ 1065 i2c_slave_create_simple(i2c[11], "adm1272", 0x44); 1066 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); 1067 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); 1068 1069 at24c_eeprom_init(i2c[4], 0x51, 128 * KiB); 1070 at24c_eeprom_init(i2c[6], 0x51, 128 * KiB); 1071 at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid, 1072 fby35_nic_fruid_len); 1073 at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid, 1074 fby35_bb_fruid_len); 1075 at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid, 1076 fby35_bmc_fruid_len); 1077 1078 /* 1079 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on 1080 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on 1081 * each. 1082 */ 1083 } 1084 qcom_dc_scm_bmc_i2c_init(AspeedMachineState * bmc)1085 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) 1086 { 1087 AspeedSoCState *soc = bmc->soc; 1088 1089 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); 1090 } 1091 qcom_dc_scm_firework_i2c_init(AspeedMachineState * bmc)1092 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) 1093 { 1094 AspeedSoCState *soc = bmc->soc; 1095 I2CSlave *therm_mux, *cpuvr_mux; 1096 1097 /* Create the generic DC-SCM hardware */ 1098 qcom_dc_scm_bmc_i2c_init(bmc); 1099 1100 /* Now create the Firework specific hardware */ 1101 1102 /* I2C7 CPUVR MUX */ 1103 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), 1104 "pca9546", 0x70); 1105 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); 1106 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); 1107 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); 1108 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); 1109 1110 /* I2C8 Thermal Diodes*/ 1111 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), 1112 "pca9548", 0x70); 1113 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); 1114 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); 1115 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); 1116 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); 1117 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); 1118 1119 /* I2C9 Fan Controller (MAX31785) */ 1120 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); 1121 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); 1122 } 1123 aspeed_get_mmio_exec(Object * obj,Error ** errp)1124 static bool aspeed_get_mmio_exec(Object *obj, Error **errp) 1125 { 1126 return ASPEED_MACHINE(obj)->mmio_exec; 1127 } 1128 aspeed_set_mmio_exec(Object * obj,bool value,Error ** errp)1129 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) 1130 { 1131 ASPEED_MACHINE(obj)->mmio_exec = value; 1132 } 1133 aspeed_machine_instance_init(Object * obj)1134 static void aspeed_machine_instance_init(Object *obj) 1135 { 1136 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); 1137 1138 ASPEED_MACHINE(obj)->mmio_exec = false; 1139 ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; 1140 } 1141 aspeed_get_fmc_model(Object * obj,Error ** errp)1142 static char *aspeed_get_fmc_model(Object *obj, Error **errp) 1143 { 1144 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1145 return g_strdup(bmc->fmc_model); 1146 } 1147 aspeed_set_fmc_model(Object * obj,const char * value,Error ** errp)1148 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) 1149 { 1150 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1151 1152 g_free(bmc->fmc_model); 1153 bmc->fmc_model = g_strdup(value); 1154 } 1155 aspeed_get_spi_model(Object * obj,Error ** errp)1156 static char *aspeed_get_spi_model(Object *obj, Error **errp) 1157 { 1158 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1159 return g_strdup(bmc->spi_model); 1160 } 1161 aspeed_set_spi_model(Object * obj,const char * value,Error ** errp)1162 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) 1163 { 1164 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1165 1166 g_free(bmc->spi_model); 1167 bmc->spi_model = g_strdup(value); 1168 } 1169 aspeed_get_bmc_console(Object * obj,Error ** errp)1170 static char *aspeed_get_bmc_console(Object *obj, Error **errp) 1171 { 1172 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1173 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1174 int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; 1175 1176 return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); 1177 } 1178 aspeed_set_bmc_console(Object * obj,const char * value,Error ** errp)1179 static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) 1180 { 1181 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1182 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); 1183 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1184 int val; 1185 int uart_first = aspeed_uart_first(sc); 1186 int uart_last = aspeed_uart_last(sc); 1187 1188 if (sscanf(value, "uart%u", &val) != 1) { 1189 error_setg(errp, "Bad value for \"uart\" property"); 1190 return; 1191 } 1192 1193 /* The number of UART depends on the SoC */ 1194 if (val < uart_first || val > uart_last) { 1195 error_setg(errp, "\"uart\" should be in range [%d - %d]", 1196 uart_first, uart_last); 1197 return; 1198 } 1199 bmc->uart_chosen = val + ASPEED_DEV_UART0; 1200 } 1201 aspeed_machine_class_props_init(ObjectClass * oc)1202 static void aspeed_machine_class_props_init(ObjectClass *oc) 1203 { 1204 object_class_property_add_bool(oc, "execute-in-place", 1205 aspeed_get_mmio_exec, 1206 aspeed_set_mmio_exec); 1207 object_class_property_set_description(oc, "execute-in-place", 1208 "boot directly from CE0 flash device"); 1209 1210 object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, 1211 aspeed_set_bmc_console); 1212 object_class_property_set_description(oc, "bmc-console", 1213 "Change the default UART to \"uartX\""); 1214 1215 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, 1216 aspeed_set_fmc_model); 1217 object_class_property_set_description(oc, "fmc-model", 1218 "Change the FMC Flash model"); 1219 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, 1220 aspeed_set_spi_model); 1221 object_class_property_set_description(oc, "spi-model", 1222 "Change the SPI Flash model"); 1223 } 1224 aspeed_machine_class_init_cpus_defaults(MachineClass * mc)1225 static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) 1226 { 1227 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); 1228 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); 1229 1230 mc->default_cpus = sc->num_cpus; 1231 mc->min_cpus = sc->num_cpus; 1232 mc->max_cpus = sc->num_cpus; 1233 mc->valid_cpu_types = sc->valid_cpu_types; 1234 } 1235 aspeed_machine_ast2600_get_boot_from_emmc(Object * obj,Error ** errp)1236 static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) 1237 { 1238 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1239 1240 return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); 1241 } 1242 aspeed_machine_ast2600_set_boot_from_emmc(Object * obj,bool value,Error ** errp)1243 static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, 1244 Error **errp) 1245 { 1246 AspeedMachineState *bmc = ASPEED_MACHINE(obj); 1247 1248 if (value) { 1249 bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1250 } else { 1251 bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; 1252 } 1253 } 1254 aspeed_machine_ast2600_class_emmc_init(ObjectClass * oc)1255 static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) 1256 { 1257 object_class_property_add_bool(oc, "boot-emmc", 1258 aspeed_machine_ast2600_get_boot_from_emmc, 1259 aspeed_machine_ast2600_set_boot_from_emmc); 1260 object_class_property_set_description(oc, "boot-emmc", 1261 "Set or unset boot from EMMC"); 1262 } 1263 aspeed_machine_class_init(ObjectClass * oc,const void * data)1264 static void aspeed_machine_class_init(ObjectClass *oc, const void *data) 1265 { 1266 MachineClass *mc = MACHINE_CLASS(oc); 1267 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1268 1269 mc->init = aspeed_machine_init; 1270 mc->no_floppy = 1; 1271 mc->no_cdrom = 1; 1272 mc->no_parallel = 1; 1273 mc->default_ram_id = "ram"; 1274 amc->macs_mask = ASPEED_MAC0_ON; 1275 amc->uart_default = ASPEED_DEV_UART5; 1276 1277 aspeed_machine_class_props_init(oc); 1278 } 1279 aspeed_machine_palmetto_class_init(ObjectClass * oc,const void * data)1280 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, 1281 const void *data) 1282 { 1283 MachineClass *mc = MACHINE_CLASS(oc); 1284 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1285 1286 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; 1287 amc->soc_name = "ast2400-a1"; 1288 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; 1289 amc->fmc_model = "n25q256a"; 1290 amc->spi_model = "mx25l25635f"; 1291 amc->num_cs = 1; 1292 amc->i2c_init = palmetto_bmc_i2c_init; 1293 mc->auto_create_sdcard = true; 1294 mc->default_ram_size = 256 * MiB; 1295 aspeed_machine_class_init_cpus_defaults(mc); 1296 }; 1297 aspeed_machine_quanta_q71l_class_init(ObjectClass * oc,const void * data)1298 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, 1299 const void *data) 1300 { 1301 MachineClass *mc = MACHINE_CLASS(oc); 1302 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1303 1304 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; 1305 amc->soc_name = "ast2400-a1"; 1306 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; 1307 amc->fmc_model = "n25q256a"; 1308 amc->spi_model = "mx25l25635e"; 1309 amc->num_cs = 1; 1310 amc->i2c_init = quanta_q71l_bmc_i2c_init; 1311 mc->auto_create_sdcard = true; 1312 mc->default_ram_size = 128 * MiB; 1313 aspeed_machine_class_init_cpus_defaults(mc); 1314 } 1315 aspeed_machine_supermicrox11_bmc_class_init(ObjectClass * oc,const void * data)1316 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, 1317 const void *data) 1318 { 1319 MachineClass *mc = MACHINE_CLASS(oc); 1320 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1321 1322 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; 1323 amc->soc_name = "ast2400-a1"; 1324 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; 1325 amc->fmc_model = "mx25l25635e"; 1326 amc->spi_model = "mx25l25635e"; 1327 amc->num_cs = 1; 1328 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1329 amc->i2c_init = palmetto_bmc_i2c_init; 1330 mc->auto_create_sdcard = true; 1331 mc->default_ram_size = 256 * MiB; 1332 aspeed_machine_class_init_cpus_defaults(mc); 1333 } 1334 aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass * oc,const void * data)1335 static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, 1336 const void *data) 1337 { 1338 MachineClass *mc = MACHINE_CLASS(oc); 1339 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1340 1341 mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; 1342 amc->soc_name = "ast2500-a1"; 1343 amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; 1344 amc->fmc_model = "mx25l25635e"; 1345 amc->spi_model = "mx25l25635e"; 1346 amc->num_cs = 1; 1347 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1348 amc->i2c_init = palmetto_bmc_i2c_init; 1349 mc->auto_create_sdcard = true; 1350 mc->default_ram_size = 512 * MiB; 1351 aspeed_machine_class_init_cpus_defaults(mc); 1352 } 1353 aspeed_machine_ast2500_evb_class_init(ObjectClass * oc,const void * data)1354 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, 1355 const void *data) 1356 { 1357 MachineClass *mc = MACHINE_CLASS(oc); 1358 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1359 1360 mc->desc = "Aspeed AST2500 EVB (ARM1176)"; 1361 amc->soc_name = "ast2500-a1"; 1362 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1363 amc->fmc_model = "mx25l25635e"; 1364 amc->spi_model = "mx25l25635f"; 1365 amc->num_cs = 1; 1366 amc->i2c_init = ast2500_evb_i2c_init; 1367 mc->auto_create_sdcard = true; 1368 mc->default_ram_size = 512 * MiB; 1369 aspeed_machine_class_init_cpus_defaults(mc); 1370 }; 1371 aspeed_machine_yosemitev2_class_init(ObjectClass * oc,const void * data)1372 static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, 1373 const void *data) 1374 { 1375 MachineClass *mc = MACHINE_CLASS(oc); 1376 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1377 1378 mc->desc = "Facebook YosemiteV2 BMC (ARM1176)"; 1379 amc->soc_name = "ast2500-a1"; 1380 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1381 amc->hw_strap2 = 0; 1382 amc->fmc_model = "n25q256a"; 1383 amc->spi_model = "mx25l25635e"; 1384 amc->num_cs = 2; 1385 amc->i2c_init = yosemitev2_bmc_i2c_init; 1386 mc->auto_create_sdcard = true; 1387 mc->default_ram_size = 512 * MiB; 1388 aspeed_machine_class_init_cpus_defaults(mc); 1389 }; 1390 aspeed_machine_romulus_class_init(ObjectClass * oc,const void * data)1391 static void aspeed_machine_romulus_class_init(ObjectClass *oc, 1392 const void *data) 1393 { 1394 MachineClass *mc = MACHINE_CLASS(oc); 1395 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1396 1397 mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; 1398 amc->soc_name = "ast2500-a1"; 1399 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; 1400 amc->fmc_model = "n25q256a"; 1401 amc->spi_model = "mx66l1g45g"; 1402 amc->num_cs = 2; 1403 amc->i2c_init = romulus_bmc_i2c_init; 1404 mc->auto_create_sdcard = true; 1405 mc->default_ram_size = 512 * MiB; 1406 aspeed_machine_class_init_cpus_defaults(mc); 1407 }; 1408 aspeed_machine_tiogapass_class_init(ObjectClass * oc,const void * data)1409 static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, 1410 const void *data) 1411 { 1412 MachineClass *mc = MACHINE_CLASS(oc); 1413 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1414 1415 mc->desc = "Facebook Tiogapass BMC (ARM1176)"; 1416 amc->soc_name = "ast2500-a1"; 1417 amc->hw_strap1 = AST2500_EVB_HW_STRAP1; 1418 amc->hw_strap2 = 0; 1419 amc->fmc_model = "n25q256a"; 1420 amc->spi_model = "mx25l25635e"; 1421 amc->num_cs = 2; 1422 amc->i2c_init = tiogapass_bmc_i2c_init; 1423 mc->auto_create_sdcard = true; 1424 mc->default_ram_size = 1 * GiB; 1425 aspeed_machine_class_init_cpus_defaults(mc); 1426 }; 1427 aspeed_machine_sonorapass_class_init(ObjectClass * oc,const void * data)1428 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, 1429 const void *data) 1430 { 1431 MachineClass *mc = MACHINE_CLASS(oc); 1432 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1433 1434 mc->desc = "OCP SonoraPass BMC (ARM1176)"; 1435 amc->soc_name = "ast2500-a1"; 1436 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; 1437 amc->fmc_model = "mx66l1g45g"; 1438 amc->spi_model = "mx66l1g45g"; 1439 amc->num_cs = 2; 1440 amc->i2c_init = sonorapass_bmc_i2c_init; 1441 mc->auto_create_sdcard = true; 1442 mc->default_ram_size = 512 * MiB; 1443 aspeed_machine_class_init_cpus_defaults(mc); 1444 }; 1445 aspeed_machine_witherspoon_class_init(ObjectClass * oc,const void * data)1446 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, 1447 const void *data) 1448 { 1449 MachineClass *mc = MACHINE_CLASS(oc); 1450 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1451 1452 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; 1453 amc->soc_name = "ast2500-a1"; 1454 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; 1455 amc->fmc_model = "mx25l25635f"; 1456 amc->spi_model = "mx66l1g45g"; 1457 amc->num_cs = 2; 1458 amc->i2c_init = witherspoon_bmc_i2c_init; 1459 mc->auto_create_sdcard = true; 1460 mc->default_ram_size = 512 * MiB; 1461 aspeed_machine_class_init_cpus_defaults(mc); 1462 }; 1463 aspeed_machine_ast2600_evb_class_init(ObjectClass * oc,const void * data)1464 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, 1465 const void *data) 1466 { 1467 MachineClass *mc = MACHINE_CLASS(oc); 1468 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1469 1470 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; 1471 amc->soc_name = "ast2600-a3"; 1472 amc->hw_strap1 = AST2600_EVB_HW_STRAP1; 1473 amc->hw_strap2 = AST2600_EVB_HW_STRAP2; 1474 amc->fmc_model = "mx66u51235f"; 1475 amc->spi_model = "mx66u51235f"; 1476 amc->num_cs = 1; 1477 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | 1478 ASPEED_MAC3_ON; 1479 amc->sdhci_wp_inverted = true; 1480 amc->i2c_init = ast2600_evb_i2c_init; 1481 mc->auto_create_sdcard = true; 1482 mc->default_ram_size = 1 * GiB; 1483 aspeed_machine_class_init_cpus_defaults(mc); 1484 aspeed_machine_ast2600_class_emmc_init(oc); 1485 }; 1486 aspeed_machine_g220a_class_init(ObjectClass * oc,const void * data)1487 static void aspeed_machine_g220a_class_init(ObjectClass *oc, const void *data) 1488 { 1489 MachineClass *mc = MACHINE_CLASS(oc); 1490 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1491 1492 mc->desc = "Bytedance G220A BMC (ARM1176)"; 1493 amc->soc_name = "ast2500-a1"; 1494 amc->hw_strap1 = G220A_BMC_HW_STRAP1; 1495 amc->fmc_model = "n25q512a"; 1496 amc->spi_model = "mx25l25635e"; 1497 amc->num_cs = 2; 1498 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1499 amc->i2c_init = g220a_bmc_i2c_init; 1500 mc->auto_create_sdcard = true; 1501 mc->default_ram_size = 1024 * MiB; 1502 aspeed_machine_class_init_cpus_defaults(mc); 1503 }; 1504 aspeed_machine_fp5280g2_class_init(ObjectClass * oc,const void * data)1505 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, 1506 const void *data) 1507 { 1508 MachineClass *mc = MACHINE_CLASS(oc); 1509 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1510 1511 mc->desc = "Inspur FP5280G2 BMC (ARM1176)"; 1512 amc->soc_name = "ast2500-a1"; 1513 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1; 1514 amc->fmc_model = "n25q512a"; 1515 amc->spi_model = "mx25l25635e"; 1516 amc->num_cs = 2; 1517 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; 1518 amc->i2c_init = fp5280g2_bmc_i2c_init; 1519 mc->auto_create_sdcard = true; 1520 mc->default_ram_size = 512 * MiB; 1521 aspeed_machine_class_init_cpus_defaults(mc); 1522 }; 1523 aspeed_machine_rainier_class_init(ObjectClass * oc,const void * data)1524 static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data) 1525 { 1526 MachineClass *mc = MACHINE_CLASS(oc); 1527 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1528 1529 mc->desc = "IBM Rainier BMC (Cortex-A7)"; 1530 amc->soc_name = "ast2600-a3"; 1531 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; 1532 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; 1533 amc->fmc_model = "mx66l1g45g"; 1534 amc->spi_model = "mx66l1g45g"; 1535 amc->num_cs = 2; 1536 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1537 amc->i2c_init = rainier_bmc_i2c_init; 1538 mc->auto_create_sdcard = true; 1539 mc->default_ram_size = 1 * GiB; 1540 aspeed_machine_class_init_cpus_defaults(mc); 1541 aspeed_machine_ast2600_class_emmc_init(oc); 1542 }; 1543 1544 #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1545 aspeed_machine_fuji_class_init(ObjectClass * oc,const void * data)1546 static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data) 1547 { 1548 MachineClass *mc = MACHINE_CLASS(oc); 1549 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1550 1551 mc->desc = "Facebook Fuji BMC (Cortex-A7)"; 1552 amc->soc_name = "ast2600-a3"; 1553 amc->hw_strap1 = FUJI_BMC_HW_STRAP1; 1554 amc->hw_strap2 = FUJI_BMC_HW_STRAP2; 1555 amc->fmc_model = "mx66l1g45g"; 1556 amc->spi_model = "mx66l1g45g"; 1557 amc->num_cs = 2; 1558 amc->macs_mask = ASPEED_MAC3_ON; 1559 amc->i2c_init = fuji_bmc_i2c_init; 1560 amc->uart_default = ASPEED_DEV_UART1; 1561 mc->auto_create_sdcard = true; 1562 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1563 aspeed_machine_class_init_cpus_defaults(mc); 1564 }; 1565 1566 #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) 1567 aspeed_machine_bletchley_class_init(ObjectClass * oc,const void * data)1568 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, 1569 const void *data) 1570 { 1571 MachineClass *mc = MACHINE_CLASS(oc); 1572 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1573 1574 mc->desc = "Facebook Bletchley BMC (Cortex-A7)"; 1575 amc->soc_name = "ast2600-a3"; 1576 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1; 1577 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2; 1578 amc->fmc_model = "w25q01jvq"; 1579 amc->spi_model = NULL; 1580 amc->num_cs = 2; 1581 amc->macs_mask = ASPEED_MAC2_ON; 1582 amc->i2c_init = bletchley_bmc_i2c_init; 1583 mc->auto_create_sdcard = true; 1584 mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; 1585 aspeed_machine_class_init_cpus_defaults(mc); 1586 } 1587 fby35_reset(MachineState * state,ResetType type)1588 static void fby35_reset(MachineState *state, ResetType type) 1589 { 1590 AspeedMachineState *bmc = ASPEED_MACHINE(state); 1591 AspeedGPIOState *gpio = &bmc->soc->gpio; 1592 1593 qemu_devices_reset(type); 1594 1595 /* Board ID: 7 (Class-1, 4 slots) */ 1596 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); 1597 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); 1598 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); 1599 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); 1600 1601 /* Slot presence pins, inverse polarity. (False means present) */ 1602 object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal); 1603 object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal); 1604 object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal); 1605 object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal); 1606 1607 /* Slot 12v power pins, normal polarity. (True means powered-on) */ 1608 object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal); 1609 object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal); 1610 object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal); 1611 object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal); 1612 } 1613 aspeed_machine_fby35_class_init(ObjectClass * oc,const void * data)1614 static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data) 1615 { 1616 MachineClass *mc = MACHINE_CLASS(oc); 1617 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1618 1619 mc->desc = "Facebook fby35 BMC (Cortex-A7)"; 1620 mc->reset = fby35_reset; 1621 amc->fmc_model = "mx66l1g45g"; 1622 amc->num_cs = 2; 1623 amc->macs_mask = ASPEED_MAC3_ON; 1624 amc->i2c_init = fby35_i2c_init; 1625 mc->auto_create_sdcard = true; 1626 /* FIXME: Replace this macro with something more general */ 1627 mc->default_ram_size = FUJI_BMC_RAM_SIZE; 1628 aspeed_machine_class_init_cpus_defaults(mc); 1629 } 1630 1631 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) 1632 /* Main SYSCLK frequency in Hz (200MHz) */ 1633 #define SYSCLK_FRQ 200000000ULL 1634 aspeed_minibmc_machine_init(MachineState * machine)1635 static void aspeed_minibmc_machine_init(MachineState *machine) 1636 { 1637 AspeedMachineState *bmc = ASPEED_MACHINE(machine); 1638 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); 1639 Clock *sysclk; 1640 1641 sysclk = clock_new(OBJECT(machine), "SYSCLK"); 1642 clock_set_hz(sysclk, SYSCLK_FRQ); 1643 1644 bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); 1645 object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); 1646 object_unref(OBJECT(bmc->soc)); 1647 qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); 1648 1649 object_property_set_link(OBJECT(bmc->soc), "memory", 1650 OBJECT(get_system_memory()), &error_abort); 1651 connect_serial_hds_to_uarts(bmc); 1652 qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); 1653 1654 if (defaults_enabled()) { 1655 aspeed_board_init_flashes(&bmc->soc->fmc, 1656 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, 1657 amc->num_cs, 1658 0); 1659 1660 aspeed_board_init_flashes(&bmc->soc->spi[0], 1661 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1662 amc->num_cs, amc->num_cs); 1663 1664 aspeed_board_init_flashes(&bmc->soc->spi[1], 1665 bmc->spi_model ? bmc->spi_model : amc->spi_model, 1666 amc->num_cs, (amc->num_cs * 2)); 1667 } 1668 1669 if (amc->i2c_init) { 1670 amc->i2c_init(bmc); 1671 } 1672 1673 armv7m_load_kernel(ARM_CPU(first_cpu), 1674 machine->kernel_filename, 1675 0, 1676 AST1030_INTERNAL_FLASH_SIZE); 1677 } 1678 ast1030_evb_i2c_init(AspeedMachineState * bmc)1679 static void ast1030_evb_i2c_init(AspeedMachineState *bmc) 1680 { 1681 AspeedSoCState *soc = bmc->soc; 1682 1683 /* U10 24C08 connects to SDA/SCL Group 1 by default */ 1684 uint8_t *eeprom_buf = g_malloc0(32 * 1024); 1685 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); 1686 1687 /* U11 LM75 connects to SDA/SCL Group 2 by default */ 1688 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); 1689 } 1690 aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass * oc,const void * data)1691 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, 1692 const void *data) 1693 { 1694 MachineClass *mc = MACHINE_CLASS(oc); 1695 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1696 1697 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; 1698 amc->soc_name = "ast1030-a1"; 1699 amc->hw_strap1 = 0; 1700 amc->hw_strap2 = 0; 1701 mc->init = aspeed_minibmc_machine_init; 1702 amc->i2c_init = ast1030_evb_i2c_init; 1703 mc->default_ram_size = 0; 1704 amc->fmc_model = "w25q80bl"; 1705 amc->spi_model = "w25q256"; 1706 amc->num_cs = 2; 1707 amc->macs_mask = 0; 1708 aspeed_machine_class_init_cpus_defaults(mc); 1709 } 1710 1711 #ifdef TARGET_AARCH64 ast2700_evb_i2c_init(AspeedMachineState * bmc)1712 static void ast2700_evb_i2c_init(AspeedMachineState *bmc) 1713 { 1714 AspeedSoCState *soc = bmc->soc; 1715 1716 /* LM75 is compatible with TMP105 driver */ 1717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), 1718 TYPE_TMP105, 0x4d); 1719 } 1720 aspeed_machine_ast2700a0_evb_class_init(ObjectClass * oc,const void * data)1721 static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, 1722 const void *data) 1723 { 1724 MachineClass *mc = MACHINE_CLASS(oc); 1725 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1726 1727 mc->alias = "ast2700-evb"; 1728 mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; 1729 amc->soc_name = "ast2700-a0"; 1730 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1731 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1732 amc->fmc_model = "w25q01jvq"; 1733 amc->spi_model = "w25q512jv"; 1734 amc->num_cs = 2; 1735 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1736 amc->uart_default = ASPEED_DEV_UART12; 1737 amc->i2c_init = ast2700_evb_i2c_init; 1738 amc->vbootrom = true; 1739 mc->auto_create_sdcard = true; 1740 mc->default_ram_size = 1 * GiB; 1741 aspeed_machine_class_init_cpus_defaults(mc); 1742 } 1743 aspeed_machine_ast2700a1_evb_class_init(ObjectClass * oc,const void * data)1744 static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, 1745 const void *data) 1746 { 1747 MachineClass *mc = MACHINE_CLASS(oc); 1748 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1749 1750 mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; 1751 amc->soc_name = "ast2700-a1"; 1752 amc->hw_strap1 = AST2700_EVB_HW_STRAP1; 1753 amc->hw_strap2 = AST2700_EVB_HW_STRAP2; 1754 amc->fmc_model = "w25q01jvq"; 1755 amc->spi_model = "w25q512jv"; 1756 amc->num_cs = 2; 1757 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; 1758 amc->uart_default = ASPEED_DEV_UART12; 1759 amc->i2c_init = ast2700_evb_i2c_init; 1760 amc->vbootrom = true; 1761 mc->auto_create_sdcard = true; 1762 mc->default_ram_size = 1 * GiB; 1763 aspeed_machine_class_init_cpus_defaults(mc); 1764 } 1765 #endif 1766 aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass * oc,const void * data)1767 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, 1768 const void *data) 1769 { 1770 MachineClass *mc = MACHINE_CLASS(oc); 1771 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1772 1773 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)"; 1774 amc->soc_name = "ast2600-a3"; 1775 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1776 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1777 amc->fmc_model = "n25q512a"; 1778 amc->spi_model = "n25q512a"; 1779 amc->num_cs = 2; 1780 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1781 amc->i2c_init = qcom_dc_scm_bmc_i2c_init; 1782 mc->auto_create_sdcard = true; 1783 mc->default_ram_size = 1 * GiB; 1784 aspeed_machine_class_init_cpus_defaults(mc); 1785 }; 1786 aspeed_machine_qcom_firework_class_init(ObjectClass * oc,const void * data)1787 static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, 1788 const void *data) 1789 { 1790 MachineClass *mc = MACHINE_CLASS(oc); 1791 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); 1792 1793 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; 1794 amc->soc_name = "ast2600-a3"; 1795 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; 1796 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; 1797 amc->fmc_model = "n25q512a"; 1798 amc->spi_model = "n25q512a"; 1799 amc->num_cs = 2; 1800 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; 1801 amc->i2c_init = qcom_dc_scm_firework_i2c_init; 1802 mc->auto_create_sdcard = true; 1803 mc->default_ram_size = 1 * GiB; 1804 aspeed_machine_class_init_cpus_defaults(mc); 1805 }; 1806 1807 static const TypeInfo aspeed_machine_types[] = { 1808 { 1809 .name = MACHINE_TYPE_NAME("palmetto-bmc"), 1810 .parent = TYPE_ASPEED_MACHINE, 1811 .class_init = aspeed_machine_palmetto_class_init, 1812 }, { 1813 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), 1814 .parent = TYPE_ASPEED_MACHINE, 1815 .class_init = aspeed_machine_supermicrox11_bmc_class_init, 1816 }, { 1817 .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), 1818 .parent = TYPE_ASPEED_MACHINE, 1819 .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, 1820 }, { 1821 .name = MACHINE_TYPE_NAME("ast2500-evb"), 1822 .parent = TYPE_ASPEED_MACHINE, 1823 .class_init = aspeed_machine_ast2500_evb_class_init, 1824 }, { 1825 .name = MACHINE_TYPE_NAME("romulus-bmc"), 1826 .parent = TYPE_ASPEED_MACHINE, 1827 .class_init = aspeed_machine_romulus_class_init, 1828 }, { 1829 .name = MACHINE_TYPE_NAME("sonorapass-bmc"), 1830 .parent = TYPE_ASPEED_MACHINE, 1831 .class_init = aspeed_machine_sonorapass_class_init, 1832 }, { 1833 .name = MACHINE_TYPE_NAME("witherspoon-bmc"), 1834 .parent = TYPE_ASPEED_MACHINE, 1835 .class_init = aspeed_machine_witherspoon_class_init, 1836 }, { 1837 .name = MACHINE_TYPE_NAME("ast2600-evb"), 1838 .parent = TYPE_ASPEED_MACHINE, 1839 .class_init = aspeed_machine_ast2600_evb_class_init, 1840 }, { 1841 .name = MACHINE_TYPE_NAME("yosemitev2-bmc"), 1842 .parent = TYPE_ASPEED_MACHINE, 1843 .class_init = aspeed_machine_yosemitev2_class_init, 1844 }, { 1845 .name = MACHINE_TYPE_NAME("tiogapass-bmc"), 1846 .parent = TYPE_ASPEED_MACHINE, 1847 .class_init = aspeed_machine_tiogapass_class_init, 1848 }, { 1849 .name = MACHINE_TYPE_NAME("g220a-bmc"), 1850 .parent = TYPE_ASPEED_MACHINE, 1851 .class_init = aspeed_machine_g220a_class_init, 1852 }, { 1853 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), 1854 .parent = TYPE_ASPEED_MACHINE, 1855 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, 1856 }, { 1857 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), 1858 .parent = TYPE_ASPEED_MACHINE, 1859 .class_init = aspeed_machine_qcom_firework_class_init, 1860 }, { 1861 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"), 1862 .parent = TYPE_ASPEED_MACHINE, 1863 .class_init = aspeed_machine_fp5280g2_class_init, 1864 }, { 1865 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), 1866 .parent = TYPE_ASPEED_MACHINE, 1867 .class_init = aspeed_machine_quanta_q71l_class_init, 1868 }, { 1869 .name = MACHINE_TYPE_NAME("rainier-bmc"), 1870 .parent = TYPE_ASPEED_MACHINE, 1871 .class_init = aspeed_machine_rainier_class_init, 1872 }, { 1873 .name = MACHINE_TYPE_NAME("fuji-bmc"), 1874 .parent = TYPE_ASPEED_MACHINE, 1875 .class_init = aspeed_machine_fuji_class_init, 1876 }, { 1877 .name = MACHINE_TYPE_NAME("bletchley-bmc"), 1878 .parent = TYPE_ASPEED_MACHINE, 1879 .class_init = aspeed_machine_bletchley_class_init, 1880 }, { 1881 .name = MACHINE_TYPE_NAME("fby35-bmc"), 1882 .parent = MACHINE_TYPE_NAME("ast2600-evb"), 1883 .class_init = aspeed_machine_fby35_class_init, 1884 }, { 1885 .name = MACHINE_TYPE_NAME("ast1030-evb"), 1886 .parent = TYPE_ASPEED_MACHINE, 1887 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, 1888 #ifdef TARGET_AARCH64 1889 }, { 1890 .name = MACHINE_TYPE_NAME("ast2700a0-evb"), 1891 .parent = TYPE_ASPEED_MACHINE, 1892 .class_init = aspeed_machine_ast2700a0_evb_class_init, 1893 }, { 1894 .name = MACHINE_TYPE_NAME("ast2700a1-evb"), 1895 .parent = TYPE_ASPEED_MACHINE, 1896 .class_init = aspeed_machine_ast2700a1_evb_class_init, 1897 #endif 1898 }, { 1899 .name = TYPE_ASPEED_MACHINE, 1900 .parent = TYPE_MACHINE, 1901 .instance_size = sizeof(AspeedMachineState), 1902 .instance_init = aspeed_machine_instance_init, 1903 .class_size = sizeof(AspeedMachineClass), 1904 .class_init = aspeed_machine_class_init, 1905 .abstract = true, 1906 } 1907 }; 1908 1909 DEFINE_TYPES(aspeed_machine_types) 1910