1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2022 Intel Corporation. All rights reserved.
7 //
8
9 #include <sound/pcm_params.h>
10 #include <sound/sof/ipc4/header.h>
11 #include "sof-audio.h"
12 #include "sof-priv.h"
13 #include "ops.h"
14 #include "ipc4-priv.h"
15 #include "ipc4-topology.h"
16 #include "ipc4-fw-reg.h"
17
sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev * sdev,u32 state,struct ipc4_pipeline_set_state_data * trigger_list)18 static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
19 struct ipc4_pipeline_set_state_data *trigger_list)
20 {
21 struct sof_ipc4_msg msg = {{ 0 }};
22 u32 primary, ipc_size;
23
24 /* trigger a single pipeline */
25 if (trigger_list->count == 1)
26 return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0],
27 state);
28
29 primary = state;
30 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
31 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
32 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
33 msg.primary = primary;
34
35 /* trigger multiple pipelines with a single IPC */
36 msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
37
38 /* ipc_size includes the count and the pipeline IDs for the number of pipelines */
39 ipc_size = sizeof(u32) * (trigger_list->count + 1);
40 msg.data_size = ipc_size;
41 msg.data_ptr = trigger_list;
42
43 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
44 }
45
sof_ipc4_set_pipeline_state(struct snd_sof_dev * sdev,u32 instance_id,u32 state)46 int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state)
47 {
48 struct sof_ipc4_msg msg = {{ 0 }};
49 u32 primary;
50
51 dev_dbg(sdev->dev, "ipc4 set pipeline instance %d state %d", instance_id, state);
52
53 primary = state;
54 primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id);
55 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
56 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
57 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
58
59 msg.primary = primary;
60
61 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
62 }
63 EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
64
sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data * trigger_list,struct snd_sof_widget * pipe_widget,s8 * pipe_priority,bool ascend)65 static void sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data *trigger_list,
66 struct snd_sof_widget *pipe_widget,
67 s8 *pipe_priority, bool ascend)
68 {
69 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
70 int i, j;
71
72 for (i = 0; i < trigger_list->count; i++) {
73 /* add pipeline from low priority to high */
74 if (ascend && pipeline->priority < pipe_priority[i])
75 break;
76 /* add pipeline from high priority to low */
77 else if (!ascend && pipeline->priority > pipe_priority[i])
78 break;
79 }
80
81 for (j = trigger_list->count - 1; j >= i; j--) {
82 trigger_list->pipeline_instance_ids[j + 1] = trigger_list->pipeline_instance_ids[j];
83 pipe_priority[j + 1] = pipe_priority[j];
84 }
85
86 trigger_list->pipeline_instance_ids[i] = pipe_widget->instance_id;
87 trigger_list->count++;
88 pipe_priority[i] = pipeline->priority;
89 }
90
91 static void
sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev * sdev,int state,struct snd_sof_pipeline * spipe,struct ipc4_pipeline_set_state_data * trigger_list,s8 * pipe_priority)92 sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
93 struct snd_sof_pipeline *spipe,
94 struct ipc4_pipeline_set_state_data *trigger_list,
95 s8 *pipe_priority)
96 {
97 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
98 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
99
100 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
101 return;
102
103 switch (state) {
104 case SOF_IPC4_PIPE_RUNNING:
105 /*
106 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
107 * for the first time
108 */
109 if (spipe->started_count == spipe->paused_count)
110 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
111 false);
112 break;
113 case SOF_IPC4_PIPE_RESET:
114 /* RESET if the pipeline is neither running nor paused */
115 if (!spipe->started_count && !spipe->paused_count)
116 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
117 true);
118 break;
119 case SOF_IPC4_PIPE_PAUSED:
120 /* Pause the pipeline only when its started_count is 1 more than paused_count */
121 if (spipe->paused_count == (spipe->started_count - 1))
122 sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
123 true);
124 break;
125 default:
126 break;
127 }
128 }
129
130 static void
sof_ipc4_update_pipeline_state(struct snd_sof_dev * sdev,int state,int cmd,struct snd_sof_pipeline * spipe,struct ipc4_pipeline_set_state_data * trigger_list)131 sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
132 struct snd_sof_pipeline *spipe,
133 struct ipc4_pipeline_set_state_data *trigger_list)
134 {
135 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
136 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
137 int i;
138
139 if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
140 return;
141
142 /* set state for pipeline if it was just triggered */
143 for (i = 0; i < trigger_list->count; i++) {
144 if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) {
145 pipeline->state = state;
146 break;
147 }
148 }
149
150 switch (state) {
151 case SOF_IPC4_PIPE_PAUSED:
152 switch (cmd) {
153 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
154 /*
155 * increment paused_count if the PAUSED is the final state during
156 * the PAUSE trigger
157 */
158 spipe->paused_count++;
159 break;
160 case SNDRV_PCM_TRIGGER_STOP:
161 case SNDRV_PCM_TRIGGER_SUSPEND:
162 /*
163 * decrement started_count if PAUSED is the final state during the
164 * STOP trigger
165 */
166 spipe->started_count--;
167 break;
168 default:
169 break;
170 }
171 break;
172 case SOF_IPC4_PIPE_RUNNING:
173 switch (cmd) {
174 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
175 /* decrement paused_count for RELEASE */
176 spipe->paused_count--;
177 break;
178 case SNDRV_PCM_TRIGGER_START:
179 case SNDRV_PCM_TRIGGER_RESUME:
180 /* increment started_count for START/RESUME */
181 spipe->started_count++;
182 break;
183 default:
184 break;
185 }
186 break;
187 default:
188 break;
189 }
190 }
191
192 /*
193 * The picture below represents the pipeline state machine wrt PCM actions corresponding to the
194 * triggers and ioctls
195 * +---------------+
196 * | |
197 * | INIT |
198 * | |
199 * +-------+-------+
200 * |
201 * |
202 * | START
203 * |
204 * |
205 * +----------------+ +------v-------+ +-------------+
206 * | | START | | HW_FREE | |
207 * | RUNNING <-------------+ PAUSED +--------------> + RESET |
208 * | | PAUSE | | | |
209 * +------+---------+ RELEASE +---------+----+ +-------------+
210 * | ^
211 * | |
212 * | |
213 * | |
214 * | PAUSE |
215 * +---------------------------------+
216 * STOP/SUSPEND
217 *
218 * Note that during system suspend, the suspend trigger is followed by a hw_free in
219 * sof_pcm_trigger(). So, the final state during suspend would be RESET.
220 * Also, since the SOF driver doesn't support full resume, streams would be restarted with the
221 * prepare ioctl before the START trigger.
222 */
223
224 /*
225 * Chained DMA is a special case where there is no processing on
226 * DSP. The samples are just moved over by host side DMA to a single
227 * buffer on DSP and directly from there to link DMA. However, the
228 * model on SOF driver has two notional pipelines, one at host DAI,
229 * and another at link DAI. They both shall have the use_chain_dma
230 * attribute.
231 */
232
sof_ipc4_chain_dma_trigger(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream_pipeline_list * pipeline_list,int state,int cmd)233 static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
234 struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
235 int state, int cmd)
236 {
237 bool allocate, enable, set_fifo_size;
238 struct sof_ipc4_msg msg = {{ 0 }};
239 int i;
240
241 switch (state) {
242 case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
243 allocate = true;
244 enable = true;
245 /*
246 * SOF assumes creation of a new stream from the presence of fifo_size
247 * in the message, so we must leave it out in pause release case.
248 */
249 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
250 set_fifo_size = false;
251 else
252 set_fifo_size = true;
253 break;
254 case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
255 allocate = true;
256 enable = false;
257 set_fifo_size = false;
258 break;
259 case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
260 allocate = false;
261 enable = false;
262 set_fifo_size = false;
263 break;
264 default:
265 dev_err(sdev->dev, "Unexpected state %d", state);
266 return -EINVAL;
267 }
268
269 msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
270 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
271 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
272
273 /*
274 * To set-up the DMA chain, the host DMA ID and SCS setting
275 * are retrieved from the host pipeline configuration. Likewise
276 * the link DMA ID and fifo_size are retrieved from the link
277 * pipeline configuration.
278 */
279 for (i = 0; i < pipeline_list->count; i++) {
280 struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
281 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
282 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
283
284 if (!pipeline->use_chain_dma) {
285 dev_err(sdev->dev,
286 "All pipelines in chained DMA stream should have use_chain_dma attribute set.");
287 return -EINVAL;
288 }
289
290 msg.primary |= pipeline->msg.primary;
291
292 /* Add fifo_size (actually DMA buffer size) field to the message */
293 if (set_fifo_size)
294 msg.extension |= pipeline->msg.extension;
295 }
296
297 if (allocate)
298 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
299
300 if (enable)
301 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
302
303 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
304 }
305
sof_ipc4_trigger_pipelines(struct snd_soc_component * component,struct snd_pcm_substream * substream,int state,int cmd)306 static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
307 struct snd_pcm_substream *substream, int state, int cmd)
308 {
309 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
310 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
311 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
312 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
313 struct ipc4_pipeline_set_state_data *trigger_list;
314 struct snd_sof_widget *pipe_widget;
315 struct sof_ipc4_pipeline *pipeline;
316 struct snd_sof_pipeline *spipe;
317 struct snd_sof_pcm *spcm;
318 u8 *pipe_priority;
319 int ret;
320 int i;
321
322 dev_dbg(sdev->dev, "trigger cmd: %d state: %d\n", cmd, state);
323
324 spcm = snd_sof_find_spcm_dai(component, rtd);
325 if (!spcm)
326 return -EINVAL;
327
328 pipeline_list = &spcm->stream[substream->stream].pipeline_list;
329
330 /* nothing to trigger if the list is empty */
331 if (!pipeline_list->pipelines || !pipeline_list->count)
332 return 0;
333
334 spipe = pipeline_list->pipelines[0];
335 pipe_widget = spipe->pipe_widget;
336 pipeline = pipe_widget->private;
337
338 /*
339 * If use_chain_dma attribute is set we proceed to chained DMA
340 * trigger function that handles the rest for the substream.
341 */
342 if (pipeline->use_chain_dma)
343 return sof_ipc4_chain_dma_trigger(sdev, pipeline_list, state, cmd);
344
345 /* allocate memory for the pipeline data */
346 trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids,
347 pipeline_list->count), GFP_KERNEL);
348 if (!trigger_list)
349 return -ENOMEM;
350
351 pipe_priority = kzalloc(pipeline_list->count, GFP_KERNEL);
352 if (!pipe_priority) {
353 kfree(trigger_list);
354 return -ENOMEM;
355 }
356
357 mutex_lock(&ipc4_data->pipeline_state_mutex);
358
359 /*
360 * IPC4 requires pipelines to be triggered in order starting at the sink and
361 * walking all the way to the source. So traverse the pipeline_list in the order
362 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
363 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
364 * in the pipeline, the order of triggering between the left/right paths will be
365 * indeterministic. But the sink->source trigger order sink->source would still be
366 * guaranteed for each fork independently.
367 */
368 if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
369 for (i = pipeline_list->count - 1; i >= 0; i--) {
370 spipe = pipeline_list->pipelines[i];
371 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
372 pipe_priority);
373 }
374 else
375 for (i = 0; i < pipeline_list->count; i++) {
376 spipe = pipeline_list->pipelines[i];
377 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
378 pipe_priority);
379 }
380
381 /* return if all pipelines are in the requested state already */
382 if (!trigger_list->count) {
383 ret = 0;
384 goto free;
385 }
386
387 /* no need to pause before reset or before pause release */
388 if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
389 goto skip_pause_transition;
390
391 /*
392 * set paused state for pipelines if the final state is PAUSED or when the pipeline
393 * is set to RUNNING for the first time after the PCM is started.
394 */
395 ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
396 if (ret < 0) {
397 dev_err(sdev->dev, "failed to pause all pipelines\n");
398 goto free;
399 }
400
401 /* update PAUSED state for all pipelines just triggered */
402 for (i = 0; i < pipeline_list->count ; i++) {
403 spipe = pipeline_list->pipelines[i];
404 sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
405 trigger_list);
406 }
407
408 /* return if this is the final state */
409 if (state == SOF_IPC4_PIPE_PAUSED)
410 goto free;
411 skip_pause_transition:
412 /* else set the RUNNING/RESET state in the DSP */
413 ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
414 if (ret < 0) {
415 dev_err(sdev->dev, "failed to set final state %d for all pipelines\n", state);
416 /*
417 * workaround: if the firmware is crashed while setting the
418 * pipelines to reset state we must ignore the error code and
419 * reset it to 0.
420 * Since the firmware is crashed we will not send IPC messages
421 * and we are going to see errors printed, but the state of the
422 * widgets will be correct for the next boot.
423 */
424 if (sdev->fw_state != SOF_FW_CRASHED || state != SOF_IPC4_PIPE_RESET)
425 goto free;
426
427 ret = 0;
428 }
429
430 /* update RUNNING/RESET state for all pipelines that were just triggered */
431 for (i = 0; i < pipeline_list->count; i++) {
432 spipe = pipeline_list->pipelines[i];
433 sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
434 }
435
436 free:
437 mutex_unlock(&ipc4_data->pipeline_state_mutex);
438 kfree(trigger_list);
439 kfree(pipe_priority);
440 return ret;
441 }
442
sof_ipc4_pcm_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)443 static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
444 struct snd_pcm_substream *substream, int cmd)
445 {
446 int state;
447
448 /* determine the pipeline state */
449 switch (cmd) {
450 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
451 state = SOF_IPC4_PIPE_PAUSED;
452 break;
453 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
454 case SNDRV_PCM_TRIGGER_RESUME:
455 case SNDRV_PCM_TRIGGER_START:
456 state = SOF_IPC4_PIPE_RUNNING;
457 break;
458 case SNDRV_PCM_TRIGGER_SUSPEND:
459 case SNDRV_PCM_TRIGGER_STOP:
460 state = SOF_IPC4_PIPE_PAUSED;
461 break;
462 default:
463 dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
464 return -EINVAL;
465 }
466
467 /* set the pipeline state */
468 return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
469 }
470
sof_ipc4_pcm_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)471 static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
472 struct snd_pcm_substream *substream)
473 {
474 /* command is not relevant with RESET, so just pass 0 */
475 return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
476 }
477
ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev * sdev,const char * link_name,struct snd_pcm_hw_params * params)478 static void ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
479 struct snd_pcm_hw_params *params)
480 {
481 struct snd_sof_dai_link *slink;
482 struct snd_sof_dai *dai;
483 bool dai_link_found = false;
484 int i;
485
486 list_for_each_entry(slink, &sdev->dai_link_list, list) {
487 if (!strcmp(slink->link->name, link_name)) {
488 dai_link_found = true;
489 break;
490 }
491 }
492
493 if (!dai_link_found)
494 return;
495
496 for (i = 0; i < slink->num_hw_configs; i++) {
497 struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
498
499 if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate)) {
500 /* set current config for all DAI's with matching name */
501 list_for_each_entry(dai, &sdev->dai_list, list)
502 if (!strcmp(slink->link->name, dai->name))
503 dai->current_config = le32_to_cpu(hw_config->id);
504 break;
505 }
506 }
507 }
508
509 /*
510 * Fixup DAI link parameters for sampling rate based on
511 * DAI copier configuration.
512 */
sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev * sdev,struct snd_pcm_hw_params * params,struct sof_ipc4_copier * ipc4_copier)513 static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
514 struct snd_pcm_hw_params *params,
515 struct sof_ipc4_copier *ipc4_copier)
516 {
517 struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
518 struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
519 int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
520 unsigned int fe_rate = params_rate(params);
521 bool fe_be_rate_match = false;
522 bool single_be_rate = true;
523 unsigned int be_rate;
524 int i;
525
526 /*
527 * Copier does not change sampling rate, so we
528 * need to only consider the input pin information.
529 */
530 for (i = 0; i < num_input_formats; i++) {
531 unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
532
533 if (i == 0)
534 be_rate = val;
535 else if (val != be_rate)
536 single_be_rate = false;
537
538 if (val == fe_rate) {
539 fe_be_rate_match = true;
540 break;
541 }
542 }
543
544 /*
545 * If rate is different than FE rate, topology must
546 * contain an SRC. But we do require topology to
547 * define a single rate in the DAI copier config in
548 * this case (FE rate may be variable).
549 */
550 if (!fe_be_rate_match) {
551 if (!single_be_rate) {
552 dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
553 return -EINVAL;
554 }
555
556 rate->min = be_rate;
557 rate->max = rate->min;
558 }
559
560 return 0;
561 }
562
sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)563 static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
564 struct snd_pcm_hw_params *params)
565 {
566 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
567 struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
568 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
569 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
570 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
571 struct sof_ipc4_audio_format *ipc4_fmt;
572 struct sof_ipc4_copier *ipc4_copier;
573 bool single_fmt = false;
574 u32 valid_bits = 0;
575 int dir, ret;
576
577 if (!dai) {
578 dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
579 rtd->dai_link->name);
580 return -EINVAL;
581 }
582
583 ipc4_copier = dai->private;
584 if (!ipc4_copier) {
585 dev_err(component->dev, "%s: No private data found for DAI %s\n",
586 __func__, rtd->dai_link->name);
587 return -EINVAL;
588 }
589
590 for_each_pcm_streams(dir) {
591 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
592
593 if (w) {
594 struct sof_ipc4_available_audio_format *available_fmt =
595 &ipc4_copier->available_fmt;
596 struct snd_sof_widget *swidget = w->dobj.private;
597 struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
598 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
599
600 /* Chain DMA does not use copiers, so no fixup needed */
601 if (pipeline->use_chain_dma)
602 return 0;
603
604 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
605 if (sof_ipc4_copier_is_single_format(sdev,
606 available_fmt->output_pin_fmts,
607 available_fmt->num_output_formats)) {
608 ipc4_fmt = &available_fmt->output_pin_fmts->audio_fmt;
609 single_fmt = true;
610 }
611 } else {
612 if (sof_ipc4_copier_is_single_format(sdev,
613 available_fmt->input_pin_fmts,
614 available_fmt->num_input_formats)) {
615 ipc4_fmt = &available_fmt->input_pin_fmts->audio_fmt;
616 single_fmt = true;
617 }
618 }
619 }
620 }
621
622 ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
623 if (ret)
624 return ret;
625
626 if (single_fmt) {
627 snd_mask_none(fmt);
628 valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(ipc4_fmt->fmt_cfg);
629 dev_dbg(component->dev, "Set %s to %d bit format\n", dai->name, valid_bits);
630 }
631
632 /* Set format if it is specified */
633 switch (valid_bits) {
634 case 16:
635 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
636 break;
637 case 24:
638 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
639 break;
640 case 32:
641 snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);
642 break;
643 default:
644 break;
645 }
646
647 switch (ipc4_copier->dai_type) {
648 case SOF_DAI_INTEL_SSP:
649 ipc4_ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
650 break;
651 default:
652 break;
653 }
654
655 return 0;
656 }
657
sof_ipc4_pcm_free(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm)658 static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
659 {
660 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
661 int stream;
662
663 for_each_pcm_streams(stream) {
664 pipeline_list = &spcm->stream[stream].pipeline_list;
665 kfree(pipeline_list->pipelines);
666 pipeline_list->pipelines = NULL;
667 kfree(spcm->stream[stream].private);
668 spcm->stream[stream].private = NULL;
669 }
670 }
671
sof_ipc4_pcm_setup(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm)672 static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
673 {
674 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
675 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
676 struct sof_ipc4_timestamp_info *stream_info;
677 bool support_info = true;
678 u32 abi_version;
679 u32 abi_offset;
680 int stream;
681
682 abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
683 sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
684 sizeof(abi_version));
685
686 if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
687 support_info = false;
688
689 for_each_pcm_streams(stream) {
690 pipeline_list = &spcm->stream[stream].pipeline_list;
691
692 /* allocate memory for max number of pipeline IDs */
693 pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
694 sizeof(struct snd_sof_widget *), GFP_KERNEL);
695 if (!pipeline_list->pipelines) {
696 sof_ipc4_pcm_free(sdev, spcm);
697 return -ENOMEM;
698 }
699
700 if (!support_info)
701 continue;
702
703 stream_info = kzalloc(sizeof(*stream_info), GFP_KERNEL);
704 if (!stream_info) {
705 sof_ipc4_pcm_free(sdev, spcm);
706 return -ENOMEM;
707 }
708
709 spcm->stream[stream].private = stream_info;
710 }
711
712 return 0;
713 }
714
sof_ipc4_build_time_info(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream * spcm)715 static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *spcm)
716 {
717 struct sof_ipc4_copier *host_copier = NULL;
718 struct sof_ipc4_copier *dai_copier = NULL;
719 struct sof_ipc4_llp_reading_slot llp_slot;
720 struct sof_ipc4_timestamp_info *info;
721 struct snd_soc_dapm_widget *widget;
722 struct snd_sof_dai *dai;
723 int i;
724
725 /* find host & dai to locate info in memory window */
726 for_each_dapm_widgets(spcm->list, i, widget) {
727 struct snd_sof_widget *swidget = widget->dobj.private;
728
729 if (!swidget)
730 continue;
731
732 if (WIDGET_IS_AIF(swidget->widget->id)) {
733 host_copier = swidget->private;
734 } else if (WIDGET_IS_DAI(swidget->widget->id)) {
735 dai = swidget->private;
736 dai_copier = dai->private;
737 }
738 }
739
740 /* both host and dai copier must be valid for time_info */
741 if (!host_copier || !dai_copier) {
742 dev_err(sdev->dev, "host or dai copier are not found\n");
743 return;
744 }
745
746 info = spcm->private;
747 info->host_copier = host_copier;
748 info->dai_copier = dai_copier;
749 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_gpdma_reading_slots) +
750 sdev->fw_info_box.offset;
751
752 /* find llp slot used by current dai */
753 for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
754 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
755 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
756 break;
757
758 info->llp_offset += sizeof(llp_slot);
759 }
760
761 if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
762 return;
763
764 /* if no llp gpdma slot is used, check aggregated sdw slot */
765 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_sndw_reading_slots) +
766 sdev->fw_info_box.offset;
767 for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
768 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
769 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
770 break;
771
772 info->llp_offset += sizeof(llp_slot);
773 }
774
775 if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
776 return;
777
778 /* check EVAD slot */
779 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_evad_reading_slot) +
780 sdev->fw_info_box.offset;
781 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
782 if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id)
783 info->llp_offset = 0;
784 }
785
sof_ipc4_pcm_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_sof_platform_stream_params * platform_params)786 static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
787 struct snd_pcm_substream *substream,
788 struct snd_pcm_hw_params *params,
789 struct snd_sof_platform_stream_params *platform_params)
790 {
791 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
792 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
793 struct sof_ipc4_timestamp_info *time_info;
794 struct snd_sof_pcm *spcm;
795
796 spcm = snd_sof_find_spcm_dai(component, rtd);
797 if (!spcm)
798 return -EINVAL;
799
800 time_info = spcm->stream[substream->stream].private;
801 /* delay calculation is not supported by current fw_reg ABI */
802 if (!time_info)
803 return 0;
804
805 time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
806 time_info->llp_offset = 0;
807
808 sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
809
810 return 0;
811 }
812
sof_ipc4_get_stream_start_offset(struct snd_sof_dev * sdev,struct snd_pcm_substream * substream,struct snd_sof_pcm_stream * stream,struct sof_ipc4_timestamp_info * time_info)813 static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
814 struct snd_pcm_substream *substream,
815 struct snd_sof_pcm_stream *stream,
816 struct sof_ipc4_timestamp_info *time_info)
817 {
818 struct sof_ipc4_copier *host_copier = time_info->host_copier;
819 struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
820 struct sof_ipc4_pipeline_registers ppl_reg;
821 u64 stream_start_position;
822 u32 dai_sample_size;
823 u32 ch, node_index;
824 u32 offset;
825
826 if (!host_copier || !dai_copier)
827 return -EINVAL;
828
829 if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID)
830 return -EINVAL;
831
832 node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
833 offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
834 sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
835 if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
836 return -EINVAL;
837
838 stream_start_position = ppl_reg.stream_start_offset;
839 ch = dai_copier->data.out_format.fmt_cfg;
840 ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
841 dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
842 /* convert offset to sample count */
843 do_div(stream_start_position, dai_sample_size);
844 time_info->stream_start_offset = stream_start_position;
845
846 return 0;
847 }
848
sof_ipc4_pcm_delay(struct snd_soc_component * component,struct snd_pcm_substream * substream)849 static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
850 struct snd_pcm_substream *substream)
851 {
852 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
853 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
854 struct sof_ipc4_timestamp_info *time_info;
855 struct sof_ipc4_llp_reading_slot llp;
856 snd_pcm_uframes_t head_ptr, tail_ptr;
857 struct snd_sof_pcm_stream *stream;
858 struct snd_sof_pcm *spcm;
859 u64 tmp_ptr;
860 int ret;
861
862 spcm = snd_sof_find_spcm_dai(component, rtd);
863 if (!spcm)
864 return 0;
865
866 stream = &spcm->stream[substream->stream];
867 time_info = stream->private;
868 if (!time_info)
869 return 0;
870
871 /*
872 * stream_start_offset is updated to memory window by FW based on
873 * pipeline statistics and it may be invalid if host query happens before
874 * the statistics is complete. And it will not change after the first initiailization.
875 */
876 if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
877 ret = sof_ipc4_get_stream_start_offset(sdev, substream, stream, time_info);
878 if (ret < 0)
879 return 0;
880 }
881
882 /*
883 * HDaudio links don't support the LLP counter reported by firmware
884 * the link position is read directly from hardware registers.
885 */
886 if (!time_info->llp_offset) {
887 tmp_ptr = snd_sof_pcm_get_stream_position(sdev, component, substream);
888 if (!tmp_ptr)
889 return 0;
890 } else {
891 sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
892 tmp_ptr = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
893 }
894
895 /* In two cases dai dma position is not accurate
896 * (1) dai pipeline is started before host pipeline
897 * (2) multiple streams mixed into one. Each stream has the same dai dma position
898 *
899 * Firmware calculates correct stream_start_offset for all cases including above two.
900 * Driver subtracts stream_start_offset from dai dma position to get accurate one
901 */
902 tmp_ptr -= time_info->stream_start_offset;
903
904 /* Calculate the delay taking into account that both pointer can wrap */
905 div64_u64_rem(tmp_ptr, substream->runtime->boundary, &tmp_ptr);
906 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
907 head_ptr = substream->runtime->status->hw_ptr;
908 tail_ptr = tmp_ptr;
909 } else {
910 head_ptr = tmp_ptr;
911 tail_ptr = substream->runtime->status->hw_ptr;
912 }
913
914 if (head_ptr < tail_ptr)
915 return substream->runtime->boundary - tail_ptr + head_ptr;
916
917 return head_ptr - tail_ptr;
918 }
919
920 const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
921 .hw_params = sof_ipc4_pcm_hw_params,
922 .trigger = sof_ipc4_pcm_trigger,
923 .hw_free = sof_ipc4_pcm_hw_free,
924 .dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
925 .pcm_setup = sof_ipc4_pcm_setup,
926 .pcm_free = sof_ipc4_pcm_free,
927 .delay = sof_ipc4_pcm_delay,
928 .ipc_first_on_start = true,
929 .platform_stop_during_hw_free = true,
930 };
931