1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "smu_v14_0_0_ppt.h" 48 #include "smu_v14_0_2_ppt.h" 49 #include "smu_v15_0_0_ppt.h" 50 #include "smu_v15_0_8_ppt.h" 51 #include "amd_pcie.h" 52 53 /* 54 * DO NOT use these for err/warn/info/debug messages. 55 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 56 * They are more MGPU friendly. 57 */ 58 #undef pr_err 59 #undef pr_warn 60 #undef pr_info 61 #undef pr_debug 62 63 static const struct amd_pm_funcs swsmu_pm_funcs; 64 static int smu_force_smuclk_levels(struct smu_context *smu, 65 enum smu_clk_type clk_type, 66 uint32_t mask); 67 static int smu_handle_task(struct smu_context *smu, 68 enum amd_dpm_forced_level level, 69 enum amd_pp_task task_id); 70 static int smu_reset(struct smu_context *smu); 71 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 72 static int smu_set_fan_control_mode(void *handle, u32 value); 73 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); 74 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 75 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 76 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 77 static void smu_power_profile_mode_get(struct smu_context *smu, 78 enum PP_SMC_POWER_PROFILE profile_mode); 79 static void smu_power_profile_mode_put(struct smu_context *smu, 80 enum PP_SMC_POWER_PROFILE profile_mode); 81 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); 82 static int smu_od_edit_dpm_table(void *handle, 83 enum PP_OD_DPM_TABLE_COMMAND type, 84 long *input, uint32_t size); 85 86 static int smu_sys_get_pp_feature_mask(void *handle, 87 char *buf) 88 { 89 struct smu_context *smu = handle; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 return smu_get_pp_feature_mask(smu, buf); 95 } 96 97 static int smu_sys_set_pp_feature_mask(void *handle, 98 uint64_t new_mask) 99 { 100 struct smu_context *smu = handle; 101 102 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 103 return -EOPNOTSUPP; 104 105 return smu_set_pp_feature_mask(smu, new_mask); 106 } 107 108 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 109 { 110 if (!smu->ppt_funcs->set_gfx_off_residency) 111 return -EINVAL; 112 113 return smu_set_gfx_off_residency(smu, value); 114 } 115 116 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 117 { 118 if (!smu->ppt_funcs->get_gfx_off_residency) 119 return -EINVAL; 120 121 return smu_get_gfx_off_residency(smu, value); 122 } 123 124 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 125 { 126 if (!smu->ppt_funcs->get_gfx_off_entrycount) 127 return -EINVAL; 128 129 return smu_get_gfx_off_entrycount(smu, value); 130 } 131 132 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 133 { 134 if (!smu->ppt_funcs->get_gfx_off_status) 135 return -EINVAL; 136 137 *value = smu_get_gfx_off_status(smu); 138 139 return 0; 140 } 141 142 int smu_set_soft_freq_range(struct smu_context *smu, 143 enum pp_clock_type type, 144 uint32_t min, 145 uint32_t max) 146 { 147 enum smu_clk_type clk_type; 148 int ret = 0; 149 150 clk_type = smu_convert_to_smuclk(type); 151 if (clk_type == SMU_CLK_COUNT) 152 return -EINVAL; 153 154 if (smu->ppt_funcs->set_soft_freq_limited_range) 155 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 156 clk_type, 157 min, 158 max, 159 false); 160 161 return ret; 162 } 163 164 int smu_get_dpm_freq_range(struct smu_context *smu, 165 enum smu_clk_type clk_type, 166 uint32_t *min, 167 uint32_t *max) 168 { 169 int ret = -ENOTSUPP; 170 171 if (!min && !max) 172 return -EINVAL; 173 174 if (smu->ppt_funcs->get_dpm_ultimate_freq) 175 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 176 clk_type, 177 min, 178 max); 179 180 return ret; 181 } 182 183 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 184 { 185 int ret = 0; 186 struct amdgpu_device *adev = smu->adev; 187 188 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 189 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 190 if (ret) 191 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 192 } 193 return ret; 194 } 195 196 static u32 smu_get_mclk(void *handle, bool low) 197 { 198 struct smu_context *smu = handle; 199 uint32_t clk_freq; 200 int ret = 0; 201 202 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 203 low ? &clk_freq : NULL, 204 !low ? &clk_freq : NULL); 205 if (ret) 206 return 0; 207 return clk_freq * 100; 208 } 209 210 static u32 smu_get_sclk(void *handle, bool low) 211 { 212 struct smu_context *smu = handle; 213 uint32_t clk_freq; 214 int ret = 0; 215 216 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 217 low ? &clk_freq : NULL, 218 !low ? &clk_freq : NULL); 219 if (ret) 220 return 0; 221 return clk_freq * 100; 222 } 223 224 static int smu_set_gfx_imu_enable(struct smu_context *smu) 225 { 226 struct amdgpu_device *adev = smu->adev; 227 228 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 229 return 0; 230 231 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 232 return 0; 233 234 return smu_set_gfx_power_up_by_imu(smu); 235 } 236 237 static bool is_vcn_enabled(struct amdgpu_device *adev) 238 { 239 int i; 240 241 for (i = 0; i < adev->num_ip_blocks; i++) { 242 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN || 243 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_JPEG) && 244 !adev->ip_blocks[i].status.valid) 245 return false; 246 } 247 248 return true; 249 } 250 251 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 252 bool enable, 253 int inst) 254 { 255 struct smu_power_context *smu_power = &smu->smu_power; 256 struct smu_power_gate *power_gate = &smu_power->power_gate; 257 int ret = 0; 258 259 /* 260 * don't poweron vcn/jpeg when they are skipped. 261 */ 262 if (!is_vcn_enabled(smu->adev)) 263 return 0; 264 265 if (!smu->ppt_funcs->dpm_set_vcn_enable) 266 return 0; 267 268 if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable) 269 return 0; 270 271 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst); 272 if (!ret) 273 atomic_set(&power_gate->vcn_gated[inst], !enable); 274 275 return ret; 276 } 277 278 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 279 bool enable) 280 { 281 struct smu_power_context *smu_power = &smu->smu_power; 282 struct smu_power_gate *power_gate = &smu_power->power_gate; 283 int ret = 0; 284 285 if (!is_vcn_enabled(smu->adev)) 286 return 0; 287 288 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 289 return 0; 290 291 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 292 return 0; 293 294 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 295 if (!ret) 296 atomic_set(&power_gate->jpeg_gated, !enable); 297 298 return ret; 299 } 300 301 static int smu_dpm_set_vpe_enable(struct smu_context *smu, 302 bool enable) 303 { 304 struct smu_power_context *smu_power = &smu->smu_power; 305 struct smu_power_gate *power_gate = &smu_power->power_gate; 306 int ret = 0; 307 308 if (!smu->ppt_funcs->dpm_set_vpe_enable) 309 return 0; 310 311 if (atomic_read(&power_gate->vpe_gated) ^ enable) 312 return 0; 313 314 ret = smu->ppt_funcs->dpm_set_vpe_enable(smu, enable); 315 if (!ret) 316 atomic_set(&power_gate->vpe_gated, !enable); 317 318 return ret; 319 } 320 321 static int smu_dpm_set_isp_enable(struct smu_context *smu, 322 bool enable) 323 { 324 struct smu_power_context *smu_power = &smu->smu_power; 325 struct smu_power_gate *power_gate = &smu_power->power_gate; 326 int ret; 327 328 if (!smu->ppt_funcs->dpm_set_isp_enable) 329 return 0; 330 331 if (atomic_read(&power_gate->isp_gated) ^ enable) 332 return 0; 333 334 ret = smu->ppt_funcs->dpm_set_isp_enable(smu, enable); 335 if (!ret) 336 atomic_set(&power_gate->isp_gated, !enable); 337 338 return ret; 339 } 340 341 static int smu_dpm_set_umsch_mm_enable(struct smu_context *smu, 342 bool enable) 343 { 344 struct smu_power_context *smu_power = &smu->smu_power; 345 struct smu_power_gate *power_gate = &smu_power->power_gate; 346 int ret = 0; 347 348 if (!smu->adev->enable_umsch_mm) 349 return 0; 350 351 if (!smu->ppt_funcs->dpm_set_umsch_mm_enable) 352 return 0; 353 354 if (atomic_read(&power_gate->umsch_mm_gated) ^ enable) 355 return 0; 356 357 ret = smu->ppt_funcs->dpm_set_umsch_mm_enable(smu, enable); 358 if (!ret) 359 atomic_set(&power_gate->umsch_mm_gated, !enable); 360 361 return ret; 362 } 363 364 static int smu_set_mall_enable(struct smu_context *smu) 365 { 366 int ret = 0; 367 368 if (!smu->ppt_funcs->set_mall_enable) 369 return 0; 370 371 ret = smu->ppt_funcs->set_mall_enable(smu); 372 373 return ret; 374 } 375 376 /** 377 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 378 * 379 * @handle: smu_context pointer 380 * @block_type: the IP block to power gate/ungate 381 * @gate: to power gate if true, ungate otherwise 382 * @inst: the instance of the IP block to power gate/ungate 383 * 384 * This API uses no smu->mutex lock protection due to: 385 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 386 * This is guarded to be race condition free by the caller. 387 * 2. Or get called on user setting request of power_dpm_force_performance_level. 388 * Under this case, the smu->mutex lock protection is already enforced on 389 * the parent API smu_force_performance_level of the call path. 390 */ 391 static int smu_dpm_set_power_gate(void *handle, 392 uint32_t block_type, 393 bool gate, 394 int inst) 395 { 396 struct smu_context *smu = handle; 397 int ret = 0; 398 399 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 400 dev_WARN(smu->adev->dev, 401 "SMU uninitialized but power %s requested for %u!\n", 402 gate ? "gate" : "ungate", block_type); 403 return -EOPNOTSUPP; 404 } 405 406 switch (block_type) { 407 /* 408 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 409 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 410 */ 411 case AMD_IP_BLOCK_TYPE_UVD: 412 case AMD_IP_BLOCK_TYPE_VCN: 413 ret = smu_dpm_set_vcn_enable(smu, !gate, inst); 414 if (ret) 415 dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n", 416 gate ? "gate" : "ungate", inst); 417 break; 418 case AMD_IP_BLOCK_TYPE_GFX: 419 ret = smu_gfx_off_control(smu, gate); 420 if (ret) 421 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 422 gate ? "enable" : "disable"); 423 break; 424 case AMD_IP_BLOCK_TYPE_SDMA: 425 ret = smu_powergate_sdma(smu, gate); 426 if (ret) 427 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 428 gate ? "gate" : "ungate"); 429 break; 430 case AMD_IP_BLOCK_TYPE_JPEG: 431 ret = smu_dpm_set_jpeg_enable(smu, !gate); 432 if (ret) 433 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 434 gate ? "gate" : "ungate"); 435 break; 436 case AMD_IP_BLOCK_TYPE_VPE: 437 ret = smu_dpm_set_vpe_enable(smu, !gate); 438 if (ret) 439 dev_err(smu->adev->dev, "Failed to power %s VPE!\n", 440 gate ? "gate" : "ungate"); 441 break; 442 case AMD_IP_BLOCK_TYPE_ISP: 443 ret = smu_dpm_set_isp_enable(smu, !gate); 444 if (ret) 445 dev_err(smu->adev->dev, "Failed to power %s ISP!\n", 446 gate ? "gate" : "ungate"); 447 break; 448 default: 449 dev_err(smu->adev->dev, "Unsupported block type!\n"); 450 return -EINVAL; 451 } 452 453 return ret; 454 } 455 456 /** 457 * smu_set_user_clk_dependencies - set user profile clock dependencies 458 * 459 * @smu: smu_context pointer 460 * @clk: enum smu_clk_type type 461 * 462 * Enable/Disable the clock dependency for the @clk type. 463 */ 464 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 465 { 466 if (smu->adev->in_suspend) 467 return; 468 469 if (clk == SMU_MCLK) { 470 smu->user_dpm_profile.clk_dependency = 0; 471 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 472 } else if (clk == SMU_FCLK) { 473 /* MCLK takes precedence over FCLK */ 474 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 475 return; 476 477 smu->user_dpm_profile.clk_dependency = 0; 478 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 479 } else if (clk == SMU_SOCCLK) { 480 /* MCLK takes precedence over SOCCLK */ 481 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 482 return; 483 484 smu->user_dpm_profile.clk_dependency = 0; 485 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 486 } else 487 /* Add clk dependencies here, if any */ 488 return; 489 } 490 491 /** 492 * smu_restore_dpm_user_profile - reinstate user dpm profile 493 * 494 * @smu: smu_context pointer 495 * 496 * Restore the saved user power configurations include power limit, 497 * clock frequencies, fan control mode and fan speed. 498 */ 499 static void smu_restore_dpm_user_profile(struct smu_context *smu) 500 { 501 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 502 int ret = 0; 503 504 if (!smu->adev->in_suspend) 505 return; 506 507 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 508 return; 509 510 /* Enable restore flag */ 511 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 512 513 /* set the user dpm power limits */ 514 for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { 515 if (!smu->user_dpm_profile.power_limits[i]) 516 continue; 517 ret = smu_set_power_limit(smu, i, 518 smu->user_dpm_profile.power_limits[i]); 519 if (ret) 520 dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); 521 } 522 523 /* set the user dpm clock configurations */ 524 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 525 enum smu_clk_type clk_type; 526 527 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 528 /* 529 * Iterate over smu clk type and force the saved user clk 530 * configs, skip if clock dependency is enabled 531 */ 532 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 533 smu->user_dpm_profile.clk_mask[clk_type]) { 534 ret = smu_force_smuclk_levels(smu, clk_type, 535 smu->user_dpm_profile.clk_mask[clk_type]); 536 if (ret) 537 dev_err(smu->adev->dev, 538 "Failed to set clock type = %d\n", clk_type); 539 } 540 } 541 } 542 543 /* set the user dpm fan configurations */ 544 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 545 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 546 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 547 if (ret != -EOPNOTSUPP) { 548 smu->user_dpm_profile.fan_speed_pwm = 0; 549 smu->user_dpm_profile.fan_speed_rpm = 0; 550 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 551 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 552 } 553 554 if (smu->user_dpm_profile.fan_speed_pwm) { 555 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 556 if (ret != -EOPNOTSUPP) 557 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 558 } 559 560 if (smu->user_dpm_profile.fan_speed_rpm) { 561 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 562 if (ret != -EOPNOTSUPP) 563 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 564 } 565 } 566 567 /* Restore user customized OD settings */ 568 if (smu->user_dpm_profile.user_od) { 569 if (smu->ppt_funcs->restore_user_od_settings) { 570 ret = smu->ppt_funcs->restore_user_od_settings(smu); 571 if (ret) 572 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 573 } 574 } 575 576 /* Disable restore flag */ 577 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 578 } 579 580 static int smu_get_power_num_states(void *handle, 581 struct pp_states_info *state_info) 582 { 583 if (!state_info) 584 return -EINVAL; 585 586 /* not support power state */ 587 memset(state_info, 0, sizeof(struct pp_states_info)); 588 state_info->nums = 1; 589 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 590 591 return 0; 592 } 593 594 bool is_support_sw_smu(struct amdgpu_device *adev) 595 { 596 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 597 if (adev->asic_type == CHIP_VEGA20) 598 return false; 599 600 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && 601 amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) 602 return true; 603 604 return false; 605 } 606 607 bool is_support_cclk_dpm(struct amdgpu_device *adev) 608 { 609 struct smu_context *smu = adev->powerplay.pp_handle; 610 611 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 612 return false; 613 614 return true; 615 } 616 617 int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, 618 uint32_t param, uint32_t *read_arg) 619 { 620 struct smu_context *smu = adev->powerplay.pp_handle; 621 int ret = -EOPNOTSUPP; 622 623 if (!smu) 624 return ret; 625 626 if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) 627 ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); 628 629 return ret; 630 } 631 632 int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, 633 enum smu_feature_mask mask) 634 { 635 struct smu_context *smu = adev->powerplay.pp_handle; 636 int ret = 0; 637 638 if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) 639 ret = smu->ppt_funcs->feature_is_enabled(smu, mask); 640 641 return ret; 642 } 643 644 static int smu_sys_get_pp_table(void *handle, 645 char **table) 646 { 647 struct smu_context *smu = handle; 648 struct smu_table_context *smu_table = &smu->smu_table; 649 650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 651 return -EOPNOTSUPP; 652 653 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 654 return -EOPNOTSUPP; 655 656 if (smu_table->hardcode_pptable) 657 *table = smu_table->hardcode_pptable; 658 else 659 *table = smu_table->power_play_table; 660 661 return smu_table->power_play_table_size; 662 } 663 664 static int smu_sys_set_pp_table(void *handle, 665 const char *buf, 666 size_t size) 667 { 668 struct smu_context *smu = handle; 669 struct smu_table_context *smu_table = &smu->smu_table; 670 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 671 int ret = 0; 672 673 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 674 return -EOPNOTSUPP; 675 676 if (header->usStructureSize != size) { 677 dev_err(smu->adev->dev, "pp table size not matched !\n"); 678 return -EIO; 679 } 680 681 if (!smu_table->hardcode_pptable || smu_table->power_play_table_size < size) { 682 kfree(smu_table->hardcode_pptable); 683 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 684 if (!smu_table->hardcode_pptable) 685 return -ENOMEM; 686 } 687 688 memcpy(smu_table->hardcode_pptable, buf, size); 689 smu_table->power_play_table = smu_table->hardcode_pptable; 690 smu_table->power_play_table_size = size; 691 692 /* 693 * Special hw_fini action(for Navi1x, the DPMs disablement will be 694 * skipped) may be needed for custom pptable uploading. 695 */ 696 smu->uploading_custom_pp_table = true; 697 698 ret = smu_reset(smu); 699 if (ret) 700 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 701 702 smu->uploading_custom_pp_table = false; 703 704 return ret; 705 } 706 707 static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) 708 { 709 /* 710 * With SCPM enabled, the allowed featuremasks setting(via 711 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 712 * That means there is no way to let PMFW knows the settings below. 713 * Thus, we just assume all the features are allowed under 714 * such scenario. 715 */ 716 if (smu->adev->scpm_enabled) { 717 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); 718 return 0; 719 } 720 721 smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); 722 723 return smu_init_allowed_features(smu); 724 } 725 726 static int smu_set_funcs(struct amdgpu_device *adev) 727 { 728 struct smu_context *smu = adev->powerplay.pp_handle; 729 730 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 731 smu->od_enabled = true; 732 733 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 734 case IP_VERSION(11, 0, 0): 735 case IP_VERSION(11, 0, 5): 736 case IP_VERSION(11, 0, 9): 737 navi10_set_ppt_funcs(smu); 738 break; 739 case IP_VERSION(11, 0, 7): 740 case IP_VERSION(11, 0, 11): 741 case IP_VERSION(11, 0, 12): 742 case IP_VERSION(11, 0, 13): 743 sienna_cichlid_set_ppt_funcs(smu); 744 break; 745 case IP_VERSION(12, 0, 0): 746 case IP_VERSION(12, 0, 1): 747 renoir_set_ppt_funcs(smu); 748 break; 749 case IP_VERSION(11, 5, 0): 750 case IP_VERSION(11, 5, 2): 751 vangogh_set_ppt_funcs(smu); 752 break; 753 case IP_VERSION(13, 0, 1): 754 case IP_VERSION(13, 0, 3): 755 case IP_VERSION(13, 0, 8): 756 yellow_carp_set_ppt_funcs(smu); 757 break; 758 case IP_VERSION(13, 0, 4): 759 case IP_VERSION(13, 0, 11): 760 smu_v13_0_4_set_ppt_funcs(smu); 761 break; 762 case IP_VERSION(13, 0, 5): 763 smu_v13_0_5_set_ppt_funcs(smu); 764 break; 765 case IP_VERSION(11, 0, 8): 766 cyan_skillfish_set_ppt_funcs(smu); 767 break; 768 case IP_VERSION(11, 0, 2): 769 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 770 arcturus_set_ppt_funcs(smu); 771 /* OD is not supported on Arcturus */ 772 smu->od_enabled = false; 773 break; 774 case IP_VERSION(13, 0, 2): 775 aldebaran_set_ppt_funcs(smu); 776 /* Enable pp_od_clk_voltage node */ 777 smu->od_enabled = true; 778 break; 779 case IP_VERSION(13, 0, 0): 780 case IP_VERSION(13, 0, 10): 781 smu_v13_0_0_set_ppt_funcs(smu); 782 break; 783 case IP_VERSION(13, 0, 6): 784 case IP_VERSION(13, 0, 14): 785 case IP_VERSION(13, 0, 12): 786 smu_v13_0_6_set_ppt_funcs(smu); 787 /* Enable pp_od_clk_voltage node */ 788 smu->od_enabled = true; 789 break; 790 case IP_VERSION(13, 0, 7): 791 smu_v13_0_7_set_ppt_funcs(smu); 792 break; 793 case IP_VERSION(14, 0, 0): 794 case IP_VERSION(14, 0, 1): 795 case IP_VERSION(14, 0, 4): 796 case IP_VERSION(14, 0, 5): 797 smu_v14_0_0_set_ppt_funcs(smu); 798 break; 799 case IP_VERSION(14, 0, 2): 800 case IP_VERSION(14, 0, 3): 801 smu_v14_0_2_set_ppt_funcs(smu); 802 break; 803 case IP_VERSION(15, 0, 0): 804 smu_v15_0_0_set_ppt_funcs(smu); 805 break; 806 case IP_VERSION(15, 0, 8): 807 smu_v15_0_8_set_ppt_funcs(smu); 808 smu->od_enabled = true; 809 break; 810 default: 811 return -EINVAL; 812 } 813 814 return 0; 815 } 816 817 static int smu_early_init(struct amdgpu_ip_block *ip_block) 818 { 819 struct amdgpu_device *adev = ip_block->adev; 820 struct smu_context *smu; 821 int r; 822 823 smu = kzalloc_obj(struct smu_context); 824 if (!smu) 825 return -ENOMEM; 826 827 smu->adev = adev; 828 smu->pm_enabled = !!amdgpu_dpm; 829 smu->is_apu = false; 830 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 831 smu->smu_baco.platform_support = false; 832 smu->smu_baco.maco_support = false; 833 smu->user_dpm_profile.fan_mode = -1; 834 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 835 836 adev->powerplay.pp_handle = smu; 837 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 838 839 r = smu_set_funcs(adev); 840 if (r) 841 return r; 842 return smu_init_microcode(smu); 843 } 844 845 static int smu_set_default_dpm_table(struct smu_context *smu) 846 { 847 struct amdgpu_device *adev = smu->adev; 848 struct smu_power_context *smu_power = &smu->smu_power; 849 struct smu_power_gate *power_gate = &smu_power->power_gate; 850 int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i; 851 int ret = 0; 852 853 if (!smu->ppt_funcs->set_default_dpm_table) 854 return 0; 855 856 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 857 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 858 vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]); 859 } 860 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 861 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 862 863 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 864 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 865 ret = smu_dpm_set_vcn_enable(smu, true, i); 866 if (ret) 867 return ret; 868 } 869 } 870 871 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 872 ret = smu_dpm_set_jpeg_enable(smu, true); 873 if (ret) 874 goto err_out; 875 } 876 877 ret = smu->ppt_funcs->set_default_dpm_table(smu); 878 if (ret) 879 dev_err(smu->adev->dev, 880 "Failed to setup default dpm clock tables!\n"); 881 882 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) 883 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 884 err_out: 885 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 886 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 887 smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i); 888 } 889 890 return ret; 891 } 892 893 static int smu_apply_default_config_table_settings(struct smu_context *smu) 894 { 895 struct amdgpu_device *adev = smu->adev; 896 int ret = 0; 897 898 ret = smu_get_default_config_table_settings(smu, 899 &adev->pm.config_table); 900 if (ret) 901 return ret; 902 903 return smu_set_config_table(smu, &adev->pm.config_table); 904 } 905 906 static int smu_late_init(struct amdgpu_ip_block *ip_block) 907 { 908 struct amdgpu_device *adev = ip_block->adev; 909 struct smu_context *smu = adev->powerplay.pp_handle; 910 int ret = 0; 911 912 smu_set_fine_grain_gfx_freq_parameters(smu); 913 914 if (!smu->pm_enabled) 915 return 0; 916 917 ret = smu_post_init(smu); 918 if (ret) { 919 dev_err(adev->dev, "Failed to post smu init!\n"); 920 return ret; 921 } 922 923 /* 924 * Explicitly notify PMFW the power mode the system in. Since 925 * the PMFW may boot the ASIC with a different mode. 926 * For those supporting ACDC switch via gpio, PMFW will 927 * handle the switch automatically. Driver involvement 928 * is unnecessary. 929 */ 930 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 931 smu_set_ac_dc(smu); 932 933 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || 934 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) 935 return 0; 936 937 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 938 ret = smu_set_default_od_settings(smu); 939 if (ret) { 940 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 941 return ret; 942 } 943 } 944 945 ret = smu_populate_umd_state_clk(smu); 946 if (ret) { 947 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 948 return ret; 949 } 950 951 ret = smu_get_asic_power_limits(smu, 952 &smu->current_power_limit, 953 &smu->default_power_limit, 954 &smu->max_power_limit, 955 &smu->min_power_limit); 956 if (ret) { 957 dev_err(adev->dev, "Failed to get asic power limits!\n"); 958 return ret; 959 } 960 961 if (!amdgpu_sriov_vf(adev)) 962 smu_get_unique_id(smu); 963 964 smu_get_fan_parameters(smu); 965 966 smu_handle_task(smu, 967 smu->smu_dpm.dpm_level, 968 AMD_PP_TASK_COMPLETE_INIT); 969 970 ret = smu_apply_default_config_table_settings(smu); 971 if (ret && (ret != -EOPNOTSUPP)) { 972 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 973 return ret; 974 } 975 976 smu_restore_dpm_user_profile(smu); 977 978 return 0; 979 } 980 981 static int smu_init_fb_allocations(struct smu_context *smu) 982 { 983 struct amdgpu_device *adev = smu->adev; 984 struct smu_table_context *smu_table = &smu->smu_table; 985 struct smu_table *tables = smu_table->tables; 986 struct smu_table *driver_table = &(smu_table->driver_table); 987 uint32_t max_table_size = 0; 988 int ret, i; 989 990 /* VRAM allocation for tool table */ 991 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 992 ret = amdgpu_bo_create_kernel(adev, 993 tables[SMU_TABLE_PMSTATUSLOG].size, 994 tables[SMU_TABLE_PMSTATUSLOG].align, 995 tables[SMU_TABLE_PMSTATUSLOG].domain, 996 &tables[SMU_TABLE_PMSTATUSLOG].bo, 997 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 998 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 999 if (ret) { 1000 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 1001 return ret; 1002 } 1003 } 1004 1005 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 1006 /* VRAM allocation for driver table */ 1007 for (i = 0; i < SMU_TABLE_COUNT; i++) { 1008 if (tables[i].size == 0) 1009 continue; 1010 1011 /* If one of the tables has VRAM domain restriction, keep it in 1012 * VRAM 1013 */ 1014 if ((tables[i].domain & 1015 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 1016 AMDGPU_GEM_DOMAIN_VRAM) 1017 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 1018 1019 if (i == SMU_TABLE_PMSTATUSLOG) 1020 continue; 1021 1022 if (max_table_size < tables[i].size) 1023 max_table_size = tables[i].size; 1024 } 1025 1026 driver_table->size = max_table_size; 1027 driver_table->align = PAGE_SIZE; 1028 1029 ret = amdgpu_bo_create_kernel(adev, 1030 driver_table->size, 1031 driver_table->align, 1032 driver_table->domain, 1033 &driver_table->bo, 1034 &driver_table->mc_address, 1035 &driver_table->cpu_addr); 1036 if (ret) { 1037 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 1038 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1039 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1040 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1041 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1042 } 1043 1044 return ret; 1045 } 1046 1047 static int smu_fini_fb_allocations(struct smu_context *smu) 1048 { 1049 struct smu_table_context *smu_table = &smu->smu_table; 1050 struct smu_table *tables = smu_table->tables; 1051 struct smu_table *driver_table = &(smu_table->driver_table); 1052 1053 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 1054 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 1055 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 1056 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 1057 1058 amdgpu_bo_free_kernel(&driver_table->bo, 1059 &driver_table->mc_address, 1060 &driver_table->cpu_addr); 1061 1062 return 0; 1063 } 1064 1065 static void smu_update_gpu_addresses(struct smu_context *smu) 1066 { 1067 struct smu_table_context *smu_table = &smu->smu_table; 1068 struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG; 1069 struct smu_table *driver_table = &(smu_table->driver_table); 1070 struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; 1071 1072 if (pm_status_table->bo) 1073 pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo); 1074 if (driver_table->bo) 1075 driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo); 1076 if (dummy_read_1_table->bo) 1077 dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo); 1078 } 1079 1080 /** 1081 * smu_alloc_memory_pool - allocate memory pool in the system memory 1082 * 1083 * @smu: amdgpu_device pointer 1084 * 1085 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 1086 * and DramLogSetDramAddr can notify it changed. 1087 * 1088 * Returns 0 on success, error on failure. 1089 */ 1090 static int smu_alloc_memory_pool(struct smu_context *smu) 1091 { 1092 struct amdgpu_device *adev = smu->adev; 1093 struct smu_table_context *smu_table = &smu->smu_table; 1094 struct smu_table *memory_pool = &smu_table->memory_pool; 1095 uint64_t pool_size = smu->pool_size; 1096 int ret = 0; 1097 1098 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 1099 return ret; 1100 1101 memory_pool->size = pool_size; 1102 memory_pool->align = PAGE_SIZE; 1103 memory_pool->domain = 1104 (adev->pm.smu_debug_mask & SMU_DEBUG_POOL_USE_VRAM) ? 1105 AMDGPU_GEM_DOMAIN_VRAM : 1106 AMDGPU_GEM_DOMAIN_GTT; 1107 1108 switch (pool_size) { 1109 case SMU_MEMORY_POOL_SIZE_256_MB: 1110 case SMU_MEMORY_POOL_SIZE_512_MB: 1111 case SMU_MEMORY_POOL_SIZE_1_GB: 1112 case SMU_MEMORY_POOL_SIZE_2_GB: 1113 ret = amdgpu_bo_create_kernel(adev, 1114 memory_pool->size, 1115 memory_pool->align, 1116 memory_pool->domain, 1117 &memory_pool->bo, 1118 &memory_pool->mc_address, 1119 &memory_pool->cpu_addr); 1120 if (ret) 1121 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 1122 break; 1123 default: 1124 break; 1125 } 1126 1127 return ret; 1128 } 1129 1130 static int smu_free_memory_pool(struct smu_context *smu) 1131 { 1132 struct smu_table_context *smu_table = &smu->smu_table; 1133 struct smu_table *memory_pool = &smu_table->memory_pool; 1134 1135 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 1136 return 0; 1137 1138 amdgpu_bo_free_kernel(&memory_pool->bo, 1139 &memory_pool->mc_address, 1140 &memory_pool->cpu_addr); 1141 1142 memset(memory_pool, 0, sizeof(struct smu_table)); 1143 1144 return 0; 1145 } 1146 1147 static int smu_alloc_dummy_read_table(struct smu_context *smu) 1148 { 1149 struct smu_table_context *smu_table = &smu->smu_table; 1150 struct smu_table *dummy_read_1_table = 1151 &smu_table->dummy_read_1_table; 1152 struct amdgpu_device *adev = smu->adev; 1153 int ret = 0; 1154 1155 if (!dummy_read_1_table->size) 1156 return 0; 1157 1158 ret = amdgpu_bo_create_kernel(adev, 1159 dummy_read_1_table->size, 1160 dummy_read_1_table->align, 1161 dummy_read_1_table->domain, 1162 &dummy_read_1_table->bo, 1163 &dummy_read_1_table->mc_address, 1164 &dummy_read_1_table->cpu_addr); 1165 if (ret) 1166 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 1167 1168 return ret; 1169 } 1170 1171 static void smu_free_dummy_read_table(struct smu_context *smu) 1172 { 1173 struct smu_table_context *smu_table = &smu->smu_table; 1174 struct smu_table *dummy_read_1_table = 1175 &smu_table->dummy_read_1_table; 1176 1177 1178 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 1179 &dummy_read_1_table->mc_address, 1180 &dummy_read_1_table->cpu_addr); 1181 1182 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 1183 } 1184 1185 static int smu_smc_table_sw_init(struct smu_context *smu) 1186 { 1187 int ret; 1188 1189 /** 1190 * Create smu_table structure, and init smc tables such as 1191 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 1192 */ 1193 ret = smu_init_smc_tables(smu); 1194 if (ret) { 1195 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 1196 return ret; 1197 } 1198 1199 /** 1200 * Create smu_power_context structure, and allocate smu_dpm_context and 1201 * context size to fill the smu_power_context data. 1202 */ 1203 ret = smu_init_power(smu); 1204 if (ret) { 1205 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1206 return ret; 1207 } 1208 1209 /* 1210 * allocate vram bos to store smc table contents. 1211 */ 1212 ret = smu_init_fb_allocations(smu); 1213 if (ret) 1214 return ret; 1215 1216 ret = smu_alloc_memory_pool(smu); 1217 if (ret) 1218 return ret; 1219 1220 ret = smu_alloc_dummy_read_table(smu); 1221 if (ret) 1222 return ret; 1223 1224 ret = smu_i2c_init(smu); 1225 if (ret) 1226 return ret; 1227 1228 return 0; 1229 } 1230 1231 static int smu_smc_table_sw_fini(struct smu_context *smu) 1232 { 1233 int ret; 1234 1235 smu_i2c_fini(smu); 1236 1237 smu_free_dummy_read_table(smu); 1238 1239 ret = smu_free_memory_pool(smu); 1240 if (ret) 1241 return ret; 1242 1243 ret = smu_fini_fb_allocations(smu); 1244 if (ret) 1245 return ret; 1246 1247 ret = smu_fini_power(smu); 1248 if (ret) { 1249 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1250 return ret; 1251 } 1252 1253 ret = smu_fini_smc_tables(smu); 1254 if (ret) { 1255 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1256 return ret; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static void smu_throttling_logging_work_fn(struct work_struct *work) 1263 { 1264 struct smu_context *smu = container_of(work, struct smu_context, 1265 throttling_logging_work); 1266 1267 smu_log_thermal_throttling(smu); 1268 } 1269 1270 static void smu_interrupt_work_fn(struct work_struct *work) 1271 { 1272 struct smu_context *smu = container_of(work, struct smu_context, 1273 interrupt_work); 1274 1275 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1276 smu->ppt_funcs->interrupt_work(smu); 1277 } 1278 1279 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1280 { 1281 struct smu_context *smu = 1282 container_of(work, struct smu_context, swctf_delayed_work.work); 1283 struct smu_temperature_range *range = 1284 &smu->thermal_range; 1285 struct amdgpu_device *adev = smu->adev; 1286 uint32_t hotspot_tmp, size; 1287 1288 /* 1289 * If the hotspot temperature is confirmed as below SW CTF setting point 1290 * after the delay enforced, nothing will be done. 1291 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1292 */ 1293 if (range->software_shutdown_temp && 1294 smu->ppt_funcs->read_sensor && 1295 !smu->ppt_funcs->read_sensor(smu, 1296 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1297 &hotspot_tmp, 1298 &size) && 1299 hotspot_tmp / 1000 < range->software_shutdown_temp) 1300 return; 1301 1302 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1303 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1304 orderly_poweroff(true); 1305 } 1306 1307 static void smu_init_xgmi_plpd_mode(struct smu_context *smu) 1308 { 1309 struct smu_dpm_context *dpm_ctxt = &(smu->smu_dpm); 1310 struct smu_dpm_policy_ctxt *policy_ctxt; 1311 struct smu_dpm_policy *policy; 1312 1313 policy = smu_get_pm_policy(smu, PP_PM_POLICY_XGMI_PLPD); 1314 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { 1315 if (policy) 1316 policy->current_level = XGMI_PLPD_DEFAULT; 1317 return; 1318 } 1319 1320 /* PMFW put PLPD into default policy after enabling the feature */ 1321 if (smu_feature_is_enabled(smu, 1322 SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT)) { 1323 if (policy) 1324 policy->current_level = XGMI_PLPD_DEFAULT; 1325 } else { 1326 policy_ctxt = dpm_ctxt->dpm_policies; 1327 if (policy_ctxt) 1328 policy_ctxt->policy_mask &= 1329 ~BIT(PP_PM_POLICY_XGMI_PLPD); 1330 } 1331 } 1332 1333 static void smu_init_power_profile(struct smu_context *smu) 1334 { 1335 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) 1336 smu->power_profile_mode = 1337 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1338 smu_power_profile_mode_get(smu, smu->power_profile_mode); 1339 } 1340 1341 void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1342 { 1343 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1344 1345 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1346 return; 1347 1348 set_bit(fea_id, fea_cap->cap_map); 1349 } 1350 1351 bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) 1352 { 1353 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1354 1355 if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) 1356 return false; 1357 1358 return test_bit(fea_id, fea_cap->cap_map); 1359 } 1360 1361 static void smu_feature_cap_init(struct smu_context *smu) 1362 { 1363 struct smu_feature_cap *fea_cap = &smu->fea_cap; 1364 1365 bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); 1366 } 1367 1368 static int smu_sw_init(struct amdgpu_ip_block *ip_block) 1369 { 1370 struct amdgpu_device *adev = ip_block->adev; 1371 struct smu_context *smu = adev->powerplay.pp_handle; 1372 int i, ret; 1373 1374 smu->pool_size = adev->pm.smu_prv_buffer_size; 1375 smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); 1376 1377 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1378 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1379 atomic64_set(&smu->throttle_int_counter, 0); 1380 smu->watermarks_bitmap = 0; 1381 1382 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1383 atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1); 1384 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1385 atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); 1386 atomic_set(&smu->smu_power.power_gate.isp_gated, 1); 1387 atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); 1388 1389 smu_init_power_profile(smu); 1390 smu->display_config = &adev->pm.pm_display_cfg; 1391 1392 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1393 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1394 1395 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1396 smu_swctf_delayed_work_handler); 1397 1398 smu_feature_cap_init(smu); 1399 1400 ret = smu_smc_table_sw_init(smu); 1401 if (ret) { 1402 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1403 return ret; 1404 } 1405 1406 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1407 ret = smu_get_vbios_bootup_values(smu); 1408 if (ret) { 1409 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1410 return ret; 1411 } 1412 1413 ret = smu_init_pptable_microcode(smu); 1414 if (ret) { 1415 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1416 return ret; 1417 } 1418 1419 ret = smu_register_irq_handler(smu); 1420 if (ret) { 1421 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1422 return ret; 1423 } 1424 1425 /* If there is no way to query fan control mode, fan control is not supported */ 1426 if (!smu->ppt_funcs->get_fan_control_mode) 1427 smu->adev->pm.no_fan = true; 1428 1429 return 0; 1430 } 1431 1432 static int smu_sw_fini(struct amdgpu_ip_block *ip_block) 1433 { 1434 struct amdgpu_device *adev = ip_block->adev; 1435 struct smu_context *smu = adev->powerplay.pp_handle; 1436 int ret; 1437 1438 ret = smu_smc_table_sw_fini(smu); 1439 if (ret) { 1440 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1441 return ret; 1442 } 1443 1444 if (smu->custom_profile_params) { 1445 kfree(smu->custom_profile_params); 1446 smu->custom_profile_params = NULL; 1447 } 1448 1449 smu_fini_microcode(smu); 1450 1451 return 0; 1452 } 1453 1454 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1455 { 1456 struct amdgpu_device *adev = smu->adev; 1457 struct smu_temperature_range *range = 1458 &smu->thermal_range; 1459 int ret = 0; 1460 1461 if (!smu->ppt_funcs->get_thermal_temperature_range) 1462 return 0; 1463 1464 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1465 if (ret) 1466 return ret; 1467 1468 adev->pm.dpm.thermal.min_temp = range->min; 1469 adev->pm.dpm.thermal.max_temp = range->max; 1470 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1471 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1472 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1473 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1474 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1475 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1476 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1477 1478 return ret; 1479 } 1480 1481 /** 1482 * smu_wbrf_handle_exclusion_ranges - consume the wbrf exclusion ranges 1483 * 1484 * @smu: smu_context pointer 1485 * 1486 * Retrieve the wbrf exclusion ranges and send them to PMFW for proper handling. 1487 * Returns 0 on success, error on failure. 1488 */ 1489 static int smu_wbrf_handle_exclusion_ranges(struct smu_context *smu) 1490 { 1491 struct wbrf_ranges_in_out wbrf_exclusion = {0}; 1492 struct freq_band_range *wifi_bands = wbrf_exclusion.band_list; 1493 struct amdgpu_device *adev = smu->adev; 1494 uint32_t num_of_wbrf_ranges = MAX_NUM_OF_WBRF_RANGES; 1495 uint64_t start, end; 1496 int ret, i, j; 1497 1498 ret = amd_wbrf_retrieve_freq_band(adev->dev, &wbrf_exclusion); 1499 if (ret) { 1500 dev_err(adev->dev, "Failed to retrieve exclusion ranges!\n"); 1501 return ret; 1502 } 1503 1504 /* 1505 * The exclusion ranges array we got might be filled with holes and duplicate 1506 * entries. For example: 1507 * {(2400, 2500), (0, 0), (6882, 6962), (2400, 2500), (0, 0), (6117, 6189), (0, 0)...} 1508 * We need to do some sortups to eliminate those holes and duplicate entries. 1509 * Expected output: {(2400, 2500), (6117, 6189), (6882, 6962), (0, 0)...} 1510 */ 1511 for (i = 0; i < num_of_wbrf_ranges; i++) { 1512 start = wifi_bands[i].start; 1513 end = wifi_bands[i].end; 1514 1515 /* get the last valid entry to fill the intermediate hole */ 1516 if (!start && !end) { 1517 for (j = num_of_wbrf_ranges - 1; j > i; j--) 1518 if (wifi_bands[j].start && wifi_bands[j].end) 1519 break; 1520 1521 /* no valid entry left */ 1522 if (j <= i) 1523 break; 1524 1525 start = wifi_bands[i].start = wifi_bands[j].start; 1526 end = wifi_bands[i].end = wifi_bands[j].end; 1527 wifi_bands[j].start = 0; 1528 wifi_bands[j].end = 0; 1529 num_of_wbrf_ranges = j; 1530 } 1531 1532 /* eliminate duplicate entries */ 1533 for (j = i + 1; j < num_of_wbrf_ranges; j++) { 1534 if ((wifi_bands[j].start == start) && (wifi_bands[j].end == end)) { 1535 wifi_bands[j].start = 0; 1536 wifi_bands[j].end = 0; 1537 } 1538 } 1539 } 1540 1541 /* Send the sorted wifi_bands to PMFW */ 1542 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1543 /* Try to set the wifi_bands again */ 1544 if (unlikely(ret == -EBUSY)) { 1545 mdelay(5); 1546 ret = smu_set_wbrf_exclusion_ranges(smu, wifi_bands); 1547 } 1548 1549 return ret; 1550 } 1551 1552 /** 1553 * smu_wbrf_event_handler - handle notify events 1554 * 1555 * @nb: notifier block 1556 * @action: event type 1557 * @_arg: event data 1558 * 1559 * Calls relevant amdgpu function in response to wbrf event 1560 * notification from kernel. 1561 */ 1562 static int smu_wbrf_event_handler(struct notifier_block *nb, 1563 unsigned long action, void *_arg) 1564 { 1565 struct smu_context *smu = container_of(nb, struct smu_context, wbrf_notifier); 1566 1567 switch (action) { 1568 case WBRF_CHANGED: 1569 schedule_delayed_work(&smu->wbrf_delayed_work, 1570 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1571 break; 1572 default: 1573 return NOTIFY_DONE; 1574 } 1575 1576 return NOTIFY_OK; 1577 } 1578 1579 /** 1580 * smu_wbrf_delayed_work_handler - callback on delayed work timer expired 1581 * 1582 * @work: struct work_struct pointer 1583 * 1584 * Flood is over and driver will consume the latest exclusion ranges. 1585 */ 1586 static void smu_wbrf_delayed_work_handler(struct work_struct *work) 1587 { 1588 struct smu_context *smu = container_of(work, struct smu_context, wbrf_delayed_work.work); 1589 1590 smu_wbrf_handle_exclusion_ranges(smu); 1591 } 1592 1593 /** 1594 * smu_wbrf_support_check - check wbrf support 1595 * 1596 * @smu: smu_context pointer 1597 * 1598 * Verifies the ACPI interface whether wbrf is supported. 1599 */ 1600 static void smu_wbrf_support_check(struct smu_context *smu) 1601 { 1602 struct amdgpu_device *adev = smu->adev; 1603 1604 smu->wbrf_supported = smu_is_asic_wbrf_supported(smu) && amdgpu_wbrf && 1605 acpi_amd_wbrf_supported_consumer(adev->dev); 1606 1607 if (smu->wbrf_supported) 1608 dev_info(adev->dev, "RF interference mitigation is supported\n"); 1609 } 1610 1611 /** 1612 * smu_wbrf_init - init driver wbrf support 1613 * 1614 * @smu: smu_context pointer 1615 * 1616 * Verifies the AMD ACPI interfaces and registers with the wbrf 1617 * notifier chain if wbrf feature is supported. 1618 * Returns 0 on success, error on failure. 1619 */ 1620 static int smu_wbrf_init(struct smu_context *smu) 1621 { 1622 int ret; 1623 1624 if (!smu->wbrf_supported) 1625 return 0; 1626 1627 INIT_DELAYED_WORK(&smu->wbrf_delayed_work, smu_wbrf_delayed_work_handler); 1628 1629 smu->wbrf_notifier.notifier_call = smu_wbrf_event_handler; 1630 ret = amd_wbrf_register_notifier(&smu->wbrf_notifier); 1631 if (ret) 1632 return ret; 1633 1634 /* 1635 * Some wifiband exclusion ranges may be already there 1636 * before our driver loaded. To make sure our driver 1637 * is awared of those exclusion ranges. 1638 */ 1639 schedule_delayed_work(&smu->wbrf_delayed_work, 1640 msecs_to_jiffies(SMU_WBRF_EVENT_HANDLING_PACE)); 1641 1642 return 0; 1643 } 1644 1645 /** 1646 * smu_wbrf_fini - tear down driver wbrf support 1647 * 1648 * @smu: smu_context pointer 1649 * 1650 * Unregisters with the wbrf notifier chain. 1651 */ 1652 static void smu_wbrf_fini(struct smu_context *smu) 1653 { 1654 if (!smu->wbrf_supported) 1655 return; 1656 1657 amd_wbrf_unregister_notifier(&smu->wbrf_notifier); 1658 1659 cancel_delayed_work_sync(&smu->wbrf_delayed_work); 1660 } 1661 1662 static int smu_smc_hw_setup(struct smu_context *smu) 1663 { 1664 struct amdgpu_device *adev = smu->adev; 1665 uint8_t pcie_gen = 0, pcie_width = 0; 1666 struct smu_feature_bits features_supported; 1667 int ret = 0; 1668 1669 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1670 case IP_VERSION(11, 0, 7): 1671 case IP_VERSION(11, 0, 11): 1672 case IP_VERSION(11, 5, 0): 1673 case IP_VERSION(11, 5, 2): 1674 case IP_VERSION(11, 0, 12): 1675 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1676 dev_info(adev->dev, "dpm has been enabled\n"); 1677 ret = smu_system_features_control(smu, true); 1678 if (ret) { 1679 dev_err(adev->dev, "Failed system features control!\n"); 1680 return ret; 1681 } 1682 1683 return smu_enable_thermal_alert(smu); 1684 } 1685 break; 1686 default: 1687 break; 1688 } 1689 1690 ret = smu_init_display_count(smu, 0); 1691 if (ret) { 1692 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1693 return ret; 1694 } 1695 1696 ret = smu_set_driver_table_location(smu); 1697 if (ret) { 1698 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1699 return ret; 1700 } 1701 1702 /* 1703 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1704 */ 1705 ret = smu_set_tool_table_location(smu); 1706 if (ret) { 1707 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1708 return ret; 1709 } 1710 1711 /* 1712 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1713 * pool location. 1714 */ 1715 ret = smu_notify_memory_pool_location(smu); 1716 if (ret) { 1717 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1718 return ret; 1719 } 1720 1721 /* 1722 * It is assumed the pptable used before runpm is same as 1723 * the one used afterwards. Thus, we can reuse the stored 1724 * copy and do not need to resetup the pptable again. 1725 */ 1726 if (!adev->in_runpm) { 1727 ret = smu_setup_pptable(smu); 1728 if (ret) { 1729 dev_err(adev->dev, "Failed to setup pptable!\n"); 1730 return ret; 1731 } 1732 } 1733 1734 /* smu_dump_pptable(smu); */ 1735 1736 /* 1737 * With SCPM enabled, PSP is responsible for the PPTable transferring 1738 * (to SMU). Driver involvement is not needed and permitted. 1739 */ 1740 if (!adev->scpm_enabled) { 1741 /* 1742 * Copy pptable bo in the vram to smc with SMU MSGs such as 1743 * SetDriverDramAddr and TransferTableDram2Smu. 1744 */ 1745 ret = smu_write_pptable(smu); 1746 if (ret) { 1747 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1748 return ret; 1749 } 1750 } 1751 1752 /* issue Run*Btc msg */ 1753 ret = smu_run_btc(smu); 1754 if (ret) 1755 return ret; 1756 1757 /* Enable UclkShadow on wbrf supported */ 1758 if (smu->wbrf_supported) { 1759 ret = smu_enable_uclk_shadow(smu, true); 1760 if (ret) { 1761 dev_err(adev->dev, "Failed to enable UclkShadow feature to support wbrf!\n"); 1762 return ret; 1763 } 1764 } 1765 1766 /* 1767 * With SCPM enabled, these actions(and relevant messages) are 1768 * not needed and permitted. 1769 */ 1770 if (!adev->scpm_enabled) { 1771 ret = smu_feature_set_allowed_mask(smu); 1772 if (ret) { 1773 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1774 return ret; 1775 } 1776 } 1777 1778 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) 1779 pcie_gen = 4; 1780 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1781 pcie_gen = 3; 1782 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1783 pcie_gen = 2; 1784 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1785 pcie_gen = 1; 1786 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1787 pcie_gen = 0; 1788 1789 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1790 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1791 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1792 */ 1793 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) 1794 pcie_width = 7; 1795 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1796 pcie_width = 6; 1797 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1798 pcie_width = 5; 1799 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1800 pcie_width = 4; 1801 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1802 pcie_width = 3; 1803 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1804 pcie_width = 2; 1805 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1806 pcie_width = 1; 1807 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1808 if (ret) { 1809 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1810 return ret; 1811 } 1812 1813 ret = smu_system_features_control(smu, true); 1814 if (ret) { 1815 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1816 return ret; 1817 } 1818 1819 smu_init_xgmi_plpd_mode(smu); 1820 1821 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1822 if (ret) { 1823 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1824 return ret; 1825 } 1826 smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, 1827 features_supported.bits); 1828 1829 if (!smu_is_dpm_running(smu)) 1830 dev_info(adev->dev, "dpm has been disabled\n"); 1831 1832 /* 1833 * Set initialized values (get from vbios) to dpm tables context such as 1834 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1835 * type of clks. 1836 */ 1837 ret = smu_set_default_dpm_table(smu); 1838 if (ret) { 1839 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1840 return ret; 1841 } 1842 1843 ret = smu_get_thermal_temperature_range(smu); 1844 if (ret) { 1845 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1846 return ret; 1847 } 1848 1849 ret = smu_enable_thermal_alert(smu); 1850 if (ret) { 1851 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1852 return ret; 1853 } 1854 1855 ret = smu_notify_display_change(smu); 1856 if (ret) { 1857 dev_err(adev->dev, "Failed to notify display change!\n"); 1858 return ret; 1859 } 1860 1861 /* 1862 * Set min deep sleep dce fclk with bootup value from vbios via 1863 * SetMinDeepSleepDcefclk MSG. 1864 */ 1865 ret = smu_set_min_dcef_deep_sleep(smu, 1866 smu->smu_table.boot_values.dcefclk / 100); 1867 if (ret) { 1868 dev_err(adev->dev, "Error setting min deepsleep dcefclk\n"); 1869 return ret; 1870 } 1871 1872 /* Init wbrf support. Properly setup the notifier */ 1873 ret = smu_wbrf_init(smu); 1874 if (ret) 1875 dev_err(adev->dev, "Error during wbrf init call\n"); 1876 1877 return ret; 1878 } 1879 1880 static int smu_start_smc_engine(struct smu_context *smu) 1881 { 1882 struct amdgpu_device *adev = smu->adev; 1883 int ret = 0; 1884 1885 if (amdgpu_virt_xgmi_migrate_enabled(adev)) 1886 smu_update_gpu_addresses(smu); 1887 1888 smu->smc_fw_state = SMU_FW_INIT; 1889 1890 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1891 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { 1892 if (smu->ppt_funcs->load_microcode) { 1893 ret = smu->ppt_funcs->load_microcode(smu); 1894 if (ret) 1895 return ret; 1896 } 1897 } 1898 } 1899 1900 if (smu->ppt_funcs->check_fw_status) { 1901 ret = smu->ppt_funcs->check_fw_status(smu); 1902 if (ret) { 1903 dev_err(adev->dev, "SMC is not ready\n"); 1904 return ret; 1905 } 1906 } 1907 1908 /* 1909 * Send msg GetDriverIfVersion to check if the return value is equal 1910 * with DRIVER_IF_VERSION of smc header. 1911 */ 1912 ret = smu_check_fw_version(smu); 1913 if (ret) 1914 return ret; 1915 1916 return ret; 1917 } 1918 1919 static int smu_hw_init(struct amdgpu_ip_block *ip_block) 1920 { 1921 int i, ret; 1922 struct amdgpu_device *adev = ip_block->adev; 1923 struct smu_context *smu = adev->powerplay.pp_handle; 1924 1925 if (amdgpu_sriov_multi_vf_mode(adev)) { 1926 smu->pm_enabled = false; 1927 return 0; 1928 } 1929 1930 ret = smu_start_smc_engine(smu); 1931 if (ret) { 1932 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1933 return ret; 1934 } 1935 1936 /* 1937 * Check whether wbrf is supported. This needs to be done 1938 * before SMU setup starts since part of SMU configuration 1939 * relies on this. 1940 */ 1941 smu_wbrf_support_check(smu); 1942 1943 if (smu->is_apu) { 1944 ret = smu_set_gfx_imu_enable(smu); 1945 if (ret) 1946 return ret; 1947 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1948 smu_dpm_set_vcn_enable(smu, true, i); 1949 smu_dpm_set_jpeg_enable(smu, true); 1950 smu_dpm_set_umsch_mm_enable(smu, true); 1951 smu_set_mall_enable(smu); 1952 smu_set_gfx_cgpg(smu, true); 1953 } 1954 1955 if (!smu->pm_enabled) 1956 return 0; 1957 1958 ret = smu_init_driver_allowed_feature_mask(smu); 1959 if (ret) 1960 return ret; 1961 1962 ret = smu_smc_hw_setup(smu); 1963 if (ret) { 1964 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1965 return ret; 1966 } 1967 1968 /* 1969 * Move maximum sustainable clock retrieving here considering 1970 * 1. It is not needed on resume(from S3). 1971 * 2. DAL settings come between .hw_init and .late_init of SMU. 1972 * And DAL needs to know the maximum sustainable clocks. Thus 1973 * it cannot be put in .late_init(). 1974 */ 1975 ret = smu_init_max_sustainable_clocks(smu); 1976 if (ret) { 1977 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1978 return ret; 1979 } 1980 1981 adev->pm.dpm_enabled = true; 1982 1983 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1984 1985 return 0; 1986 } 1987 1988 static int smu_disable_dpms(struct smu_context *smu) 1989 { 1990 struct amdgpu_device *adev = smu->adev; 1991 int ret = 0; 1992 bool use_baco = !smu->is_apu && 1993 ((amdgpu_in_reset(adev) && 1994 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1995 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1996 1997 /* 1998 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1999 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 2000 */ 2001 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2002 case IP_VERSION(13, 0, 0): 2003 case IP_VERSION(13, 0, 7): 2004 case IP_VERSION(13, 0, 10): 2005 case IP_VERSION(14, 0, 2): 2006 case IP_VERSION(14, 0, 3): 2007 return 0; 2008 default: 2009 break; 2010 } 2011 2012 /* 2013 * For custom pptable uploading, skip the DPM features 2014 * disable process on Navi1x ASICs. 2015 * - As the gfx related features are under control of 2016 * RLC on those ASICs. RLC reinitialization will be 2017 * needed to reenable them. That will cost much more 2018 * efforts. 2019 * 2020 * - SMU firmware can handle the DPM reenablement 2021 * properly. 2022 */ 2023 if (smu->uploading_custom_pp_table) { 2024 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2025 case IP_VERSION(11, 0, 0): 2026 case IP_VERSION(11, 0, 5): 2027 case IP_VERSION(11, 0, 9): 2028 case IP_VERSION(11, 0, 7): 2029 case IP_VERSION(11, 0, 11): 2030 case IP_VERSION(11, 5, 0): 2031 case IP_VERSION(11, 5, 2): 2032 case IP_VERSION(11, 0, 12): 2033 case IP_VERSION(11, 0, 13): 2034 return 0; 2035 default: 2036 break; 2037 } 2038 } 2039 2040 /* 2041 * For Sienna_Cichlid, PMFW will handle the features disablement properly 2042 * on BACO in. Driver involvement is unnecessary. 2043 */ 2044 if (use_baco) { 2045 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2046 case IP_VERSION(11, 0, 7): 2047 case IP_VERSION(11, 0, 0): 2048 case IP_VERSION(11, 0, 5): 2049 case IP_VERSION(11, 0, 9): 2050 case IP_VERSION(13, 0, 7): 2051 return 0; 2052 default: 2053 break; 2054 } 2055 } 2056 2057 /* 2058 * For GFX11 and subsequent APUs, PMFW will handle the features disablement properly 2059 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 2060 */ 2061 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) >= 11 && 2062 smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) 2063 return 0; 2064 2065 /* vangogh s0ix */ 2066 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || 2067 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && 2068 adev->in_s0ix) 2069 return 0; 2070 2071 /* 2072 * For gpu reset, runpm and hibernation through BACO, 2073 * BACO feature has to be kept enabled. 2074 */ 2075 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 2076 ret = smu_disable_all_features_with_exception(smu, 2077 SMU_FEATURE_BACO_BIT); 2078 if (ret) 2079 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 2080 } else { 2081 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 2082 if (!adev->scpm_enabled) { 2083 ret = smu_system_features_control(smu, false); 2084 if (ret) 2085 dev_err(adev->dev, "Failed to disable smu features.\n"); 2086 } 2087 } 2088 2089 /* Notify SMU RLC is going to be off, stop RLC and SMU interaction. 2090 * otherwise SMU will hang while interacting with RLC if RLC is halted 2091 * this is a WA for Vangogh asic which fix the SMU hang issue. 2092 */ 2093 ret = smu_notify_rlc_state(smu, false); 2094 if (ret) { 2095 dev_err(adev->dev, "Fail to notify rlc status!\n"); 2096 return ret; 2097 } 2098 2099 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2) && 2100 !((adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs) && 2101 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 2102 adev->gfx.rlc.funcs->stop(adev); 2103 2104 return ret; 2105 } 2106 2107 static int smu_smc_hw_cleanup(struct smu_context *smu) 2108 { 2109 struct amdgpu_device *adev = smu->adev; 2110 int ret = 0; 2111 2112 smu_wbrf_fini(smu); 2113 2114 cancel_work_sync(&smu->throttling_logging_work); 2115 cancel_work_sync(&smu->interrupt_work); 2116 2117 ret = smu_disable_thermal_alert(smu); 2118 if (ret) { 2119 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 2120 return ret; 2121 } 2122 2123 cancel_delayed_work_sync(&smu->swctf_delayed_work); 2124 2125 ret = smu_disable_dpms(smu); 2126 if (ret) { 2127 dev_err(adev->dev, "Fail to disable dpm features!\n"); 2128 return ret; 2129 } 2130 2131 return 0; 2132 } 2133 2134 static int smu_reset_mp1_state(struct smu_context *smu) 2135 { 2136 struct amdgpu_device *adev = smu->adev; 2137 int ret = 0; 2138 2139 if ((!adev->in_runpm) && (!adev->in_suspend) && 2140 (!amdgpu_in_reset(adev)) && !smu->is_apu && 2141 amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) 2142 ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 2143 2144 return ret; 2145 } 2146 2147 static int smu_hw_fini(struct amdgpu_ip_block *ip_block) 2148 { 2149 struct amdgpu_device *adev = ip_block->adev; 2150 struct smu_context *smu = adev->powerplay.pp_handle; 2151 int i, ret; 2152 2153 if (amdgpu_sriov_multi_vf_mode(adev)) 2154 return 0; 2155 2156 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2157 smu_dpm_set_vcn_enable(smu, false, i); 2158 adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE; 2159 } 2160 smu_dpm_set_jpeg_enable(smu, false); 2161 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 2162 smu_dpm_set_umsch_mm_enable(smu, false); 2163 2164 if (!smu->pm_enabled) 2165 return 0; 2166 2167 adev->pm.dpm_enabled = false; 2168 2169 ret = smu_smc_hw_cleanup(smu); 2170 if (ret) 2171 return ret; 2172 2173 ret = smu_reset_mp1_state(smu); 2174 if (ret) 2175 return ret; 2176 2177 return 0; 2178 } 2179 2180 static void smu_late_fini(struct amdgpu_ip_block *ip_block) 2181 { 2182 struct amdgpu_device *adev = ip_block->adev; 2183 struct smu_context *smu = adev->powerplay.pp_handle; 2184 2185 kfree(smu); 2186 } 2187 2188 static int smu_reset(struct smu_context *smu) 2189 { 2190 struct amdgpu_device *adev = smu->adev; 2191 struct amdgpu_ip_block *ip_block; 2192 int ret; 2193 2194 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); 2195 if (!ip_block) 2196 return -EINVAL; 2197 2198 ret = smu_hw_fini(ip_block); 2199 if (ret) 2200 return ret; 2201 2202 ret = smu_hw_init(ip_block); 2203 if (ret) 2204 return ret; 2205 2206 ret = smu_late_init(ip_block); 2207 if (ret) 2208 return ret; 2209 2210 return 0; 2211 } 2212 2213 static int smu_suspend(struct amdgpu_ip_block *ip_block) 2214 { 2215 struct amdgpu_device *adev = ip_block->adev; 2216 struct smu_context *smu = adev->powerplay.pp_handle; 2217 int ret; 2218 uint64_t count; 2219 2220 if (amdgpu_sriov_multi_vf_mode(adev)) 2221 return 0; 2222 2223 if (!smu->pm_enabled) 2224 return 0; 2225 2226 adev->pm.dpm_enabled = false; 2227 2228 ret = smu_smc_hw_cleanup(smu); 2229 if (ret) 2230 return ret; 2231 2232 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 2233 2234 smu_set_gfx_cgpg(smu, false); 2235 2236 /* 2237 * pwfw resets entrycount when device is suspended, so we save the 2238 * last value to be used when we resume to keep it consistent 2239 */ 2240 ret = smu_get_entrycount_gfxoff(smu, &count); 2241 if (!ret) 2242 adev->gfx.gfx_off_entrycount = count; 2243 2244 /* clear this on suspend so it will get reprogrammed on resume */ 2245 smu->workload_mask = 0; 2246 2247 return 0; 2248 } 2249 2250 static int smu_resume(struct amdgpu_ip_block *ip_block) 2251 { 2252 int ret; 2253 struct amdgpu_device *adev = ip_block->adev; 2254 struct smu_context *smu = adev->powerplay.pp_handle; 2255 2256 if (amdgpu_sriov_multi_vf_mode(adev)) 2257 return 0; 2258 2259 if (!smu->pm_enabled) 2260 return 0; 2261 2262 dev_info(adev->dev, "SMU is resuming...\n"); 2263 2264 ret = smu_start_smc_engine(smu); 2265 if (ret) { 2266 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 2267 return ret; 2268 } 2269 2270 ret = smu_smc_hw_setup(smu); 2271 if (ret) { 2272 dev_err(adev->dev, "Failed to setup smc hw!\n"); 2273 return ret; 2274 } 2275 2276 ret = smu_set_gfx_imu_enable(smu); 2277 if (ret) 2278 return ret; 2279 2280 smu_set_gfx_cgpg(smu, true); 2281 2282 smu->disable_uclk_switch = 0; 2283 2284 adev->pm.dpm_enabled = true; 2285 2286 dev_info(adev->dev, "SMU is resumed successfully!\n"); 2287 2288 return 0; 2289 } 2290 2291 static int smu_display_configuration_change(void *handle, 2292 const struct amd_pp_display_configuration *display_config) 2293 { 2294 struct smu_context *smu = handle; 2295 2296 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2297 return -EOPNOTSUPP; 2298 2299 if (!display_config) 2300 return -EINVAL; 2301 2302 smu_set_min_dcef_deep_sleep(smu, 2303 display_config->min_dcef_deep_sleep_set_clk / 100); 2304 2305 return 0; 2306 } 2307 2308 static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2309 enum amd_clockgating_state state) 2310 { 2311 return 0; 2312 } 2313 2314 static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block, 2315 enum amd_powergating_state state) 2316 { 2317 return 0; 2318 } 2319 2320 static int smu_enable_umd_pstate(void *handle, 2321 enum amd_dpm_forced_level *level) 2322 { 2323 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 2324 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 2325 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 2326 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 2327 2328 struct smu_context *smu = (struct smu_context*)(handle); 2329 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2330 2331 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2332 return -EINVAL; 2333 2334 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 2335 /* enter umd pstate, save current level, disable gfx cg*/ 2336 if (*level & profile_mode_mask) { 2337 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 2338 smu_gpo_control(smu, false); 2339 smu_gfx_ulv_control(smu, false); 2340 smu_deep_sleep_control(smu, false); 2341 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 2342 } 2343 } else { 2344 /* exit umd pstate, restore level, enable gfx cg*/ 2345 if (!(*level & profile_mode_mask)) { 2346 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 2347 *level = smu_dpm_ctx->saved_dpm_level; 2348 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 2349 smu_deep_sleep_control(smu, true); 2350 smu_gfx_ulv_control(smu, true); 2351 smu_gpo_control(smu, true); 2352 } 2353 } 2354 2355 return 0; 2356 } 2357 2358 static int smu_bump_power_profile_mode(struct smu_context *smu, 2359 long *custom_params, 2360 u32 custom_params_max_idx) 2361 { 2362 u32 workload_mask = 0; 2363 int i, ret = 0; 2364 2365 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) { 2366 if (smu->workload_refcount[i]) 2367 workload_mask |= 1 << i; 2368 } 2369 2370 if (smu->workload_mask == workload_mask) 2371 return 0; 2372 2373 if (smu->ppt_funcs->set_power_profile_mode) 2374 ret = smu->ppt_funcs->set_power_profile_mode(smu, workload_mask, 2375 custom_params, 2376 custom_params_max_idx); 2377 2378 if (!ret) 2379 smu->workload_mask = workload_mask; 2380 2381 return ret; 2382 } 2383 2384 static void smu_power_profile_mode_get(struct smu_context *smu, 2385 enum PP_SMC_POWER_PROFILE profile_mode) 2386 { 2387 smu->workload_refcount[profile_mode]++; 2388 } 2389 2390 static void smu_power_profile_mode_put(struct smu_context *smu, 2391 enum PP_SMC_POWER_PROFILE profile_mode) 2392 { 2393 if (smu->workload_refcount[profile_mode]) 2394 smu->workload_refcount[profile_mode]--; 2395 } 2396 2397 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 2398 enum amd_dpm_forced_level level, 2399 bool skip_display_settings) 2400 { 2401 int ret = 0; 2402 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2403 2404 if (!skip_display_settings) { 2405 ret = smu_display_config_changed(smu); 2406 if (ret) { 2407 dev_err(smu->adev->dev, "Failed to change display config!"); 2408 return ret; 2409 } 2410 } 2411 2412 ret = smu_apply_clocks_adjust_rules(smu); 2413 if (ret) { 2414 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 2415 return ret; 2416 } 2417 2418 if (!skip_display_settings) { 2419 ret = smu_notify_smc_display_config(smu); 2420 if (ret) { 2421 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 2422 return ret; 2423 } 2424 } 2425 2426 if (smu_dpm_ctx->dpm_level != level) { 2427 ret = smu_asic_set_performance_level(smu, level); 2428 if (ret) { 2429 if (ret == -EOPNOTSUPP) 2430 dev_info(smu->adev->dev, "set performance level %d not supported", 2431 level); 2432 else 2433 dev_err(smu->adev->dev, "Failed to set performance level %d", 2434 level); 2435 return ret; 2436 } 2437 2438 /* update the saved copy */ 2439 smu_dpm_ctx->dpm_level = level; 2440 } 2441 2442 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2443 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 2444 smu_bump_power_profile_mode(smu, NULL, 0); 2445 2446 return ret; 2447 } 2448 2449 static int smu_handle_task(struct smu_context *smu, 2450 enum amd_dpm_forced_level level, 2451 enum amd_pp_task task_id) 2452 { 2453 int ret = 0; 2454 2455 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2456 return -EOPNOTSUPP; 2457 2458 switch (task_id) { 2459 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 2460 ret = smu_pre_display_config_changed(smu); 2461 if (ret) 2462 return ret; 2463 ret = smu_adjust_power_state_dynamic(smu, level, false); 2464 break; 2465 case AMD_PP_TASK_COMPLETE_INIT: 2466 ret = smu_adjust_power_state_dynamic(smu, level, true); 2467 break; 2468 case AMD_PP_TASK_READJUST_POWER_STATE: 2469 ret = smu_adjust_power_state_dynamic(smu, level, true); 2470 break; 2471 default: 2472 break; 2473 } 2474 2475 return ret; 2476 } 2477 2478 static int smu_handle_dpm_task(void *handle, 2479 enum amd_pp_task task_id, 2480 enum amd_pm_state_type *user_state) 2481 { 2482 struct smu_context *smu = handle; 2483 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 2484 2485 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 2486 2487 } 2488 2489 static int smu_switch_power_profile(void *handle, 2490 enum PP_SMC_POWER_PROFILE type, 2491 bool enable) 2492 { 2493 struct smu_context *smu = handle; 2494 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2495 int ret; 2496 2497 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2498 return -EOPNOTSUPP; 2499 2500 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 2501 return -EINVAL; 2502 2503 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2504 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2505 if (enable) 2506 smu_power_profile_mode_get(smu, type); 2507 else 2508 smu_power_profile_mode_put(smu, type); 2509 /* don't switch the active workload when paused */ 2510 if (smu->pause_workload) 2511 ret = 0; 2512 else 2513 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2514 if (ret) { 2515 if (enable) 2516 smu_power_profile_mode_put(smu, type); 2517 else 2518 smu_power_profile_mode_get(smu, type); 2519 return ret; 2520 } 2521 } 2522 2523 return 0; 2524 } 2525 2526 static int smu_pause_power_profile(void *handle, 2527 bool pause) 2528 { 2529 struct smu_context *smu = handle; 2530 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2531 u32 workload_mask = 1 << PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 2532 int ret; 2533 2534 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2535 return -EOPNOTSUPP; 2536 2537 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 2538 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 2539 smu->pause_workload = pause; 2540 2541 /* force to bootup default profile */ 2542 if (smu->pause_workload && smu->ppt_funcs->set_power_profile_mode) 2543 ret = smu->ppt_funcs->set_power_profile_mode(smu, 2544 workload_mask, 2545 NULL, 2546 0); 2547 else 2548 ret = smu_bump_power_profile_mode(smu, NULL, 0); 2549 return ret; 2550 } 2551 2552 return 0; 2553 } 2554 2555 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 2556 { 2557 struct smu_context *smu = handle; 2558 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2559 2560 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2561 return -EOPNOTSUPP; 2562 2563 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2564 return -EINVAL; 2565 2566 return smu_dpm_ctx->dpm_level; 2567 } 2568 2569 static int smu_force_performance_level(void *handle, 2570 enum amd_dpm_forced_level level) 2571 { 2572 struct smu_context *smu = handle; 2573 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2574 int ret = 0; 2575 2576 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2577 return -EOPNOTSUPP; 2578 2579 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 2580 return -EINVAL; 2581 2582 ret = smu_enable_umd_pstate(smu, &level); 2583 if (ret) 2584 return ret; 2585 2586 ret = smu_handle_task(smu, level, 2587 AMD_PP_TASK_READJUST_POWER_STATE); 2588 2589 /* reset user dpm clock state */ 2590 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2591 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2592 smu->user_dpm_profile.clk_dependency = 0; 2593 } 2594 2595 return ret; 2596 } 2597 2598 static int smu_set_display_count(void *handle, uint32_t count) 2599 { 2600 struct smu_context *smu = handle; 2601 2602 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2603 return -EOPNOTSUPP; 2604 2605 return smu_init_display_count(smu, count); 2606 } 2607 2608 static int smu_force_smuclk_levels(struct smu_context *smu, 2609 enum smu_clk_type clk_type, 2610 uint32_t mask) 2611 { 2612 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2613 int ret = 0; 2614 2615 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2616 return -EOPNOTSUPP; 2617 2618 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2619 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2620 return -EINVAL; 2621 } 2622 2623 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2624 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2625 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2626 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2627 smu_set_user_clk_dependencies(smu, clk_type); 2628 } 2629 } 2630 2631 return ret; 2632 } 2633 2634 static int smu_force_ppclk_levels(void *handle, 2635 enum pp_clock_type type, 2636 uint32_t mask) 2637 { 2638 struct smu_context *smu = handle; 2639 enum smu_clk_type clk_type; 2640 2641 switch (type) { 2642 case PP_SCLK: 2643 clk_type = SMU_SCLK; break; 2644 case PP_MCLK: 2645 clk_type = SMU_MCLK; break; 2646 case PP_PCIE: 2647 clk_type = SMU_PCIE; break; 2648 case PP_SOCCLK: 2649 clk_type = SMU_SOCCLK; break; 2650 case PP_FCLK: 2651 clk_type = SMU_FCLK; break; 2652 case PP_DCEFCLK: 2653 clk_type = SMU_DCEFCLK; break; 2654 case PP_VCLK: 2655 clk_type = SMU_VCLK; break; 2656 case PP_VCLK1: 2657 clk_type = SMU_VCLK1; break; 2658 case PP_DCLK: 2659 clk_type = SMU_DCLK; break; 2660 case PP_DCLK1: 2661 clk_type = SMU_DCLK1; break; 2662 case OD_SCLK: 2663 clk_type = SMU_OD_SCLK; break; 2664 case OD_MCLK: 2665 clk_type = SMU_OD_MCLK; break; 2666 case OD_VDDC_CURVE: 2667 clk_type = SMU_OD_VDDC_CURVE; break; 2668 case OD_RANGE: 2669 clk_type = SMU_OD_RANGE; break; 2670 default: 2671 return -EINVAL; 2672 } 2673 2674 return smu_force_smuclk_levels(smu, clk_type, mask); 2675 } 2676 2677 /* 2678 * On system suspending or resetting, the dpm_enabled 2679 * flag will be cleared. So that those SMU services which 2680 * are not supported will be gated. 2681 * However, the mp1 state setting should still be granted 2682 * even if the dpm_enabled cleared. 2683 */ 2684 static int smu_set_mp1_state(void *handle, 2685 enum pp_mp1_state mp1_state) 2686 { 2687 struct smu_context *smu = handle; 2688 int ret = 0; 2689 2690 if (!smu->pm_enabled) 2691 return -EOPNOTSUPP; 2692 2693 if (smu->ppt_funcs && 2694 smu->ppt_funcs->set_mp1_state) 2695 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2696 2697 return ret; 2698 } 2699 2700 static int smu_set_df_cstate(void *handle, 2701 enum pp_df_cstate state) 2702 { 2703 struct smu_context *smu = handle; 2704 int ret = 0; 2705 2706 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2707 return -EOPNOTSUPP; 2708 2709 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2710 return 0; 2711 2712 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2713 if (ret) 2714 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2715 2716 return ret; 2717 } 2718 2719 int smu_write_watermarks_table(struct smu_context *smu) 2720 { 2721 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2722 return -EOPNOTSUPP; 2723 2724 return smu_set_watermarks_table(smu, NULL); 2725 } 2726 2727 static int smu_set_watermarks_for_clock_ranges(void *handle, 2728 struct pp_smu_wm_range_sets *clock_ranges) 2729 { 2730 struct smu_context *smu = handle; 2731 2732 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2733 return -EOPNOTSUPP; 2734 2735 if (smu->disable_watermark) 2736 return 0; 2737 2738 return smu_set_watermarks_table(smu, clock_ranges); 2739 } 2740 2741 int smu_set_ac_dc(struct smu_context *smu) 2742 { 2743 int ret = 0; 2744 2745 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2746 return -EOPNOTSUPP; 2747 2748 /* controlled by firmware */ 2749 if (smu->dc_controlled_by_gpio) 2750 return 0; 2751 2752 ret = smu_set_power_source(smu, 2753 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2754 SMU_POWER_SOURCE_DC); 2755 if (ret) 2756 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2757 smu->adev->pm.ac_power ? "AC" : "DC"); 2758 2759 return ret; 2760 } 2761 2762 const struct amd_ip_funcs smu_ip_funcs = { 2763 .name = "smu", 2764 .early_init = smu_early_init, 2765 .late_init = smu_late_init, 2766 .sw_init = smu_sw_init, 2767 .sw_fini = smu_sw_fini, 2768 .hw_init = smu_hw_init, 2769 .hw_fini = smu_hw_fini, 2770 .late_fini = smu_late_fini, 2771 .suspend = smu_suspend, 2772 .resume = smu_resume, 2773 .is_idle = NULL, 2774 .check_soft_reset = NULL, 2775 .wait_for_idle = NULL, 2776 .soft_reset = NULL, 2777 .set_clockgating_state = smu_set_clockgating_state, 2778 .set_powergating_state = smu_set_powergating_state, 2779 }; 2780 2781 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2782 .type = AMD_IP_BLOCK_TYPE_SMC, 2783 .major = 11, 2784 .minor = 0, 2785 .rev = 0, 2786 .funcs = &smu_ip_funcs, 2787 }; 2788 2789 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2790 .type = AMD_IP_BLOCK_TYPE_SMC, 2791 .major = 12, 2792 .minor = 0, 2793 .rev = 0, 2794 .funcs = &smu_ip_funcs, 2795 }; 2796 2797 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2798 .type = AMD_IP_BLOCK_TYPE_SMC, 2799 .major = 13, 2800 .minor = 0, 2801 .rev = 0, 2802 .funcs = &smu_ip_funcs, 2803 }; 2804 2805 const struct amdgpu_ip_block_version smu_v14_0_ip_block = { 2806 .type = AMD_IP_BLOCK_TYPE_SMC, 2807 .major = 14, 2808 .minor = 0, 2809 .rev = 0, 2810 .funcs = &smu_ip_funcs, 2811 }; 2812 2813 const struct amdgpu_ip_block_version smu_v15_0_ip_block = { 2814 .type = AMD_IP_BLOCK_TYPE_SMC, 2815 .major = 15, 2816 .minor = 0, 2817 .rev = 0, 2818 .funcs = &smu_ip_funcs, 2819 }; 2820 2821 const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) 2822 { 2823 struct smu_context *smu = (struct smu_context *)handle; 2824 const struct ras_smu_drv *tmp = NULL; 2825 int ret; 2826 2827 ret = smu_get_ras_smu_drv(smu, &tmp); 2828 2829 return ret ? NULL : tmp; 2830 } 2831 2832 static int smu_load_microcode(void *handle) 2833 { 2834 struct smu_context *smu = handle; 2835 struct amdgpu_device *adev = smu->adev; 2836 int ret = 0; 2837 2838 if (!smu->pm_enabled) 2839 return -EOPNOTSUPP; 2840 2841 /* This should be used for non PSP loading */ 2842 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2843 return 0; 2844 2845 if (smu->ppt_funcs->load_microcode) { 2846 ret = smu->ppt_funcs->load_microcode(smu); 2847 if (ret) { 2848 dev_err(adev->dev, "Load microcode failed\n"); 2849 return ret; 2850 } 2851 } 2852 2853 if (smu->ppt_funcs->check_fw_status) { 2854 ret = smu->ppt_funcs->check_fw_status(smu); 2855 if (ret) { 2856 dev_err(adev->dev, "SMC is not ready\n"); 2857 return ret; 2858 } 2859 } 2860 2861 return ret; 2862 } 2863 2864 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2865 { 2866 int ret = 0; 2867 2868 if (smu->ppt_funcs->set_gfx_cgpg) 2869 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2870 2871 return ret; 2872 } 2873 2874 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2875 { 2876 struct smu_context *smu = handle; 2877 int ret = 0; 2878 2879 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2880 return -EOPNOTSUPP; 2881 2882 if (!smu->ppt_funcs->set_fan_speed_rpm) 2883 return -EOPNOTSUPP; 2884 2885 if (speed == U32_MAX) 2886 return -EINVAL; 2887 2888 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2889 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2890 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2891 smu->user_dpm_profile.fan_speed_rpm = speed; 2892 2893 /* Override custom PWM setting as they cannot co-exist */ 2894 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2895 smu->user_dpm_profile.fan_speed_pwm = 0; 2896 } 2897 2898 return ret; 2899 } 2900 2901 /** 2902 * smu_get_power_limit - Request one of the SMU Power Limits 2903 * 2904 * @handle: pointer to smu context 2905 * @limit: requested limit is written back to this variable 2906 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2907 * @pp_power_type: &pp_power_type type of power 2908 * Return: 0 on success, <0 on error 2909 * 2910 */ 2911 int smu_get_power_limit(void *handle, 2912 uint32_t *limit, 2913 enum pp_power_limit_level pp_limit_level, 2914 enum pp_power_type pp_power_type) 2915 { 2916 struct smu_context *smu = handle; 2917 struct amdgpu_device *adev = smu->adev; 2918 enum smu_ppt_limit_level limit_level; 2919 uint32_t limit_type; 2920 int ret = 0; 2921 2922 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2923 return -EOPNOTSUPP; 2924 2925 if (!limit) 2926 return -EINVAL; 2927 2928 switch (pp_power_type) { 2929 case PP_PWR_TYPE_SUSTAINED: 2930 limit_type = SMU_DEFAULT_PPT_LIMIT; 2931 break; 2932 case PP_PWR_TYPE_FAST: 2933 limit_type = SMU_FAST_PPT_LIMIT; 2934 break; 2935 default: 2936 return -EOPNOTSUPP; 2937 } 2938 2939 switch (pp_limit_level) { 2940 case PP_PWR_LIMIT_CURRENT: 2941 limit_level = SMU_PPT_LIMIT_CURRENT; 2942 break; 2943 case PP_PWR_LIMIT_DEFAULT: 2944 limit_level = SMU_PPT_LIMIT_DEFAULT; 2945 break; 2946 case PP_PWR_LIMIT_MAX: 2947 limit_level = SMU_PPT_LIMIT_MAX; 2948 break; 2949 case PP_PWR_LIMIT_MIN: 2950 limit_level = SMU_PPT_LIMIT_MIN; 2951 break; 2952 default: 2953 return -EOPNOTSUPP; 2954 } 2955 2956 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2957 if (smu->ppt_funcs->get_ppt_limit) 2958 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2959 else 2960 return -EOPNOTSUPP; 2961 } else { 2962 switch (limit_level) { 2963 case SMU_PPT_LIMIT_CURRENT: 2964 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2965 case IP_VERSION(13, 0, 2): 2966 case IP_VERSION(13, 0, 6): 2967 case IP_VERSION(13, 0, 12): 2968 case IP_VERSION(13, 0, 14): 2969 case IP_VERSION(11, 0, 7): 2970 case IP_VERSION(11, 0, 11): 2971 case IP_VERSION(11, 0, 12): 2972 case IP_VERSION(11, 0, 13): 2973 case IP_VERSION(15, 0, 8): 2974 ret = smu_get_asic_power_limits(smu, 2975 &smu->current_power_limit, 2976 NULL, NULL, NULL); 2977 break; 2978 default: 2979 break; 2980 } 2981 *limit = smu->current_power_limit; 2982 break; 2983 case SMU_PPT_LIMIT_DEFAULT: 2984 *limit = smu->default_power_limit; 2985 break; 2986 case SMU_PPT_LIMIT_MAX: 2987 *limit = smu->max_power_limit; 2988 break; 2989 case SMU_PPT_LIMIT_MIN: 2990 *limit = smu->min_power_limit; 2991 break; 2992 default: 2993 return -EINVAL; 2994 } 2995 } 2996 2997 return ret; 2998 } 2999 3000 static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) 3001 { 3002 struct smu_context *smu = handle; 3003 int ret = 0; 3004 3005 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3006 return -EOPNOTSUPP; 3007 3008 if (limit_type == SMU_DEFAULT_PPT_LIMIT) { 3009 if (!limit) 3010 limit = smu->current_power_limit; 3011 if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { 3012 dev_err(smu->adev->dev, 3013 "New power limit (%d) is out of range [%d,%d]\n", 3014 limit, smu->min_power_limit, smu->max_power_limit); 3015 return -EINVAL; 3016 } 3017 } 3018 3019 if (smu->ppt_funcs->set_power_limit) { 3020 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 3021 if (ret) 3022 return ret; 3023 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 3024 smu->user_dpm_profile.power_limits[limit_type] = limit; 3025 } 3026 3027 return 0; 3028 } 3029 3030 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 3031 { 3032 enum smu_clk_type clk_type; 3033 3034 switch (type) { 3035 case PP_SCLK: 3036 clk_type = SMU_SCLK; break; 3037 case PP_MCLK: 3038 clk_type = SMU_MCLK; break; 3039 case PP_PCIE: 3040 clk_type = SMU_PCIE; break; 3041 case PP_SOCCLK: 3042 clk_type = SMU_SOCCLK; break; 3043 case PP_FCLK: 3044 clk_type = SMU_FCLK; break; 3045 case PP_DCEFCLK: 3046 clk_type = SMU_DCEFCLK; break; 3047 case PP_VCLK: 3048 clk_type = SMU_VCLK; break; 3049 case PP_VCLK1: 3050 clk_type = SMU_VCLK1; break; 3051 case PP_DCLK: 3052 clk_type = SMU_DCLK; break; 3053 case PP_DCLK1: 3054 clk_type = SMU_DCLK1; break; 3055 case PP_ISPICLK: 3056 clk_type = SMU_ISPICLK; 3057 break; 3058 case PP_ISPXCLK: 3059 clk_type = SMU_ISPXCLK; 3060 break; 3061 case OD_SCLK: 3062 clk_type = SMU_OD_SCLK; break; 3063 case OD_MCLK: 3064 clk_type = SMU_OD_MCLK; break; 3065 case OD_FCLK: 3066 clk_type = SMU_OD_FCLK; break; 3067 case OD_VDDC_CURVE: 3068 clk_type = SMU_OD_VDDC_CURVE; break; 3069 case OD_RANGE: 3070 clk_type = SMU_OD_RANGE; break; 3071 case OD_VDDGFX_OFFSET: 3072 clk_type = SMU_OD_VDDGFX_OFFSET; break; 3073 case OD_CCLK: 3074 clk_type = SMU_OD_CCLK; break; 3075 case OD_FAN_CURVE: 3076 clk_type = SMU_OD_FAN_CURVE; break; 3077 case OD_ACOUSTIC_LIMIT: 3078 clk_type = SMU_OD_ACOUSTIC_LIMIT; break; 3079 case OD_ACOUSTIC_TARGET: 3080 clk_type = SMU_OD_ACOUSTIC_TARGET; break; 3081 case OD_FAN_TARGET_TEMPERATURE: 3082 clk_type = SMU_OD_FAN_TARGET_TEMPERATURE; break; 3083 case OD_FAN_MINIMUM_PWM: 3084 clk_type = SMU_OD_FAN_MINIMUM_PWM; break; 3085 case OD_FAN_ZERO_RPM_ENABLE: 3086 clk_type = SMU_OD_FAN_ZERO_RPM_ENABLE; break; 3087 case OD_FAN_ZERO_RPM_STOP_TEMP: 3088 clk_type = SMU_OD_FAN_ZERO_RPM_STOP_TEMP; break; 3089 default: 3090 clk_type = SMU_CLK_COUNT; break; 3091 } 3092 3093 return clk_type; 3094 } 3095 3096 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 3097 { 3098 struct smu_context *smu = handle; 3099 enum smu_clk_type clk_type; 3100 3101 clk_type = smu_convert_to_smuclk(type); 3102 if (clk_type == SMU_CLK_COUNT) 3103 return -EINVAL; 3104 3105 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3106 return -EOPNOTSUPP; 3107 3108 if (!smu->ppt_funcs->emit_clk_levels) 3109 return -ENOENT; 3110 3111 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 3112 3113 } 3114 3115 static int smu_od_edit_dpm_table(void *handle, 3116 enum PP_OD_DPM_TABLE_COMMAND type, 3117 long *input, uint32_t size) 3118 { 3119 struct smu_context *smu = handle; 3120 int ret = 0; 3121 3122 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3123 return -EOPNOTSUPP; 3124 3125 if (smu->ppt_funcs->od_edit_dpm_table) { 3126 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 3127 } 3128 3129 return ret; 3130 } 3131 3132 static int smu_read_sensor(void *handle, 3133 int sensor, 3134 void *data, 3135 int *size_arg) 3136 { 3137 struct smu_context *smu = handle; 3138 struct amdgpu_device *adev = smu->adev; 3139 struct smu_umd_pstate_table *pstate_table = 3140 &smu->pstate_table; 3141 int i, ret = 0; 3142 uint32_t *size, size_val; 3143 3144 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3145 return -EOPNOTSUPP; 3146 3147 if (!data || !size_arg) 3148 return -EINVAL; 3149 3150 size_val = *size_arg; 3151 size = &size_val; 3152 3153 if (smu->ppt_funcs->read_sensor) 3154 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 3155 goto unlock; 3156 3157 switch (sensor) { 3158 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 3159 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 3160 *size = 4; 3161 break; 3162 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 3163 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 3164 *size = 4; 3165 break; 3166 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 3167 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 3168 *size = 4; 3169 break; 3170 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 3171 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 3172 *size = 4; 3173 break; 3174 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { 3175 struct smu_feature_bits feature_mask; 3176 uint32_t features[2]; 3177 3178 /* TBD: need to handle for > 64 bits */ 3179 ret = smu_feature_get_enabled_mask(smu, &feature_mask); 3180 if (!ret) { 3181 smu_feature_bits_to_arr32(&feature_mask, features, 64); 3182 *(uint64_t *)data = *(uint64_t *)features; 3183 } 3184 *size = 8; 3185 break; 3186 } 3187 case AMDGPU_PP_SENSOR_UVD_POWER: 3188 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 3189 *size = 4; 3190 break; 3191 case AMDGPU_PP_SENSOR_VCE_POWER: 3192 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 3193 *size = 4; 3194 break; 3195 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 3196 *(uint32_t *)data = 0; 3197 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 3198 if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) { 3199 *(uint32_t *)data = 1; 3200 break; 3201 } 3202 } 3203 *size = 4; 3204 break; 3205 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 3206 *(uint32_t *)data = 0; 3207 *size = 4; 3208 break; 3209 default: 3210 *size = 0; 3211 ret = -EOPNOTSUPP; 3212 break; 3213 } 3214 3215 unlock: 3216 // assign uint32_t to int 3217 *size_arg = size_val; 3218 3219 return ret; 3220 } 3221 3222 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 3223 { 3224 int ret = -EOPNOTSUPP; 3225 struct smu_context *smu = handle; 3226 3227 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 3228 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 3229 3230 return ret; 3231 } 3232 3233 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 3234 { 3235 int ret = -EOPNOTSUPP; 3236 struct smu_context *smu = handle; 3237 3238 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 3239 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 3240 3241 return ret; 3242 } 3243 3244 static int smu_get_power_profile_mode(void *handle, char *buf) 3245 { 3246 struct smu_context *smu = handle; 3247 3248 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3249 !smu->ppt_funcs->get_power_profile_mode) 3250 return -EOPNOTSUPP; 3251 if (!buf) 3252 return -EINVAL; 3253 3254 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 3255 } 3256 3257 static int smu_set_power_profile_mode(void *handle, 3258 long *param, 3259 uint32_t param_size) 3260 { 3261 struct smu_context *smu = handle; 3262 bool custom = false; 3263 int ret = 0; 3264 3265 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 3266 !smu->ppt_funcs->set_power_profile_mode) 3267 return -EOPNOTSUPP; 3268 3269 if (param[param_size] == PP_SMC_POWER_PROFILE_CUSTOM) { 3270 custom = true; 3271 /* clear frontend mask so custom changes propogate */ 3272 smu->workload_mask = 0; 3273 } 3274 3275 if ((param[param_size] != smu->power_profile_mode) || custom) { 3276 /* clear the old user preference */ 3277 smu_power_profile_mode_put(smu, smu->power_profile_mode); 3278 /* set the new user preference */ 3279 smu_power_profile_mode_get(smu, param[param_size]); 3280 ret = smu_bump_power_profile_mode(smu, 3281 custom ? param : NULL, 3282 custom ? param_size : 0); 3283 if (ret) 3284 smu_power_profile_mode_put(smu, param[param_size]); 3285 else 3286 /* store the user's preference */ 3287 smu->power_profile_mode = param[param_size]; 3288 } 3289 3290 return ret; 3291 } 3292 3293 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 3294 { 3295 struct smu_context *smu = handle; 3296 3297 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3298 return -EOPNOTSUPP; 3299 3300 if (!smu->ppt_funcs->get_fan_control_mode) 3301 return -EOPNOTSUPP; 3302 3303 if (!fan_mode) 3304 return -EINVAL; 3305 3306 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 3307 3308 return 0; 3309 } 3310 3311 static int smu_set_fan_control_mode(void *handle, u32 value) 3312 { 3313 struct smu_context *smu = handle; 3314 int ret = 0; 3315 3316 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3317 return -EOPNOTSUPP; 3318 3319 if (!smu->ppt_funcs->set_fan_control_mode) 3320 return -EOPNOTSUPP; 3321 3322 if (value == U32_MAX) 3323 return -EINVAL; 3324 3325 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 3326 if (ret) 3327 goto out; 3328 3329 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3330 smu->user_dpm_profile.fan_mode = value; 3331 3332 /* reset user dpm fan speed */ 3333 if (value != AMD_FAN_CTRL_MANUAL) { 3334 smu->user_dpm_profile.fan_speed_pwm = 0; 3335 smu->user_dpm_profile.fan_speed_rpm = 0; 3336 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 3337 } 3338 } 3339 3340 out: 3341 return ret; 3342 } 3343 3344 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 3345 { 3346 struct smu_context *smu = handle; 3347 int ret = 0; 3348 3349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3350 return -EOPNOTSUPP; 3351 3352 if (!smu->ppt_funcs->get_fan_speed_pwm) 3353 return -EOPNOTSUPP; 3354 3355 if (!speed) 3356 return -EINVAL; 3357 3358 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 3359 3360 return ret; 3361 } 3362 3363 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 3364 { 3365 struct smu_context *smu = handle; 3366 int ret = 0; 3367 3368 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3369 return -EOPNOTSUPP; 3370 3371 if (!smu->ppt_funcs->set_fan_speed_pwm) 3372 return -EOPNOTSUPP; 3373 3374 if (speed == U32_MAX) 3375 return -EINVAL; 3376 3377 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 3378 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 3379 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 3380 smu->user_dpm_profile.fan_speed_pwm = speed; 3381 3382 /* Override custom RPM setting as they cannot co-exist */ 3383 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 3384 smu->user_dpm_profile.fan_speed_rpm = 0; 3385 } 3386 3387 return ret; 3388 } 3389 3390 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 3391 { 3392 struct smu_context *smu = handle; 3393 int ret = 0; 3394 3395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3396 return -EOPNOTSUPP; 3397 3398 if (!smu->ppt_funcs->get_fan_speed_rpm) 3399 return -EOPNOTSUPP; 3400 3401 if (!speed) 3402 return -EINVAL; 3403 3404 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 3405 3406 return ret; 3407 } 3408 3409 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 3410 { 3411 struct smu_context *smu = handle; 3412 3413 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3414 return -EOPNOTSUPP; 3415 3416 return smu_set_min_dcef_deep_sleep(smu, clk); 3417 } 3418 3419 static int smu_get_clock_by_type_with_latency(void *handle, 3420 enum amd_pp_clock_type type, 3421 struct pp_clock_levels_with_latency *clocks) 3422 { 3423 struct smu_context *smu = handle; 3424 enum smu_clk_type clk_type; 3425 int ret = 0; 3426 3427 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3428 return -EOPNOTSUPP; 3429 3430 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 3431 switch (type) { 3432 case amd_pp_sys_clock: 3433 clk_type = SMU_GFXCLK; 3434 break; 3435 case amd_pp_mem_clock: 3436 clk_type = SMU_MCLK; 3437 break; 3438 case amd_pp_dcef_clock: 3439 clk_type = SMU_DCEFCLK; 3440 break; 3441 case amd_pp_disp_clock: 3442 clk_type = SMU_DISPCLK; 3443 break; 3444 default: 3445 dev_err(smu->adev->dev, "Invalid clock type!\n"); 3446 return -EINVAL; 3447 } 3448 3449 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 3450 } 3451 3452 return ret; 3453 } 3454 3455 static int smu_display_clock_voltage_request(void *handle, 3456 struct pp_display_clock_request *clock_req) 3457 { 3458 struct smu_context *smu = handle; 3459 int ret = 0; 3460 3461 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3462 return -EOPNOTSUPP; 3463 3464 if (smu->ppt_funcs->display_clock_voltage_request) 3465 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 3466 3467 return ret; 3468 } 3469 3470 3471 static int smu_display_disable_memory_clock_switch(void *handle, 3472 bool disable_memory_clock_switch) 3473 { 3474 struct smu_context *smu = handle; 3475 int ret = -EINVAL; 3476 3477 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3478 return -EOPNOTSUPP; 3479 3480 if (smu->ppt_funcs->display_disable_memory_clock_switch) 3481 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 3482 3483 return ret; 3484 } 3485 3486 static int smu_set_xgmi_pstate(void *handle, 3487 uint32_t pstate) 3488 { 3489 struct smu_context *smu = handle; 3490 int ret = 0; 3491 3492 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3493 return -EOPNOTSUPP; 3494 3495 if (smu->ppt_funcs->set_xgmi_pstate) 3496 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 3497 3498 if (ret) 3499 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 3500 3501 return ret; 3502 } 3503 3504 static int smu_get_baco_capability(void *handle) 3505 { 3506 struct smu_context *smu = handle; 3507 3508 if (!smu->pm_enabled) 3509 return false; 3510 3511 if (!smu->ppt_funcs || !smu->ppt_funcs->get_bamaco_support) 3512 return false; 3513 3514 return smu->ppt_funcs->get_bamaco_support(smu); 3515 } 3516 3517 static int smu_baco_set_state(void *handle, int state) 3518 { 3519 struct smu_context *smu = handle; 3520 int ret = 0; 3521 3522 if (!smu->pm_enabled) 3523 return -EOPNOTSUPP; 3524 3525 if (state == 0) { 3526 if (smu->ppt_funcs->baco_exit) 3527 ret = smu->ppt_funcs->baco_exit(smu); 3528 } else if (state == 1) { 3529 if (smu->ppt_funcs->baco_enter) 3530 ret = smu->ppt_funcs->baco_enter(smu); 3531 } else { 3532 return -EINVAL; 3533 } 3534 3535 if (ret) 3536 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 3537 (state)?"enter":"exit"); 3538 3539 return ret; 3540 } 3541 3542 bool smu_mode1_reset_is_support(struct smu_context *smu) 3543 { 3544 bool ret = false; 3545 3546 if (!smu->pm_enabled) 3547 return false; 3548 3549 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 3550 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 3551 3552 return ret; 3553 } 3554 3555 bool smu_link_reset_is_support(struct smu_context *smu) 3556 { 3557 if (!smu->pm_enabled) 3558 return false; 3559 3560 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); 3561 } 3562 3563 int smu_mode1_reset(struct smu_context *smu) 3564 { 3565 int ret = 0; 3566 3567 if (!smu->pm_enabled) 3568 return -EOPNOTSUPP; 3569 3570 if (smu->ppt_funcs->mode1_reset) 3571 ret = smu->ppt_funcs->mode1_reset(smu); 3572 3573 return ret; 3574 } 3575 3576 static int smu_mode2_reset(void *handle) 3577 { 3578 struct smu_context *smu = handle; 3579 int ret = 0; 3580 3581 if (!smu->pm_enabled) 3582 return -EOPNOTSUPP; 3583 3584 if (smu->ppt_funcs->mode2_reset) 3585 ret = smu->ppt_funcs->mode2_reset(smu); 3586 3587 if (ret) 3588 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 3589 3590 return ret; 3591 } 3592 3593 int smu_link_reset(struct smu_context *smu) 3594 { 3595 int ret = 0; 3596 3597 if (!smu->pm_enabled) 3598 return -EOPNOTSUPP; 3599 3600 if (smu->ppt_funcs->link_reset) 3601 ret = smu->ppt_funcs->link_reset(smu); 3602 3603 return ret; 3604 } 3605 3606 static int smu_enable_gfx_features(void *handle) 3607 { 3608 struct smu_context *smu = handle; 3609 int ret = 0; 3610 3611 if (!smu->pm_enabled) 3612 return -EOPNOTSUPP; 3613 3614 if (smu->ppt_funcs->enable_gfx_features) 3615 ret = smu->ppt_funcs->enable_gfx_features(smu); 3616 3617 if (ret) 3618 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 3619 3620 return ret; 3621 } 3622 3623 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 3624 struct pp_smu_nv_clock_table *max_clocks) 3625 { 3626 struct smu_context *smu = handle; 3627 int ret = 0; 3628 3629 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3630 return -EOPNOTSUPP; 3631 3632 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 3633 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 3634 3635 return ret; 3636 } 3637 3638 static int smu_get_uclk_dpm_states(void *handle, 3639 unsigned int *clock_values_in_khz, 3640 unsigned int *num_states) 3641 { 3642 struct smu_context *smu = handle; 3643 int ret = 0; 3644 3645 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3646 return -EOPNOTSUPP; 3647 3648 if (smu->ppt_funcs->get_uclk_dpm_states) 3649 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3650 3651 return ret; 3652 } 3653 3654 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3655 { 3656 struct smu_context *smu = handle; 3657 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3658 3659 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3660 return -EOPNOTSUPP; 3661 3662 if (smu->ppt_funcs->get_current_power_state) 3663 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3664 3665 return pm_state; 3666 } 3667 3668 static int smu_get_dpm_clock_table(void *handle, 3669 struct dpm_clocks *clock_table) 3670 { 3671 struct smu_context *smu = handle; 3672 int ret = 0; 3673 3674 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3675 return -EOPNOTSUPP; 3676 3677 if (smu->ppt_funcs->get_dpm_clock_table) 3678 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3679 3680 return ret; 3681 } 3682 3683 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3684 { 3685 struct smu_context *smu = handle; 3686 struct smu_table_context *smu_table = &smu->smu_table; 3687 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3688 struct smu_driver_table *gpu_metrics_table; 3689 3690 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3691 return -EOPNOTSUPP; 3692 3693 if (!smu->ppt_funcs->get_gpu_metrics) 3694 return -EOPNOTSUPP; 3695 3696 gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; 3697 3698 /* If cached table is valid, return it */ 3699 if (smu_driver_table_is_valid(gpu_metrics_table)) { 3700 *table = gpu_metrics_table->cache.buffer; 3701 return gpu_metrics_table->cache.size; 3702 } 3703 3704 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3705 } 3706 3707 static ssize_t smu_sys_get_pm_metrics(void *handle, void *pm_metrics, 3708 size_t size) 3709 { 3710 struct smu_context *smu = handle; 3711 3712 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3713 return -EOPNOTSUPP; 3714 3715 if (!smu->ppt_funcs->get_pm_metrics) 3716 return -EOPNOTSUPP; 3717 3718 return smu->ppt_funcs->get_pm_metrics(smu, pm_metrics, size); 3719 } 3720 3721 static int smu_enable_mgpu_fan_boost(void *handle) 3722 { 3723 struct smu_context *smu = handle; 3724 int ret = 0; 3725 3726 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3727 return -EOPNOTSUPP; 3728 3729 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3730 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3731 3732 return ret; 3733 } 3734 3735 static int smu_gfx_state_change_set(void *handle, 3736 uint32_t state) 3737 { 3738 struct smu_context *smu = handle; 3739 int ret = 0; 3740 3741 if (smu->ppt_funcs->gfx_state_change_set) 3742 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3743 3744 return ret; 3745 } 3746 3747 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3748 { 3749 int ret = 0; 3750 3751 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3752 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3753 3754 return ret; 3755 } 3756 3757 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3758 { 3759 int ret = -EOPNOTSUPP; 3760 3761 if (smu->ppt_funcs && 3762 smu->ppt_funcs->get_ecc_info) 3763 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3764 3765 return ret; 3766 3767 } 3768 3769 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3770 { 3771 struct smu_context *smu = handle; 3772 struct smu_table_context *smu_table = &smu->smu_table; 3773 struct smu_table *memory_pool = &smu_table->memory_pool; 3774 3775 if (!addr || !size) 3776 return -EINVAL; 3777 3778 *addr = NULL; 3779 *size = 0; 3780 if (memory_pool->bo) { 3781 *addr = memory_pool->cpu_addr; 3782 *size = memory_pool->size; 3783 } 3784 3785 return 0; 3786 } 3787 3788 static void smu_print_dpm_policy(struct smu_dpm_policy *policy, char *sysbuf, 3789 size_t *size) 3790 { 3791 size_t offset = *size; 3792 int level; 3793 3794 for_each_set_bit(level, &policy->level_mask, PP_POLICY_MAX_LEVELS) { 3795 if (level == policy->current_level) 3796 offset += sysfs_emit_at(sysbuf, offset, 3797 "%d : %s*\n", level, 3798 policy->desc->get_desc(policy, level)); 3799 else 3800 offset += sysfs_emit_at(sysbuf, offset, 3801 "%d : %s\n", level, 3802 policy->desc->get_desc(policy, level)); 3803 } 3804 3805 *size = offset; 3806 } 3807 3808 ssize_t smu_get_pm_policy_info(struct smu_context *smu, 3809 enum pp_pm_policy p_type, char *sysbuf) 3810 { 3811 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3812 struct smu_dpm_policy_ctxt *policy_ctxt; 3813 struct smu_dpm_policy *dpm_policy; 3814 size_t offset = 0; 3815 3816 policy_ctxt = dpm_ctxt->dpm_policies; 3817 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3818 !policy_ctxt->policy_mask) 3819 return -EOPNOTSUPP; 3820 3821 if (p_type == PP_PM_POLICY_NONE) 3822 return -EINVAL; 3823 3824 dpm_policy = smu_get_pm_policy(smu, p_type); 3825 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->desc) 3826 return -ENOENT; 3827 3828 if (!sysbuf) 3829 return -EINVAL; 3830 3831 smu_print_dpm_policy(dpm_policy, sysbuf, &offset); 3832 3833 return offset; 3834 } 3835 3836 struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, 3837 enum pp_pm_policy p_type) 3838 { 3839 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3840 struct smu_dpm_policy_ctxt *policy_ctxt; 3841 int i; 3842 3843 policy_ctxt = dpm_ctxt->dpm_policies; 3844 if (!policy_ctxt) 3845 return NULL; 3846 3847 for (i = 0; i < hweight32(policy_ctxt->policy_mask); ++i) { 3848 if (policy_ctxt->policies[i].policy_type == p_type) 3849 return &policy_ctxt->policies[i]; 3850 } 3851 3852 return NULL; 3853 } 3854 3855 int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, 3856 int level) 3857 { 3858 struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; 3859 struct smu_dpm_policy *dpm_policy = NULL; 3860 struct smu_dpm_policy_ctxt *policy_ctxt; 3861 int ret = -EOPNOTSUPP; 3862 3863 policy_ctxt = dpm_ctxt->dpm_policies; 3864 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !policy_ctxt || 3865 !policy_ctxt->policy_mask) 3866 return ret; 3867 3868 if (level < 0 || level >= PP_POLICY_MAX_LEVELS) 3869 return -EINVAL; 3870 3871 dpm_policy = smu_get_pm_policy(smu, p_type); 3872 3873 if (!dpm_policy || !dpm_policy->level_mask || !dpm_policy->set_policy) 3874 return ret; 3875 3876 if (dpm_policy->current_level == level) 3877 return 0; 3878 3879 ret = dpm_policy->set_policy(smu, level); 3880 3881 if (!ret) 3882 dpm_policy->current_level = level; 3883 3884 return ret; 3885 } 3886 3887 static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) 3888 { 3889 struct smu_context *smu = handle; 3890 struct smu_table_context *smu_table = &smu->smu_table; 3891 struct smu_driver_table *driver_tables = smu_table->driver_tables; 3892 enum smu_driver_table_id table_id; 3893 struct smu_driver_table *temp_table; 3894 3895 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3896 return -EOPNOTSUPP; 3897 3898 if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) 3899 return -EOPNOTSUPP; 3900 3901 table_id = smu_metrics_get_temp_table_id(type); 3902 3903 if (table_id == SMU_DRIVER_TABLE_COUNT) 3904 return -EINVAL; 3905 3906 temp_table = &driver_tables[table_id]; 3907 3908 /* If the request is to get size alone, return the cached table size */ 3909 if (!table && temp_table->cache.size) 3910 return temp_table->cache.size; 3911 3912 if (smu_driver_table_is_valid(temp_table)) { 3913 memcpy(table, temp_table->cache.buffer, temp_table->cache.size); 3914 return temp_table->cache.size; 3915 } 3916 3917 return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); 3918 } 3919 3920 static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) 3921 { 3922 struct smu_context *smu = handle; 3923 bool ret = false; 3924 3925 if (!smu->pm_enabled) 3926 return false; 3927 3928 if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) 3929 ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); 3930 3931 return ret; 3932 } 3933 3934 static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) 3935 { 3936 struct smu_context *smu = handle; 3937 3938 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3939 return -EOPNOTSUPP; 3940 3941 if (!smu->adev->xcp_mgr || !smu->ppt_funcs->get_xcp_metrics) 3942 return -EOPNOTSUPP; 3943 3944 return smu->ppt_funcs->get_xcp_metrics(smu, xcp_id, table); 3945 } 3946 3947 static const struct amd_pm_funcs swsmu_pm_funcs = { 3948 /* export for sysfs */ 3949 .set_fan_control_mode = smu_set_fan_control_mode, 3950 .get_fan_control_mode = smu_get_fan_control_mode, 3951 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3952 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3953 .force_clock_level = smu_force_ppclk_levels, 3954 .emit_clock_levels = smu_emit_ppclk_levels, 3955 .force_performance_level = smu_force_performance_level, 3956 .read_sensor = smu_read_sensor, 3957 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3958 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3959 .get_performance_level = smu_get_performance_level, 3960 .get_current_power_state = smu_get_current_power_state, 3961 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3962 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3963 .get_pp_num_states = smu_get_power_num_states, 3964 .get_pp_table = smu_sys_get_pp_table, 3965 .set_pp_table = smu_sys_set_pp_table, 3966 .switch_power_profile = smu_switch_power_profile, 3967 .pause_power_profile = smu_pause_power_profile, 3968 /* export to amdgpu */ 3969 .dispatch_tasks = smu_handle_dpm_task, 3970 .load_firmware = smu_load_microcode, 3971 .set_powergating_by_smu = smu_dpm_set_power_gate, 3972 .set_power_limit = smu_set_power_limit, 3973 .get_power_limit = smu_get_power_limit, 3974 .get_power_profile_mode = smu_get_power_profile_mode, 3975 .set_power_profile_mode = smu_set_power_profile_mode, 3976 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3977 .set_mp1_state = smu_set_mp1_state, 3978 .gfx_state_change_set = smu_gfx_state_change_set, 3979 /* export to DC */ 3980 .get_sclk = smu_get_sclk, 3981 .get_mclk = smu_get_mclk, 3982 .display_configuration_change = smu_display_configuration_change, 3983 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3984 .display_clock_voltage_request = smu_display_clock_voltage_request, 3985 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3986 .set_active_display_count = smu_set_display_count, 3987 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3988 .get_asic_baco_capability = smu_get_baco_capability, 3989 .set_asic_baco_state = smu_baco_set_state, 3990 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3991 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3992 .asic_reset_mode_2 = smu_mode2_reset, 3993 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3994 .set_df_cstate = smu_set_df_cstate, 3995 .set_xgmi_pstate = smu_set_xgmi_pstate, 3996 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3997 .get_pm_metrics = smu_sys_get_pm_metrics, 3998 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3999 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 4000 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 4001 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 4002 .get_dpm_clock_table = smu_get_dpm_clock_table, 4003 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 4004 .get_xcp_metrics = smu_sys_get_xcp_metrics, 4005 .get_temp_metrics = smu_sys_get_temp_metrics, 4006 .temp_metrics_is_supported = smu_temp_metrics_is_supported, 4007 }; 4008 4009 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 4010 uint64_t event_arg) 4011 { 4012 int ret = -EINVAL; 4013 4014 if (smu->ppt_funcs->wait_for_event) 4015 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 4016 4017 return ret; 4018 } 4019 4020 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 4021 { 4022 4023 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 4024 return -EOPNOTSUPP; 4025 4026 /* Confirm the buffer allocated is of correct size */ 4027 if (size != smu->stb_context.stb_buf_size) 4028 return -EINVAL; 4029 4030 /* 4031 * No need to lock smu mutex as we access STB directly through MMIO 4032 * and not going through SMU messaging route (for now at least). 4033 * For registers access rely on implementation internal locking. 4034 */ 4035 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 4036 } 4037 4038 #if defined(CONFIG_DEBUG_FS) 4039 4040 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 4041 { 4042 struct amdgpu_device *adev = filp->f_inode->i_private; 4043 struct smu_context *smu = adev->powerplay.pp_handle; 4044 unsigned char *buf; 4045 int r; 4046 4047 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 4048 if (!buf) 4049 return -ENOMEM; 4050 4051 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 4052 if (r) 4053 goto out; 4054 4055 filp->private_data = buf; 4056 4057 return 0; 4058 4059 out: 4060 kvfree(buf); 4061 return r; 4062 } 4063 4064 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 4065 loff_t *pos) 4066 { 4067 struct amdgpu_device *adev = filp->f_inode->i_private; 4068 struct smu_context *smu = adev->powerplay.pp_handle; 4069 4070 4071 if (!filp->private_data) 4072 return -EINVAL; 4073 4074 return simple_read_from_buffer(buf, 4075 size, 4076 pos, filp->private_data, 4077 smu->stb_context.stb_buf_size); 4078 } 4079 4080 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 4081 { 4082 kvfree(filp->private_data); 4083 filp->private_data = NULL; 4084 4085 return 0; 4086 } 4087 4088 /* 4089 * We have to define not only read method but also 4090 * open and release because .read takes up to PAGE_SIZE 4091 * data each time so and so is invoked multiple times. 4092 * We allocate the STB buffer in .open and release it 4093 * in .release 4094 */ 4095 static const struct file_operations smu_stb_debugfs_fops = { 4096 .owner = THIS_MODULE, 4097 .open = smu_stb_debugfs_open, 4098 .read = smu_stb_debugfs_read, 4099 .release = smu_stb_debugfs_release, 4100 .llseek = default_llseek, 4101 }; 4102 4103 #endif 4104 4105 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 4106 { 4107 #if defined(CONFIG_DEBUG_FS) 4108 4109 struct smu_context *smu = adev->powerplay.pp_handle; 4110 4111 if (!smu || (!smu->stb_context.stb_buf_size)) 4112 return; 4113 4114 debugfs_create_file_size("amdgpu_smu_stb_dump", 4115 S_IRUSR, 4116 adev_to_drm(adev)->primary->debugfs_root, 4117 adev, 4118 &smu_stb_debugfs_fops, 4119 smu->stb_context.stb_buf_size); 4120 #endif 4121 } 4122 4123 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 4124 { 4125 int ret = 0; 4126 4127 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 4128 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 4129 4130 return ret; 4131 } 4132 4133 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 4134 { 4135 int ret = 0; 4136 4137 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 4138 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 4139 4140 return ret; 4141 } 4142 4143 int smu_send_rma_reason(struct smu_context *smu) 4144 { 4145 int ret = 0; 4146 4147 if (smu->ppt_funcs && smu->ppt_funcs->send_rma_reason) 4148 ret = smu->ppt_funcs->send_rma_reason(smu); 4149 4150 return ret; 4151 } 4152 4153 /** 4154 * smu_reset_sdma_is_supported - Check if SDMA reset is supported by SMU 4155 * @smu: smu_context pointer 4156 * 4157 * This function checks if the SMU supports resetting the SDMA engine. 4158 * It returns true if supported, false otherwise. 4159 */ 4160 bool smu_reset_sdma_is_supported(struct smu_context *smu) 4161 { 4162 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); 4163 } 4164 4165 int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) 4166 { 4167 int ret = 0; 4168 4169 if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma) 4170 ret = smu->ppt_funcs->reset_sdma(smu, inst_mask); 4171 4172 return ret; 4173 } 4174 4175 bool smu_reset_vcn_is_supported(struct smu_context *smu) 4176 { 4177 return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); 4178 } 4179 4180 int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) 4181 { 4182 if (smu->ppt_funcs && smu->ppt_funcs->dpm_reset_vcn) 4183 smu->ppt_funcs->dpm_reset_vcn(smu, inst_mask); 4184 4185 return 0; 4186 } 4187