1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 #define SMC_DPM_FEATURE \
80 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
81 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \
82 FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \
83 FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \
84 FEATURE_MASK(FEATURE_DPM_VCN))
85
86 /* possible frequency drift (1Mhz) */
87 #define EPSILON 1
88
89 #define smnPCIE_ESM_CTRL 0x93D0
90 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
91 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
92 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
93 #define MAX_LINK_WIDTH 6
94
95 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
96 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
97 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
98 #define LINK_SPEED_MAX 4
99 #define SMU_13_0_6_DSCLK_THRESHOLD 140
100
101 #define MCA_BANK_IPID(_ip, _hwid, _type) \
102 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
103
104 #define SMU_CAP(x) SMU_13_0_6_CAPS_##x
105
106 enum smu_v13_0_6_caps {
107 SMU_CAP(DPM),
108 SMU_CAP(DPM_POLICY),
109 SMU_CAP(OTHER_END_METRICS),
110 SMU_CAP(SET_UCLK_MAX),
111 SMU_CAP(PCIE_METRICS),
112 SMU_CAP(MCA_DEBUG_MODE),
113 SMU_CAP(PER_INST_METRICS),
114 SMU_CAP(CTF_LIMIT),
115 SMU_CAP(RMA_MSG),
116 SMU_CAP(ACA_SYND),
117 SMU_CAP(SDMA_RESET),
118 SMU_CAP(STATIC_METRICS),
119 SMU_CAP(ALL),
120 };
121
122 struct mca_bank_ipid {
123 enum amdgpu_mca_ip ip;
124 uint16_t hwid;
125 uint16_t mcatype;
126 };
127
128 struct mca_ras_info {
129 enum amdgpu_ras_block blkid;
130 enum amdgpu_mca_ip ip;
131 int *err_code_array;
132 int err_code_count;
133 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
134 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
135 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
136 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
137 };
138
139 #define P2S_TABLE_ID_A 0x50325341
140 #define P2S_TABLE_ID_X 0x50325358
141 #define P2S_TABLE_ID_3 0x50325303
142
143 // clang-format off
144 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
145 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
146 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
147 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
148 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
149 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
150 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
151 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
152 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
153 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
154 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
155 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
156 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
157 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
158 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
159 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
160 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
161 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
162 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
163 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
164 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
165 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
166 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
167 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
168 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
169 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
170 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
171 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
172 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
173 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
174 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
175 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
176 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
177 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
178 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
179 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
180 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
181 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
182 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
183 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
184 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
185 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
186 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
187 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
188 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
189 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
190 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
191 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
192 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
193 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
194 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
195 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
196 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
197 };
198
199 // clang-format on
200 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
201 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
202 CLK_MAP(FCLK, PPCLK_FCLK),
203 CLK_MAP(UCLK, PPCLK_UCLK),
204 CLK_MAP(MCLK, PPCLK_UCLK),
205 CLK_MAP(DCLK, PPCLK_DCLK),
206 CLK_MAP(VCLK, PPCLK_VCLK),
207 CLK_MAP(LCLK, PPCLK_LCLK),
208 };
209
210 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
216 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
217 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
218 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
219 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
220 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
221 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
222 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
223 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
224 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
225 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
226 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
227 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
228 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
229 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
230 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
231 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
232 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
233 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
234 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN),
235 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK),
236 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK),
237 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK),
238 };
239
240 #define TABLE_PMSTATUSLOG 0
241 #define TABLE_SMU_METRICS 1
242 #define TABLE_I2C_COMMANDS 2
243 #define TABLE_COUNT 3
244
245 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
246 TAB_MAP(PMSTATUSLOG),
247 TAB_MAP(SMU_METRICS),
248 TAB_MAP(I2C_COMMANDS),
249 };
250
251 static const uint8_t smu_v13_0_6_throttler_map[] = {
252 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
253 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
254 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
255 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
256 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
257 };
258
259 #define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
260 (metrics_v0->field) : (metrics_v2->field))
261 #define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
262 (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
263 #define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
264 sizeof(MetricsTableV1_t),\
265 sizeof(MetricsTableV2_t)))
266
267 struct smu_v13_0_6_dpm_map {
268 enum smu_clk_type clk_type;
269 uint32_t feature_num;
270 struct smu_13_0_dpm_table *dpm_table;
271 uint32_t *freq_table;
272 };
273
smu_v13_0_6_get_metrics_version(struct smu_context * smu)274 static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
275 {
276 if ((smu->adev->flags & AMD_IS_APU) &&
277 smu->smc_fw_version <= 0x4556900)
278 return METRICS_VERSION_V1;
279 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
280 IP_VERSION(13, 0, 12))
281 return METRICS_VERSION_V2;
282
283 return METRICS_VERSION_V0;
284 }
285
smu_v13_0_6_cap_set(struct smu_context * smu,enum smu_v13_0_6_caps cap)286 static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
287 enum smu_v13_0_6_caps cap)
288 {
289 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
290
291 dpm_context->caps |= BIT_ULL(cap);
292 }
293
smu_v13_0_6_cap_clear(struct smu_context * smu,enum smu_v13_0_6_caps cap)294 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
295 enum smu_v13_0_6_caps cap)
296 {
297 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
298
299 dpm_context->caps &= ~BIT_ULL(cap);
300 }
301
smu_v13_0_6_cap_supported(struct smu_context * smu,enum smu_v13_0_6_caps cap)302 static inline bool smu_v13_0_6_cap_supported(struct smu_context *smu,
303 enum smu_v13_0_6_caps cap)
304 {
305 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
306
307 return !!(dpm_context->caps & BIT_ULL(cap));
308 }
309
smu_v13_0_14_init_caps(struct smu_context * smu)310 static void smu_v13_0_14_init_caps(struct smu_context *smu)
311 {
312 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
313 SMU_CAP(SET_UCLK_MAX),
314 SMU_CAP(DPM_POLICY),
315 SMU_CAP(PCIE_METRICS),
316 SMU_CAP(CTF_LIMIT),
317 SMU_CAP(MCA_DEBUG_MODE),
318 SMU_CAP(RMA_MSG),
319 SMU_CAP(ACA_SYND) };
320 uint32_t fw_ver = smu->smc_fw_version;
321
322 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
323 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
324
325 if (fw_ver >= 0x05550E00)
326 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
327 if (fw_ver >= 0x05550B00)
328 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
329 if (fw_ver >= 0x5551200)
330 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
331 }
332
smu_v13_0_12_init_caps(struct smu_context * smu)333 static void smu_v13_0_12_init_caps(struct smu_context *smu)
334 {
335 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
336 SMU_CAP(PCIE_METRICS),
337 SMU_CAP(CTF_LIMIT),
338 SMU_CAP(MCA_DEBUG_MODE),
339 SMU_CAP(RMA_MSG),
340 SMU_CAP(ACA_SYND),
341 SMU_CAP(OTHER_END_METRICS),
342 SMU_CAP(PER_INST_METRICS) };
343 uint32_t fw_ver = smu->smc_fw_version;
344
345 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
346 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
347
348 if (fw_ver < 0x00561900)
349 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
350
351 if (fw_ver >= 0x00561700)
352 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
353
354 if (fw_ver >= 0x00561E00)
355 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
356 }
357
smu_v13_0_6_init_caps(struct smu_context * smu)358 static void smu_v13_0_6_init_caps(struct smu_context *smu)
359 {
360 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
361 SMU_CAP(SET_UCLK_MAX),
362 SMU_CAP(DPM_POLICY),
363 SMU_CAP(PCIE_METRICS),
364 SMU_CAP(CTF_LIMIT),
365 SMU_CAP(MCA_DEBUG_MODE),
366 SMU_CAP(RMA_MSG),
367 SMU_CAP(ACA_SYND) };
368 struct amdgpu_device *adev = smu->adev;
369 uint32_t fw_ver = smu->smc_fw_version;
370 uint32_t pgm = (fw_ver >> 24) & 0xFF;
371
372 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
373 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
374
375 if (fw_ver < 0x552F00)
376 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
377 if (fw_ver < 0x554500)
378 smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
379
380 if (adev->flags & AMD_IS_APU) {
381 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
382 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
383 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
384 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
385
386 if (fw_ver >= 0x04556A00)
387 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
388 } else {
389 if (fw_ver >= 0x557600)
390 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
391 if (fw_ver < 0x00556000)
392 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
393 if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
394 smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
395 if (fw_ver < 0x556300)
396 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
397 if (fw_ver < 0x554800)
398 smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
399 if (fw_ver >= 0x556F00)
400 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
401 if (fw_ver < 0x00555a00)
402 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
403 if (fw_ver < 0x00555600)
404 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
405 }
406 if (((pgm == 7) && (fw_ver >= 0x7550700)) ||
407 ((pgm == 0) && (fw_ver >= 0x00557900)) ||
408 ((pgm == 4) && (fw_ver >= 0x4557000)))
409 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
410 }
411
smu_v13_0_x_init_caps(struct smu_context * smu)412 static void smu_v13_0_x_init_caps(struct smu_context *smu)
413 {
414 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
415 case IP_VERSION(13, 0, 12):
416 return smu_v13_0_12_init_caps(smu);
417 case IP_VERSION(13, 0, 14):
418 return smu_v13_0_14_init_caps(smu);
419 default:
420 return smu_v13_0_6_init_caps(smu);
421 }
422 }
423
smu_v13_0_6_check_fw_version(struct smu_context * smu)424 static int smu_v13_0_6_check_fw_version(struct smu_context *smu)
425 {
426 int r;
427
428 r = smu_v13_0_check_fw_version(smu);
429 /* Initialize caps flags once fw version is fetched */
430 if (!r)
431 smu_v13_0_x_init_caps(smu);
432
433 return r;
434 }
435
smu_v13_0_6_init_microcode(struct smu_context * smu)436 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
437 {
438 const struct smc_firmware_header_v2_1 *v2_1;
439 const struct common_firmware_header *hdr;
440 struct amdgpu_firmware_info *ucode = NULL;
441 struct smc_soft_pptable_entry *entries;
442 struct amdgpu_device *adev = smu->adev;
443 uint32_t p2s_table_id = P2S_TABLE_ID_A;
444 int ret = 0, i, p2stable_count;
445 int var = (adev->pdev->device & 0xF);
446 char ucode_prefix[15];
447
448 /* No need to load P2S tables in IOV mode or for smu v13.0.12 */
449 if (amdgpu_sriov_vf(adev) ||
450 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)))
451 return 0;
452
453 if (!(adev->flags & AMD_IS_APU)) {
454 p2s_table_id = P2S_TABLE_ID_X;
455 if (var == 0x5)
456 p2s_table_id = P2S_TABLE_ID_3;
457 }
458
459 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
460 sizeof(ucode_prefix));
461 ret = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
462 "amdgpu/%s.bin", ucode_prefix);
463 if (ret)
464 goto out;
465
466 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
467 amdgpu_ucode_print_smc_hdr(hdr);
468
469 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
470 * are used to carry p2s tables.
471 */
472 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
473 entries = (struct smc_soft_pptable_entry
474 *)((uint8_t *)v2_1 +
475 le32_to_cpu(v2_1->pptable_entry_offset));
476 p2stable_count = le32_to_cpu(v2_1->pptable_count);
477 for (i = 0; i < p2stable_count; i++) {
478 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
479 smu->pptable_firmware.data =
480 ((uint8_t *)v2_1 +
481 le32_to_cpu(entries[i].ppt_offset_bytes));
482 smu->pptable_firmware.size =
483 le32_to_cpu(entries[i].ppt_size_bytes);
484 break;
485 }
486 }
487
488 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
489 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
490 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
491 ucode->fw = &smu->pptable_firmware;
492 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
493 }
494
495 return 0;
496 out:
497 amdgpu_ucode_release(&adev->pm.fw);
498
499 return ret;
500 }
501
smu_v13_0_6_tables_init(struct smu_context * smu)502 static int smu_v13_0_6_tables_init(struct smu_context *smu)
503 {
504 struct smu_table_context *smu_table = &smu->smu_table;
505 struct smu_table *tables = smu_table->tables;
506 struct amdgpu_device *adev = smu->adev;
507 int gpu_metrcs_size = METRICS_TABLE_SIZE;
508
509 if (!(adev->flags & AMD_IS_APU))
510 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
512
513 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
514 max(gpu_metrcs_size,
515 smu_v13_0_12_get_max_metrics_size()),
516 PAGE_SIZE,
517 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
518
519 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
520 PAGE_SIZE,
521 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
522
523 smu_table->metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
524 if (!smu_table->metrics_table)
525 return -ENOMEM;
526 smu_table->metrics_time = 0;
527
528 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_7);
529 smu_table->gpu_metrics_table =
530 kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
531 if (!smu_table->gpu_metrics_table) {
532 kfree(smu_table->metrics_table);
533 return -ENOMEM;
534 }
535
536 smu_table->driver_pptable =
537 kzalloc(sizeof(struct PPTable_t), GFP_KERNEL);
538 if (!smu_table->driver_pptable) {
539 kfree(smu_table->metrics_table);
540 kfree(smu_table->gpu_metrics_table);
541 return -ENOMEM;
542 }
543
544 return 0;
545 }
546
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)547 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
548 int policy)
549 {
550 struct amdgpu_device *adev = smu->adev;
551 int ret, param;
552
553 switch (policy) {
554 case SOC_PSTATE_DEFAULT:
555 param = 0;
556 break;
557 case SOC_PSTATE_0:
558 param = 1;
559 break;
560 case SOC_PSTATE_1:
561 param = 2;
562 break;
563 case SOC_PSTATE_2:
564 param = 3;
565 break;
566 default:
567 return -EINVAL;
568 }
569
570 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetThrottlingPolicy,
571 param, NULL);
572
573 if (ret)
574 dev_err(adev->dev, "select soc pstate policy %d failed",
575 policy);
576
577 return ret;
578 }
579
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)580 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
581 {
582 struct amdgpu_device *adev = smu->adev;
583 int ret, param;
584
585 switch (level) {
586 case XGMI_PLPD_DEFAULT:
587 param = PPSMC_PLPD_MODE_DEFAULT;
588 break;
589 case XGMI_PLPD_OPTIMIZED:
590 param = PPSMC_PLPD_MODE_OPTIMIZED;
591 break;
592 case XGMI_PLPD_DISALLOW:
593 param = 0;
594 break;
595 default:
596 return -EINVAL;
597 }
598
599 if (level == XGMI_PLPD_DISALLOW)
600 ret = smu_cmn_send_smc_msg_with_param(
601 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
602 else
603 /* change xgmi per-link power down policy */
604 ret = smu_cmn_send_smc_msg_with_param(
605 smu, SMU_MSG_SelectPLPDMode, param, NULL);
606
607 if (ret)
608 dev_err(adev->dev,
609 "select xgmi per-link power down policy %d failed\n",
610 level);
611
612 return ret;
613 }
614
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)615 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
616 {
617 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
618 struct smu_dpm_policy *policy;
619
620 smu_dpm->dpm_context =
621 kzalloc(sizeof(struct smu_13_0_dpm_context), GFP_KERNEL);
622 if (!smu_dpm->dpm_context)
623 return -ENOMEM;
624 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
625
626 smu_dpm->dpm_policies =
627 kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL);
628 if (!smu_dpm->dpm_policies) {
629 kfree(smu_dpm->dpm_context);
630 return -ENOMEM;
631 }
632
633 if (!(smu->adev->flags & AMD_IS_APU)) {
634 policy = &(smu_dpm->dpm_policies->policies[0]);
635
636 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
637 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
638 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
639 BIT(SOC_PSTATE_2);
640 policy->current_level = SOC_PSTATE_DEFAULT;
641 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
642 smu_cmn_generic_soc_policy_desc(policy);
643 smu_dpm->dpm_policies->policy_mask |=
644 BIT(PP_PM_POLICY_SOC_PSTATE);
645 }
646 policy = &(smu_dpm->dpm_policies->policies[1]);
647
648 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
649 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
650 BIT(XGMI_PLPD_OPTIMIZED);
651 policy->current_level = XGMI_PLPD_DEFAULT;
652 policy->set_policy = smu_v13_0_6_select_plpd_policy;
653 smu_cmn_generic_plpd_policy_desc(policy);
654 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
655
656 return 0;
657 }
658
smu_v13_0_6_init_smc_tables(struct smu_context * smu)659 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
660 {
661 int ret = 0;
662
663 ret = smu_v13_0_6_tables_init(smu);
664 if (ret)
665 return ret;
666
667 ret = smu_v13_0_6_allocate_dpm_context(smu);
668
669 return ret;
670 }
671
smu_v13_0_6_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)672 static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu,
673 uint32_t *feature_mask,
674 uint32_t num)
675 {
676 if (num > 2)
677 return -EINVAL;
678
679 /* pptable will handle the features to enable */
680 memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
681
682 return 0;
683 }
684
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)685 static int smu_v13_0_6_get_metrics_table(struct smu_context *smu,
686 void *metrics_table, bool bypass_cache)
687 {
688 struct smu_table_context *smu_table = &smu->smu_table;
689 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
690 struct smu_table *table = &smu_table->driver_table;
691 int ret;
692
693 if (bypass_cache || !smu_table->metrics_time ||
694 time_after(jiffies,
695 smu_table->metrics_time + msecs_to_jiffies(1))) {
696 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
697 if (ret) {
698 dev_info(smu->adev->dev,
699 "Failed to export SMU metrics table!\n");
700 return ret;
701 }
702
703 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
704 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
705
706 smu_table->metrics_time = jiffies;
707 }
708
709 if (metrics_table)
710 memcpy(metrics_table, smu_table->metrics_table, table_size);
711
712 return 0;
713 }
714
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)715 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
716 void *metrics, size_t max_size)
717 {
718 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
719 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
720 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
721 struct amdgpu_pm_metrics *pm_metrics = metrics;
722 uint32_t pmfw_version;
723 int ret;
724
725 if (!pm_metrics || !max_size)
726 return -EINVAL;
727
728 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
729 return -EOVERFLOW;
730
731 /* Don't use cached metrics data */
732 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
733 if (ret)
734 return ret;
735
736 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
737
738 memset(&pm_metrics->common_header, 0,
739 sizeof(pm_metrics->common_header));
740 pm_metrics->common_header.mp1_ip_discovery_version =
741 amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
742 pm_metrics->common_header.pmfw_version = pmfw_version;
743 pm_metrics->common_header.pmmetrics_version = table_version;
744 pm_metrics->common_header.structure_size =
745 sizeof(pm_metrics->common_header) + table_size;
746
747 return pm_metrics->common_header.structure_size;
748 }
749
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)750 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
751 {
752 struct smu_table_context *smu_table = &smu->smu_table;
753 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
754 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
755 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
756 struct PPTable_t *pptable =
757 (struct PPTable_t *)smu_table->driver_pptable;
758 int version = smu_v13_0_6_get_metrics_version(smu);
759 int ret, i, retry = 100;
760 uint32_t table_version;
761
762 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
763 return smu_v13_0_12_setup_driver_pptable(smu);
764
765 /* Store one-time values in driver PPTable */
766 if (!pptable->Init) {
767 while (--retry) {
768 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
769 if (ret)
770 return ret;
771
772 /* Ensure that metrics have been updated */
773 if (GET_METRIC_FIELD(AccumulationCounter, version))
774 break;
775
776 usleep_range(1000, 1100);
777 }
778
779 if (!retry)
780 return -ETIME;
781
782 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
783 &table_version);
784 if (ret)
785 return ret;
786 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
787 table_version;
788
789 pptable->MaxSocketPowerLimit =
790 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
791 pptable->MaxGfxclkFrequency =
792 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
793 pptable->MinGfxclkFrequency =
794 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
795
796 for (i = 0; i < 4; ++i) {
797 pptable->FclkFrequencyTable[i] =
798 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
799 pptable->UclkFrequencyTable[i] =
800 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
801 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
802 GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
803 pptable->VclkFrequencyTable[i] =
804 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
805 pptable->DclkFrequencyTable[i] =
806 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
807 pptable->LclkFrequencyTable[i] =
808 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
809 }
810
811 /* use AID0 serial number by default */
812 pptable->PublicSerialNumber_AID =
813 GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
814
815 pptable->Init = true;
816 }
817
818 return 0;
819 }
820
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)821 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
822 enum smu_clk_type clk_type,
823 uint32_t *min, uint32_t *max)
824 {
825 struct smu_table_context *smu_table = &smu->smu_table;
826 struct PPTable_t *pptable =
827 (struct PPTable_t *)smu_table->driver_pptable;
828 uint32_t clock_limit = 0, param;
829 int ret = 0, clk_id = 0;
830
831 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
832 switch (clk_type) {
833 case SMU_MCLK:
834 case SMU_UCLK:
835 if (pptable->Init)
836 clock_limit = pptable->UclkFrequencyTable[0];
837 break;
838 case SMU_GFXCLK:
839 case SMU_SCLK:
840 if (pptable->Init)
841 clock_limit = pptable->MinGfxclkFrequency;
842 break;
843 case SMU_SOCCLK:
844 if (pptable->Init)
845 clock_limit = pptable->SocclkFrequencyTable[0];
846 break;
847 case SMU_FCLK:
848 if (pptable->Init)
849 clock_limit = pptable->FclkFrequencyTable[0];
850 break;
851 case SMU_VCLK:
852 if (pptable->Init)
853 clock_limit = pptable->VclkFrequencyTable[0];
854 break;
855 case SMU_DCLK:
856 if (pptable->Init)
857 clock_limit = pptable->DclkFrequencyTable[0];
858 break;
859 default:
860 break;
861 }
862
863 if (min)
864 *min = clock_limit;
865
866 if (max)
867 *max = clock_limit;
868
869 return 0;
870 }
871
872 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
873 clk_id = smu_cmn_to_asic_specific_index(
874 smu, CMN2ASIC_MAPPING_CLK, clk_type);
875 if (clk_id < 0) {
876 ret = -EINVAL;
877 goto failed;
878 }
879 param = (clk_id & 0xffff) << 16;
880 }
881
882 if (max) {
883 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
884 ret = smu_cmn_send_smc_msg(
885 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
886 else
887 ret = smu_cmn_send_smc_msg_with_param(
888 smu, SMU_MSG_GetMaxDpmFreq, param, max);
889 if (ret)
890 goto failed;
891 }
892
893 if (min) {
894 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
895 ret = smu_cmn_send_smc_msg(
896 smu, SMU_MSG_GetMinGfxclkFrequency, min);
897 else
898 ret = smu_cmn_send_smc_msg_with_param(
899 smu, SMU_MSG_GetMinDpmFreq, param, min);
900 }
901
902 failed:
903 return ret;
904 }
905
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)906 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
907 enum smu_clk_type clk_type,
908 uint32_t *levels)
909 {
910 int ret;
911
912 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
913 if (!ret)
914 ++(*levels);
915
916 return ret;
917 }
918
smu_v13_0_6_pm_policy_init(struct smu_context * smu)919 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
920 {
921 struct smu_dpm_policy *policy;
922
923 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
924 if (policy)
925 policy->current_level = SOC_PSTATE_DEFAULT;
926 }
927
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)928 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
929 {
930 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
931 struct smu_table_context *smu_table = &smu->smu_table;
932 struct smu_13_0_dpm_table *dpm_table = NULL;
933 struct PPTable_t *pptable =
934 (struct PPTable_t *)smu_table->driver_pptable;
935 uint32_t gfxclkmin, gfxclkmax, levels;
936 int ret = 0, i, j;
937 struct smu_v13_0_6_dpm_map dpm_map[] = {
938 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
939 &dpm_context->dpm_tables.soc_table,
940 pptable->SocclkFrequencyTable },
941 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
942 &dpm_context->dpm_tables.uclk_table,
943 pptable->UclkFrequencyTable },
944 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
945 &dpm_context->dpm_tables.fclk_table,
946 pptable->FclkFrequencyTable },
947 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
948 &dpm_context->dpm_tables.vclk_table,
949 pptable->VclkFrequencyTable },
950 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
951 &dpm_context->dpm_tables.dclk_table,
952 pptable->DclkFrequencyTable },
953 };
954
955 smu_v13_0_6_setup_driver_pptable(smu);
956
957 /* DPM policy not supported in older firmwares */
958 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
959 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
960
961 smu_dpm->dpm_policies->policy_mask &=
962 ~BIT(PP_PM_POLICY_SOC_PSTATE);
963 }
964
965 smu_v13_0_6_pm_policy_init(smu);
966 /* gfxclk dpm table setup */
967 dpm_table = &dpm_context->dpm_tables.gfx_table;
968 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
969 /* In the case of gfxclk, only fine-grained dpm is honored.
970 * Get min/max values from FW.
971 */
972 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
973 &gfxclkmin, &gfxclkmax);
974 if (ret)
975 return ret;
976
977 dpm_table->count = 2;
978 dpm_table->dpm_levels[0].value = gfxclkmin;
979 dpm_table->dpm_levels[0].enabled = true;
980 dpm_table->dpm_levels[1].value = gfxclkmax;
981 dpm_table->dpm_levels[1].enabled = true;
982 dpm_table->min = dpm_table->dpm_levels[0].value;
983 dpm_table->max = dpm_table->dpm_levels[1].value;
984 } else {
985 dpm_table->count = 1;
986 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
987 dpm_table->dpm_levels[0].enabled = true;
988 dpm_table->min = dpm_table->dpm_levels[0].value;
989 dpm_table->max = dpm_table->dpm_levels[0].value;
990 }
991
992 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
993 dpm_table = dpm_map[j].dpm_table;
994 levels = 1;
995 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
996 ret = smu_v13_0_6_get_dpm_level_count(
997 smu, dpm_map[j].clk_type, &levels);
998 if (ret)
999 return ret;
1000 }
1001 dpm_table->count = levels;
1002 for (i = 0; i < dpm_table->count; ++i) {
1003 dpm_table->dpm_levels[i].value =
1004 dpm_map[j].freq_table[i];
1005 dpm_table->dpm_levels[i].enabled = true;
1006
1007 }
1008 dpm_table->min = dpm_table->dpm_levels[0].value;
1009 dpm_table->max = dpm_table->dpm_levels[levels - 1].value;
1010
1011 }
1012
1013 return 0;
1014 }
1015
smu_v13_0_6_setup_pptable(struct smu_context * smu)1016 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
1017 {
1018 struct smu_table_context *table_context = &smu->smu_table;
1019
1020 /* TODO: PPTable is not available.
1021 * 1) Find an alternate way to get 'PPTable values' here.
1022 * 2) Check if there is SW CTF
1023 */
1024 table_context->thermal_controller_type = 0;
1025
1026 return 0;
1027 }
1028
smu_v13_0_6_check_fw_status(struct smu_context * smu)1029 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
1030 {
1031 struct amdgpu_device *adev = smu->adev;
1032 uint32_t mp1_fw_flags;
1033
1034 mp1_fw_flags =
1035 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
1036
1037 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
1038 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
1039 return 0;
1040
1041 return -EIO;
1042 }
1043
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)1044 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
1045 {
1046 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1047 struct smu_13_0_dpm_table *gfx_table =
1048 &dpm_context->dpm_tables.gfx_table;
1049 struct smu_13_0_dpm_table *mem_table =
1050 &dpm_context->dpm_tables.uclk_table;
1051 struct smu_13_0_dpm_table *soc_table =
1052 &dpm_context->dpm_tables.soc_table;
1053 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1054
1055 pstate_table->gfxclk_pstate.min = gfx_table->min;
1056 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1057 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1058 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1059
1060 pstate_table->uclk_pstate.min = mem_table->min;
1061 pstate_table->uclk_pstate.peak = mem_table->max;
1062 pstate_table->uclk_pstate.curr.min = mem_table->min;
1063 pstate_table->uclk_pstate.curr.max = mem_table->max;
1064
1065 pstate_table->socclk_pstate.min = soc_table->min;
1066 pstate_table->socclk_pstate.peak = soc_table->max;
1067 pstate_table->socclk_pstate.curr.min = soc_table->min;
1068 pstate_table->socclk_pstate.curr.max = soc_table->max;
1069
1070 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
1071 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
1072 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
1073 pstate_table->gfxclk_pstate.standard =
1074 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
1075 pstate_table->uclk_pstate.standard =
1076 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
1077 pstate_table->socclk_pstate.standard =
1078 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
1079 } else {
1080 pstate_table->gfxclk_pstate.standard =
1081 pstate_table->gfxclk_pstate.min;
1082 pstate_table->uclk_pstate.standard =
1083 pstate_table->uclk_pstate.min;
1084 pstate_table->socclk_pstate.standard =
1085 pstate_table->socclk_pstate.min;
1086 }
1087
1088 return 0;
1089 }
1090
smu_v13_0_6_get_clk_table(struct smu_context * smu,struct pp_clock_levels_with_latency * clocks,struct smu_13_0_dpm_table * dpm_table)1091 static int smu_v13_0_6_get_clk_table(struct smu_context *smu,
1092 struct pp_clock_levels_with_latency *clocks,
1093 struct smu_13_0_dpm_table *dpm_table)
1094 {
1095 int i, count;
1096
1097 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS :
1098 dpm_table->count;
1099 clocks->num_levels = count;
1100
1101 for (i = 0; i < count; i++) {
1102 clocks->data[i].clocks_in_khz =
1103 dpm_table->dpm_levels[i].value * 1000;
1104 clocks->data[i].latency_in_us = 0;
1105 }
1106
1107 return 0;
1108 }
1109
smu_v13_0_6_freqs_in_same_level(int32_t frequency1,int32_t frequency2)1110 static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1,
1111 int32_t frequency2)
1112 {
1113 return (abs(frequency1 - frequency2) <= EPSILON);
1114 }
1115
smu_v13_0_6_get_throttler_status(struct smu_context * smu)1116 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
1117 {
1118 struct smu_power_context *smu_power = &smu->smu_power;
1119 struct smu_13_0_power_context *power_context = smu_power->power_context;
1120 uint32_t throttler_status = 0;
1121
1122 throttler_status = atomic_read(&power_context->throttle_status);
1123 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
1124
1125 return throttler_status;
1126 }
1127
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1128 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
1129 MetricsMember_t member,
1130 uint32_t *value)
1131 {
1132 struct smu_table_context *smu_table = &smu->smu_table;
1133 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
1134 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
1135 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
1136 int version = smu_v13_0_6_get_metrics_version(smu);
1137 struct amdgpu_device *adev = smu->adev;
1138 int ret = 0;
1139 int xcc_id;
1140
1141 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
1142 if (ret)
1143 return ret;
1144
1145 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
1146 return smu_v13_0_12_get_smu_metrics_data(smu, member, value);
1147
1148 /* For clocks with multiple instances, only report the first one */
1149 switch (member) {
1150 case METRICS_CURR_GFXCLK:
1151 case METRICS_AVERAGE_GFXCLK:
1152 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
1153 xcc_id = GET_INST(GC, 0);
1154 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
1155 } else {
1156 *value = 0;
1157 }
1158 break;
1159 case METRICS_CURR_SOCCLK:
1160 case METRICS_AVERAGE_SOCCLK:
1161 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
1162 break;
1163 case METRICS_CURR_UCLK:
1164 case METRICS_AVERAGE_UCLK:
1165 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
1166 break;
1167 case METRICS_CURR_VCLK:
1168 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
1169 break;
1170 case METRICS_CURR_DCLK:
1171 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
1172 break;
1173 case METRICS_CURR_FCLK:
1174 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
1175 break;
1176 case METRICS_AVERAGE_GFXACTIVITY:
1177 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
1178 break;
1179 case METRICS_AVERAGE_MEMACTIVITY:
1180 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
1181 break;
1182 case METRICS_CURR_SOCKETPOWER:
1183 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
1184 break;
1185 case METRICS_TEMPERATURE_HOTSPOT:
1186 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
1187 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1188 break;
1189 case METRICS_TEMPERATURE_MEM:
1190 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
1191 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1192 break;
1193 /* This is the max of all VRs and not just SOC VR.
1194 * No need to define another data type for the same.
1195 */
1196 case METRICS_TEMPERATURE_VRSOC:
1197 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
1198 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1199 break;
1200 default:
1201 *value = UINT_MAX;
1202 break;
1203 }
1204
1205 return ret;
1206 }
1207
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1208 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1209 enum smu_clk_type clk_type,
1210 uint32_t *value)
1211 {
1212 MetricsMember_t member_type;
1213
1214 if (!value)
1215 return -EINVAL;
1216
1217 switch (clk_type) {
1218 case SMU_GFXCLK:
1219 member_type = METRICS_CURR_GFXCLK;
1220 break;
1221 case SMU_UCLK:
1222 member_type = METRICS_CURR_UCLK;
1223 break;
1224 case SMU_SOCCLK:
1225 member_type = METRICS_CURR_SOCCLK;
1226 break;
1227 case SMU_VCLK:
1228 member_type = METRICS_CURR_VCLK;
1229 break;
1230 case SMU_DCLK:
1231 member_type = METRICS_CURR_DCLK;
1232 break;
1233 case SMU_FCLK:
1234 member_type = METRICS_CURR_FCLK;
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1241 }
1242
smu_v13_0_6_print_clks(struct smu_context * smu,char * buf,int size,struct smu_13_0_dpm_table * single_dpm_table,uint32_t curr_clk,const char * clk_name)1243 static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size,
1244 struct smu_13_0_dpm_table *single_dpm_table,
1245 uint32_t curr_clk, const char *clk_name)
1246 {
1247 struct pp_clock_levels_with_latency clocks;
1248 int i, ret, level = -1;
1249 uint32_t clk1, clk2;
1250
1251 ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table);
1252 if (ret) {
1253 dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!",
1254 clk_name);
1255 return ret;
1256 }
1257
1258 if (!clocks.num_levels)
1259 return -EINVAL;
1260
1261 if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) {
1262 size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk);
1263 for (i = 0; i < clocks.num_levels; i++)
1264 size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i,
1265 clocks.data[i].clocks_in_khz /
1266 1000);
1267
1268 } else {
1269 if ((clocks.num_levels == 1) ||
1270 (curr_clk < (clocks.data[0].clocks_in_khz / 1000)))
1271 level = 0;
1272 for (i = 0; i < clocks.num_levels; i++) {
1273 clk1 = clocks.data[i].clocks_in_khz / 1000;
1274
1275 if (i < (clocks.num_levels - 1))
1276 clk2 = clocks.data[i + 1].clocks_in_khz / 1000;
1277
1278 if (curr_clk == clk1) {
1279 level = i;
1280 } else if (curr_clk >= clk1 && curr_clk < clk2) {
1281 level = (curr_clk - clk1) <= (clk2 - curr_clk) ?
1282 i :
1283 i + 1;
1284 }
1285
1286 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
1287 clk1, (level == i) ? "*" : "");
1288 }
1289 }
1290
1291 return size;
1292 }
1293
smu_v13_0_6_print_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf)1294 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
1295 enum smu_clk_type type, char *buf)
1296 {
1297 int now, size = 0;
1298 int ret = 0;
1299 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1300 struct smu_13_0_dpm_table *single_dpm_table;
1301 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1302 struct smu_13_0_dpm_context *dpm_context = NULL;
1303 uint32_t min_clk, max_clk;
1304
1305 smu_cmn_get_sysfs_buf(&buf, &size);
1306
1307 if (amdgpu_ras_intr_triggered()) {
1308 size += sysfs_emit_at(buf, size, "unavailable\n");
1309 return size;
1310 }
1311
1312 dpm_context = smu_dpm->dpm_context;
1313
1314 switch (type) {
1315 case SMU_OD_SCLK:
1316 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1317 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1318 pstate_table->gfxclk_pstate.curr.min,
1319 pstate_table->gfxclk_pstate.curr.max);
1320 break;
1321 case SMU_SCLK:
1322 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK,
1323 &now);
1324 if (ret) {
1325 dev_err(smu->adev->dev,
1326 "Attempt to get current gfx clk Failed!");
1327 return ret;
1328 }
1329
1330 min_clk = pstate_table->gfxclk_pstate.curr.min;
1331 max_clk = pstate_table->gfxclk_pstate.curr.max;
1332
1333 if (now < SMU_13_0_6_DSCLK_THRESHOLD) {
1334 size += sysfs_emit_at(buf, size, "S: %uMhz *\n",
1335 now);
1336 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1337 min_clk);
1338 size += sysfs_emit_at(buf, size, "1: %uMhz\n",
1339 max_clk);
1340
1341 } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) &&
1342 !smu_v13_0_6_freqs_in_same_level(now, max_clk)) {
1343 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1344 min_clk);
1345 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1346 now);
1347 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1348 max_clk);
1349 } else {
1350 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1351 min_clk,
1352 smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : "");
1353 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1354 max_clk,
1355 smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : "");
1356 }
1357
1358 break;
1359
1360 case SMU_OD_MCLK:
1361 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
1362 return 0;
1363
1364 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1365 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1366 pstate_table->uclk_pstate.curr.min,
1367 pstate_table->uclk_pstate.curr.max);
1368 break;
1369 case SMU_MCLK:
1370 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK,
1371 &now);
1372 if (ret) {
1373 dev_err(smu->adev->dev,
1374 "Attempt to get current mclk Failed!");
1375 return ret;
1376 }
1377
1378 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1379
1380 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1381 now, "mclk");
1382
1383 case SMU_SOCCLK:
1384 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK,
1385 &now);
1386 if (ret) {
1387 dev_err(smu->adev->dev,
1388 "Attempt to get current socclk Failed!");
1389 return ret;
1390 }
1391
1392 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1393
1394 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1395 now, "socclk");
1396
1397 case SMU_FCLK:
1398 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK,
1399 &now);
1400 if (ret) {
1401 dev_err(smu->adev->dev,
1402 "Attempt to get current fclk Failed!");
1403 return ret;
1404 }
1405
1406 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1407
1408 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1409 now, "fclk");
1410
1411 case SMU_VCLK:
1412 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK,
1413 &now);
1414 if (ret) {
1415 dev_err(smu->adev->dev,
1416 "Attempt to get current vclk Failed!");
1417 return ret;
1418 }
1419
1420 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1421
1422 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1423 now, "vclk");
1424
1425 case SMU_DCLK:
1426 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK,
1427 &now);
1428 if (ret) {
1429 dev_err(smu->adev->dev,
1430 "Attempt to get current dclk Failed!");
1431 return ret;
1432 }
1433
1434 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1435
1436 return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table,
1437 now, "dclk");
1438
1439 default:
1440 break;
1441 }
1442
1443 return size;
1444 }
1445
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1446 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1447 uint32_t feature_mask, uint32_t level)
1448 {
1449 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1450 uint32_t freq;
1451 int ret = 0;
1452
1453 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1454 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1455 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1456 ret = smu_cmn_send_smc_msg_with_param(
1457 smu,
1458 (max ? SMU_MSG_SetSoftMaxGfxClk :
1459 SMU_MSG_SetSoftMinGfxclk),
1460 freq & 0xffff, NULL);
1461 if (ret) {
1462 dev_err(smu->adev->dev,
1463 "Failed to set soft %s gfxclk !\n",
1464 max ? "max" : "min");
1465 return ret;
1466 }
1467 }
1468
1469 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1470 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1471 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1472 .value;
1473 ret = smu_cmn_send_smc_msg_with_param(
1474 smu,
1475 (max ? SMU_MSG_SetSoftMaxByFreq :
1476 SMU_MSG_SetSoftMinByFreq),
1477 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1478 if (ret) {
1479 dev_err(smu->adev->dev,
1480 "Failed to set soft %s memclk !\n",
1481 max ? "max" : "min");
1482 return ret;
1483 }
1484 }
1485
1486 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1487 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1488 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1489 ret = smu_cmn_send_smc_msg_with_param(
1490 smu,
1491 (max ? SMU_MSG_SetSoftMaxByFreq :
1492 SMU_MSG_SetSoftMinByFreq),
1493 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1494 if (ret) {
1495 dev_err(smu->adev->dev,
1496 "Failed to set soft %s socclk !\n",
1497 max ? "max" : "min");
1498 return ret;
1499 }
1500 }
1501
1502 return ret;
1503 }
1504
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1505 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1506 enum smu_clk_type type, uint32_t mask)
1507 {
1508 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1509 struct smu_13_0_dpm_table *single_dpm_table = NULL;
1510 uint32_t soft_min_level, soft_max_level;
1511 int ret = 0;
1512
1513 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1514 soft_max_level = mask ? (fls(mask) - 1) : 0;
1515
1516 switch (type) {
1517 case SMU_SCLK:
1518 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1519 if (soft_max_level >= single_dpm_table->count) {
1520 dev_err(smu->adev->dev,
1521 "Clock level specified %d is over max allowed %d\n",
1522 soft_max_level, single_dpm_table->count - 1);
1523 ret = -EINVAL;
1524 break;
1525 }
1526
1527 ret = smu_v13_0_6_upload_dpm_level(
1528 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1529 soft_min_level);
1530 if (ret) {
1531 dev_err(smu->adev->dev,
1532 "Failed to upload boot level to lowest!\n");
1533 break;
1534 }
1535
1536 ret = smu_v13_0_6_upload_dpm_level(
1537 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1538 soft_max_level);
1539 if (ret)
1540 dev_err(smu->adev->dev,
1541 "Failed to upload dpm max level to highest!\n");
1542
1543 break;
1544
1545 case SMU_MCLK:
1546 case SMU_SOCCLK:
1547 case SMU_FCLK:
1548 /*
1549 * Should not arrive here since smu_13_0_6 does not
1550 * support mclk/socclk/fclk softmin/softmax settings
1551 */
1552 ret = -EINVAL;
1553 break;
1554
1555 default:
1556 break;
1557 }
1558
1559 return ret;
1560 }
1561
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1562 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1563 enum amd_pp_sensors sensor,
1564 uint32_t *value)
1565 {
1566 int ret = 0;
1567
1568 if (!value)
1569 return -EINVAL;
1570
1571 switch (sensor) {
1572 case AMDGPU_PP_SENSOR_GPU_LOAD:
1573 ret = smu_v13_0_6_get_smu_metrics_data(
1574 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1575 break;
1576 case AMDGPU_PP_SENSOR_MEM_LOAD:
1577 ret = smu_v13_0_6_get_smu_metrics_data(
1578 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1579 break;
1580 default:
1581 dev_err(smu->adev->dev,
1582 "Invalid sensor for retrieving clock activity\n");
1583 return -EINVAL;
1584 }
1585
1586 return ret;
1587 }
1588
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1589 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1590 enum amd_pp_sensors sensor,
1591 uint32_t *value)
1592 {
1593 int ret = 0;
1594
1595 if (!value)
1596 return -EINVAL;
1597
1598 switch (sensor) {
1599 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1600 ret = smu_v13_0_6_get_smu_metrics_data(
1601 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1602 break;
1603 case AMDGPU_PP_SENSOR_MEM_TEMP:
1604 ret = smu_v13_0_6_get_smu_metrics_data(
1605 smu, METRICS_TEMPERATURE_MEM, value);
1606 break;
1607 default:
1608 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1609 return -EINVAL;
1610 }
1611
1612 return ret;
1613 }
1614
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1615 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1616 enum amd_pp_sensors sensor, void *data,
1617 uint32_t *size)
1618 {
1619 int ret = 0;
1620
1621 if (amdgpu_ras_intr_triggered())
1622 return 0;
1623
1624 if (!data || !size)
1625 return -EINVAL;
1626
1627 switch (sensor) {
1628 case AMDGPU_PP_SENSOR_MEM_LOAD:
1629 case AMDGPU_PP_SENSOR_GPU_LOAD:
1630 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1631 (uint32_t *)data);
1632 *size = 4;
1633 break;
1634 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1635 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1636 METRICS_CURR_SOCKETPOWER,
1637 (uint32_t *)data);
1638 *size = 4;
1639 break;
1640 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1641 case AMDGPU_PP_SENSOR_MEM_TEMP:
1642 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1643 (uint32_t *)data);
1644 *size = 4;
1645 break;
1646 case AMDGPU_PP_SENSOR_GFX_MCLK:
1647 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1648 smu, SMU_UCLK, (uint32_t *)data);
1649 /* the output clock frequency in 10K unit */
1650 *(uint32_t *)data *= 100;
1651 *size = 4;
1652 break;
1653 case AMDGPU_PP_SENSOR_GFX_SCLK:
1654 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1655 smu, SMU_GFXCLK, (uint32_t *)data);
1656 *(uint32_t *)data *= 100;
1657 *size = 4;
1658 break;
1659 case AMDGPU_PP_SENSOR_VDDGFX:
1660 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1661 *size = 4;
1662 break;
1663 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1664 default:
1665 ret = -EOPNOTSUPP;
1666 break;
1667 }
1668
1669 return ret;
1670 }
1671
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1672 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1673 uint32_t *current_power_limit,
1674 uint32_t *default_power_limit,
1675 uint32_t *max_power_limit,
1676 uint32_t *min_power_limit)
1677 {
1678 struct smu_table_context *smu_table = &smu->smu_table;
1679 struct PPTable_t *pptable =
1680 (struct PPTable_t *)smu_table->driver_pptable;
1681 uint32_t power_limit = 0;
1682 int ret;
1683
1684 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1685
1686 if (ret) {
1687 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1688 return -EINVAL;
1689 }
1690
1691 if (current_power_limit)
1692 *current_power_limit = power_limit;
1693 if (default_power_limit)
1694 *default_power_limit = power_limit;
1695
1696 if (max_power_limit) {
1697 *max_power_limit = pptable->MaxSocketPowerLimit;
1698 }
1699
1700 if (min_power_limit)
1701 *min_power_limit = 0;
1702 return 0;
1703 }
1704
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1705 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1706 enum smu_ppt_limit_type limit_type,
1707 uint32_t limit)
1708 {
1709 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1710 }
1711
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1712 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1713 struct amdgpu_irq_src *source,
1714 struct amdgpu_iv_entry *entry)
1715 {
1716 struct smu_context *smu = adev->powerplay.pp_handle;
1717 struct smu_power_context *smu_power = &smu->smu_power;
1718 struct smu_13_0_power_context *power_context = smu_power->power_context;
1719 uint32_t client_id = entry->client_id;
1720 uint32_t ctxid = entry->src_data[0];
1721 uint32_t src_id = entry->src_id;
1722 uint32_t data;
1723
1724 if (client_id == SOC15_IH_CLIENTID_MP1) {
1725 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1726 /* ACK SMUToHost interrupt */
1727 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1728 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1729 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1730 /*
1731 * ctxid is used to distinguish different events for SMCToHost
1732 * interrupt.
1733 */
1734 switch (ctxid) {
1735 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1736 /*
1737 * Increment the throttle interrupt counter
1738 */
1739 atomic64_inc(&smu->throttle_int_counter);
1740
1741 if (!atomic_read(&adev->throttling_logging_enabled))
1742 return 0;
1743
1744 /* This uses the new method which fixes the
1745 * incorrect throttling status reporting
1746 * through metrics table. For older FWs,
1747 * it will be ignored.
1748 */
1749 if (__ratelimit(&adev->throttling_logging_rs)) {
1750 atomic_set(
1751 &power_context->throttle_status,
1752 entry->src_data[1]);
1753 schedule_work(&smu->throttling_logging_work);
1754 }
1755 break;
1756 default:
1757 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1758 ctxid, client_id);
1759 break;
1760 }
1761 }
1762 }
1763
1764 return 0;
1765 }
1766
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1767 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1768 struct amdgpu_irq_src *source,
1769 unsigned tyep,
1770 enum amdgpu_interrupt_state state)
1771 {
1772 uint32_t val = 0;
1773
1774 switch (state) {
1775 case AMDGPU_IRQ_STATE_DISABLE:
1776 /* For MP1 SW irqs */
1777 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1778 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1779 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1780
1781 break;
1782 case AMDGPU_IRQ_STATE_ENABLE:
1783 /* For MP1 SW irqs */
1784 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1785 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1786 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1787 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1788
1789 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1790 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1791 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1792
1793 break;
1794 default:
1795 break;
1796 }
1797
1798 return 0;
1799 }
1800
1801 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1802 .set = smu_v13_0_6_set_irq_state,
1803 .process = smu_v13_0_6_irq_process,
1804 };
1805
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1806 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1807 {
1808 struct amdgpu_device *adev = smu->adev;
1809 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1810 int ret = 0;
1811
1812 if (amdgpu_sriov_vf(adev))
1813 return 0;
1814
1815 irq_src->num_types = 1;
1816 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1817
1818 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1819 IH_INTERRUPT_ID_TO_DRIVER,
1820 irq_src);
1821 if (ret)
1822 return ret;
1823
1824 return ret;
1825 }
1826
smu_v13_0_6_notify_unload(struct smu_context * smu)1827 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1828 {
1829 if (amdgpu_in_reset(smu->adev))
1830 return 0;
1831
1832 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1833 /* Ignore return, just intimate FW that driver is not going to be there */
1834 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1835
1836 return 0;
1837 }
1838
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1839 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1840 {
1841 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1842 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
1843 return 0;
1844
1845 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1846 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1847 NULL);
1848 }
1849
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1850 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1851 bool enable)
1852 {
1853 struct amdgpu_device *adev = smu->adev;
1854 int ret = 0;
1855
1856 if (amdgpu_sriov_vf(adev))
1857 return 0;
1858
1859 if (enable) {
1860 if (!(adev->flags & AMD_IS_APU))
1861 ret = smu_v13_0_system_features_control(smu, enable);
1862 } else {
1863 /* Notify FW that the device is no longer driver managed */
1864 smu_v13_0_6_notify_unload(smu);
1865 }
1866
1867 return ret;
1868 }
1869
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1870 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1871 uint32_t min,
1872 uint32_t max)
1873 {
1874 int ret;
1875
1876 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1877 max & 0xffff, NULL);
1878 if (ret)
1879 return ret;
1880
1881 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1882 min & 0xffff, NULL);
1883
1884 return ret;
1885 }
1886
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1887 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1888 enum amd_dpm_forced_level level)
1889 {
1890 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1891 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1892 struct smu_13_0_dpm_table *gfx_table =
1893 &dpm_context->dpm_tables.gfx_table;
1894 struct smu_13_0_dpm_table *uclk_table =
1895 &dpm_context->dpm_tables.uclk_table;
1896 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1897 int ret;
1898
1899 /* Disable determinism if switching to another mode */
1900 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1901 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1902 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1903 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1904 }
1905
1906 switch (level) {
1907 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1908 return 0;
1909
1910 case AMD_DPM_FORCED_LEVEL_AUTO:
1911 if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) ||
1912 (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) {
1913 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1914 smu, gfx_table->min, gfx_table->max);
1915 if (ret)
1916 return ret;
1917
1918 pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
1919 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1920 }
1921
1922 if (uclk_table->max != pstate_table->uclk_pstate.curr.max) {
1923 /* Min UCLK is not expected to be changed */
1924 ret = smu_v13_0_set_soft_freq_limited_range(
1925 smu, SMU_UCLK, 0, uclk_table->max, false);
1926 if (ret)
1927 return ret;
1928 pstate_table->uclk_pstate.curr.max = uclk_table->max;
1929 }
1930 pstate_table->uclk_pstate.custom.max = 0;
1931
1932 return 0;
1933 case AMD_DPM_FORCED_LEVEL_MANUAL:
1934 return 0;
1935 default:
1936 break;
1937 }
1938
1939 return -EOPNOTSUPP;
1940 }
1941
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1942 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
1943 enum smu_clk_type clk_type,
1944 uint32_t min, uint32_t max,
1945 bool automatic)
1946 {
1947 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1948 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1949 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1950 struct amdgpu_device *adev = smu->adev;
1951 uint32_t min_clk;
1952 uint32_t max_clk;
1953 int ret = 0;
1954
1955 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
1956 clk_type != SMU_UCLK)
1957 return -EINVAL;
1958
1959 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
1960 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1961 return -EINVAL;
1962
1963 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1964 if (min >= max) {
1965 dev_err(smu->adev->dev,
1966 "Minimum clk should be less than the maximum allowed clock\n");
1967 return -EINVAL;
1968 }
1969
1970 if (clk_type == SMU_GFXCLK) {
1971 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1972 (max == pstate_table->gfxclk_pstate.curr.max))
1973 return 0;
1974
1975 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
1976 smu, min, max);
1977 if (!ret) {
1978 pstate_table->gfxclk_pstate.curr.min = min;
1979 pstate_table->gfxclk_pstate.curr.max = max;
1980 }
1981 }
1982
1983 if (clk_type == SMU_UCLK) {
1984 if (max == pstate_table->uclk_pstate.curr.max)
1985 return 0;
1986 /* For VF, only allowed in FW versions 85.102 or greater */
1987 if (!smu_v13_0_6_cap_supported(smu,
1988 SMU_CAP(SET_UCLK_MAX)))
1989 return -EOPNOTSUPP;
1990 /* Only max clock limiting is allowed for UCLK */
1991 ret = smu_v13_0_set_soft_freq_limited_range(
1992 smu, SMU_UCLK, 0, max, false);
1993 if (!ret)
1994 pstate_table->uclk_pstate.curr.max = max;
1995 }
1996
1997 return ret;
1998 }
1999
2000 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2001 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
2002 (max > dpm_context->dpm_tables.gfx_table.max)) {
2003 dev_warn(
2004 adev->dev,
2005 "Invalid max frequency %d MHz specified for determinism\n",
2006 max);
2007 return -EINVAL;
2008 }
2009
2010 /* Restore default min/max clocks and enable determinism */
2011 min_clk = dpm_context->dpm_tables.gfx_table.min;
2012 max_clk = dpm_context->dpm_tables.gfx_table.max;
2013 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
2014 max_clk);
2015 if (!ret) {
2016 usleep_range(500, 1000);
2017 ret = smu_cmn_send_smc_msg_with_param(
2018 smu, SMU_MSG_EnableDeterminism, max, NULL);
2019 if (ret) {
2020 dev_err(adev->dev,
2021 "Failed to enable determinism at GFX clock %d MHz\n",
2022 max);
2023 } else {
2024 pstate_table->gfxclk_pstate.curr.min = min_clk;
2025 pstate_table->gfxclk_pstate.curr.max = max;
2026 }
2027 }
2028 }
2029
2030 return ret;
2031 }
2032
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2033 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
2034 enum PP_OD_DPM_TABLE_COMMAND type,
2035 long input[], uint32_t size)
2036 {
2037 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2038 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2039 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2040 uint32_t min_clk;
2041 uint32_t max_clk;
2042 int ret = 0;
2043
2044 /* Only allowed in manual or determinism mode */
2045 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2046 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2047 return -EINVAL;
2048
2049 switch (type) {
2050 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2051 if (size != 2) {
2052 dev_err(smu->adev->dev,
2053 "Input parameter number not correct\n");
2054 return -EINVAL;
2055 }
2056
2057 if (input[0] == 0) {
2058 if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
2059 dev_warn(
2060 smu->adev->dev,
2061 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
2062 input[1],
2063 dpm_context->dpm_tables.gfx_table.min);
2064 pstate_table->gfxclk_pstate.custom.min =
2065 pstate_table->gfxclk_pstate.curr.min;
2066 return -EINVAL;
2067 }
2068
2069 pstate_table->gfxclk_pstate.custom.min = input[1];
2070 } else if (input[0] == 1) {
2071 if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
2072 dev_warn(
2073 smu->adev->dev,
2074 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2075 input[1],
2076 dpm_context->dpm_tables.gfx_table.max);
2077 pstate_table->gfxclk_pstate.custom.max =
2078 pstate_table->gfxclk_pstate.curr.max;
2079 return -EINVAL;
2080 }
2081
2082 pstate_table->gfxclk_pstate.custom.max = input[1];
2083 } else {
2084 return -EINVAL;
2085 }
2086 break;
2087 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2088 if (size != 2) {
2089 dev_err(smu->adev->dev,
2090 "Input parameter number not correct\n");
2091 return -EINVAL;
2092 }
2093
2094 if (!smu_cmn_feature_is_enabled(smu,
2095 SMU_FEATURE_DPM_UCLK_BIT)) {
2096 dev_warn(smu->adev->dev,
2097 "UCLK_LIMITS setting not supported!\n");
2098 return -EOPNOTSUPP;
2099 }
2100
2101 if (input[0] == 0) {
2102 dev_info(smu->adev->dev,
2103 "Setting min UCLK level is not supported");
2104 return -EINVAL;
2105 } else if (input[0] == 1) {
2106 if (input[1] > dpm_context->dpm_tables.uclk_table.max) {
2107 dev_warn(
2108 smu->adev->dev,
2109 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2110 input[1],
2111 dpm_context->dpm_tables.uclk_table.max);
2112 pstate_table->uclk_pstate.custom.max =
2113 pstate_table->uclk_pstate.curr.max;
2114 return -EINVAL;
2115 }
2116
2117 pstate_table->uclk_pstate.custom.max = input[1];
2118 }
2119 break;
2120
2121 case PP_OD_RESTORE_DEFAULT_TABLE:
2122 if (size != 0) {
2123 dev_err(smu->adev->dev,
2124 "Input parameter number not correct\n");
2125 return -EINVAL;
2126 } else {
2127 /* Use the default frequencies for manual and determinism mode */
2128 min_clk = dpm_context->dpm_tables.gfx_table.min;
2129 max_clk = dpm_context->dpm_tables.gfx_table.max;
2130
2131 ret = smu_v13_0_6_set_soft_freq_limited_range(
2132 smu, SMU_GFXCLK, min_clk, max_clk, false);
2133
2134 if (ret)
2135 return ret;
2136
2137 min_clk = dpm_context->dpm_tables.uclk_table.min;
2138 max_clk = dpm_context->dpm_tables.uclk_table.max;
2139 ret = smu_v13_0_6_set_soft_freq_limited_range(
2140 smu, SMU_UCLK, min_clk, max_clk, false);
2141 if (ret)
2142 return ret;
2143 pstate_table->uclk_pstate.custom.max = 0;
2144 }
2145 break;
2146 case PP_OD_COMMIT_DPM_TABLE:
2147 if (size != 0) {
2148 dev_err(smu->adev->dev,
2149 "Input parameter number not correct\n");
2150 return -EINVAL;
2151 } else {
2152 if (!pstate_table->gfxclk_pstate.custom.min)
2153 pstate_table->gfxclk_pstate.custom.min =
2154 pstate_table->gfxclk_pstate.curr.min;
2155
2156 if (!pstate_table->gfxclk_pstate.custom.max)
2157 pstate_table->gfxclk_pstate.custom.max =
2158 pstate_table->gfxclk_pstate.curr.max;
2159
2160 min_clk = pstate_table->gfxclk_pstate.custom.min;
2161 max_clk = pstate_table->gfxclk_pstate.custom.max;
2162
2163 ret = smu_v13_0_6_set_soft_freq_limited_range(
2164 smu, SMU_GFXCLK, min_clk, max_clk, false);
2165
2166 if (ret)
2167 return ret;
2168
2169 if (!pstate_table->uclk_pstate.custom.max)
2170 return 0;
2171
2172 min_clk = pstate_table->uclk_pstate.curr.min;
2173 max_clk = pstate_table->uclk_pstate.custom.max;
2174 return smu_v13_0_6_set_soft_freq_limited_range(
2175 smu, SMU_UCLK, min_clk, max_clk, false);
2176 }
2177 break;
2178 default:
2179 return -ENOSYS;
2180 }
2181
2182 return ret;
2183 }
2184
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)2185 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2186 uint64_t *feature_mask)
2187 {
2188 int ret;
2189
2190 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2191
2192 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
2193 *feature_mask = 0;
2194 ret = 0;
2195 }
2196
2197 return ret;
2198 }
2199
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2200 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2201 {
2202 int ret;
2203 uint64_t feature_enabled;
2204
2205 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
2206 return smu_v13_0_12_is_dpm_running(smu);
2207
2208 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2209
2210 if (ret)
2211 return false;
2212
2213 return !!(feature_enabled & SMC_DPM_FEATURE);
2214 }
2215
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2216 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2217 void *table_data)
2218 {
2219 struct smu_table_context *smu_table = &smu->smu_table;
2220 struct smu_table *table = &smu_table->driver_table;
2221 struct amdgpu_device *adev = smu->adev;
2222 uint32_t table_size;
2223 int ret = 0;
2224
2225 if (!table_data)
2226 return -EINVAL;
2227
2228 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2229
2230 memcpy(table->cpu_addr, table_data, table_size);
2231 /* Flush hdp cache */
2232 amdgpu_asic_flush_hdp(adev, NULL);
2233 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2234 NULL);
2235
2236 return ret;
2237 }
2238
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2239 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2240 struct i2c_msg *msg, int num_msgs)
2241 {
2242 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2243 struct amdgpu_device *adev = smu_i2c->adev;
2244 struct smu_context *smu = adev->powerplay.pp_handle;
2245 struct smu_table_context *smu_table = &smu->smu_table;
2246 struct smu_table *table = &smu_table->driver_table;
2247 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2248 int i, j, r, c;
2249 u16 dir;
2250
2251 if (!adev->pm.dpm_enabled)
2252 return -EBUSY;
2253
2254 req = kzalloc(sizeof(*req), GFP_KERNEL);
2255 if (!req)
2256 return -ENOMEM;
2257
2258 req->I2CcontrollerPort = smu_i2c->port;
2259 req->I2CSpeed = I2C_SPEED_FAST_400K;
2260 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2261 dir = msg[0].flags & I2C_M_RD;
2262
2263 for (c = i = 0; i < num_msgs; i++) {
2264 for (j = 0; j < msg[i].len; j++, c++) {
2265 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2266
2267 if (!(msg[i].flags & I2C_M_RD)) {
2268 /* write */
2269 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2270 cmd->ReadWriteData = msg[i].buf[j];
2271 }
2272
2273 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2274 /* The direction changes.
2275 */
2276 dir = msg[i].flags & I2C_M_RD;
2277 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2278 }
2279
2280 req->NumCmds++;
2281
2282 /*
2283 * Insert STOP if we are at the last byte of either last
2284 * message for the transaction or the client explicitly
2285 * requires a STOP at this particular message.
2286 */
2287 if ((j == msg[i].len - 1) &&
2288 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2289 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2290 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2291 }
2292 }
2293 }
2294 mutex_lock(&adev->pm.mutex);
2295 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2296 if (r) {
2297 /* Retry once, in case of an i2c collision */
2298 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2299 if (r)
2300 goto fail;
2301 }
2302
2303 for (c = i = 0; i < num_msgs; i++) {
2304 if (!(msg[i].flags & I2C_M_RD)) {
2305 c += msg[i].len;
2306 continue;
2307 }
2308 for (j = 0; j < msg[i].len; j++, c++) {
2309 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2310
2311 msg[i].buf[j] = cmd->ReadWriteData;
2312 }
2313 }
2314 r = num_msgs;
2315 fail:
2316 mutex_unlock(&adev->pm.mutex);
2317 kfree(req);
2318 return r;
2319 }
2320
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2321 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2322 {
2323 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2324 }
2325
2326 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2327 .master_xfer = smu_v13_0_6_i2c_xfer,
2328 .functionality = smu_v13_0_6_i2c_func,
2329 };
2330
2331 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2332 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2333 .max_read_len = MAX_SW_I2C_COMMANDS,
2334 .max_write_len = MAX_SW_I2C_COMMANDS,
2335 .max_comb_1st_msg_len = 2,
2336 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2337 };
2338
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2339 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2340 {
2341 struct amdgpu_device *adev = smu->adev;
2342 int res, i;
2343
2344 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2345 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2346 struct i2c_adapter *control = &smu_i2c->adapter;
2347
2348 smu_i2c->adev = adev;
2349 smu_i2c->port = i;
2350 mutex_init(&smu_i2c->mutex);
2351 control->owner = THIS_MODULE;
2352 control->dev.parent = &adev->pdev->dev;
2353 control->algo = &smu_v13_0_6_i2c_algo;
2354 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2355 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2356 i2c_set_adapdata(control, smu_i2c);
2357
2358 res = i2c_add_adapter(control);
2359 if (res) {
2360 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2361 goto Out_err;
2362 }
2363 }
2364
2365 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2366 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2367
2368 return 0;
2369 Out_err:
2370 for ( ; i >= 0; i--) {
2371 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2372 struct i2c_adapter *control = &smu_i2c->adapter;
2373
2374 i2c_del_adapter(control);
2375 }
2376 return res;
2377 }
2378
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2379 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2380 {
2381 struct amdgpu_device *adev = smu->adev;
2382 int i;
2383
2384 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2385 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2386 struct i2c_adapter *control = &smu_i2c->adapter;
2387
2388 i2c_del_adapter(control);
2389 }
2390 adev->pm.ras_eeprom_i2c_bus = NULL;
2391 adev->pm.fru_eeprom_i2c_bus = NULL;
2392 }
2393
smu_v13_0_6_get_unique_id(struct smu_context * smu)2394 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2395 {
2396 struct amdgpu_device *adev = smu->adev;
2397 struct smu_table_context *smu_table = &smu->smu_table;
2398 struct PPTable_t *pptable =
2399 (struct PPTable_t *)smu_table->driver_pptable;
2400
2401 adev->unique_id = pptable->PublicSerialNumber_AID;
2402 }
2403
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2404 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2405 {
2406 /* smu_13_0_6 does not support baco */
2407
2408 return 0;
2409 }
2410
2411 static const char *const throttling_logging_label[] = {
2412 [THROTTLER_PROCHOT_BIT] = "Prochot",
2413 [THROTTLER_PPT_BIT] = "PPT",
2414 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2415 [THROTTLER_THERMAL_VR_BIT] = "VR",
2416 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2417 };
2418
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2419 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2420 {
2421 int throttler_idx, throttling_events = 0, buf_idx = 0;
2422 struct amdgpu_device *adev = smu->adev;
2423 uint32_t throttler_status;
2424 char log_buf[256];
2425
2426 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2427 if (!throttler_status)
2428 return;
2429
2430 memset(log_buf, 0, sizeof(log_buf));
2431 for (throttler_idx = 0;
2432 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2433 throttler_idx++) {
2434 if (throttler_status & (1U << throttler_idx)) {
2435 throttling_events++;
2436 buf_idx += snprintf(
2437 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2438 "%s%s", throttling_events > 1 ? " and " : "",
2439 throttling_logging_label[throttler_idx]);
2440 if (buf_idx >= sizeof(log_buf)) {
2441 dev_err(adev->dev, "buffer overflow!\n");
2442 log_buf[sizeof(log_buf) - 1] = '\0';
2443 break;
2444 }
2445 }
2446 }
2447
2448 dev_warn(adev->dev,
2449 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2450 log_buf);
2451 kgd2kfd_smi_event_throttle(
2452 smu->adev->kfd.dev,
2453 smu_cmn_get_indep_throttler_status(throttler_status,
2454 smu_v13_0_6_throttler_map));
2455 }
2456
2457 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2458 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2459 {
2460 struct amdgpu_device *adev = smu->adev;
2461
2462 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2463 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2464 }
2465
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2466 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2467 {
2468 struct amdgpu_device *adev = smu->adev;
2469 uint32_t speed_level;
2470 uint32_t esm_ctrl;
2471
2472 /* TODO: confirm this on real target */
2473 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2474 if ((esm_ctrl >> 15) & 0x1)
2475 return (((esm_ctrl >> 8) & 0x7F) + 128);
2476
2477 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2478 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2479 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2480 if (speed_level > LINK_SPEED_MAX)
2481 speed_level = 0;
2482
2483 return pcie_gen_to_speed(speed_level + 1);
2484 }
2485
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2486 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2487 {
2488 struct smu_table_context *smu_table = &smu->smu_table;
2489 struct gpu_metrics_v1_7 *gpu_metrics =
2490 (struct gpu_metrics_v1_7 *)smu_table->gpu_metrics_table;
2491 int version = smu_v13_0_6_get_metrics_version(smu);
2492 int ret = 0, xcc_id, inst, i, j, k, idx;
2493 struct amdgpu_device *adev = smu->adev;
2494 MetricsTableV0_t *metrics_v0;
2495 MetricsTableV1_t *metrics_v1;
2496 MetricsTableV2_t *metrics_v2;
2497 struct amdgpu_xcp *xcp;
2498 u16 link_width_level;
2499 u8 num_jpeg_rings;
2500 u32 inst_mask;
2501 bool per_inst;
2502
2503 metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
2504 ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, true);
2505 if (ret) {
2506 kfree(metrics_v0);
2507 return ret;
2508 }
2509
2510 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
2511 return smu_v13_0_12_get_gpu_metrics(smu, table);
2512
2513 metrics_v1 = (MetricsTableV1_t *)metrics_v0;
2514 metrics_v2 = (MetricsTableV2_t *)metrics_v0;
2515
2516 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 7);
2517
2518 gpu_metrics->temperature_hotspot =
2519 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
2520 /* Individual HBM stack temperature is not reported */
2521 gpu_metrics->temperature_mem =
2522 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
2523 /* Reports max temperature of all voltage rails */
2524 gpu_metrics->temperature_vrsoc =
2525 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
2526
2527 gpu_metrics->average_gfx_activity =
2528 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
2529 gpu_metrics->average_umc_activity =
2530 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
2531
2532 gpu_metrics->mem_max_bandwidth =
2533 SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
2534
2535 gpu_metrics->curr_socket_power =
2536 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
2537 /* Energy counter reported in 15.259uJ (2^-16) units */
2538 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
2539
2540 for (i = 0; i < MAX_GFX_CLKS; i++) {
2541 xcc_id = GET_INST(GC, i);
2542 if (xcc_id >= 0)
2543 gpu_metrics->current_gfxclk[i] =
2544 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
2545
2546 if (i < MAX_CLKS) {
2547 gpu_metrics->current_socclk[i] =
2548 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
2549 inst = GET_INST(VCN, i);
2550 if (inst >= 0) {
2551 gpu_metrics->current_vclk0[i] =
2552 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
2553 version)[inst]);
2554 gpu_metrics->current_dclk0[i] =
2555 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
2556 version)[inst]);
2557 }
2558 }
2559 }
2560
2561 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2562
2563 /* Total accumulated cycle counter */
2564 gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
2565
2566 /* Accumulated throttler residencies */
2567 gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
2568 gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
2569 gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
2570 gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
2571 gpu_metrics->hbm_thm_residency_acc =
2572 GET_METRIC_FIELD(HbmThmResidencyAcc, version);
2573
2574 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2575 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
2576 version) >> GET_INST(GC, 0);
2577
2578 if (!(adev->flags & AMD_IS_APU)) {
2579 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2580 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2581 * for pf from registers
2582 */
2583 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
2584 gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
2585 gpu_metrics->pcie_link_speed =
2586 pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
2587 } else if (!amdgpu_sriov_vf(adev)) {
2588 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2589 if (link_width_level > MAX_LINK_WIDTH)
2590 link_width_level = 0;
2591
2592 gpu_metrics->pcie_link_width =
2593 DECODE_LANE_WIDTH(link_width_level);
2594 gpu_metrics->pcie_link_speed =
2595 smu_v13_0_6_get_current_pcie_link_speed(smu);
2596 }
2597
2598 gpu_metrics->pcie_bandwidth_acc =
2599 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
2600 gpu_metrics->pcie_bandwidth_inst =
2601 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
2602 gpu_metrics->pcie_l0_to_recov_count_acc =
2603 GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
2604 gpu_metrics->pcie_replay_count_acc =
2605 GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
2606 gpu_metrics->pcie_replay_rover_count_acc =
2607 GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
2608 gpu_metrics->pcie_nak_sent_count_acc =
2609 GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
2610 gpu_metrics->pcie_nak_rcvd_count_acc =
2611 GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
2612 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
2613 gpu_metrics->pcie_lc_perf_other_end_recovery =
2614 GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
2615
2616 }
2617
2618 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2619
2620 gpu_metrics->gfx_activity_acc =
2621 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
2622 gpu_metrics->mem_activity_acc =
2623 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
2624
2625 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2626 gpu_metrics->xgmi_read_data_acc[i] =
2627 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
2628 gpu_metrics->xgmi_write_data_acc[i] =
2629 SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
2630 ret = amdgpu_get_xgmi_link_status(adev, i);
2631 if (ret >= 0)
2632 gpu_metrics->xgmi_link_status[i] = ret;
2633 }
2634
2635 gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
2636
2637 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2638
2639 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2640 for_each_xcp(adev->xcp_mgr, xcp, i) {
2641 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2642 idx = 0;
2643 for_each_inst(k, inst_mask) {
2644 /* Both JPEG and VCN has same instances */
2645 inst = GET_INST(VCN, k);
2646
2647 for (j = 0; j < num_jpeg_rings; ++j) {
2648 gpu_metrics->xcp_stats[i].jpeg_busy
2649 [(idx * num_jpeg_rings) + j] =
2650 SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
2651 [(inst * num_jpeg_rings) + j]);
2652 }
2653 gpu_metrics->xcp_stats[i].vcn_busy[idx] =
2654 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2655 idx++;
2656
2657 }
2658
2659 if (per_inst) {
2660 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2661 idx = 0;
2662 for_each_inst(k, inst_mask) {
2663 inst = GET_INST(GC, k);
2664 gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
2665 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2666 gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
2667 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
2668 version)[inst]);
2669 idx++;
2670 }
2671 }
2672 }
2673
2674 gpu_metrics->xgmi_link_width = GET_METRIC_FIELD(XgmiWidth, version);
2675 gpu_metrics->xgmi_link_speed = GET_METRIC_FIELD(XgmiBitrate, version);
2676
2677 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
2678
2679 *table = (void *)gpu_metrics;
2680 kfree(metrics_v0);
2681
2682 return sizeof(*gpu_metrics);
2683 }
2684
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2685 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2686 {
2687 struct amdgpu_device *adev = smu->adev;
2688 int i;
2689
2690 for (i = 0; i < 16; i++)
2691 pci_write_config_dword(adev->pdev, i * 4,
2692 adev->pdev->saved_config_space[i]);
2693 pci_restore_msi_state(adev->pdev);
2694 }
2695
smu_v13_0_6_mode2_reset(struct smu_context * smu)2696 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2697 {
2698 int ret = 0, index;
2699 struct amdgpu_device *adev = smu->adev;
2700 int timeout = 10;
2701
2702 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2703 SMU_MSG_GfxDeviceDriverReset);
2704 if (index < 0)
2705 return index;
2706
2707 mutex_lock(&smu->message_lock);
2708
2709 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
2710 SMU_RESET_MODE_2);
2711
2712 /* Reset takes a bit longer, wait for 200ms. */
2713 msleep(200);
2714
2715 dev_dbg(smu->adev->dev, "restore config space...\n");
2716 /* Restore the config space saved during init */
2717 amdgpu_device_load_pci_state(adev->pdev);
2718
2719 /* Certain platforms have switches which assign virtual BAR values to
2720 * devices. OS uses the virtual BAR values and device behind the switch
2721 * is assgined another BAR value. When device's config space registers
2722 * are queried, switch returns the virtual BAR values. When mode-2 reset
2723 * is performed, switch is unaware of it, and will continue to return
2724 * the same virtual values to the OS.This affects
2725 * pci_restore_config_space() API as it doesn't write the value saved if
2726 * the current value read from config space is the same as what is
2727 * saved. As a workaround, make sure the config space is restored
2728 * always.
2729 */
2730 if (!(adev->flags & AMD_IS_APU))
2731 smu_v13_0_6_restore_pci_config(smu);
2732
2733 dev_dbg(smu->adev->dev, "wait for reset ack\n");
2734 do {
2735 ret = smu_cmn_wait_for_response(smu);
2736 /* Wait a bit more time for getting ACK */
2737 if (ret == -ETIME) {
2738 --timeout;
2739 usleep_range(500, 1000);
2740 continue;
2741 }
2742
2743 if (ret)
2744 goto out;
2745
2746 } while (ret == -ETIME && timeout);
2747
2748 out:
2749 mutex_unlock(&smu->message_lock);
2750
2751 if (ret)
2752 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
2753 ret);
2754
2755 return ret;
2756 }
2757
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2758 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
2759 struct smu_temperature_range *range)
2760 {
2761 struct amdgpu_device *adev = smu->adev;
2762 u32 aid_temp, xcd_temp, max_temp;
2763 u32 ccd_temp = 0;
2764 int ret;
2765
2766 if (amdgpu_sriov_vf(smu->adev))
2767 return 0;
2768
2769 if (!range)
2770 return -EINVAL;
2771
2772 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
2773 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
2774 return 0;
2775
2776 /* Get SOC Max operating temperature */
2777 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2778 PPSMC_AID_THM_TYPE, &aid_temp);
2779 if (ret)
2780 goto failed;
2781 if (adev->flags & AMD_IS_APU) {
2782 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2783 PPSMC_CCD_THM_TYPE, &ccd_temp);
2784 if (ret)
2785 goto failed;
2786 }
2787 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2788 PPSMC_XCD_THM_TYPE, &xcd_temp);
2789 if (ret)
2790 goto failed;
2791 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
2792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2793
2794 /* Get HBM Max operating temperature */
2795 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
2796 PPSMC_HBM_THM_TYPE, &max_temp);
2797 if (ret)
2798 goto failed;
2799 range->mem_emergency_max =
2800 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2801
2802 /* Get SOC thermal throttle limit */
2803 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2804 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
2805 &max_temp);
2806 if (ret)
2807 goto failed;
2808 range->hotspot_crit_max =
2809 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2810
2811 /* Get HBM thermal throttle limit */
2812 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
2813 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
2814 &max_temp);
2815 if (ret)
2816 goto failed;
2817
2818 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2819
2820 failed:
2821 return ret;
2822 }
2823
smu_v13_0_6_mode1_reset(struct smu_context * smu)2824 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
2825 {
2826 struct amdgpu_device *adev = smu->adev;
2827 u32 fatal_err, param;
2828 int ret = 0;
2829
2830 fatal_err = 0;
2831 param = SMU_RESET_MODE_1;
2832
2833 /* fatal error triggered by ras, PMFW supports the flag */
2834 if (amdgpu_ras_get_fed_status(adev))
2835 fatal_err = 1;
2836
2837 param |= (fatal_err << 16);
2838 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
2839 param, NULL);
2840
2841 if (!ret)
2842 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2843
2844 return ret;
2845 }
2846
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)2847 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
2848 {
2849 return true;
2850 }
2851
smu_v13_0_6_is_mode2_reset_supported(struct smu_context * smu)2852 static bool smu_v13_0_6_is_mode2_reset_supported(struct smu_context *smu)
2853 {
2854 return true;
2855 }
2856
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)2857 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
2858 uint32_t size)
2859 {
2860 int ret = 0;
2861
2862 /* message SMU to update the bad page number on SMUBUS */
2863 ret = smu_cmn_send_smc_msg_with_param(
2864 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
2865 if (ret)
2866 dev_err(smu->adev->dev,
2867 "[%s] failed to message SMU to update HBM bad pages number\n",
2868 __func__);
2869
2870 return ret;
2871 }
2872
smu_v13_0_6_send_rma_reason(struct smu_context * smu)2873 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
2874 {
2875 int ret;
2876
2877 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
2878 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
2879 return 0;
2880
2881 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
2882 if (ret)
2883 dev_err(smu->adev->dev,
2884 "[%s] failed to send BadPageThreshold event to SMU\n",
2885 __func__);
2886
2887 return ret;
2888 }
2889
2890 /**
2891 * smu_v13_0_6_reset_sdma_is_supported - Check if SDMA reset is supported
2892 * @smu: smu_context pointer
2893 *
2894 * This function checks if the SMU supports resetting the SDMA engine.
2895 * It returns false if the capability is not supported.
2896 */
smu_v13_0_6_reset_sdma_is_supported(struct smu_context * smu)2897 static bool smu_v13_0_6_reset_sdma_is_supported(struct smu_context *smu)
2898 {
2899 bool ret = true;
2900
2901 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET))) {
2902 dev_info(smu->adev->dev,
2903 "SDMA reset capability is not supported\n");
2904 ret = false;
2905 }
2906
2907 return ret;
2908 }
2909
smu_v13_0_6_reset_sdma(struct smu_context * smu,uint32_t inst_mask)2910 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
2911 {
2912 int ret = 0;
2913
2914 if (!smu_v13_0_6_reset_sdma_is_supported(smu))
2915 return -EOPNOTSUPP;
2916
2917 ret = smu_cmn_send_smc_msg_with_param(smu,
2918 SMU_MSG_ResetSDMA, inst_mask, NULL);
2919 if (ret)
2920 dev_err(smu->adev->dev,
2921 "failed to send ResetSDMA event with mask 0x%x\n",
2922 inst_mask);
2923
2924 return ret;
2925 }
2926
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)2927 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
2928 {
2929 struct smu_context *smu = adev->powerplay.pp_handle;
2930
2931 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
2932 }
2933
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)2934 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
2935 {
2936 uint32_t msg;
2937 int ret;
2938
2939 if (!count)
2940 return -EINVAL;
2941
2942 switch (type) {
2943 case AMDGPU_MCA_ERROR_TYPE_UE:
2944 msg = SMU_MSG_QueryValidMcaCount;
2945 break;
2946 case AMDGPU_MCA_ERROR_TYPE_CE:
2947 msg = SMU_MSG_QueryValidMcaCeCount;
2948 break;
2949 default:
2950 return -EINVAL;
2951 }
2952
2953 ret = smu_cmn_send_smc_msg(smu, msg, count);
2954 if (ret) {
2955 *count = 0;
2956 return ret;
2957 }
2958
2959 return 0;
2960 }
2961
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)2962 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2963 int idx, int offset, uint32_t *val)
2964 {
2965 uint32_t msg, param;
2966
2967 switch (type) {
2968 case AMDGPU_MCA_ERROR_TYPE_UE:
2969 msg = SMU_MSG_McaBankDumpDW;
2970 break;
2971 case AMDGPU_MCA_ERROR_TYPE_CE:
2972 msg = SMU_MSG_McaBankCeDumpDW;
2973 break;
2974 default:
2975 return -EINVAL;
2976 }
2977
2978 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
2979
2980 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
2981 }
2982
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)2983 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
2984 int idx, int offset, uint32_t *val, int count)
2985 {
2986 int ret, i;
2987
2988 if (!val)
2989 return -EINVAL;
2990
2991 for (i = 0; i < count; i++) {
2992 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
2993 if (ret)
2994 return ret;
2995 }
2996
2997 return 0;
2998 }
2999
3000 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
3001 MCA_BANK_IPID(UMC, 0x96, 0x0),
3002 MCA_BANK_IPID(SMU, 0x01, 0x1),
3003 MCA_BANK_IPID(MP5, 0x01, 0x2),
3004 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
3005 };
3006
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)3007 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
3008 {
3009 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
3010 u32 instidhi, instid;
3011
3012 /* NOTE: All MCA IPID register share the same format,
3013 * so the driver can share the MCMP1 register header file.
3014 * */
3015
3016 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
3017 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
3018
3019 /*
3020 * Unfied DieID Format: SAASS. A:AID, S:Socket.
3021 * Unfied DieID[4] = InstanceId[0]
3022 * Unfied DieID[0:3] = InstanceIdHi[0:3]
3023 */
3024 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
3025 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
3026 info->aid = ((instidhi >> 2) & 0x03);
3027 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
3028 }
3029
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)3030 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3031 int idx, int reg_idx, uint64_t *val)
3032 {
3033 struct smu_context *smu = adev->powerplay.pp_handle;
3034 uint32_t data[2] = {0, 0};
3035 int ret;
3036
3037 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
3038 return -EINVAL;
3039
3040 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3041 if (ret)
3042 return ret;
3043
3044 *val = (uint64_t)data[1] << 32 | data[0];
3045
3046 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3047 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3048
3049 return 0;
3050 }
3051
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3052 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3053 int idx, struct mca_bank_entry *entry)
3054 {
3055 int i, ret;
3056
3057 /* NOTE: populated all mca register by default */
3058 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
3059 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
3060 if (ret)
3061 return ret;
3062 }
3063
3064 entry->idx = idx;
3065 entry->type = type;
3066
3067 mca_bank_entry_info_decode(entry, &entry->info);
3068
3069 return 0;
3070 }
3071
mca_decode_ipid_to_hwip(uint64_t val)3072 static int mca_decode_ipid_to_hwip(uint64_t val)
3073 {
3074 const struct mca_bank_ipid *ipid;
3075 uint16_t hwid, mcatype;
3076 int i;
3077
3078 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
3079 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3080
3081 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
3082 ipid = &smu_v13_0_6_mca_ipid_table[i];
3083
3084 if (!ipid->hwid)
3085 continue;
3086
3087 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
3088 return i;
3089 }
3090
3091 return AMDGPU_MCA_IP_UNKNOW;
3092 }
3093
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3094 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3095 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3096 {
3097 uint64_t status0;
3098 uint32_t ext_error_code;
3099 uint32_t odecc_err_cnt;
3100
3101 status0 = entry->regs[MCA_REG_IDX_STATUS];
3102 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
3103 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3104
3105 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3106 *count = 0;
3107 return 0;
3108 }
3109
3110 if (umc_v12_0_is_deferred_error(adev, status0) ||
3111 umc_v12_0_is_uncorrectable_error(adev, status0) ||
3112 umc_v12_0_is_correctable_error(adev, status0))
3113 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
3114
3115 amdgpu_umc_update_ecc_status(adev,
3116 entry->regs[MCA_REG_IDX_STATUS],
3117 entry->regs[MCA_REG_IDX_IPID],
3118 entry->regs[MCA_REG_IDX_ADDR]);
3119
3120 return 0;
3121 }
3122
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3123 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3124 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
3125 uint32_t *count)
3126 {
3127 u32 ext_error_code;
3128 u32 err_cnt;
3129
3130 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
3131 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3132
3133 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3134 (ext_error_code == 0 || ext_error_code == 9))
3135 *count = err_cnt;
3136 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
3137 *count = err_cnt;
3138
3139 return 0;
3140 }
3141
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)3142 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3143 uint32_t errcode)
3144 {
3145 int i;
3146
3147 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
3148 return true;
3149
3150 for (i = 0; i < mca_ras->err_code_count; i++) {
3151 if (errcode == mca_ras->err_code_array[i])
3152 return true;
3153 }
3154
3155 return false;
3156 }
3157
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3158 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3159 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3160 {
3161 uint64_t status0, misc0;
3162
3163 status0 = entry->regs[MCA_REG_IDX_STATUS];
3164 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3165 *count = 0;
3166 return 0;
3167 }
3168
3169 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3170 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3171 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3172 *count = 1;
3173 return 0;
3174 } else {
3175 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3176 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3177 }
3178
3179 return 0;
3180 }
3181
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3182 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3183 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3184 {
3185 uint64_t status0, misc0;
3186
3187 status0 = entry->regs[MCA_REG_IDX_STATUS];
3188 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3189 *count = 0;
3190 return 0;
3191 }
3192
3193 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3194 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3195 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3196 if (count)
3197 *count = 1;
3198 return 0;
3199 }
3200
3201 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3202 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3203
3204 return 0;
3205 }
3206
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3207 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3208 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3209 {
3210 uint32_t instlo;
3211
3212 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3213 instlo &= GENMASK(31, 1);
3214 switch (instlo) {
3215 case 0x36430400: /* SMNAID XCD 0 */
3216 case 0x38430400: /* SMNAID XCD 1 */
3217 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
3218 return true;
3219 default:
3220 return false;
3221 }
3222
3223 return false;
3224 };
3225
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3226 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3227 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3228 {
3229 struct smu_context *smu = adev->powerplay.pp_handle;
3230 uint32_t errcode, instlo;
3231
3232 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3233 instlo &= GENMASK(31, 1);
3234 if (instlo != 0x03b30400)
3235 return false;
3236
3237 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
3238 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
3239 errcode &= 0xff;
3240 } else {
3241 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
3242 }
3243
3244 return mca_smu_check_error_code(adev, mca_ras, errcode);
3245 }
3246
3247 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
3248 static int mmhub_err_codes[] = {
3249 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
3250 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
3251 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
3252 };
3253
3254 static int vcn_err_codes[] = {
3255 CODE_VIDD, CODE_VIDV,
3256 };
3257 static int jpeg_err_codes[] = {
3258 CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
3259 CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
3260 CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
3261 CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
3262 };
3263
3264 static const struct mca_ras_info mca_ras_table[] = {
3265 {
3266 .blkid = AMDGPU_RAS_BLOCK__UMC,
3267 .ip = AMDGPU_MCA_IP_UMC,
3268 .get_err_count = mca_umc_mca_get_err_count,
3269 }, {
3270 .blkid = AMDGPU_RAS_BLOCK__GFX,
3271 .ip = AMDGPU_MCA_IP_SMU,
3272 .get_err_count = mca_gfx_mca_get_err_count,
3273 .bank_is_valid = mca_gfx_smu_bank_is_valid,
3274 }, {
3275 .blkid = AMDGPU_RAS_BLOCK__SDMA,
3276 .ip = AMDGPU_MCA_IP_SMU,
3277 .err_code_array = sdma_err_codes,
3278 .err_code_count = ARRAY_SIZE(sdma_err_codes),
3279 .get_err_count = mca_smu_mca_get_err_count,
3280 .bank_is_valid = mca_smu_bank_is_valid,
3281 }, {
3282 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
3283 .ip = AMDGPU_MCA_IP_SMU,
3284 .err_code_array = mmhub_err_codes,
3285 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3286 .get_err_count = mca_smu_mca_get_err_count,
3287 .bank_is_valid = mca_smu_bank_is_valid,
3288 }, {
3289 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3290 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3291 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3292 }, {
3293 .blkid = AMDGPU_RAS_BLOCK__VCN,
3294 .ip = AMDGPU_MCA_IP_SMU,
3295 .err_code_array = vcn_err_codes,
3296 .err_code_count = ARRAY_SIZE(vcn_err_codes),
3297 .get_err_count = mca_smu_mca_get_err_count,
3298 .bank_is_valid = mca_smu_bank_is_valid,
3299 }, {
3300 .blkid = AMDGPU_RAS_BLOCK__JPEG,
3301 .ip = AMDGPU_MCA_IP_SMU,
3302 .err_code_array = jpeg_err_codes,
3303 .err_code_count = ARRAY_SIZE(jpeg_err_codes),
3304 .get_err_count = mca_smu_mca_get_err_count,
3305 .bank_is_valid = mca_smu_bank_is_valid,
3306 },
3307 };
3308
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3309 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3310 {
3311 int i;
3312
3313 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3314 if (mca_ras_table[i].blkid == blkid)
3315 return &mca_ras_table[i];
3316 }
3317
3318 return NULL;
3319 }
3320
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3321 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3322 {
3323 struct smu_context *smu = adev->powerplay.pp_handle;
3324 int ret;
3325
3326 switch (type) {
3327 case AMDGPU_MCA_ERROR_TYPE_UE:
3328 case AMDGPU_MCA_ERROR_TYPE_CE:
3329 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3330 break;
3331 default:
3332 ret = -EINVAL;
3333 break;
3334 }
3335
3336 return ret;
3337 }
3338
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3339 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3340 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3341 {
3342 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3343 return false;
3344
3345 if (mca_ras->bank_is_valid)
3346 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3347
3348 return true;
3349 }
3350
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3351 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3352 struct mca_bank_entry *entry, uint32_t *count)
3353 {
3354 const struct mca_ras_info *mca_ras;
3355
3356 if (!entry || !count)
3357 return -EINVAL;
3358
3359 mca_ras = mca_get_mca_ras_info(adev, blk);
3360 if (!mca_ras)
3361 return -EOPNOTSUPP;
3362
3363 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3364 *count = 0;
3365 return 0;
3366 }
3367
3368 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3369 }
3370
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3371 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3372 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3373 {
3374 return mca_get_mca_entry(adev, type, idx, entry);
3375 }
3376
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3377 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3378 enum amdgpu_mca_error_type type, uint32_t *count)
3379 {
3380 return mca_get_valid_mca_count(adev, type, count);
3381 }
3382
3383 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3384 .max_ue_count = 12,
3385 .max_ce_count = 12,
3386 .mca_set_debug_mode = mca_smu_set_debug_mode,
3387 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3388 .mca_get_mca_entry = mca_smu_get_mca_entry,
3389 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3390 };
3391
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3392 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3393 {
3394 struct smu_context *smu = adev->powerplay.pp_handle;
3395
3396 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3397 }
3398
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3399 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3400 {
3401 uint32_t msg;
3402 int ret;
3403
3404 if (!count)
3405 return -EINVAL;
3406
3407 switch (type) {
3408 case ACA_SMU_TYPE_UE:
3409 msg = SMU_MSG_QueryValidMcaCount;
3410 break;
3411 case ACA_SMU_TYPE_CE:
3412 msg = SMU_MSG_QueryValidMcaCeCount;
3413 break;
3414 default:
3415 return -EINVAL;
3416 }
3417
3418 ret = smu_cmn_send_smc_msg(smu, msg, count);
3419 if (ret) {
3420 *count = 0;
3421 return ret;
3422 }
3423
3424 return 0;
3425 }
3426
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3427 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3428 enum aca_smu_type type, u32 *count)
3429 {
3430 struct smu_context *smu = adev->powerplay.pp_handle;
3431 int ret;
3432
3433 switch (type) {
3434 case ACA_SMU_TYPE_UE:
3435 case ACA_SMU_TYPE_CE:
3436 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3437 break;
3438 default:
3439 ret = -EINVAL;
3440 break;
3441 }
3442
3443 return ret;
3444 }
3445
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3446 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3447 int idx, int offset, u32 *val)
3448 {
3449 uint32_t msg, param;
3450
3451 switch (type) {
3452 case ACA_SMU_TYPE_UE:
3453 msg = SMU_MSG_McaBankDumpDW;
3454 break;
3455 case ACA_SMU_TYPE_CE:
3456 msg = SMU_MSG_McaBankCeDumpDW;
3457 break;
3458 default:
3459 return -EINVAL;
3460 }
3461
3462 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3463
3464 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3465 }
3466
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3467 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3468 int idx, int offset, u32 *val, int count)
3469 {
3470 int ret, i;
3471
3472 if (!val)
3473 return -EINVAL;
3474
3475 for (i = 0; i < count; i++) {
3476 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3477 if (ret)
3478 return ret;
3479 }
3480
3481 return 0;
3482 }
3483
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3484 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3485 int idx, int reg_idx, u64 *val)
3486 {
3487 struct smu_context *smu = adev->powerplay.pp_handle;
3488 u32 data[2] = {0, 0};
3489 int ret;
3490
3491 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3492 return -EINVAL;
3493
3494 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3495 if (ret)
3496 return ret;
3497
3498 *val = (u64)data[1] << 32 | data[0];
3499
3500 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3501 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3502
3503 return 0;
3504 }
3505
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3506 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3507 enum aca_smu_type type, int idx, struct aca_bank *bank)
3508 {
3509 int i, ret, count;
3510
3511 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3512 for (i = 0; i < count; i++) {
3513 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3514 if (ret)
3515 return ret;
3516 }
3517
3518 return 0;
3519 }
3520
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3521 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3522 {
3523 struct smu_context *smu = adev->powerplay.pp_handle;
3524 int error_code;
3525
3526 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
3527 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3528 else
3529 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3530
3531 return error_code & 0xff;
3532 }
3533
3534 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3535 .max_ue_bank_count = 12,
3536 .max_ce_bank_count = 12,
3537 .set_debug_mode = aca_smu_set_debug_mode,
3538 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3539 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3540 .parse_error_code = aca_smu_parse_error_code,
3541 };
3542
3543 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3544 /* init dpm */
3545 .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask,
3546 /* dpm/clk tables */
3547 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3548 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3549 .print_clk_levels = smu_v13_0_6_print_clk_levels,
3550 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3551 .read_sensor = smu_v13_0_6_read_sensor,
3552 .set_performance_level = smu_v13_0_6_set_performance_level,
3553 .get_power_limit = smu_v13_0_6_get_power_limit,
3554 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3555 .get_unique_id = smu_v13_0_6_get_unique_id,
3556 .init_microcode = smu_v13_0_6_init_microcode,
3557 .fini_microcode = smu_v13_0_fini_microcode,
3558 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3559 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3560 .init_power = smu_v13_0_init_power,
3561 .fini_power = smu_v13_0_fini_power,
3562 .check_fw_status = smu_v13_0_6_check_fw_status,
3563 /* pptable related */
3564 .check_fw_version = smu_v13_0_6_check_fw_version,
3565 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3566 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3567 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3568 .system_features_control = smu_v13_0_6_system_features_control,
3569 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3570 .send_smc_msg = smu_cmn_send_smc_msg,
3571 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3572 .feature_is_enabled = smu_cmn_feature_is_enabled,
3573 .set_power_limit = smu_v13_0_6_set_power_limit,
3574 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3575 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3576 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3577 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3578 .setup_pptable = smu_v13_0_6_setup_pptable,
3579 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3580 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3581 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3582 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3583 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3584 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3585 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3586 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3587 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3588 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3589 .mode2_reset_is_support = smu_v13_0_6_is_mode2_reset_supported,
3590 .mode1_reset = smu_v13_0_6_mode1_reset,
3591 .mode2_reset = smu_v13_0_6_mode2_reset,
3592 .wait_for_event = smu_v13_0_wait_for_event,
3593 .i2c_init = smu_v13_0_6_i2c_control_init,
3594 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3595 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3596 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3597 .reset_sdma = smu_v13_0_6_reset_sdma,
3598 .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported,
3599 };
3600
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)3601 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
3602 {
3603 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
3604 smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3605 smu_v13_0_12_message_map : smu_v13_0_6_message_map;
3606 smu->clock_map = smu_v13_0_6_clk_map;
3607 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
3608 smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;
3609 smu->table_map = smu_v13_0_6_table_map;
3610 smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
3611 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
3612 smu_v13_0_set_smu_mailbox_registers(smu);
3613 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
3614 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
3615 }
3616