1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas SDHI
4 *
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
8 * Copyright (C) 2009 Magnus Damm
9 *
10 * Based on "Compaq ASIC3 support":
11 *
12 * Copyright 2001 Compaq Computer Corporation.
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
15 *
16 * Authors: Phil Blundell <pb@handhelds.org>,
17 * Samuel Ortiz <sameo@openedhand.com>
18 *
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_domain.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/slot-gpio.h>
31 #include <linux/mfd/tmio.h>
32 #include <linux/sh_dma.h>
33 #include <linux/delay.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/pinctrl-state.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/sys_soc.h>
38
39 #include "renesas_sdhi.h"
40 #include "tmio_mmc.h"
41
42 #define HOST_MODE 0xe4
43
44 #define SDHI_VER_GEN2_SDR50 0x490c
45 #define SDHI_VER_RZ_A1 0x820b
46 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
47 #define SDHI_VER_GEN2_SDR104 0xcb0d
48 #define SDHI_VER_GEN3_SD 0xcc10
49 #define SDHI_VER_GEN3_SDMMC 0xcd10
50
51 #define SDHI_GEN3_MMC0_ADDR 0xee140000
52
renesas_sdhi_sdbuf_width(struct tmio_mmc_host * host,int width)53 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
54 {
55 u32 val;
56
57 /*
58 * see also
59 * renesas_sdhi_of_data :: dma_buswidth
60 */
61 switch (sd_ctrl_read16(host, CTL_VERSION)) {
62 case SDHI_VER_GEN2_SDR50:
63 val = (width == 32) ? 0x0001 : 0x0000;
64 break;
65 case SDHI_VER_GEN2_SDR104:
66 val = (width == 32) ? 0x0000 : 0x0001;
67 break;
68 case SDHI_VER_GEN3_SD:
69 case SDHI_VER_GEN3_SDMMC:
70 if (width == 64)
71 val = 0x0000;
72 else if (width == 32)
73 val = 0x0101;
74 else
75 val = 0x0001;
76 break;
77 default:
78 /* nothing to do */
79 return;
80 }
81
82 sd_ctrl_write16(host, HOST_MODE, val);
83 }
84
renesas_sdhi_clk_enable(struct tmio_mmc_host * host)85 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
86 {
87 struct mmc_host *mmc = host->mmc;
88 struct renesas_sdhi *priv = host_to_priv(host);
89 int ret;
90
91 ret = clk_prepare_enable(priv->clk_cd);
92 if (ret < 0)
93 return ret;
94
95 /*
96 * The clock driver may not know what maximum frequency
97 * actually works, so it should be set with the max-frequency
98 * property which will already have been read to f_max. If it
99 * was missing, assume the current frequency is the maximum.
100 */
101 if (!mmc->f_max)
102 mmc->f_max = clk_get_rate(priv->clk);
103
104 /*
105 * Minimum frequency is the minimum input clock frequency
106 * divided by our maximum divider.
107 */
108 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
109
110 /* enable 16bit data access on SDBUF as default */
111 renesas_sdhi_sdbuf_width(host, 16);
112
113 return 0;
114 }
115
renesas_sdhi_clk_update(struct tmio_mmc_host * host,unsigned int new_clock)116 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
117 unsigned int new_clock)
118 {
119 struct renesas_sdhi *priv = host_to_priv(host);
120 unsigned int freq, diff, best_freq = 0, diff_min = ~0;
121 int i;
122
123 /*
124 * We simply return the current rate if a) we are not on a R-Car Gen2+
125 * SoC (may work for others, but untested) or b) if the SCC needs its
126 * clock during tuning, so we don't change the external clock setup.
127 */
128 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc))
129 return clk_get_rate(priv->clk);
130
131 /*
132 * We want the bus clock to be as close as possible to, but no
133 * greater than, new_clock. As we can divide by 1 << i for
134 * any i in [0, 9] we want the input clock to be as close as
135 * possible, but no greater than, new_clock << i.
136 */
137 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
138 freq = clk_round_rate(priv->clk, new_clock << i);
139 if (freq > (new_clock << i)) {
140 /* Too fast; look for a slightly slower option */
141 freq = clk_round_rate(priv->clk,
142 (new_clock << i) / 4 * 3);
143 if (freq > (new_clock << i))
144 continue;
145 }
146
147 diff = new_clock - (freq >> i);
148 if (diff <= diff_min) {
149 best_freq = freq;
150 diff_min = diff;
151 }
152 }
153
154 clk_set_rate(priv->clk, best_freq);
155
156 return clk_get_rate(priv->clk);
157 }
158
renesas_sdhi_set_clock(struct tmio_mmc_host * host,unsigned int new_clock)159 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
160 unsigned int new_clock)
161 {
162 u32 clk = 0, clock;
163
164 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
165 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
166
167 if (new_clock == 0) {
168 host->mmc->actual_clock = 0;
169 goto out;
170 }
171
172 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock);
173 clock = host->mmc->actual_clock / 512;
174
175 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
176 clock <<= 1;
177
178 /* 1/1 clock is option */
179 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
180 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
181 clk |= 0xff;
182 else
183 clk &= ~0xff;
184 }
185
186 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
187 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
188 usleep_range(10000, 11000);
189
190 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
191 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
192
193 out:
194 /* HW engineers overrode docs: no sleep needed on R-Car2+ */
195 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
196 usleep_range(10000, 11000);
197 }
198
renesas_sdhi_clk_disable(struct tmio_mmc_host * host)199 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
200 {
201 struct renesas_sdhi *priv = host_to_priv(host);
202
203 clk_disable_unprepare(priv->clk_cd);
204 }
205
renesas_sdhi_card_busy(struct mmc_host * mmc)206 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
207 {
208 struct tmio_mmc_host *host = mmc_priv(mmc);
209
210 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
211 TMIO_STAT_DAT0);
212 }
213
renesas_sdhi_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)214 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
215 struct mmc_ios *ios)
216 {
217 struct tmio_mmc_host *host = mmc_priv(mmc);
218 struct renesas_sdhi *priv = host_to_priv(host);
219 struct pinctrl_state *pin_state;
220 int ret;
221
222 switch (ios->signal_voltage) {
223 case MMC_SIGNAL_VOLTAGE_330:
224 pin_state = priv->pins_default;
225 break;
226 case MMC_SIGNAL_VOLTAGE_180:
227 pin_state = priv->pins_uhs;
228 break;
229 default:
230 return -EINVAL;
231 }
232
233 /*
234 * If anything is missing, assume signal voltage is fixed at
235 * 3.3V and succeed/fail accordingly.
236 */
237 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
238 return ios->signal_voltage ==
239 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
240
241 ret = mmc_regulator_set_vqmmc(host->mmc, ios);
242 if (ret < 0)
243 return ret;
244
245 return pinctrl_select_state(priv->pinctrl, pin_state);
246 }
247
248 /* SCC registers */
249 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
250 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002
251 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004
252 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006
253 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
254 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
255 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C
256 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E
257 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014
258 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016
259 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018
260 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A
261 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C
262
263 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
264 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
265 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
266
267 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
268
269 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
270
271 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
272 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
273 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
274
275 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
276 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
277 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24))
278
279 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
280 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
281
282 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */
283 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
284
285 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */
286 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
287 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
288 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
289
290 /* Definitions for values the SH_MOBILE_SDHI_SCC register */
291 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
292 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
293 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
294
295 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
296 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15,
297 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
298 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11,
299 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
300 };
301
302 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
303 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
304 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
305 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17,
306 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
307 };
308
309 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
310 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
311 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
312 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10,
313 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
314 };
315
sd_scc_read32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,int addr)316 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
317 struct renesas_sdhi *priv, int addr)
318 {
319 return readl(priv->scc_ctl + (addr << host->bus_shift));
320 }
321
sd_scc_write32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,int addr,u32 val)322 static inline void sd_scc_write32(struct tmio_mmc_host *host,
323 struct renesas_sdhi *priv,
324 int addr, u32 val)
325 {
326 writel(val, priv->scc_ctl + (addr << host->bus_shift));
327 }
328
renesas_sdhi_init_tuning(struct tmio_mmc_host * host)329 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
330 {
331 struct renesas_sdhi *priv;
332
333 priv = host_to_priv(host);
334
335 /* Initialize SCC */
336 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
337
338 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
339 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
340
341 /* set sampling clock selection range */
342 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
343 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
344 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
345
346 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
347 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
348 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
349
350 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
351 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
352 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
353
354 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
355
356 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
357 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
358
359 /* Read TAPNUM */
360 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
361 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
362 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
363 }
364
renesas_sdhi_hs400_complete(struct mmc_host * mmc)365 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc)
366 {
367 struct tmio_mmc_host *host = mmc_priv(mmc);
368 struct renesas_sdhi *priv = host_to_priv(host);
369 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
370 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
371
372 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
373 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
374
375 /* Set HS400 mode */
376 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
377 sd_ctrl_read16(host, CTL_SDIF_MODE));
378
379 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF,
380 priv->scc_tappos_hs400);
381
382 /* Gen3 can't do automatic tap correction with HS400, so disable it */
383 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC)
384 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
385 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
386 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
387
388 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
389 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
390 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
391 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
392
393 /* Set the sampling clock selection range of HS400 mode */
394 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
395 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
396 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
397
398 /* Avoid bad TAP */
399 if (bad_taps & BIT(priv->tap_set)) {
400 u32 new_tap = (priv->tap_set + 1) % priv->tap_num;
401
402 if (bad_taps & BIT(new_tap))
403 new_tap = (priv->tap_set - 1) % priv->tap_num;
404
405 if (bad_taps & BIT(new_tap)) {
406 new_tap = priv->tap_set;
407 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n");
408 }
409
410 priv->tap_set = new_tap;
411 }
412
413 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
414 priv->tap_set / (use_4tap ? 2 : 1));
415
416 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
417 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
418 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
419
420 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
421 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
422
423 if (priv->adjust_hs400_calib_table)
424 priv->needs_adjust_hs400 = true;
425 }
426
renesas_sdhi_reset_scc(struct tmio_mmc_host * host,struct renesas_sdhi * priv)427 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
428 struct renesas_sdhi *priv)
429 {
430 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
431 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
432
433 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
434 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
435 sd_scc_read32(host, priv,
436 SH_MOBILE_SDHI_SCC_CKSEL));
437 }
438
renesas_sdhi_disable_scc(struct mmc_host * mmc)439 static void renesas_sdhi_disable_scc(struct mmc_host *mmc)
440 {
441 struct tmio_mmc_host *host = mmc_priv(mmc);
442 struct renesas_sdhi *priv = host_to_priv(host);
443
444 renesas_sdhi_reset_scc(host, priv);
445
446 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
447 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
448 sd_scc_read32(host, priv,
449 SH_MOBILE_SDHI_SCC_DTCNTL));
450
451 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
452 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
453 }
454
sd_scc_tmpport_read32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,u32 addr)455 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host,
456 struct renesas_sdhi *priv, u32 addr)
457 {
458 /* read mode */
459 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
460 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
461 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
462
463 /* access start and stop */
464 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
465 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
466 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
467
468 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7);
469 }
470
sd_scc_tmpport_write32(struct tmio_mmc_host * host,struct renesas_sdhi * priv,u32 addr,u32 val)471 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host,
472 struct renesas_sdhi *priv, u32 addr, u32 val)
473 {
474 /* write mode */
475 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5,
476 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
477 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr));
478
479 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val);
480
481 /* access start and stop */
482 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4,
483 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START);
484 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0);
485 }
486
renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host * host)487 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host)
488 {
489 struct renesas_sdhi *priv = host_to_priv(host);
490 u32 calib_code;
491
492 /* disable write protect */
493 sd_scc_tmpport_write32(host, priv, 0x00,
494 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
495 /* read calibration code and adjust */
496 calib_code = sd_scc_tmpport_read32(host, priv, 0x26);
497 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
498
499 sd_scc_tmpport_write32(host, priv, 0x22,
500 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE |
501 priv->adjust_hs400_calib_table[calib_code]);
502
503 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */
504 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3);
505
506 /* adjustment done, clear flag */
507 priv->needs_adjust_hs400 = false;
508 }
509
renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host * host)510 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host)
511 {
512 struct renesas_sdhi *priv = host_to_priv(host);
513
514 /* disable write protect */
515 sd_scc_tmpport_write32(host, priv, 0x00,
516 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
517 /* disable manual calibration */
518 sd_scc_tmpport_write32(host, priv, 0x22, 0);
519 /* clear offset value of TMPPORT3 */
520 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0);
521 }
522
renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host * host,struct renesas_sdhi * priv)523 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
524 struct renesas_sdhi *priv)
525 {
526 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
527 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
528
529 /* Reset HS400 mode */
530 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
531 sd_ctrl_read16(host, CTL_SDIF_MODE));
532
533 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
534
535 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
536 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
537 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
538 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
539
540 if (priv->adjust_hs400_calib_table)
541 renesas_sdhi_adjust_hs400_mode_disable(host);
542
543 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
544 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
545 }
546
renesas_sdhi_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)547 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
548 {
549 struct tmio_mmc_host *host = mmc_priv(mmc);
550
551 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
552 return 0;
553 }
554
renesas_sdhi_reset(struct tmio_mmc_host * host)555 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
556 {
557 struct renesas_sdhi *priv = host_to_priv(host);
558
559 renesas_sdhi_reset_scc(host, priv);
560 renesas_sdhi_reset_hs400_mode(host, priv);
561 priv->needs_adjust_hs400 = false;
562
563 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
564 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
565
566 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
567 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
568 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
569
570 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2)
571 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK,
572 TMIO_MASK_INIT_RCAR2);
573 }
574
575 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3
576
renesas_sdhi_select_tuning(struct tmio_mmc_host * host)577 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
578 {
579 struct renesas_sdhi *priv = host_to_priv(host);
580 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i;
581 unsigned int taps_size = priv->tap_num * 2, min_tap_row;
582 unsigned long *bitmap;
583
584 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
585
586 /*
587 * When tuning CMD19 is issued twice for each tap, merge the
588 * result requiring the tap to be good in both runs before
589 * considering it for tuning selection.
590 */
591 for (i = 0; i < taps_size; i++) {
592 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1);
593
594 if (!test_bit(i, priv->taps))
595 clear_bit(i + offset, priv->taps);
596
597 if (!test_bit(i, priv->smpcmp))
598 clear_bit(i + offset, priv->smpcmp);
599 }
600
601 /*
602 * If all TAP are OK, the sampling clock position is selected by
603 * identifying the change point of data.
604 */
605 if (bitmap_full(priv->taps, taps_size)) {
606 bitmap = priv->smpcmp;
607 min_tap_row = 1;
608 } else {
609 bitmap = priv->taps;
610 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW;
611 }
612
613 /*
614 * Find the longest consecutive run of successful probes. If that
615 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the
616 * center index as the tap, otherwise bail out.
617 */
618 bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) {
619 if (re - rs > tap_cnt) {
620 tap_end = re;
621 tap_start = rs;
622 tap_cnt = tap_end - tap_start;
623 }
624 }
625
626 if (tap_cnt >= min_tap_row)
627 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num;
628 else
629 return -EIO;
630
631 /* Set SCC */
632 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set);
633
634 /* Enable auto re-tuning */
635 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
636 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
637 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
638
639 return 0;
640 }
641
renesas_sdhi_execute_tuning(struct mmc_host * mmc,u32 opcode)642 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode)
643 {
644 struct tmio_mmc_host *host = mmc_priv(mmc);
645 struct renesas_sdhi *priv = host_to_priv(host);
646 int i, ret;
647
648 priv->tap_num = renesas_sdhi_init_tuning(host);
649 if (!priv->tap_num)
650 return 0; /* Tuning is not supported */
651
652 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) {
653 dev_err(&host->pdev->dev,
654 "Too many taps, please update 'taps' in tmio_mmc_host!\n");
655 return -EINVAL;
656 }
657
658 bitmap_zero(priv->taps, priv->tap_num * 2);
659 bitmap_zero(priv->smpcmp, priv->tap_num * 2);
660
661 /* Issue CMD19 twice for each tap */
662 for (i = 0; i < 2 * priv->tap_num; i++) {
663 /* Set sampling clock position */
664 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num);
665
666 if (mmc_send_tuning(mmc, opcode, NULL) == 0)
667 set_bit(i, priv->taps);
668
669 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0)
670 set_bit(i, priv->smpcmp);
671 }
672
673 ret = renesas_sdhi_select_tuning(host);
674 if (ret < 0)
675 renesas_sdhi_reset(host);
676 return ret;
677 }
678
renesas_sdhi_manual_correction(struct tmio_mmc_host * host,bool use_4tap)679 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap)
680 {
681 struct renesas_sdhi *priv = host_to_priv(host);
682 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set;
683 u32 val;
684
685 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ);
686 if (!val)
687 return false;
688
689 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
690
691 /* Change TAP position according to correction status */
692 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC &&
693 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
694 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0;
695 /*
696 * With HS400, the DAT signal is based on DS, not CLK.
697 * Therefore, use only CMD status.
698 */
699 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) &
700 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR;
701 if (!smpcmp) {
702 return false; /* no error in CMD signal */
703 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) {
704 new_tap++;
705 error_tap--;
706 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) {
707 new_tap--;
708 error_tap++;
709 } else {
710 return true; /* need retune */
711 }
712
713 /*
714 * When new_tap is a bad tap, we cannot change. Then, we compare
715 * with the HS200 tuning result. When smpcmp[error_tap] is OK,
716 * we can at least retune.
717 */
718 if (bad_taps & BIT(new_tap % priv->tap_num))
719 return test_bit(error_tap % priv->tap_num, priv->smpcmp);
720 } else {
721 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)
722 return true; /* need retune */
723 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP)
724 new_tap++;
725 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN)
726 new_tap--;
727 else
728 return false;
729 }
730
731 priv->tap_set = (new_tap % priv->tap_num);
732 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
733 priv->tap_set / (use_4tap ? 2 : 1));
734
735 return false;
736 }
737
renesas_sdhi_auto_correction(struct tmio_mmc_host * host)738 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host)
739 {
740 struct renesas_sdhi *priv = host_to_priv(host);
741
742 /* Check SCC error */
743 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
744 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
745 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
746 return true;
747 }
748
749 return false;
750 }
751
renesas_sdhi_check_scc_error(struct tmio_mmc_host * host)752 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
753 {
754 struct renesas_sdhi *priv = host_to_priv(host);
755 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
756
757 /*
758 * Skip checking SCC errors when running on 4 taps in HS400 mode as
759 * any retuning would still result in the same 4 taps being used.
760 */
761 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
762 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
763 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
764 return false;
765
766 if (mmc_doing_tune(host->mmc))
767 return false;
768
769 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
770 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN)
771 return renesas_sdhi_auto_correction(host);
772
773 return renesas_sdhi_manual_correction(host, use_4tap);
774 }
775
renesas_sdhi_wait_idle(struct tmio_mmc_host * host,u32 bit)776 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
777 {
778 int timeout = 1000;
779 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
780 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
781
782 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
783 & bit) == wait_state)
784 udelay(1);
785
786 if (!timeout) {
787 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
788 return -EBUSY;
789 }
790
791 return 0;
792 }
793
renesas_sdhi_write16_hook(struct tmio_mmc_host * host,int addr)794 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
795 {
796 u32 bit = TMIO_STAT_SCLKDIVEN;
797
798 switch (addr) {
799 case CTL_SD_CMD:
800 case CTL_STOP_INTERNAL_ACTION:
801 case CTL_XFER_BLK_COUNT:
802 case CTL_SD_XFER_LEN:
803 case CTL_SD_MEM_CARD_OPT:
804 case CTL_TRANSACTION_CTL:
805 case CTL_DMA_ENABLE:
806 case HOST_MODE:
807 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
808 bit = TMIO_STAT_CMD_BUSY;
809 fallthrough;
810 case CTL_SD_CARD_CLK_CTL:
811 return renesas_sdhi_wait_idle(host, bit);
812 }
813
814 return 0;
815 }
816
renesas_sdhi_multi_io_quirk(struct mmc_card * card,unsigned int direction,int blk_size)817 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
818 unsigned int direction, int blk_size)
819 {
820 /*
821 * In Renesas controllers, when performing a
822 * multiple block read of one or two blocks,
823 * depending on the timing with which the
824 * response register is read, the response
825 * value may not be read properly.
826 * Use single block read for this HW bug
827 */
828 if ((direction == MMC_DATA_READ) &&
829 blk_size == 2)
830 return 1;
831
832 return blk_size;
833 }
834
renesas_sdhi_fixup_request(struct tmio_mmc_host * host,struct mmc_request * mrq)835 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq)
836 {
837 struct renesas_sdhi *priv = host_to_priv(host);
838
839 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS)
840 renesas_sdhi_adjust_hs400_mode_enable(host);
841 }
renesas_sdhi_enable_dma(struct tmio_mmc_host * host,bool enable)842 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
843 {
844 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
845 int width = (host->bus_shift == 2) ? 64 : 32;
846
847 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
848 renesas_sdhi_sdbuf_width(host, enable ? width : 16);
849 }
850
851 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
852 .hs400_disabled = true,
853 .hs400_4taps = true,
854 };
855
856 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
857 .hs400_4taps = true,
858 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
859 };
860
861 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
862 .hs400_disabled = true,
863 };
864
865 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
866 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
867 };
868
869 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
870 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
871 };
872
873 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
874 .hs400_4taps = true,
875 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
876 .hs400_calib_table = r8a7796_es13_calib_table,
877 };
878
879 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
880 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
881 .hs400_calib_table = r8a77965_calib_table,
882 };
883
884 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
885 .hs400_calib_table = r8a77990_calib_table,
886 };
887
888 /*
889 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
890 * So, we want to treat them equally and only have a match for ES1.2 to enforce
891 * this if there ever will be a way to distinguish ES1.2.
892 */
893 static const struct soc_device_attribute sdhi_quirks_match[] = {
894 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
895 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
896 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
897 { .soc_id = "r8a7795", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps2367 },
898 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
899 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
900 { .soc_id = "r8a7796", .revision = "ES3.*", .data = &sdhi_quirks_bad_taps1357 },
901 { .soc_id = "r8a77965", .data = &sdhi_quirks_r8a77965 },
902 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 },
903 { .soc_id = "r8a77990", .data = &sdhi_quirks_r8a77990 },
904 { /* Sentinel. */ },
905 };
906
renesas_sdhi_probe(struct platform_device * pdev,const struct tmio_mmc_dma_ops * dma_ops)907 int renesas_sdhi_probe(struct platform_device *pdev,
908 const struct tmio_mmc_dma_ops *dma_ops)
909 {
910 struct tmio_mmc_data *mmd = pdev->dev.platform_data;
911 const struct renesas_sdhi_quirks *quirks = NULL;
912 const struct renesas_sdhi_of_data *of_data;
913 const struct soc_device_attribute *attr;
914 struct tmio_mmc_data *mmc_data;
915 struct tmio_mmc_dma *dma_priv;
916 struct tmio_mmc_host *host;
917 struct renesas_sdhi *priv;
918 int num_irqs, irq, ret, i;
919 struct resource *res;
920 u16 ver;
921
922 of_data = of_device_get_match_data(&pdev->dev);
923
924 attr = soc_device_match(sdhi_quirks_match);
925 if (attr)
926 quirks = attr->data;
927
928 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
929 if (!res)
930 return -EINVAL;
931
932 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
933 GFP_KERNEL);
934 if (!priv)
935 return -ENOMEM;
936
937 priv->quirks = quirks;
938 mmc_data = &priv->mmc_data;
939 dma_priv = &priv->dma_priv;
940
941 priv->clk = devm_clk_get(&pdev->dev, NULL);
942 if (IS_ERR(priv->clk)) {
943 ret = PTR_ERR(priv->clk);
944 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
945 return ret;
946 }
947
948 /*
949 * Some controllers provide a 2nd clock just to run the internal card
950 * detection logic. Unfortunately, the existing driver architecture does
951 * not support a separation of clocks for runtime PM usage. When
952 * native hotplug is used, the tmio driver assumes that the core
953 * must continue to run for card detect to stay active, so we cannot
954 * disable it.
955 * Additionally, it is prohibited to supply a clock to the core but not
956 * to the card detect circuit. That leaves us with if separate clocks
957 * are presented, we must treat them both as virtually 1 clock.
958 */
959 priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
960 if (IS_ERR(priv->clk_cd))
961 priv->clk_cd = NULL;
962
963 priv->pinctrl = devm_pinctrl_get(&pdev->dev);
964 if (!IS_ERR(priv->pinctrl)) {
965 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
966 PINCTRL_STATE_DEFAULT);
967 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
968 "state_uhs");
969 }
970
971 host = tmio_mmc_host_alloc(pdev, mmc_data);
972 if (IS_ERR(host))
973 return PTR_ERR(host);
974
975 if (of_data) {
976 mmc_data->flags |= of_data->tmio_flags;
977 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
978 mmc_data->capabilities |= of_data->capabilities;
979 mmc_data->capabilities2 |= of_data->capabilities2;
980 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
981 mmc_data->max_blk_count = of_data->max_blk_count;
982 mmc_data->max_segs = of_data->max_segs;
983 dma_priv->dma_buswidth = of_data->dma_buswidth;
984 host->bus_shift = of_data->bus_shift;
985 }
986
987 host->write16_hook = renesas_sdhi_write16_hook;
988 host->clk_enable = renesas_sdhi_clk_enable;
989 host->clk_disable = renesas_sdhi_clk_disable;
990 host->set_clock = renesas_sdhi_set_clock;
991 host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
992 host->dma_ops = dma_ops;
993
994 if (quirks && quirks->hs400_disabled)
995 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
996
997 /* For some SoC, we disable internal WP. GPIO may override this */
998 if (mmc_can_gpio_ro(host->mmc))
999 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
1000
1001 /* SDR speeds are only available on Gen2+ */
1002 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
1003 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
1004 host->ops.card_busy = renesas_sdhi_card_busy;
1005 host->ops.start_signal_voltage_switch =
1006 renesas_sdhi_start_signal_voltage_switch;
1007 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27;
1008
1009 if (of_data && of_data->scc_offset) {
1010 priv->scc_ctl = host->ctl + of_data->scc_offset;
1011 host->reset = renesas_sdhi_reset;
1012 }
1013 }
1014
1015 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
1016 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
1017 host->bus_shift = 1;
1018
1019 if (mmd)
1020 *mmc_data = *mmd;
1021
1022 dma_priv->filter = shdma_chan_filter;
1023 dma_priv->enable = renesas_sdhi_enable_dma;
1024
1025 mmc_data->alignment_shift = 1; /* 2-byte alignment */
1026 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1027
1028 /*
1029 * All SDHI blocks support 2-byte and larger block sizes in 4-bit
1030 * bus width mode.
1031 */
1032 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
1033
1034 /*
1035 * All SDHI blocks support SDIO IRQ signalling.
1036 */
1037 mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
1038
1039 /* All SDHI have CMD12 control bit */
1040 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
1041
1042 /* All SDHI have SDIO status bits which must be 1 */
1043 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
1044
1045 dev_pm_domain_start(&pdev->dev);
1046
1047 ret = renesas_sdhi_clk_enable(host);
1048 if (ret)
1049 goto efree;
1050
1051 ver = sd_ctrl_read16(host, CTL_VERSION);
1052 /* GEN2_SDR104 is first known SDHI to use 32bit block count */
1053 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)
1054 mmc_data->max_blk_count = U16_MAX;
1055
1056 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
1057 if (ver == SDHI_VER_GEN2_SDR50)
1058 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
1059
1060 if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) {
1061 host->fixup_request = renesas_sdhi_fixup_request;
1062 priv->adjust_hs400_calib_table = *(
1063 res->start == SDHI_GEN3_MMC0_ADDR ?
1064 quirks->hs400_calib_table :
1065 quirks->hs400_calib_table + 1);
1066 }
1067
1068 ret = tmio_mmc_host_probe(host);
1069 if (ret < 0)
1070 goto edisclk;
1071
1072 /* Enable tuning iff we have an SCC and a supported mode */
1073 if (of_data && of_data->scc_offset &&
1074 (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
1075 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
1076 MMC_CAP2_HS400_1_8V))) {
1077 const struct renesas_sdhi_scc *taps = of_data->taps;
1078 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps;
1079 bool hit = false;
1080
1081 for (i = 0; i < of_data->taps_num; i++) {
1082 if (taps[i].clk_rate == 0 ||
1083 taps[i].clk_rate == host->mmc->f_max) {
1084 priv->scc_tappos = taps->tap;
1085 priv->scc_tappos_hs400 = use_4tap ?
1086 taps->tap_hs400_4tap :
1087 taps->tap;
1088 hit = true;
1089 break;
1090 }
1091 }
1092
1093 if (!hit)
1094 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n");
1095
1096 host->check_retune = renesas_sdhi_check_scc_error;
1097 host->ops.execute_tuning = renesas_sdhi_execute_tuning;
1098 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
1099 host->ops.hs400_downgrade = renesas_sdhi_disable_scc;
1100 host->ops.hs400_complete = renesas_sdhi_hs400_complete;
1101 }
1102
1103 num_irqs = platform_irq_count(pdev);
1104 if (num_irqs < 0) {
1105 ret = num_irqs;
1106 goto eirq;
1107 }
1108
1109 /* There must be at least one IRQ source */
1110 if (!num_irqs) {
1111 ret = -ENXIO;
1112 goto eirq;
1113 }
1114
1115 for (i = 0; i < num_irqs; i++) {
1116 irq = platform_get_irq(pdev, i);
1117 if (irq < 0) {
1118 ret = irq;
1119 goto eirq;
1120 }
1121
1122 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
1123 dev_name(&pdev->dev), host);
1124 if (ret)
1125 goto eirq;
1126 }
1127
1128 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n",
1129 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000);
1130
1131 return ret;
1132
1133 eirq:
1134 tmio_mmc_host_remove(host);
1135 edisclk:
1136 renesas_sdhi_clk_disable(host);
1137 efree:
1138 tmio_mmc_host_free(host);
1139
1140 return ret;
1141 }
1142 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
1143
renesas_sdhi_remove(struct platform_device * pdev)1144 int renesas_sdhi_remove(struct platform_device *pdev)
1145 {
1146 struct tmio_mmc_host *host = platform_get_drvdata(pdev);
1147
1148 tmio_mmc_host_remove(host);
1149 renesas_sdhi_clk_disable(host);
1150 tmio_mmc_host_free(host);
1151
1152 return 0;
1153 }
1154 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
1155
1156 MODULE_LICENSE("GPL v2");
1157