1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_de.h"
9 #include "intel_display_trace.h"
10 #include "intel_display_types.h"
11 #include "intel_fb.h"
12 #include "skl_scaler.h"
13 #include "skl_universal_plane.h"
14
15 /*
16 * The hardware phase 0.0 refers to the center of the pixel.
17 * We want to start from the top/left edge which is phase
18 * -0.5. That matches how the hardware calculates the scaling
19 * factors (from top-left of the first pixel to bottom-right
20 * of the last pixel, as opposed to the pixel centers).
21 *
22 * For 4:2:0 subsampled chroma planes we obviously have to
23 * adjust that so that the chroma sample position lands in
24 * the right spot.
25 *
26 * Note that for packed YCbCr 4:2:2 formats there is no way to
27 * control chroma siting. The hardware simply replicates the
28 * chroma samples for both of the luma samples, and thus we don't
29 * actually get the expected MPEG2 chroma siting convention :(
30 * The same behaviour is observed on pre-SKL platforms as well.
31 *
32 * Theory behind the formula (note that we ignore sub-pixel
33 * source coordinates):
34 * s = source sample position
35 * d = destination sample position
36 *
37 * Downscaling 4:1:
38 * -0.5
39 * | 0.0
40 * | | 1.5 (initial phase)
41 * | | |
42 * v v v
43 * | s | s | s | s |
44 * | d |
45 *
46 * Upscaling 1:4:
47 * -0.5
48 * | -0.375 (initial phase)
49 * | | 0.0
50 * | | |
51 * v v v
52 * | s |
53 * | d | d | d | d |
54 */
skl_scaler_calc_phase(int sub,int scale,bool chroma_cosited)55 static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
56 {
57 int phase = -0x8000;
58 u16 trip = 0;
59
60 if (chroma_cosited)
61 phase += (sub - 1) * 0x8000 / sub;
62
63 phase += scale / (2 * sub);
64
65 /*
66 * Hardware initial phase limited to [-0.5:1.5].
67 * Since the max hardware scale factor is 3.0, we
68 * should never actually exceed 1.0 here.
69 */
70 WARN_ON(phase < -0x8000 || phase > 0x18000);
71
72 if (phase < 0)
73 phase = 0x10000 + phase;
74 else
75 trip = PS_PHASE_TRIP;
76
77 return ((phase >> 2) & PS_PHASE_MASK) | trip;
78 }
79
skl_scaler_min_src_size(const struct drm_format_info * format,u64 modifier,int * min_w,int * min_h)80 static void skl_scaler_min_src_size(const struct drm_format_info *format,
81 u64 modifier, int *min_w, int *min_h)
82 {
83 if (format && intel_format_info_is_yuv_semiplanar(format, modifier)) {
84 *min_w = 16;
85 *min_h = 16;
86 } else {
87 *min_w = 8;
88 *min_h = 8;
89 }
90 }
91
skl_scaler_max_src_size(struct intel_crtc * crtc,int * max_w,int * max_h)92 static void skl_scaler_max_src_size(struct intel_crtc *crtc,
93 int *max_w, int *max_h)
94 {
95 struct intel_display *display = to_intel_display(crtc);
96
97 if (DISPLAY_VER(display) >= 14) {
98 *max_w = 4096;
99 *max_h = 8192;
100 } else if (DISPLAY_VER(display) >= 12) {
101 *max_w = 5120;
102 *max_h = 8192;
103 } else if (DISPLAY_VER(display) == 11) {
104 *max_w = 5120;
105 *max_h = 4096;
106 } else {
107 *max_w = 4096;
108 *max_h = 4096;
109 }
110 }
111
skl_scaler_min_dst_size(int * min_w,int * min_h)112 static void skl_scaler_min_dst_size(int *min_w, int *min_h)
113 {
114 *min_w = 8;
115 *min_h = 8;
116 }
117
skl_scaler_max_dst_size(struct intel_crtc * crtc,int * max_w,int * max_h)118 static void skl_scaler_max_dst_size(struct intel_crtc *crtc,
119 int *max_w, int *max_h)
120 {
121 struct intel_display *display = to_intel_display(crtc);
122
123 if (DISPLAY_VER(display) >= 12) {
124 *max_w = 8192;
125 *max_h = 8192;
126 } else if (DISPLAY_VER(display) == 11) {
127 *max_w = 5120;
128 *max_h = 4096;
129 } else {
130 *max_w = 4096;
131 *max_h = 4096;
132 }
133 }
134
135 static int
skl_update_scaler(struct intel_crtc_state * crtc_state,bool force_detach,unsigned int scaler_user,int * scaler_id,int src_w,int src_h,int dst_w,int dst_h,const struct drm_format_info * format,u64 modifier,bool need_scaler)136 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
137 unsigned int scaler_user, int *scaler_id,
138 int src_w, int src_h, int dst_w, int dst_h,
139 const struct drm_format_info *format,
140 u64 modifier, bool need_scaler)
141 {
142 struct intel_display *display = to_intel_display(crtc_state);
143 struct intel_crtc_scaler_state *scaler_state =
144 &crtc_state->scaler_state;
145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
146 const struct drm_display_mode *adjusted_mode =
147 &crtc_state->hw.adjusted_mode;
148 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
149 int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
150 int min_src_w, min_src_h, min_dst_w, min_dst_h;
151 int max_src_w, max_src_h, max_dst_w, max_dst_h;
152
153 /*
154 * Src coordinates are already rotated by 270 degrees for
155 * the 90/270 degree plane rotation cases (to match the
156 * GTT mapping), hence no need to account for rotation here.
157 */
158 if (src_w != dst_w || src_h != dst_h)
159 need_scaler = true;
160
161 /*
162 * Scaling/fitting not supported in IF-ID mode in GEN9+
163 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
164 * Once NV12 is enabled, handle it here while allocating scaler
165 * for NV12.
166 */
167 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable &&
168 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
169 drm_dbg_kms(display->drm,
170 "[CRTC:%d:%s] scaling not supported with IF-ID mode\n",
171 crtc->base.base.id, crtc->base.name);
172 return -EINVAL;
173 }
174
175 /*
176 * if plane is being disabled or scaler is no more required or force detach
177 * - free scaler binded to this plane/crtc
178 * - in order to do this, update crtc->scaler_usage
179 *
180 * Here scaler state in crtc_state is set free so that
181 * scaler can be assigned to other user. Actual register
182 * update to free the scaler is done in plane/panel-fit programming.
183 * For this purpose crtc/plane_state->scaler_id isn't reset here.
184 */
185 if (force_detach || !need_scaler) {
186 if (*scaler_id >= 0) {
187 scaler_state->scaler_users &= ~(1 << scaler_user);
188 scaler_state->scalers[*scaler_id].in_use = false;
189
190 drm_dbg_kms(display->drm,
191 "[CRTC:%d:%s] scaler_user index %u.%u: "
192 "Staged freeing scaler id %d scaler_users = 0x%x\n",
193 crtc->base.base.id, crtc->base.name,
194 crtc->pipe, scaler_user, *scaler_id,
195 scaler_state->scaler_users);
196 *scaler_id = -1;
197 }
198 return 0;
199 }
200
201 skl_scaler_min_src_size(format, modifier, &min_src_w, &min_src_h);
202 skl_scaler_max_src_size(crtc, &max_src_w, &max_src_h);
203
204 skl_scaler_min_dst_size(&min_dst_w, &min_dst_h);
205 skl_scaler_max_dst_size(crtc, &max_dst_w, &max_dst_h);
206
207 /* range checks */
208 if (src_w < min_src_w || src_h < min_src_h ||
209 dst_w < min_dst_w || dst_h < min_dst_h ||
210 src_w > max_src_w || src_h > max_src_h ||
211 dst_w > max_dst_w || dst_h > max_dst_h) {
212 drm_dbg_kms(display->drm,
213 "[CRTC:%d:%s] scaler_user index %u.%u: src %ux%u dst %ux%u "
214 "size is out of scaler range\n",
215 crtc->base.base.id, crtc->base.name,
216 crtc->pipe, scaler_user, src_w, src_h,
217 dst_w, dst_h);
218 return -EINVAL;
219 }
220
221 /*
222 * The pipe scaler does not use all the bits of PIPESRC, at least
223 * on the earlier platforms. So even when we're scaling a plane
224 * the *pipe* source size must not be too large. For simplicity
225 * we assume the limits match the scaler destination size limits.
226 * Might not be 100% accurate on all platforms, but good enough for
227 * now.
228 */
229 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) {
230 drm_dbg_kms(display->drm,
231 "[CRTC:%d:%s] scaler_user index %u.%u: pipe src size %ux%u "
232 "is out of scaler range\n",
233 crtc->base.base.id, crtc->base.name,
234 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
235 return -EINVAL;
236 }
237
238 /* mark this plane as a scaler user in crtc_state */
239 scaler_state->scaler_users |= (1 << scaler_user);
240 drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: "
241 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
242 crtc->base.base.id, crtc->base.name,
243 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
244 scaler_state->scaler_users);
245
246 return 0;
247 }
248
skl_update_scaler_crtc(struct intel_crtc_state * crtc_state)249 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
250 {
251 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
252 int width, height;
253
254 if (crtc_state->pch_pfit.enabled) {
255 width = drm_rect_width(&crtc_state->pch_pfit.dst);
256 height = drm_rect_height(&crtc_state->pch_pfit.dst);
257 } else {
258 width = pipe_mode->crtc_hdisplay;
259 height = pipe_mode->crtc_vdisplay;
260 }
261 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
262 SKL_CRTC_INDEX,
263 &crtc_state->scaler_state.scaler_id,
264 drm_rect_width(&crtc_state->pipe_src),
265 drm_rect_height(&crtc_state->pipe_src),
266 width, height, NULL, 0,
267 crtc_state->pch_pfit.enabled);
268 }
269
270 /**
271 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
272 * @crtc_state: crtc's scaler state
273 * @plane_state: atomic plane state to update
274 *
275 * Return
276 * 0 - scaler_usage updated successfully
277 * error - requested scaling cannot be supported or other error condition
278 */
skl_update_scaler_plane(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)279 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
280 struct intel_plane_state *plane_state)
281 {
282 struct intel_display *display = to_intel_display(plane_state);
283 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
284 struct drm_framebuffer *fb = plane_state->hw.fb;
285 bool force_detach = !fb || !plane_state->uapi.visible;
286 bool need_scaler = false;
287
288 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
289 if (!icl_is_hdr_plane(display, plane->id) &&
290 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
291 need_scaler = true;
292
293 return skl_update_scaler(crtc_state, force_detach,
294 drm_plane_index(&plane->base),
295 &plane_state->scaler_id,
296 drm_rect_width(&plane_state->uapi.src) >> 16,
297 drm_rect_height(&plane_state->uapi.src) >> 16,
298 drm_rect_width(&plane_state->uapi.dst),
299 drm_rect_height(&plane_state->uapi.dst),
300 fb ? fb->format : NULL,
301 fb ? fb->modifier : 0,
302 need_scaler);
303 }
304
intel_allocate_scaler(struct intel_crtc_scaler_state * scaler_state,struct intel_crtc * crtc)305 static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state,
306 struct intel_crtc *crtc)
307 {
308 int i;
309
310 for (i = 0; i < crtc->num_scalers; i++) {
311 if (scaler_state->scalers[i].in_use)
312 continue;
313
314 scaler_state->scalers[i].in_use = true;
315
316 return i;
317 }
318
319 return -1;
320 }
321
322 static void
calculate_max_scale(struct intel_crtc * crtc,bool is_yuv_semiplanar,int scaler_id,int * max_hscale,int * max_vscale)323 calculate_max_scale(struct intel_crtc *crtc,
324 bool is_yuv_semiplanar,
325 int scaler_id,
326 int *max_hscale, int *max_vscale)
327 {
328 struct intel_display *display = to_intel_display(crtc);
329
330 /*
331 * FIXME: When two scalers are needed, but only one of
332 * them needs to downscale, we should make sure that
333 * the one that needs downscaling support is assigned
334 * as the first scaler, so we don't reject downscaling
335 * unnecessarily.
336 */
337
338 if (DISPLAY_VER(display) >= 14) {
339 /*
340 * On versions 14 and up, only the first
341 * scaler supports a vertical scaling factor
342 * of more than 1.0, while a horizontal
343 * scaling factor of 3.0 is supported.
344 */
345 *max_hscale = 0x30000 - 1;
346
347 if (scaler_id == 0)
348 *max_vscale = 0x30000 - 1;
349 else
350 *max_vscale = 0x10000;
351 } else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) {
352 *max_hscale = 0x30000 - 1;
353 *max_vscale = 0x30000 - 1;
354 } else {
355 *max_hscale = 0x20000 - 1;
356 *max_vscale = 0x20000 - 1;
357 }
358 }
359
intel_atomic_setup_scaler(struct intel_crtc_state * crtc_state,int num_scalers_need,struct intel_crtc * crtc,const char * name,int idx,struct intel_plane_state * plane_state,int * scaler_id)360 static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
361 int num_scalers_need, struct intel_crtc *crtc,
362 const char *name, int idx,
363 struct intel_plane_state *plane_state,
364 int *scaler_id)
365 {
366 struct intel_display *display = to_intel_display(crtc);
367 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
368 u32 mode;
369 int hscale = 0;
370 int vscale = 0;
371
372 if (*scaler_id < 0)
373 *scaler_id = intel_allocate_scaler(scaler_state, crtc);
374
375 if (drm_WARN(display->drm, *scaler_id < 0,
376 "Cannot find scaler for %s:%d\n", name, idx))
377 return -EINVAL;
378
379 /* set scaler mode */
380 if (plane_state && plane_state->hw.fb &&
381 plane_state->hw.fb->format->is_yuv &&
382 plane_state->hw.fb->format->num_planes > 1) {
383 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
384
385 if (DISPLAY_VER(display) == 9) {
386 mode = SKL_PS_SCALER_MODE_NV12;
387 } else if (icl_is_hdr_plane(display, plane->id)) {
388 /*
389 * On gen11+'s HDR planes we only use the scaler for
390 * scaling. They have a dedicated chroma upsampler, so
391 * we don't need the scaler to upsample the UV plane.
392 */
393 mode = PS_SCALER_MODE_NORMAL;
394 } else {
395 struct intel_plane *linked =
396 plane_state->planar_linked_plane;
397
398 mode = PS_SCALER_MODE_PLANAR;
399
400 if (linked)
401 mode |= PS_BINDING_Y_PLANE(linked->id);
402 }
403 } else if (DISPLAY_VER(display) >= 10) {
404 mode = PS_SCALER_MODE_NORMAL;
405 } else if (num_scalers_need == 1 && crtc->num_scalers > 1) {
406 /*
407 * when only 1 scaler is in use on a pipe with 2 scalers
408 * scaler 0 operates in high quality (HQ) mode.
409 * In this case use scaler 0 to take advantage of HQ mode
410 */
411 scaler_state->scalers[*scaler_id].in_use = false;
412 *scaler_id = 0;
413 scaler_state->scalers[0].in_use = true;
414 mode = SKL_PS_SCALER_MODE_HQ;
415 } else {
416 mode = SKL_PS_SCALER_MODE_DYN;
417 }
418
419 if (plane_state && plane_state->hw.fb) {
420 const struct drm_framebuffer *fb = plane_state->hw.fb;
421 const struct drm_rect *src = &plane_state->uapi.src;
422 const struct drm_rect *dst = &plane_state->uapi.dst;
423 int max_hscale, max_vscale;
424
425 calculate_max_scale(crtc,
426 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier),
427 *scaler_id, &max_hscale, &max_vscale);
428
429 /*
430 * FIXME: We should change the if-else block above to
431 * support HQ vs dynamic scaler properly.
432 */
433
434 /* Check if required scaling is within limits */
435 hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
436 vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
437
438 if (hscale < 0 || vscale < 0) {
439 drm_dbg_kms(display->drm,
440 "[CRTC:%d:%s] scaler %d doesn't support required plane scaling\n",
441 crtc->base.base.id, crtc->base.name, *scaler_id);
442 drm_rect_debug_print("src: ", src, true);
443 drm_rect_debug_print("dst: ", dst, false);
444
445 return -EINVAL;
446 }
447 }
448
449 if (crtc_state->pch_pfit.enabled) {
450 struct drm_rect src;
451 int max_hscale, max_vscale;
452
453 drm_rect_init(&src, 0, 0,
454 drm_rect_width(&crtc_state->pipe_src) << 16,
455 drm_rect_height(&crtc_state->pipe_src) << 16);
456
457 calculate_max_scale(crtc, 0, *scaler_id,
458 &max_hscale, &max_vscale);
459
460 /*
461 * When configured for Pipe YUV 420 encoding for port output,
462 * limit downscaling to less than 1.5 (source/destination) in
463 * the horizontal direction and 1.0 in the vertical direction.
464 */
465 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
466 max_hscale = 0x18000 - 1;
467 max_vscale = 0x10000;
468 }
469
470 hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,
471 0, max_hscale);
472 vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,
473 0, max_vscale);
474
475 if (hscale < 0 || vscale < 0) {
476 drm_dbg_kms(display->drm,
477 "Scaler %d doesn't support required pipe scaling\n",
478 *scaler_id);
479 drm_rect_debug_print("src: ", &src, true);
480 drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false);
481
482 return -EINVAL;
483 }
484 }
485
486 scaler_state->scalers[*scaler_id].hscale = hscale;
487 scaler_state->scalers[*scaler_id].vscale = vscale;
488
489 drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n",
490 crtc->base.base.id, crtc->base.name,
491 crtc->pipe, *scaler_id, name, idx);
492 scaler_state->scalers[*scaler_id].mode = mode;
493
494 return 0;
495 }
496
setup_crtc_scaler(struct intel_atomic_state * state,struct intel_crtc * crtc)497 static int setup_crtc_scaler(struct intel_atomic_state *state,
498 struct intel_crtc *crtc)
499 {
500 struct intel_crtc_state *crtc_state =
501 intel_atomic_get_new_crtc_state(state, crtc);
502 struct intel_crtc_scaler_state *scaler_state =
503 &crtc_state->scaler_state;
504
505 return intel_atomic_setup_scaler(crtc_state,
506 hweight32(scaler_state->scaler_users),
507 crtc, "CRTC", crtc->base.base.id,
508 NULL, &scaler_state->scaler_id);
509 }
510
setup_plane_scaler(struct intel_atomic_state * state,struct intel_crtc * crtc,struct intel_plane * plane)511 static int setup_plane_scaler(struct intel_atomic_state *state,
512 struct intel_crtc *crtc,
513 struct intel_plane *plane)
514 {
515 struct intel_display *display = to_intel_display(state);
516 struct intel_crtc_state *crtc_state =
517 intel_atomic_get_new_crtc_state(state, crtc);
518 struct intel_crtc_scaler_state *scaler_state =
519 &crtc_state->scaler_state;
520 struct intel_plane_state *plane_state;
521
522 /* plane on different crtc cannot be a scaler user of this crtc */
523 if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe))
524 return 0;
525
526 plane_state = intel_atomic_get_new_plane_state(state, plane);
527
528 /*
529 * GLK+ scalers don't have a HQ mode so it
530 * isn't necessary to change between HQ and dyn mode
531 * on those platforms.
532 */
533 if (!plane_state && DISPLAY_VER(display) >= 10)
534 return 0;
535
536 plane_state = intel_atomic_get_plane_state(state, plane);
537 if (IS_ERR(plane_state))
538 return PTR_ERR(plane_state);
539
540 return intel_atomic_setup_scaler(crtc_state,
541 hweight32(scaler_state->scaler_users),
542 crtc, "PLANE", plane->base.base.id,
543 plane_state, &plane_state->scaler_id);
544 }
545
546 /**
547 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
548 * @state: atomic state
549 * @crtc: crtc
550 *
551 * This function sets up scalers based on staged scaling requests for
552 * a @crtc and its planes. It is called from crtc level check path. If request
553 * is a supportable request, it attaches scalers to requested planes and crtc.
554 *
555 * This function takes into account the current scaler(s) in use by any planes
556 * not being part of this atomic state
557 *
558 * Returns:
559 * 0 - scalers were setup successfully
560 * error code - otherwise
561 */
intel_atomic_setup_scalers(struct intel_atomic_state * state,struct intel_crtc * crtc)562 int intel_atomic_setup_scalers(struct intel_atomic_state *state,
563 struct intel_crtc *crtc)
564 {
565 struct intel_display *display = to_intel_display(crtc);
566 struct intel_crtc_state *crtc_state =
567 intel_atomic_get_new_crtc_state(state, crtc);
568 struct intel_crtc_scaler_state *scaler_state =
569 &crtc_state->scaler_state;
570 int num_scalers_need;
571 int i;
572
573 num_scalers_need = hweight32(scaler_state->scaler_users);
574
575 /*
576 * High level flow:
577 * - staged scaler requests are already in scaler_state->scaler_users
578 * - check whether staged scaling requests can be supported
579 * - add planes using scalers that aren't in current transaction
580 * - assign scalers to requested users
581 * - as part of plane commit, scalers will be committed
582 * (i.e., either attached or detached) to respective planes in hw
583 * - as part of crtc_commit, scaler will be either attached or detached
584 * to crtc in hw
585 */
586
587 /* fail if required scalers > available scalers */
588 if (num_scalers_need > crtc->num_scalers) {
589 drm_dbg_kms(display->drm,
590 "[CRTC:%d:%s] too many scaling requests %d > %d\n",
591 crtc->base.base.id, crtc->base.name,
592 num_scalers_need, crtc->num_scalers);
593 return -EINVAL;
594 }
595
596 /* walkthrough scaler_users bits and start assigning scalers */
597 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
598 int ret;
599
600 /* skip if scaler not required */
601 if (!(scaler_state->scaler_users & (1 << i)))
602 continue;
603
604 if (i == SKL_CRTC_INDEX) {
605 ret = setup_crtc_scaler(state, crtc);
606 if (ret)
607 return ret;
608 } else {
609 struct intel_plane *plane =
610 to_intel_plane(drm_plane_from_index(display->drm, i));
611
612 ret = setup_plane_scaler(state, crtc, plane);
613 if (ret)
614 return ret;
615 }
616 }
617
618 return 0;
619 }
620
glk_coef_tap(int i)621 static int glk_coef_tap(int i)
622 {
623 return i % 7;
624 }
625
glk_nearest_filter_coef(int t)626 static u16 glk_nearest_filter_coef(int t)
627 {
628 return t == 3 ? 0x0800 : 0x3000;
629 }
630
631 /*
632 * Theory behind setting nearest-neighbor integer scaling:
633 *
634 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
635 * The letter represents the filter tap (D is the center tap) and the number
636 * represents the coefficient set for a phase (0-16).
637 *
638 * +------------+--------------------------+--------------------------+
639 * |Index value | Data value coefficient 1 | Data value coefficient 2 |
640 * +------------+--------------------------+--------------------------+
641 * | 00h | B0 | A0 |
642 * +------------+--------------------------+--------------------------+
643 * | 01h | D0 | C0 |
644 * +------------+--------------------------+--------------------------+
645 * | 02h | F0 | E0 |
646 * +------------+--------------------------+--------------------------+
647 * | 03h | A1 | G0 |
648 * +------------+--------------------------+--------------------------+
649 * | 04h | C1 | B1 |
650 * +------------+--------------------------+--------------------------+
651 * | ... | ... | ... |
652 * +------------+--------------------------+--------------------------+
653 * | 38h | B16 | A16 |
654 * +------------+--------------------------+--------------------------+
655 * | 39h | D16 | C16 |
656 * +------------+--------------------------+--------------------------+
657 * | 3Ah | F16 | C16 |
658 * +------------+--------------------------+--------------------------+
659 * | 3Bh | Reserved | G16 |
660 * +------------+--------------------------+--------------------------+
661 *
662 * To enable nearest-neighbor scaling: program scaler coefficients with
663 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
664 * SCALER_COEFFICIENT_FORMAT
665 *
666 */
667
glk_program_nearest_filter_coefs(struct intel_display * display,struct intel_dsb * dsb,enum pipe pipe,int id,int set)668 static void glk_program_nearest_filter_coefs(struct intel_display *display,
669 struct intel_dsb *dsb,
670 enum pipe pipe, int id, int set)
671 {
672 int i;
673
674 intel_de_write_dsb(display, dsb,
675 GLK_PS_COEF_INDEX_SET(pipe, id, set),
676 PS_COEF_INDEX_AUTO_INC);
677
678 for (i = 0; i < 17 * 7; i += 2) {
679 u32 tmp;
680 int t;
681
682 t = glk_coef_tap(i);
683 tmp = glk_nearest_filter_coef(t);
684
685 t = glk_coef_tap(i + 1);
686 tmp |= glk_nearest_filter_coef(t) << 16;
687
688 intel_de_write_dsb(display, dsb,
689 GLK_PS_COEF_DATA_SET(pipe, id, set), tmp);
690 }
691
692 intel_de_write_dsb(display, dsb,
693 GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
694 }
695
skl_scaler_get_filter_select(enum drm_scaling_filter filter,int set)696 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
697 {
698 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
699 return (PS_FILTER_PROGRAMMED |
700 PS_Y_VERT_FILTER_SELECT(set) |
701 PS_Y_HORZ_FILTER_SELECT(set) |
702 PS_UV_VERT_FILTER_SELECT(set) |
703 PS_UV_HORZ_FILTER_SELECT(set));
704 }
705
706 return PS_FILTER_MEDIUM;
707 }
708
skl_scaler_setup_filter(struct intel_display * display,struct intel_dsb * dsb,enum pipe pipe,int id,int set,enum drm_scaling_filter filter)709 static void skl_scaler_setup_filter(struct intel_display *display,
710 struct intel_dsb *dsb, enum pipe pipe,
711 int id, int set, enum drm_scaling_filter filter)
712 {
713 switch (filter) {
714 case DRM_SCALING_FILTER_DEFAULT:
715 break;
716 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
717 glk_program_nearest_filter_coefs(display, dsb, pipe, id, set);
718 break;
719 default:
720 MISSING_CASE(filter);
721 }
722 }
723
skl_pfit_enable(const struct intel_crtc_state * crtc_state)724 void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
725 {
726 struct intel_display *display = to_intel_display(crtc_state);
727 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
728 const struct intel_crtc_scaler_state *scaler_state =
729 &crtc_state->scaler_state;
730 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
731 u16 uv_rgb_hphase, uv_rgb_vphase;
732 enum pipe pipe = crtc->pipe;
733 int width = drm_rect_width(dst);
734 int height = drm_rect_height(dst);
735 int x = dst->x1;
736 int y = dst->y1;
737 int hscale, vscale;
738 struct drm_rect src;
739 int id;
740 u32 ps_ctrl;
741
742 if (!crtc_state->pch_pfit.enabled)
743 return;
744
745 if (drm_WARN_ON(display->drm,
746 crtc_state->scaler_state.scaler_id < 0))
747 return;
748
749 drm_rect_init(&src, 0, 0,
750 drm_rect_width(&crtc_state->pipe_src) << 16,
751 drm_rect_height(&crtc_state->pipe_src) << 16);
752
753 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
754 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
755
756 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
757 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
758
759 id = scaler_state->scaler_id;
760
761 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
762 skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
763
764 trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height);
765
766 skl_scaler_setup_filter(display, NULL, pipe, id, 0,
767 crtc_state->hw.scaling_filter);
768
769 intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl);
770
771 intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id),
772 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
773 intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id),
774 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
775 intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id),
776 PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
777 intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id),
778 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
779 }
780
781 void
skl_program_plane_scaler(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)782 skl_program_plane_scaler(struct intel_dsb *dsb,
783 struct intel_plane *plane,
784 const struct intel_crtc_state *crtc_state,
785 const struct intel_plane_state *plane_state)
786 {
787 struct intel_display *display = to_intel_display(plane);
788 const struct drm_framebuffer *fb = plane_state->hw.fb;
789 enum pipe pipe = plane->pipe;
790 int scaler_id = plane_state->scaler_id;
791 const struct intel_scaler *scaler =
792 &crtc_state->scaler_state.scalers[scaler_id];
793 int crtc_x = plane_state->uapi.dst.x1;
794 int crtc_y = plane_state->uapi.dst.y1;
795 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
796 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
797 u16 y_hphase, uv_rgb_hphase;
798 u16 y_vphase, uv_rgb_vphase;
799 int hscale, vscale;
800 u32 ps_ctrl;
801
802 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
803 &plane_state->uapi.dst,
804 0, INT_MAX);
805 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
806 &plane_state->uapi.dst,
807 0, INT_MAX);
808
809 /* TODO: handle sub-pixel coordinates */
810 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
811 !icl_is_hdr_plane(display, plane->id)) {
812 y_hphase = skl_scaler_calc_phase(1, hscale, false);
813 y_vphase = skl_scaler_calc_phase(1, vscale, false);
814
815 /* MPEG2 chroma siting convention */
816 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
817 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
818 } else {
819 /* not used */
820 y_hphase = 0;
821 y_vphase = 0;
822
823 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
824 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
825 }
826
827 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
828 skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
829
830 trace_intel_plane_scaler_update_arm(plane, scaler_id,
831 crtc_x, crtc_y, crtc_w, crtc_h);
832
833 skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0,
834 plane_state->hw.scaling_filter);
835
836 intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id),
837 ps_ctrl);
838 intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id),
839 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
840 intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id),
841 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
842 intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id),
843 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
844 intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id),
845 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
846 }
847
skl_detach_scaler(struct intel_dsb * dsb,struct intel_crtc * crtc,int id)848 static void skl_detach_scaler(struct intel_dsb *dsb,
849 struct intel_crtc *crtc, int id)
850 {
851 struct intel_display *display = to_intel_display(crtc);
852
853 trace_intel_scaler_disable_arm(crtc, id);
854
855 intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0);
856 intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0);
857 intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
858 }
859
860 /*
861 * This function detaches (aka. unbinds) unused scalers in hardware
862 */
skl_detach_scalers(struct intel_dsb * dsb,const struct intel_crtc_state * crtc_state)863 void skl_detach_scalers(struct intel_dsb *dsb,
864 const struct intel_crtc_state *crtc_state)
865 {
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
867 const struct intel_crtc_scaler_state *scaler_state =
868 &crtc_state->scaler_state;
869 int i;
870
871 /* loop through and disable scalers that aren't in use */
872 for (i = 0; i < crtc->num_scalers; i++) {
873 if (!scaler_state->scalers[i].in_use)
874 skl_detach_scaler(dsb, crtc, i);
875 }
876 }
877
skl_scaler_disable(const struct intel_crtc_state * old_crtc_state)878 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
879 {
880 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
881 int i;
882
883 for (i = 0; i < crtc->num_scalers; i++)
884 skl_detach_scaler(NULL, crtc, i);
885 }
886
skl_scaler_get_config(struct intel_crtc_state * crtc_state)887 void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
888 {
889 struct intel_display *display = to_intel_display(crtc_state);
890 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
891 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
892 int id = -1;
893 int i;
894
895 /* find scaler attached to this pipe */
896 for (i = 0; i < crtc->num_scalers; i++) {
897 u32 ctl, pos, size;
898
899 ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i));
900 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
901 continue;
902
903 id = i;
904 crtc_state->pch_pfit.enabled = true;
905
906 pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i));
907 size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i));
908
909 drm_rect_init(&crtc_state->pch_pfit.dst,
910 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
911 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
912 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
913 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
914
915 scaler_state->scalers[i].in_use = true;
916 break;
917 }
918
919 scaler_state->scaler_id = id;
920 if (id >= 0)
921 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
922 else
923 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
924 }
925