1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017 SiFive, Inc.
6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
7 *
8 * Provides a board compatible with the SiFive Freedom U SDK:
9 *
10 * 0) UART
11 * 1) CLINT (Core Level Interruptor)
12 * 2) PLIC (Platform Level Interrupt Controller)
13 * 3) PRCI (Power, Reset, Clock, Interrupt)
14 * 4) GPIO (General Purpose Input/Output Controller)
15 * 5) OTP (One-Time Programmable) memory with stored serial number
16 * 6) GEM (Gigabit Ethernet Controller) and management block
17 * 7) DMA (Direct Memory Access Controller)
18 * 8) SPI0 connected to an SPI flash
19 * 9) SPI2 connected to an SD card
20 * 10) PWM0 and PWM1
21 *
22 * This board currently generates devicetree dynamically that indicates at least
23 * two harts and up to five harts.
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms and conditions of the GNU General Public License,
27 * version 2 or later, as published by the Free Software Foundation.
28 *
29 * This program is distributed in the hope it will be useful, but WITHOUT
30 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
31 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
32 * more details.
33 *
34 * You should have received a copy of the GNU General Public License along with
35 * this program. If not, see <http://www.gnu.org/licenses/>.
36 */
37
38 #include "qemu/osdep.h"
39 #include "qemu/error-report.h"
40 #include "qapi/error.h"
41 #include "qapi/visitor.h"
42 #include "hw/boards.h"
43 #include "hw/irq.h"
44 #include "hw/loader.h"
45 #include "hw/sysbus.h"
46 #include "hw/cpu/cluster.h"
47 #include "hw/misc/unimp.h"
48 #include "hw/sd/sd.h"
49 #include "hw/ssi/ssi.h"
50 #include "target/riscv/cpu.h"
51 #include "hw/riscv/riscv_hart.h"
52 #include "hw/riscv/sifive_u.h"
53 #include "hw/riscv/boot.h"
54 #include "hw/char/sifive_uart.h"
55 #include "hw/intc/riscv_aclint.h"
56 #include "hw/intc/sifive_plic.h"
57 #include "chardev/char.h"
58 #include "net/eth.h"
59 #include "system/device_tree.h"
60 #include "system/runstate.h"
61 #include "system/system.h"
62
63 #include <libfdt.h>
64
65 /* CLINT timebase frequency */
66 #define CLINT_TIMEBASE_FREQ 1000000
67
68 static const MemMapEntry sifive_u_memmap[] = {
69 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
70 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
72 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
73 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
74 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
75 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
76 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
77 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
78 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
79 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 },
80 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
81 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
82 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
83 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
84 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
85 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
86 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
87 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
88 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
89 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
90 };
91
92 #define OTP_SERIAL 1
93 #define GEM_REVISION 0x10070109
94
create_fdt(SiFiveUState * s,const MemMapEntry * memmap,bool is_32_bit)95 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
96 bool is_32_bit)
97 {
98 MachineState *ms = MACHINE(s);
99 uint64_t mem_size = ms->ram_size;
100 void *fdt;
101 int cpu;
102 uint32_t *cells;
103 char *nodename;
104 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
105 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
106 static const char * const ethclk_names[2] = { "pclk", "hclk" };
107 static const char * const clint_compat[2] = {
108 "sifive,clint0", "riscv,clint0"
109 };
110 static const char * const plic_compat[2] = {
111 "sifive,plic-1.0.0", "riscv,plic0"
112 };
113
114 fdt = ms->fdt = create_device_tree(&s->fdt_size);
115 if (!fdt) {
116 error_report("create_device_tree() failed");
117 exit(1);
118 }
119
120 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
121 qemu_fdt_setprop_string(fdt, "/", "compatible",
122 "sifive,hifive-unleashed-a00");
123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
124 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
125
126 qemu_fdt_add_subnode(fdt, "/soc");
127 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
128 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
129 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
130 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
131
132 hfclk_phandle = phandle++;
133 nodename = g_strdup_printf("/hfclk");
134 qemu_fdt_add_subnode(fdt, nodename);
135 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
136 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
137 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
138 SIFIVE_U_HFCLK_FREQ);
139 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
140 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
141 g_free(nodename);
142
143 rtcclk_phandle = phandle++;
144 nodename = g_strdup_printf("/rtcclk");
145 qemu_fdt_add_subnode(fdt, nodename);
146 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
147 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
148 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
149 SIFIVE_U_RTCCLK_FREQ);
150 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
151 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
152 g_free(nodename);
153
154 nodename = g_strdup_printf("/memory@%lx",
155 (long)memmap[SIFIVE_U_DEV_DRAM].base);
156 qemu_fdt_add_subnode(fdt, nodename);
157 qemu_fdt_setprop_cells(fdt, nodename, "reg",
158 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
159 mem_size >> 32, mem_size);
160 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
161 g_free(nodename);
162
163 qemu_fdt_add_subnode(fdt, "/cpus");
164 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
165 CLINT_TIMEBASE_FREQ);
166 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
167 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
168
169 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
170 int cpu_phandle = phandle++;
171 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
172 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
173 qemu_fdt_add_subnode(fdt, nodename);
174 /* cpu 0 is the management hart that does not have mmu */
175 if (cpu != 0) {
176 if (is_32_bit) {
177 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
178 } else {
179 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
180 }
181 riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename);
182 } else {
183 riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename);
184 }
185 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
186 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
187 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
188 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
189 qemu_fdt_add_subnode(fdt, intc);
190 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
191 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
192 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
193 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
194 g_free(intc);
195 g_free(nodename);
196 }
197
198 cells = g_new0(uint32_t, ms->smp.cpus * 4);
199 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
200 nodename =
201 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
202 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
203 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
204 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
205 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
206 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
207 g_free(nodename);
208 }
209 nodename = g_strdup_printf("/soc/clint@%lx",
210 (long)memmap[SIFIVE_U_DEV_CLINT].base);
211 qemu_fdt_add_subnode(fdt, nodename);
212 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
213 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
214 qemu_fdt_setprop_cells(fdt, nodename, "reg",
215 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
216 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
217 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
218 cells, ms->smp.cpus * sizeof(uint32_t) * 4);
219 g_free(cells);
220 g_free(nodename);
221
222 nodename = g_strdup_printf("/soc/otp@%lx",
223 (long)memmap[SIFIVE_U_DEV_OTP].base);
224 qemu_fdt_add_subnode(fdt, nodename);
225 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
226 qemu_fdt_setprop_cells(fdt, nodename, "reg",
227 0x0, memmap[SIFIVE_U_DEV_OTP].base,
228 0x0, memmap[SIFIVE_U_DEV_OTP].size);
229 qemu_fdt_setprop_string(fdt, nodename, "compatible",
230 "sifive,fu540-c000-otp");
231 g_free(nodename);
232
233 prci_phandle = phandle++;
234 nodename = g_strdup_printf("/soc/clock-controller@%lx",
235 (long)memmap[SIFIVE_U_DEV_PRCI].base);
236 qemu_fdt_add_subnode(fdt, nodename);
237 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
238 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
239 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
240 hfclk_phandle, rtcclk_phandle);
241 qemu_fdt_setprop_cells(fdt, nodename, "reg",
242 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
243 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
244 qemu_fdt_setprop_string(fdt, nodename, "compatible",
245 "sifive,fu540-c000-prci");
246 g_free(nodename);
247
248 plic_phandle = phandle++;
249 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
250 for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
251 nodename =
252 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
253 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
254 /* cpu 0 is the management hart that does not have S-mode */
255 if (cpu == 0) {
256 cells[0] = cpu_to_be32(intc_phandle);
257 cells[1] = cpu_to_be32(IRQ_M_EXT);
258 } else {
259 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
260 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
261 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
262 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
263 }
264 g_free(nodename);
265 }
266 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
267 (long)memmap[SIFIVE_U_DEV_PLIC].base);
268 qemu_fdt_add_subnode(fdt, nodename);
269 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
270 qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
271 (char **)&plic_compat, ARRAY_SIZE(plic_compat));
272 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
273 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
274 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
275 qemu_fdt_setprop_cells(fdt, nodename, "reg",
276 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
277 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
278 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
279 SIFIVE_U_PLIC_NUM_SOURCES - 1);
280 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
281 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
282 g_free(cells);
283 g_free(nodename);
284
285 gpio_phandle = phandle++;
286 nodename = g_strdup_printf("/soc/gpio@%lx",
287 (long)memmap[SIFIVE_U_DEV_GPIO].base);
288 qemu_fdt_add_subnode(fdt, nodename);
289 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
290 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
291 prci_phandle, PRCI_CLK_TLCLK);
292 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
293 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
294 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
295 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
296 qemu_fdt_setprop_cells(fdt, nodename, "reg",
297 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
298 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
299 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
300 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
301 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
302 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
303 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
304 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
305 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
306 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
307 g_free(nodename);
308
309 nodename = g_strdup_printf("/gpio-restart");
310 qemu_fdt_add_subnode(fdt, nodename);
311 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
312 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
313 g_free(nodename);
314
315 nodename = g_strdup_printf("/soc/dma@%lx",
316 (long)memmap[SIFIVE_U_DEV_PDMA].base);
317 qemu_fdt_add_subnode(fdt, nodename);
318 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
319 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
320 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
321 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
322 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
323 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
324 qemu_fdt_setprop_cells(fdt, nodename, "reg",
325 0x0, memmap[SIFIVE_U_DEV_PDMA].base,
326 0x0, memmap[SIFIVE_U_DEV_PDMA].size);
327 qemu_fdt_setprop_string(fdt, nodename, "compatible",
328 "sifive,fu540-c000-pdma");
329 g_free(nodename);
330
331 nodename = g_strdup_printf("/soc/cache-controller@%lx",
332 (long)memmap[SIFIVE_U_DEV_L2CC].base);
333 qemu_fdt_add_subnode(fdt, nodename);
334 qemu_fdt_setprop_cells(fdt, nodename, "reg",
335 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
336 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
337 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
338 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
339 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
340 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
341 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
342 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
343 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
344 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
345 qemu_fdt_setprop_string(fdt, nodename, "compatible",
346 "sifive,fu540-c000-ccache");
347 g_free(nodename);
348
349 nodename = g_strdup_printf("/soc/spi@%lx",
350 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
351 qemu_fdt_add_subnode(fdt, nodename);
352 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
353 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
354 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
355 prci_phandle, PRCI_CLK_TLCLK);
356 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
357 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
358 qemu_fdt_setprop_cells(fdt, nodename, "reg",
359 0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
360 0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
361 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
362 g_free(nodename);
363
364 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
365 (long)memmap[SIFIVE_U_DEV_QSPI2].base);
366 qemu_fdt_add_subnode(fdt, nodename);
367 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
368 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
369 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
370 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
371 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
372 g_free(nodename);
373
374 nodename = g_strdup_printf("/soc/spi@%lx",
375 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
376 qemu_fdt_add_subnode(fdt, nodename);
377 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
378 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
379 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
380 prci_phandle, PRCI_CLK_TLCLK);
381 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
382 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
383 qemu_fdt_setprop_cells(fdt, nodename, "reg",
384 0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
385 0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
386 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
387 g_free(nodename);
388
389 nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
390 (long)memmap[SIFIVE_U_DEV_QSPI0].base);
391 qemu_fdt_add_subnode(fdt, nodename);
392 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
393 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
394 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
395 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
396 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
397 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
398 g_free(nodename);
399
400 phy_phandle = phandle++;
401 nodename = g_strdup_printf("/soc/ethernet@%lx",
402 (long)memmap[SIFIVE_U_DEV_GEM].base);
403 qemu_fdt_add_subnode(fdt, nodename);
404 qemu_fdt_setprop_string(fdt, nodename, "compatible",
405 "sifive,fu540-c000-gem");
406 qemu_fdt_setprop_cells(fdt, nodename, "reg",
407 0x0, memmap[SIFIVE_U_DEV_GEM].base,
408 0x0, memmap[SIFIVE_U_DEV_GEM].size,
409 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
410 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
411 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
412 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
413 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
414 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
415 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
416 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
417 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
418 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
419 (char **)ðclk_names, ARRAY_SIZE(ethclk_names));
420 qemu_fdt_setprop(fdt, nodename, "local-mac-address",
421 s->soc.gem.conf.macaddr.a, ETH_ALEN);
422 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
423 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
424
425 qemu_fdt_add_subnode(fdt, "/aliases");
426 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
427
428 g_free(nodename);
429
430 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
431 (long)memmap[SIFIVE_U_DEV_GEM].base);
432 qemu_fdt_add_subnode(fdt, nodename);
433 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
434 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
435 g_free(nodename);
436
437 nodename = g_strdup_printf("/soc/pwm@%lx",
438 (long)memmap[SIFIVE_U_DEV_PWM0].base);
439 qemu_fdt_add_subnode(fdt, nodename);
440 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
441 qemu_fdt_setprop_cells(fdt, nodename, "reg",
442 0x0, memmap[SIFIVE_U_DEV_PWM0].base,
443 0x0, memmap[SIFIVE_U_DEV_PWM0].size);
444 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
445 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
446 SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
447 SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
448 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
449 prci_phandle, PRCI_CLK_TLCLK);
450 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
451 g_free(nodename);
452
453 nodename = g_strdup_printf("/soc/pwm@%lx",
454 (long)memmap[SIFIVE_U_DEV_PWM1].base);
455 qemu_fdt_add_subnode(fdt, nodename);
456 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
457 qemu_fdt_setprop_cells(fdt, nodename, "reg",
458 0x0, memmap[SIFIVE_U_DEV_PWM1].base,
459 0x0, memmap[SIFIVE_U_DEV_PWM1].size);
460 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
461 qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
462 SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
463 SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
464 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
465 prci_phandle, PRCI_CLK_TLCLK);
466 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
467 g_free(nodename);
468
469 nodename = g_strdup_printf("/soc/serial@%lx",
470 (long)memmap[SIFIVE_U_DEV_UART1].base);
471 qemu_fdt_add_subnode(fdt, nodename);
472 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
473 qemu_fdt_setprop_cells(fdt, nodename, "reg",
474 0x0, memmap[SIFIVE_U_DEV_UART1].base,
475 0x0, memmap[SIFIVE_U_DEV_UART1].size);
476 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
477 prci_phandle, PRCI_CLK_TLCLK);
478 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
479 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
480
481 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
482 g_free(nodename);
483
484 nodename = g_strdup_printf("/soc/serial@%lx",
485 (long)memmap[SIFIVE_U_DEV_UART0].base);
486 qemu_fdt_add_subnode(fdt, nodename);
487 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
488 qemu_fdt_setprop_cells(fdt, nodename, "reg",
489 0x0, memmap[SIFIVE_U_DEV_UART0].base,
490 0x0, memmap[SIFIVE_U_DEV_UART0].size);
491 qemu_fdt_setprop_cells(fdt, nodename, "clocks",
492 prci_phandle, PRCI_CLK_TLCLK);
493 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
494 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
495
496 qemu_fdt_add_subnode(fdt, "/chosen");
497 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
498 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
499
500 g_free(nodename);
501 }
502
sifive_u_machine_reset(void * opaque,int n,int level)503 static void sifive_u_machine_reset(void *opaque, int n, int level)
504 {
505 /* gpio pin active low triggers reset */
506 if (!level) {
507 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
508 }
509 }
510
sifive_u_machine_init(MachineState * machine)511 static void sifive_u_machine_init(MachineState *machine)
512 {
513 const MemMapEntry *memmap = sifive_u_memmap;
514 SiFiveUState *s = RISCV_U_MACHINE(machine);
515 MemoryRegion *system_memory = get_system_memory();
516 MemoryRegion *flash0 = g_new(MemoryRegion, 1);
517 hwaddr start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
518 target_ulong firmware_end_addr, kernel_start_addr;
519 const char *firmware_name;
520 uint32_t start_addr_hi32 = 0x00000000;
521 uint32_t fdt_load_addr_hi32 = 0x00000000;
522 int i;
523 uint64_t fdt_load_addr;
524 uint64_t kernel_entry;
525 DriveInfo *dinfo;
526 BlockBackend *blk;
527 DeviceState *flash_dev, *sd_dev, *card_dev;
528 qemu_irq flash_cs, sd_cs;
529 RISCVBootInfo boot_info;
530
531 /* Initialize SoC */
532 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
533 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
534 &error_abort);
535 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
536 &error_abort);
537 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
538
539 /* register RAM */
540 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
541 machine->ram);
542
543 /* register QSPI0 Flash */
544 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
545 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
546 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
547 flash0);
548
549 /* register gpio-restart */
550 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
551 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
552
553 /* load/create device tree */
554 if (machine->dtb) {
555 machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
556 if (!machine->fdt) {
557 error_report("load_device_tree() failed");
558 exit(1);
559 }
560 } else {
561 create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
562 }
563
564 if (s->start_in_flash) {
565 /*
566 * If start_in_flash property is given, assign s->msel to a value
567 * that representing booting from QSPI0 memory-mapped flash.
568 *
569 * This also means that when both start_in_flash and msel properties
570 * are given, start_in_flash takes the precedence over msel.
571 *
572 * Note this is to keep backward compatibility not to break existing
573 * users that use start_in_flash property.
574 */
575 s->msel = MSEL_MEMMAP_QSPI0_FLASH;
576 }
577
578 switch (s->msel) {
579 case MSEL_MEMMAP_QSPI0_FLASH:
580 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
581 break;
582 case MSEL_L2LIM_QSPI0_FLASH:
583 case MSEL_L2LIM_QSPI2_SD:
584 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
585 break;
586 default:
587 start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
588 break;
589 }
590
591 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
592 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
593 &start_addr, NULL);
594
595 riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
596 if (machine->kernel_filename) {
597 kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
598 firmware_end_addr);
599 riscv_load_kernel(machine, &boot_info, kernel_start_addr,
600 true, NULL);
601 kernel_entry = boot_info.image_low_addr;
602 } else {
603 /*
604 * If dynamic firmware is used, it doesn't know where is the next mode
605 * if kernel argument is not set.
606 */
607 kernel_entry = 0;
608 }
609
610 fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
611 memmap[SIFIVE_U_DEV_DRAM].size,
612 machine, &boot_info);
613 riscv_load_fdt(fdt_load_addr, machine->fdt);
614
615 if (!riscv_is_32bit(&s->soc.u_cpus)) {
616 start_addr_hi32 = (uint64_t)start_addr >> 32;
617 fdt_load_addr_hi32 = fdt_load_addr >> 32;
618 }
619
620 /* reset vector */
621 uint32_t reset_vec[12] = {
622 s->msel, /* MSEL pin state */
623 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
624 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
625 0xf1402573, /* csrr a0, mhartid */
626 0,
627 0,
628 0x00028067, /* jr t0 */
629 start_addr, /* start: .dword */
630 start_addr_hi32,
631 fdt_load_addr, /* fdt_laddr: .dword */
632 fdt_load_addr_hi32,
633 0x00000000,
634 /* fw_dyn: */
635 };
636 if (riscv_is_32bit(&s->soc.u_cpus)) {
637 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
638 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
639 } else {
640 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
641 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
642 }
643
644
645 /* copy in the reset vector in little_endian byte order */
646 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
647 reset_vec[i] = cpu_to_le32(reset_vec[i]);
648 }
649 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
650 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
651
652 riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus,
653 memmap[SIFIVE_U_DEV_MROM].base,
654 memmap[SIFIVE_U_DEV_MROM].size,
655 sizeof(reset_vec), kernel_entry);
656
657 /* Connect an SPI flash to SPI0 */
658 flash_dev = qdev_new("is25wp256");
659 dinfo = drive_get(IF_MTD, 0, 0);
660 if (dinfo) {
661 qdev_prop_set_drive_err(flash_dev, "drive",
662 blk_by_legacy_dinfo(dinfo),
663 &error_fatal);
664 }
665 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
666
667 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
668 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
669
670 /* Connect an SD card to SPI2 */
671 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
672
673 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
674 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
675
676 dinfo = drive_get(IF_SD, 0, 0);
677 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
678 card_dev = qdev_new(TYPE_SD_CARD_SPI);
679 qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal);
680 qdev_realize_and_unref(card_dev,
681 qdev_get_child_bus(sd_dev, "sd-bus"),
682 &error_fatal);
683 }
684
sifive_u_machine_get_start_in_flash(Object * obj,Error ** errp)685 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
686 {
687 SiFiveUState *s = RISCV_U_MACHINE(obj);
688
689 return s->start_in_flash;
690 }
691
sifive_u_machine_set_start_in_flash(Object * obj,bool value,Error ** errp)692 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
693 {
694 SiFiveUState *s = RISCV_U_MACHINE(obj);
695
696 s->start_in_flash = value;
697 }
698
sifive_u_machine_instance_init(Object * obj)699 static void sifive_u_machine_instance_init(Object *obj)
700 {
701 SiFiveUState *s = RISCV_U_MACHINE(obj);
702
703 s->start_in_flash = false;
704 s->msel = 0;
705 object_property_add_uint32_ptr(obj, "msel", &s->msel,
706 OBJ_PROP_FLAG_READWRITE);
707 object_property_set_description(obj, "msel",
708 "Mode Select (MSEL[3:0]) pin state");
709
710 s->serial = OTP_SERIAL;
711 object_property_add_uint32_ptr(obj, "serial", &s->serial,
712 OBJ_PROP_FLAG_READWRITE);
713 object_property_set_description(obj, "serial", "Board serial number");
714 }
715
sifive_u_machine_class_init(ObjectClass * oc,const void * data)716 static void sifive_u_machine_class_init(ObjectClass *oc, const void *data)
717 {
718 MachineClass *mc = MACHINE_CLASS(oc);
719
720 mc->desc = "RISC-V Board compatible with SiFive U SDK";
721 mc->init = sifive_u_machine_init;
722 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
723 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
724 mc->default_cpu_type = SIFIVE_U_CPU;
725 mc->default_cpus = mc->min_cpus;
726 mc->default_ram_id = "riscv.sifive.u.ram";
727 mc->auto_create_sdcard = true;
728
729 object_class_property_add_bool(oc, "start-in-flash",
730 sifive_u_machine_get_start_in_flash,
731 sifive_u_machine_set_start_in_flash);
732 object_class_property_set_description(oc, "start-in-flash",
733 "Set on to tell QEMU's ROM to jump to "
734 "flash. Otherwise QEMU will jump to DRAM "
735 "or L2LIM depending on the msel value");
736 }
737
738 static const TypeInfo sifive_u_machine_typeinfo = {
739 .name = MACHINE_TYPE_NAME("sifive_u"),
740 .parent = TYPE_MACHINE,
741 .class_init = sifive_u_machine_class_init,
742 .instance_init = sifive_u_machine_instance_init,
743 .instance_size = sizeof(SiFiveUState),
744 };
745
sifive_u_machine_init_register_types(void)746 static void sifive_u_machine_init_register_types(void)
747 {
748 type_register_static(&sifive_u_machine_typeinfo);
749 }
750
type_init(sifive_u_machine_init_register_types)751 type_init(sifive_u_machine_init_register_types)
752
753 static void sifive_u_soc_instance_init(Object *obj)
754 {
755 SiFiveUSoCState *s = RISCV_U_SOC(obj);
756
757 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
758 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
759
760 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
761 TYPE_RISCV_HART_ARRAY);
762 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
763 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
764 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
765 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
766
767 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
768 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
769
770 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
771 TYPE_RISCV_HART_ARRAY);
772
773 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
774 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
775 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
776 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
777 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
778 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
779 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
780 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM);
781 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM);
782 }
783
sifive_u_soc_realize(DeviceState * dev,Error ** errp)784 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
785 {
786 MachineState *ms = MACHINE(qdev_get_machine());
787 SiFiveUSoCState *s = RISCV_U_SOC(dev);
788 const MemMapEntry *memmap = sifive_u_memmap;
789 MemoryRegion *system_memory = get_system_memory();
790 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
791 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
792 char *plic_hart_config;
793 int i, j;
794
795 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
796 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
797 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
798 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
799
800 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
801 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
802 /*
803 * The cluster must be realized after the RISC-V hart array container,
804 * as the container's CPU object is only created on realize, and the
805 * CPU must exist and have been parented into the cluster before the
806 * cluster is realized.
807 */
808 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
809 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
810
811 /* boot rom */
812 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
813 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
814 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
815 mask_rom);
816
817 /*
818 * Add L2-LIM at reset size.
819 * This should be reduced in size as the L2 Cache Controller WayEnable
820 * register is incremented. Unfortunately I don't see a nice (or any) way
821 * to handle reducing or blocking out the L2 LIM while still allowing it
822 * be re returned to all enabled after a reset. For the time being, just
823 * leave it enabled all the time. This won't break anything, but will be
824 * too generous to misbehaving guests.
825 */
826 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
827 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
828 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
829 l2lim_mem);
830
831 /* create PLIC hart topology configuration string */
832 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
833
834 /* MMIO */
835 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
836 plic_hart_config, ms->smp.cpus, 0,
837 SIFIVE_U_PLIC_NUM_SOURCES,
838 SIFIVE_U_PLIC_NUM_PRIORITIES,
839 SIFIVE_U_PLIC_PRIORITY_BASE,
840 SIFIVE_U_PLIC_PENDING_BASE,
841 SIFIVE_U_PLIC_ENABLE_BASE,
842 SIFIVE_U_PLIC_ENABLE_STRIDE,
843 SIFIVE_U_PLIC_CONTEXT_BASE,
844 SIFIVE_U_PLIC_CONTEXT_STRIDE,
845 memmap[SIFIVE_U_DEV_PLIC].size);
846 g_free(plic_hart_config);
847 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
848 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
849 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
850 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
851 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
852 ms->smp.cpus, false);
853 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
854 RISCV_ACLINT_SWI_SIZE,
855 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
856 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
857 CLINT_TIMEBASE_FREQ, false);
858
859 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
860 return;
861 }
862 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
863
864 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
865 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
866 return;
867 }
868 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
869
870 /* Pass all GPIOs to the SOC layer so they are available to the board */
871 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
872
873 /* Connect GPIO interrupts to the PLIC */
874 for (i = 0; i < 16; i++) {
875 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
876 qdev_get_gpio_in(DEVICE(s->plic),
877 SIFIVE_U_GPIO_IRQ0 + i));
878 }
879
880 /* PDMA */
881 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
882 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
883
884 /* Connect PDMA interrupts to the PLIC */
885 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
886 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
887 qdev_get_gpio_in(DEVICE(s->plic),
888 SIFIVE_U_PDMA_IRQ0 + i));
889 }
890
891 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
892 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
893 return;
894 }
895 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
896
897 qemu_configure_nic_device(DEVICE(&s->gem), true, NULL);
898 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
899 &error_abort);
900 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
901 return;
902 }
903 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
904 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
905 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
906
907 /* PWM */
908 for (i = 0; i < 2; i++) {
909 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) {
910 return;
911 }
912 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0,
913 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i));
914
915 /* Connect PWM interrupts to the PLIC */
916 for (j = 0; j < SIFIVE_PWM_IRQS; j++) {
917 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j,
918 qdev_get_gpio_in(DEVICE(s->plic),
919 SIFIVE_U_PWM0_IRQ0 + (i * 4) + j));
920 }
921 }
922
923 create_unimplemented_device("riscv.sifive.u.gem-mgmt",
924 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
925
926 create_unimplemented_device("riscv.sifive.u.dmc",
927 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
928
929 create_unimplemented_device("riscv.sifive.u.l2cc",
930 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
931
932 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
933 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
934 memmap[SIFIVE_U_DEV_QSPI0].base);
935 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
936 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
937 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
938 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
939 memmap[SIFIVE_U_DEV_QSPI2].base);
940 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
941 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
942 }
943
944 static const Property sifive_u_soc_props[] = {
945 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
946 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
947 };
948
sifive_u_soc_class_init(ObjectClass * oc,const void * data)949 static void sifive_u_soc_class_init(ObjectClass *oc, const void *data)
950 {
951 DeviceClass *dc = DEVICE_CLASS(oc);
952
953 device_class_set_props(dc, sifive_u_soc_props);
954 dc->realize = sifive_u_soc_realize;
955 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
956 dc->user_creatable = false;
957 }
958
959 static const TypeInfo sifive_u_soc_type_info = {
960 .name = TYPE_RISCV_U_SOC,
961 .parent = TYPE_DEVICE,
962 .instance_size = sizeof(SiFiveUSoCState),
963 .instance_init = sifive_u_soc_instance_init,
964 .class_init = sifive_u_soc_class_init,
965 };
966
sifive_u_soc_register_types(void)967 static void sifive_u_soc_register_types(void)
968 {
969 type_register_static(&sifive_u_soc_type_info);
970 }
971
972 type_init(sifive_u_soc_register_types)
973