1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_dpm.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_sienna_cichlid.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "sienna_cichlid_ppt.h"
40 #include "smu_v11_0_7_pptable.h"
41 #include "smu_v11_0_7_ppsmc.h"
42 #include "nbio/nbio_2_3_offset.h"
43 #include "nbio/nbio_2_3_sh_mask.h"
44 #include "thm/thm_11_0_2_offset.h"
45 #include "thm/thm_11_0_2_sh_mask.h"
46 #include "mp/mp_11_0_offset.h"
47 #include "mp/mp_11_0_sh_mask.h"
48
49 #include "asic_reg/mp/mp_11_0_sh_mask.h"
50 #include "amdgpu_ras.h"
51 #include "smu_cmn.h"
52
53 /*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58 #undef pr_err
59 #undef pr_warn
60 #undef pr_info
61 #undef pr_debug
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76 #define GET_PPTABLE_MEMBER(field, member) \
77 do { \
78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \
79 IP_VERSION(11, 0, 13)) \
80 (*member) = (smu->smu_table.driver_pptable + \
81 offsetof(PPTable_beige_goby_t, field)); \
82 else \
83 (*member) = (smu->smu_table.driver_pptable + \
84 offsetof(PPTable_t, field)); \
85 } while (0)
86
87 /* STB FIFO depth is in 64bit units */
88 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
89
90 /*
91 * SMU support ECCTABLE since version 58.70.0,
92 * use this to check whether ECCTABLE feature is supported.
93 */
94 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
95
get_table_size(struct smu_context * smu)96 static int get_table_size(struct smu_context *smu)
97 {
98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
99 return sizeof(PPTable_beige_goby_t);
100 else
101 return sizeof(PPTable_t);
102 }
103
104 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
105 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
106 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
107 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
108 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
109 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
110 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
111 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
112 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
113 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
114 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
115 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
116 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
117 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
120 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
121 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
122 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
123 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
124 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
125 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
126 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
128 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
136 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
137 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
138 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
139 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
140 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
141 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
142 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
143 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
145 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
146 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
148 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
149 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
150 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
151 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
152 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
153 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
154 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
155 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
156 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
158 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
159 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
160 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
161 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
162 };
163
164 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
165 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
166 CLK_MAP(SCLK, PPCLK_GFXCLK),
167 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
168 CLK_MAP(FCLK, PPCLK_FCLK),
169 CLK_MAP(UCLK, PPCLK_UCLK),
170 CLK_MAP(MCLK, PPCLK_UCLK),
171 CLK_MAP(DCLK, PPCLK_DCLK_0),
172 CLK_MAP(DCLK1, PPCLK_DCLK_1),
173 CLK_MAP(VCLK, PPCLK_VCLK_0),
174 CLK_MAP(VCLK1, PPCLK_VCLK_1),
175 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
177 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
178 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
179 };
180
181 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
182 FEA_MAP(DPM_PREFETCHER),
183 FEA_MAP(DPM_GFXCLK),
184 FEA_MAP(DPM_GFX_GPO),
185 FEA_MAP(DPM_UCLK),
186 FEA_MAP(DPM_FCLK),
187 FEA_MAP(DPM_SOCCLK),
188 FEA_MAP(DPM_MP0CLK),
189 FEA_MAP(DPM_LINK),
190 FEA_MAP(DPM_DCEFCLK),
191 FEA_MAP(DPM_XGMI),
192 FEA_MAP(MEM_VDDCI_SCALING),
193 FEA_MAP(MEM_MVDD_SCALING),
194 FEA_MAP(DS_GFXCLK),
195 FEA_MAP(DS_SOCCLK),
196 FEA_MAP(DS_FCLK),
197 FEA_MAP(DS_LCLK),
198 FEA_MAP(DS_DCEFCLK),
199 FEA_MAP(DS_UCLK),
200 FEA_MAP(GFX_ULV),
201 FEA_MAP(FW_DSTATE),
202 FEA_MAP(GFXOFF),
203 FEA_MAP(BACO),
204 FEA_MAP(MM_DPM_PG),
205 FEA_MAP(RSMU_SMN_CG),
206 FEA_MAP(PPT),
207 FEA_MAP(TDC),
208 FEA_MAP(APCC_PLUS),
209 FEA_MAP(GTHR),
210 FEA_MAP(ACDC),
211 FEA_MAP(VR0HOT),
212 FEA_MAP(VR1HOT),
213 FEA_MAP(FW_CTF),
214 FEA_MAP(FAN_CONTROL),
215 FEA_MAP(THERMAL),
216 FEA_MAP(GFX_DCS),
217 FEA_MAP(RM),
218 FEA_MAP(LED_DISPLAY),
219 FEA_MAP(GFX_SS),
220 FEA_MAP(OUT_OF_BAND_MONITOR),
221 FEA_MAP(TEMP_DEPENDENT_VMIN),
222 FEA_MAP(MMHUB_PG),
223 FEA_MAP(ATHUB_PG),
224 FEA_MAP(APCC_DFLL),
225 };
226
227 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
228 TAB_MAP(PPTABLE),
229 TAB_MAP(WATERMARKS),
230 TAB_MAP(AVFS_PSM_DEBUG),
231 TAB_MAP(AVFS_FUSE_OVERRIDE),
232 TAB_MAP(PMSTATUSLOG),
233 TAB_MAP(SMU_METRICS),
234 TAB_MAP(DRIVER_SMU_CONFIG),
235 TAB_MAP(ACTIVITY_MONITOR_COEFF),
236 TAB_MAP(OVERDRIVE),
237 TAB_MAP(I2C_COMMANDS),
238 TAB_MAP(PACE),
239 TAB_MAP(ECCINFO),
240 };
241
242 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
243 PWR_MAP(AC),
244 PWR_MAP(DC),
245 };
246
247 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
255 };
256
257 static const uint8_t sienna_cichlid_throttler_map[] = {
258 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
259 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
260 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
261 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
262 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
263 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
265 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
266 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
267 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
268 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
269 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
270 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
271 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
272 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
273 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
274 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
275 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
276 };
277
278 static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)279 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
281 {
282 struct amdgpu_device *adev = smu->adev;
283
284 if (num > 2)
285 return -EINVAL;
286
287 memset(feature_mask, 0, sizeof(uint32_t) * num);
288
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
291 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
294 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
295 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
296 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
297 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
298 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
299 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
300 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
301 | FEATURE_MASK(FEATURE_PPT_BIT)
302 | FEATURE_MASK(FEATURE_TDC_BIT)
303 | FEATURE_MASK(FEATURE_BACO_BIT)
304 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
305 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
306 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
307 | FEATURE_MASK(FEATURE_THERMAL_BIT)
308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
313 }
314
315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
317 !(adev->flags & AMD_IS_APU))
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
319
320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
322 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
323 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
324
325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
327
328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
330
331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
333
334 if (adev->pm.pp_feature & PP_ULV_MASK)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
336
337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
339
340 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
342
343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
345
346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
348
349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
352
353 if (smu->dc_controlled_by_gpio)
354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
355
356 if (amdgpu_device_should_use_aspm(adev))
357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
358
359 return 0;
360 }
361
sienna_cichlid_check_bxco_support(struct smu_context * smu)362 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
363 {
364 struct smu_table_context *table_context = &smu->smu_table;
365 struct smu_11_0_7_powerplay_table *powerplay_table =
366 table_context->power_play_table;
367 struct smu_baco_context *smu_baco = &smu->smu_baco;
368 struct amdgpu_device *adev = smu->adev;
369 uint32_t val;
370
371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
372 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
373 smu_baco->platform_support =
374 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
375 false;
376
377 /*
378 * Disable BACO entry/exit completely on below SKUs to
379 * avoid hardware intermittent failures.
380 */
381 if (((adev->pdev->device == 0x73A1) &&
382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73BF) &&
384 (adev->pdev->revision == 0xCF)) ||
385 ((adev->pdev->device == 0x7422) &&
386 (adev->pdev->revision == 0x00)) ||
387 ((adev->pdev->device == 0x73A3) &&
388 (adev->pdev->revision == 0x00)) ||
389 ((adev->pdev->device == 0x73E3) &&
390 (adev->pdev->revision == 0x00)))
391 smu_baco->platform_support = false;
392
393 }
394 }
395
sienna_cichlid_check_fan_support(struct smu_context * smu)396 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
397 {
398 struct smu_table_context *table_context = &smu->smu_table;
399 PPTable_t *pptable = table_context->driver_pptable;
400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
401
402 /* Fan control is not possible if PPTable has it disabled */
403 smu->adev->pm.no_fan =
404 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
405 if (smu->adev->pm.no_fan)
406 dev_info_once(smu->adev->dev,
407 "PMFW based fan control disabled");
408 }
409
sienna_cichlid_check_powerplay_table(struct smu_context * smu)410 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
411 {
412 struct smu_table_context *table_context = &smu->smu_table;
413 struct smu_11_0_7_powerplay_table *powerplay_table =
414 table_context->power_play_table;
415
416 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
417 smu->dc_controlled_by_gpio = true;
418
419 sienna_cichlid_check_bxco_support(smu);
420 sienna_cichlid_check_fan_support(smu);
421
422 table_context->thermal_controller_type =
423 powerplay_table->thermal_controller_type;
424
425 /*
426 * Instead of having its own buffer space and get overdrive_table copied,
427 * smu->od_settings just points to the actual overdrive_table
428 */
429 smu->od_settings = &powerplay_table->overdrive_table;
430
431 return 0;
432 }
433
sienna_cichlid_append_powerplay_table(struct smu_context * smu)434 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
435 {
436 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
437 int index, ret;
438 PPTable_beige_goby_t *ppt_beige_goby;
439 PPTable_t *ppt;
440
441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
442 ppt_beige_goby = smu->smu_table.driver_pptable;
443 else
444 ppt = smu->smu_table.driver_pptable;
445
446 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
447 smc_dpm_info);
448
449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
450 (uint8_t **)&smc_dpm_table);
451 if (ret)
452 return ret;
453
454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
455 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
456 smc_dpm_table, I2cControllers);
457 else
458 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
459 smc_dpm_table, I2cControllers);
460
461 return 0;
462 }
463
sienna_cichlid_store_powerplay_table(struct smu_context * smu)464 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
465 {
466 struct smu_table_context *table_context = &smu->smu_table;
467 struct smu_11_0_7_powerplay_table *powerplay_table =
468 table_context->power_play_table;
469 int table_size;
470
471 table_size = get_table_size(smu);
472 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
473 table_size);
474
475 return 0;
476 }
477
sienna_cichlid_patch_pptable_quirk(struct smu_context * smu)478 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
479 {
480 struct amdgpu_device *adev = smu->adev;
481 uint32_t *board_reserved;
482 uint16_t *freq_table_gfx;
483 uint32_t i;
484
485 /* Fix some OEM SKU specific stability issues */
486 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
487 if ((adev->pdev->device == 0x73DF) &&
488 (adev->pdev->revision == 0XC3) &&
489 (adev->pdev->subsystem_device == 0x16C2) &&
490 (adev->pdev->subsystem_vendor == 0x1043))
491 board_reserved[0] = 1387;
492
493 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
494 if ((adev->pdev->device == 0x73DF) &&
495 (adev->pdev->revision == 0XC3) &&
496 ((adev->pdev->subsystem_device == 0x16C2) ||
497 (adev->pdev->subsystem_device == 0x133C)) &&
498 (adev->pdev->subsystem_vendor == 0x1043)) {
499 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
500 if (freq_table_gfx[i] > 2500)
501 freq_table_gfx[i] = 2500;
502 }
503 }
504
505 return 0;
506 }
507
sienna_cichlid_setup_pptable(struct smu_context * smu)508 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
509 {
510 int ret = 0;
511
512 ret = smu_v11_0_setup_pptable(smu);
513 if (ret)
514 return ret;
515
516 ret = sienna_cichlid_store_powerplay_table(smu);
517 if (ret)
518 return ret;
519
520 ret = sienna_cichlid_append_powerplay_table(smu);
521 if (ret)
522 return ret;
523
524 ret = sienna_cichlid_check_powerplay_table(smu);
525 if (ret)
526 return ret;
527
528 return sienna_cichlid_patch_pptable_quirk(smu);
529 }
530
sienna_cichlid_tables_init(struct smu_context * smu)531 static int sienna_cichlid_tables_init(struct smu_context *smu)
532 {
533 struct smu_table_context *smu_table = &smu->smu_table;
534 struct smu_table *tables = smu_table->tables;
535 int table_size;
536
537 table_size = get_table_size(smu);
538 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
540 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
542 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
548 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
550 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
551 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
552 AMDGPU_GEM_DOMAIN_VRAM);
553 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
554 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
555 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
556 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
557
558 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
559 if (!smu_table->metrics_table)
560 goto err0_out;
561 smu_table->metrics_time = 0;
562
563 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
564 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
565 if (!smu_table->gpu_metrics_table)
566 goto err1_out;
567
568 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
569 if (!smu_table->watermarks_table)
570 goto err2_out;
571
572 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
573 if (!smu_table->ecc_table)
574 goto err3_out;
575
576 smu_table->driver_smu_config_table =
577 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
578 if (!smu_table->driver_smu_config_table)
579 goto err4_out;
580
581 return 0;
582
583 err4_out:
584 kfree(smu_table->ecc_table);
585 err3_out:
586 kfree(smu_table->watermarks_table);
587 err2_out:
588 kfree(smu_table->gpu_metrics_table);
589 err1_out:
590 kfree(smu_table->metrics_table);
591 err0_out:
592 return -ENOMEM;
593 }
594
sienna_cichlid_get_throttler_status_locked(struct smu_context * smu,bool use_metrics_v3,bool use_metrics_v2)595 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
596 bool use_metrics_v3,
597 bool use_metrics_v2)
598 {
599 struct smu_table_context *smu_table= &smu->smu_table;
600 SmuMetricsExternal_t *metrics_ext =
601 (SmuMetricsExternal_t *)(smu_table->metrics_table);
602 uint32_t throttler_status = 0;
603 int i;
604
605 if (use_metrics_v3) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
607 throttler_status |=
608 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
609 } else if (use_metrics_v2) {
610 for (i = 0; i < THROTTLER_COUNT; i++)
611 throttler_status |=
612 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
613 } else {
614 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
615 }
616
617 return throttler_status;
618 }
619
sienna_cichlid_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)620 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
621 uint32_t *current_power_limit,
622 uint32_t *default_power_limit,
623 uint32_t *max_power_limit,
624 uint32_t *min_power_limit)
625 {
626 struct smu_11_0_7_powerplay_table *powerplay_table =
627 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
628 uint32_t power_limit, od_percent_upper, od_percent_lower;
629 uint16_t *table_member;
630
631 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
632
633 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
634 power_limit =
635 table_member[PPT_THROTTLER_PPT0];
636 }
637
638 if (current_power_limit)
639 *current_power_limit = power_limit;
640 if (default_power_limit)
641 *default_power_limit = power_limit;
642
643 if (smu->od_enabled)
644 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
645 else
646 od_percent_upper = 0;
647
648 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
649
650 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
651 od_percent_upper, od_percent_lower, power_limit);
652
653 if (max_power_limit) {
654 *max_power_limit = power_limit * (100 + od_percent_upper);
655 *max_power_limit /= 100;
656 }
657
658 if (min_power_limit) {
659 *min_power_limit = power_limit * (100 - od_percent_lower);
660 *min_power_limit /= 100;
661 }
662 return 0;
663 }
664
sienna_cichlid_get_smartshift_power_percentage(struct smu_context * smu,uint32_t * apu_percent,uint32_t * dgpu_percent)665 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
666 uint32_t *apu_percent,
667 uint32_t *dgpu_percent)
668 {
669 struct smu_table_context *smu_table = &smu->smu_table;
670 SmuMetrics_V4_t *metrics_v4 =
671 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
672 uint16_t powerRatio = 0;
673 uint16_t apu_power_limit = 0;
674 uint16_t dgpu_power_limit = 0;
675 uint32_t apu_boost = 0;
676 uint32_t dgpu_boost = 0;
677 uint32_t cur_power_limit;
678
679 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
680 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL);
681 apu_power_limit = metrics_v4->ApuSTAPMLimit;
682 dgpu_power_limit = cur_power_limit;
683 powerRatio = (((apu_power_limit +
684 dgpu_power_limit) * 100) /
685 metrics_v4->ApuSTAPMSmartShiftLimit);
686 if (powerRatio > 100) {
687 apu_power_limit = (apu_power_limit * 100) /
688 powerRatio;
689 dgpu_power_limit = (dgpu_power_limit * 100) /
690 powerRatio;
691 }
692 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
693 apu_power_limit != 0) {
694 apu_boost = ((metrics_v4->AverageApuSocketPower -
695 apu_power_limit) * 100) /
696 apu_power_limit;
697 if (apu_boost > 100)
698 apu_boost = 100;
699 }
700
701 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
702 dgpu_power_limit != 0) {
703 dgpu_boost = ((metrics_v4->AverageSocketPower -
704 dgpu_power_limit) * 100) /
705 dgpu_power_limit;
706 if (dgpu_boost > 100)
707 dgpu_boost = 100;
708 }
709
710 if (dgpu_boost >= apu_boost)
711 apu_boost = 0;
712 else
713 dgpu_boost = 0;
714 }
715 *apu_percent = apu_boost;
716 *dgpu_percent = dgpu_boost;
717 }
718
sienna_cichlid_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)719 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
720 MetricsMember_t member,
721 uint32_t *value)
722 {
723 struct smu_table_context *smu_table= &smu->smu_table;
724 SmuMetrics_t *metrics =
725 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
726 SmuMetrics_V2_t *metrics_v2 =
727 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
728 SmuMetrics_V3_t *metrics_v3 =
729 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
730 bool use_metrics_v2 = false;
731 bool use_metrics_v3 = false;
732 uint16_t average_gfx_activity;
733 int ret = 0;
734 uint32_t apu_percent = 0;
735 uint32_t dgpu_percent = 0;
736
737 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
738 case IP_VERSION(11, 0, 7):
739 if (smu->smc_fw_version >= 0x3A4900)
740 use_metrics_v3 = true;
741 else if (smu->smc_fw_version >= 0x3A4300)
742 use_metrics_v2 = true;
743 break;
744 case IP_VERSION(11, 0, 11):
745 if (smu->smc_fw_version >= 0x412D00)
746 use_metrics_v2 = true;
747 break;
748 case IP_VERSION(11, 0, 12):
749 if (smu->smc_fw_version >= 0x3B2300)
750 use_metrics_v2 = true;
751 break;
752 case IP_VERSION(11, 0, 13):
753 if (smu->smc_fw_version >= 0x491100)
754 use_metrics_v2 = true;
755 break;
756 default:
757 break;
758 }
759
760 ret = smu_cmn_get_metrics_table(smu,
761 NULL,
762 false);
763 if (ret)
764 return ret;
765
766 switch (member) {
767 case METRICS_CURR_GFXCLK:
768 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
769 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
770 metrics->CurrClock[PPCLK_GFXCLK];
771 break;
772 case METRICS_CURR_SOCCLK:
773 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
774 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
775 metrics->CurrClock[PPCLK_SOCCLK];
776 break;
777 case METRICS_CURR_UCLK:
778 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
779 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
780 metrics->CurrClock[PPCLK_UCLK];
781 break;
782 case METRICS_CURR_VCLK:
783 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
784 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
785 metrics->CurrClock[PPCLK_VCLK_0];
786 break;
787 case METRICS_CURR_VCLK1:
788 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
789 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
790 metrics->CurrClock[PPCLK_VCLK_1];
791 break;
792 case METRICS_CURR_DCLK:
793 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
794 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
795 metrics->CurrClock[PPCLK_DCLK_0];
796 break;
797 case METRICS_CURR_DCLK1:
798 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
799 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
800 metrics->CurrClock[PPCLK_DCLK_1];
801 break;
802 case METRICS_CURR_DCEFCLK:
803 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
804 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
805 metrics->CurrClock[PPCLK_DCEFCLK];
806 break;
807 case METRICS_CURR_FCLK:
808 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
809 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
810 metrics->CurrClock[PPCLK_FCLK];
811 break;
812 case METRICS_AVERAGE_GFXCLK:
813 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
814 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
815 metrics->AverageGfxActivity;
816 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
817 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
818 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
819 metrics->AverageGfxclkFrequencyPostDs;
820 else
821 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
822 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
823 metrics->AverageGfxclkFrequencyPreDs;
824 break;
825 case METRICS_AVERAGE_FCLK:
826 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
827 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
828 metrics->AverageFclkFrequencyPostDs;
829 break;
830 case METRICS_AVERAGE_UCLK:
831 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
832 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
833 metrics->AverageUclkFrequencyPostDs;
834 break;
835 case METRICS_AVERAGE_GFXACTIVITY:
836 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
837 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
838 metrics->AverageGfxActivity;
839 break;
840 case METRICS_AVERAGE_MEMACTIVITY:
841 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
842 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
843 metrics->AverageUclkActivity;
844 break;
845 case METRICS_AVERAGE_SOCKETPOWER:
846 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
847 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
848 metrics->AverageSocketPower << 8;
849 break;
850 case METRICS_TEMPERATURE_EDGE:
851 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
852 use_metrics_v2 ? metrics_v2->TemperatureEdge :
853 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
854 break;
855 case METRICS_TEMPERATURE_HOTSPOT:
856 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
857 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
858 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
859 break;
860 case METRICS_TEMPERATURE_MEM:
861 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
862 use_metrics_v2 ? metrics_v2->TemperatureMem :
863 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
864 break;
865 case METRICS_TEMPERATURE_VRGFX:
866 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
867 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
868 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
869 break;
870 case METRICS_TEMPERATURE_VRSOC:
871 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
872 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
873 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
874 break;
875 case METRICS_THROTTLER_STATUS:
876 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
877 break;
878 case METRICS_CURR_FANSPEED:
879 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
880 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
881 break;
882 case METRICS_UNIQUE_ID_UPPER32:
883 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
884 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
885 break;
886 case METRICS_UNIQUE_ID_LOWER32:
887 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
888 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
889 break;
890 case METRICS_SS_APU_SHARE:
891 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
892 *value = apu_percent;
893 break;
894 case METRICS_SS_DGPU_SHARE:
895 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
896 *value = dgpu_percent;
897 break;
898
899 default:
900 *value = UINT_MAX;
901 break;
902 }
903
904 return ret;
905
906 }
907
sienna_cichlid_allocate_dpm_context(struct smu_context * smu)908 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
909 {
910 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
911
912 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
913 GFP_KERNEL);
914 if (!smu_dpm->dpm_context)
915 return -ENOMEM;
916
917 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
918
919 return 0;
920 }
921
922 static void sienna_cichlid_stb_init(struct smu_context *smu);
923
sienna_cichlid_init_smc_tables(struct smu_context * smu)924 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
925 {
926 struct amdgpu_device *adev = smu->adev;
927 int ret = 0;
928
929 ret = sienna_cichlid_tables_init(smu);
930 if (ret)
931 return ret;
932
933 ret = sienna_cichlid_allocate_dpm_context(smu);
934 if (ret)
935 return ret;
936
937 if (!amdgpu_sriov_vf(adev))
938 sienna_cichlid_stb_init(smu);
939
940 return smu_v11_0_init_smc_tables(smu);
941 }
942
sienna_cichlid_set_default_dpm_table(struct smu_context * smu)943 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
944 {
945 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
946 struct smu_11_0_dpm_table *dpm_table;
947 struct amdgpu_device *adev = smu->adev;
948 int i, ret = 0;
949 DpmDescriptor_t *table_member;
950
951 /* socclk dpm table setup */
952 dpm_table = &dpm_context->dpm_tables.soc_table;
953 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
954 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
955 ret = smu_v11_0_set_single_dpm_table(smu,
956 SMU_SOCCLK,
957 dpm_table);
958 if (ret)
959 return ret;
960 dpm_table->is_fine_grained =
961 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
962 } else {
963 dpm_table->count = 1;
964 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
965 dpm_table->dpm_levels[0].enabled = true;
966 dpm_table->min = dpm_table->dpm_levels[0].value;
967 dpm_table->max = dpm_table->dpm_levels[0].value;
968 }
969
970 /* gfxclk dpm table setup */
971 dpm_table = &dpm_context->dpm_tables.gfx_table;
972 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
973 ret = smu_v11_0_set_single_dpm_table(smu,
974 SMU_GFXCLK,
975 dpm_table);
976 if (ret)
977 return ret;
978 dpm_table->is_fine_grained =
979 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
980 } else {
981 dpm_table->count = 1;
982 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
983 dpm_table->dpm_levels[0].enabled = true;
984 dpm_table->min = dpm_table->dpm_levels[0].value;
985 dpm_table->max = dpm_table->dpm_levels[0].value;
986 }
987
988 /* uclk dpm table setup */
989 dpm_table = &dpm_context->dpm_tables.uclk_table;
990 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
991 ret = smu_v11_0_set_single_dpm_table(smu,
992 SMU_UCLK,
993 dpm_table);
994 if (ret)
995 return ret;
996 dpm_table->is_fine_grained =
997 !table_member[PPCLK_UCLK].SnapToDiscrete;
998 } else {
999 dpm_table->count = 1;
1000 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1001 dpm_table->dpm_levels[0].enabled = true;
1002 dpm_table->min = dpm_table->dpm_levels[0].value;
1003 dpm_table->max = dpm_table->dpm_levels[0].value;
1004 }
1005
1006 /* fclk dpm table setup */
1007 dpm_table = &dpm_context->dpm_tables.fclk_table;
1008 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1009 ret = smu_v11_0_set_single_dpm_table(smu,
1010 SMU_FCLK,
1011 dpm_table);
1012 if (ret)
1013 return ret;
1014 dpm_table->is_fine_grained =
1015 !table_member[PPCLK_FCLK].SnapToDiscrete;
1016 } else {
1017 dpm_table->count = 1;
1018 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1019 dpm_table->dpm_levels[0].enabled = true;
1020 dpm_table->min = dpm_table->dpm_levels[0].value;
1021 dpm_table->max = dpm_table->dpm_levels[0].value;
1022 }
1023
1024 /* vclk0/1 dpm table setup */
1025 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1026 if (adev->vcn.harvest_config & (1 << i))
1027 continue;
1028
1029 dpm_table = &dpm_context->dpm_tables.vclk_table;
1030 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1031 ret = smu_v11_0_set_single_dpm_table(smu,
1032 i ? SMU_VCLK1 : SMU_VCLK,
1033 dpm_table);
1034 if (ret)
1035 return ret;
1036 dpm_table->is_fine_grained =
1037 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1038 } else {
1039 dpm_table->count = 1;
1040 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1041 dpm_table->dpm_levels[0].enabled = true;
1042 dpm_table->min = dpm_table->dpm_levels[0].value;
1043 dpm_table->max = dpm_table->dpm_levels[0].value;
1044 }
1045 }
1046
1047 /* dclk0/1 dpm table setup */
1048 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1049 if (adev->vcn.harvest_config & (1 << i))
1050 continue;
1051 dpm_table = &dpm_context->dpm_tables.dclk_table;
1052 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1053 ret = smu_v11_0_set_single_dpm_table(smu,
1054 i ? SMU_DCLK1 : SMU_DCLK,
1055 dpm_table);
1056 if (ret)
1057 return ret;
1058 dpm_table->is_fine_grained =
1059 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1060 } else {
1061 dpm_table->count = 1;
1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1063 dpm_table->dpm_levels[0].enabled = true;
1064 dpm_table->min = dpm_table->dpm_levels[0].value;
1065 dpm_table->max = dpm_table->dpm_levels[0].value;
1066 }
1067 }
1068
1069 /* dcefclk dpm table setup */
1070 dpm_table = &dpm_context->dpm_tables.dcef_table;
1071 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1072 ret = smu_v11_0_set_single_dpm_table(smu,
1073 SMU_DCEFCLK,
1074 dpm_table);
1075 if (ret)
1076 return ret;
1077 dpm_table->is_fine_grained =
1078 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1079 } else {
1080 dpm_table->count = 1;
1081 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1082 dpm_table->dpm_levels[0].enabled = true;
1083 dpm_table->min = dpm_table->dpm_levels[0].value;
1084 dpm_table->max = dpm_table->dpm_levels[0].value;
1085 }
1086
1087 /* pixelclk dpm table setup */
1088 dpm_table = &dpm_context->dpm_tables.pixel_table;
1089 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1090 ret = smu_v11_0_set_single_dpm_table(smu,
1091 SMU_PIXCLK,
1092 dpm_table);
1093 if (ret)
1094 return ret;
1095 dpm_table->is_fine_grained =
1096 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1097 } else {
1098 dpm_table->count = 1;
1099 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1100 dpm_table->dpm_levels[0].enabled = true;
1101 dpm_table->min = dpm_table->dpm_levels[0].value;
1102 dpm_table->max = dpm_table->dpm_levels[0].value;
1103 }
1104
1105 /* displayclk dpm table setup */
1106 dpm_table = &dpm_context->dpm_tables.display_table;
1107 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1108 ret = smu_v11_0_set_single_dpm_table(smu,
1109 SMU_DISPCLK,
1110 dpm_table);
1111 if (ret)
1112 return ret;
1113 dpm_table->is_fine_grained =
1114 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1115 } else {
1116 dpm_table->count = 1;
1117 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1118 dpm_table->dpm_levels[0].enabled = true;
1119 dpm_table->min = dpm_table->dpm_levels[0].value;
1120 dpm_table->max = dpm_table->dpm_levels[0].value;
1121 }
1122
1123 /* phyclk dpm table setup */
1124 dpm_table = &dpm_context->dpm_tables.phy_table;
1125 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1126 ret = smu_v11_0_set_single_dpm_table(smu,
1127 SMU_PHYCLK,
1128 dpm_table);
1129 if (ret)
1130 return ret;
1131 dpm_table->is_fine_grained =
1132 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1133 } else {
1134 dpm_table->count = 1;
1135 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1136 dpm_table->dpm_levels[0].enabled = true;
1137 dpm_table->min = dpm_table->dpm_levels[0].value;
1138 dpm_table->max = dpm_table->dpm_levels[0].value;
1139 }
1140
1141 return 0;
1142 }
1143
sienna_cichlid_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1144 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1145 {
1146 struct amdgpu_device *adev = smu->adev;
1147 int i, ret = 0;
1148
1149 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1150 if (adev->vcn.harvest_config & (1 << i))
1151 continue;
1152 /* vcn dpm on is a prerequisite for vcn power gate messages */
1153 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1154 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1155 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1156 0x10000 * i, NULL);
1157 if (ret)
1158 return ret;
1159 }
1160 }
1161
1162 return ret;
1163 }
1164
sienna_cichlid_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)1165 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1166 {
1167 int ret = 0;
1168
1169 if (enable) {
1170 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1171 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1172 if (ret)
1173 return ret;
1174 }
1175 } else {
1176 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1177 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1178 if (ret)
1179 return ret;
1180 }
1181 }
1182
1183 return ret;
1184 }
1185
sienna_cichlid_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1186 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1187 enum smu_clk_type clk_type,
1188 uint32_t *value)
1189 {
1190 MetricsMember_t member_type;
1191 int clk_id = 0;
1192
1193 clk_id = smu_cmn_to_asic_specific_index(smu,
1194 CMN2ASIC_MAPPING_CLK,
1195 clk_type);
1196 if (clk_id < 0)
1197 return clk_id;
1198
1199 switch (clk_id) {
1200 case PPCLK_GFXCLK:
1201 member_type = METRICS_CURR_GFXCLK;
1202 break;
1203 case PPCLK_UCLK:
1204 member_type = METRICS_CURR_UCLK;
1205 break;
1206 case PPCLK_SOCCLK:
1207 member_type = METRICS_CURR_SOCCLK;
1208 break;
1209 case PPCLK_FCLK:
1210 member_type = METRICS_CURR_FCLK;
1211 break;
1212 case PPCLK_VCLK_0:
1213 member_type = METRICS_CURR_VCLK;
1214 break;
1215 case PPCLK_VCLK_1:
1216 member_type = METRICS_CURR_VCLK1;
1217 break;
1218 case PPCLK_DCLK_0:
1219 member_type = METRICS_CURR_DCLK;
1220 break;
1221 case PPCLK_DCLK_1:
1222 member_type = METRICS_CURR_DCLK1;
1223 break;
1224 case PPCLK_DCEFCLK:
1225 member_type = METRICS_CURR_DCEFCLK;
1226 break;
1227 default:
1228 return -EINVAL;
1229 }
1230
1231 return sienna_cichlid_get_smu_metrics_data(smu,
1232 member_type,
1233 value);
1234
1235 }
1236
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1237 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1238 {
1239 DpmDescriptor_t *dpm_desc = NULL;
1240 DpmDescriptor_t *table_member;
1241 uint32_t clk_index = 0;
1242
1243 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1244 clk_index = smu_cmn_to_asic_specific_index(smu,
1245 CMN2ASIC_MAPPING_CLK,
1246 clk_type);
1247 dpm_desc = &table_member[clk_index];
1248
1249 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1250 return dpm_desc->SnapToDiscrete == 0;
1251 }
1252
sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODFEATURE_CAP cap)1253 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1254 enum SMU_11_0_7_ODFEATURE_CAP cap)
1255 {
1256 return od_table->cap[cap];
1257 }
1258
sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1259 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1260 enum SMU_11_0_7_ODSETTING_ID setting,
1261 uint32_t *min, uint32_t *max)
1262 {
1263 if (min)
1264 *min = od_table->min[setting];
1265 if (max)
1266 *max = od_table->max[setting];
1267 }
1268
sienna_cichlid_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1269 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1270 enum smu_clk_type clk_type, char *buf)
1271 {
1272 struct amdgpu_device *adev = smu->adev;
1273 struct smu_table_context *table_context = &smu->smu_table;
1274 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1275 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1276 uint16_t *table_member;
1277
1278 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1279 OverDriveTable_t *od_table =
1280 (OverDriveTable_t *)table_context->overdrive_table;
1281 int i, size = 0, ret = 0;
1282 uint32_t cur_value = 0, value = 0, count = 0;
1283 uint32_t freq_values[3] = {0};
1284 uint32_t mark_index = 0;
1285 uint32_t gen_speed, lane_width;
1286 uint32_t min_value, max_value;
1287
1288 smu_cmn_get_sysfs_buf(&buf, &size);
1289
1290 switch (clk_type) {
1291 case SMU_GFXCLK:
1292 case SMU_SCLK:
1293 case SMU_SOCCLK:
1294 case SMU_MCLK:
1295 case SMU_UCLK:
1296 case SMU_FCLK:
1297 case SMU_VCLK:
1298 case SMU_VCLK1:
1299 case SMU_DCLK:
1300 case SMU_DCLK1:
1301 case SMU_DCEFCLK:
1302 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1303 if (ret)
1304 goto print_clk_out;
1305
1306 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1307 if (ret)
1308 goto print_clk_out;
1309
1310 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1311 for (i = 0; i < count; i++) {
1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1313 if (ret)
1314 goto print_clk_out;
1315
1316 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1317 cur_value == value ? "*" : "");
1318 }
1319 } else {
1320 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1321 if (ret)
1322 goto print_clk_out;
1323 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1324 if (ret)
1325 goto print_clk_out;
1326
1327 freq_values[1] = cur_value;
1328 mark_index = cur_value == freq_values[0] ? 0 :
1329 cur_value == freq_values[2] ? 2 : 1;
1330
1331 count = 3;
1332 if (mark_index != 1) {
1333 count = 2;
1334 freq_values[1] = freq_values[2];
1335 }
1336
1337 for (i = 0; i < count; i++) {
1338 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1339 cur_value == freq_values[i] ? "*" : "");
1340 }
1341
1342 }
1343 break;
1344 case SMU_PCIE:
1345 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1346 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1347 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1348 for (i = 0; i < NUM_LINK_LEVELS; i++)
1349 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1350 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1351 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1352 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1353 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1354 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1355 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1356 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1357 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1358 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1359 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1360 table_member[i],
1361 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1362 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1363 "*" : "");
1364 break;
1365 case SMU_OD_SCLK:
1366 if (!smu->od_enabled || !od_table || !od_settings)
1367 break;
1368
1369 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1370 break;
1371
1372 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1373 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1374 break;
1375
1376 case SMU_OD_MCLK:
1377 if (!smu->od_enabled || !od_table || !od_settings)
1378 break;
1379
1380 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1381 break;
1382
1383 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1384 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1385 break;
1386
1387 case SMU_OD_VDDGFX_OFFSET:
1388 if (!smu->od_enabled || !od_table || !od_settings)
1389 break;
1390
1391 /*
1392 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1393 * and onwards SMU firmwares.
1394 */
1395 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1396 IP_VERSION(11, 0, 7)) &&
1397 (smu->smc_fw_version < 0x003a2900))
1398 break;
1399
1400 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1401 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1402 break;
1403
1404 case SMU_OD_RANGE:
1405 if (!smu->od_enabled || !od_table || !od_settings)
1406 break;
1407
1408 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1409
1410 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1411 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1412 &min_value, NULL);
1413 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1414 NULL, &max_value);
1415 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1416 min_value, max_value);
1417 }
1418
1419 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1420 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1421 &min_value, NULL);
1422 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1423 NULL, &max_value);
1424 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1425 min_value, max_value);
1426 }
1427 break;
1428
1429 default:
1430 break;
1431 }
1432
1433 print_clk_out:
1434 return size;
1435 }
1436
sienna_cichlid_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1437 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1438 enum smu_clk_type clk_type, uint32_t mask)
1439 {
1440 int ret = 0;
1441 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1442
1443 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1444 soft_max_level = mask ? (fls(mask) - 1) : 0;
1445
1446 switch (clk_type) {
1447 case SMU_GFXCLK:
1448 case SMU_SCLK:
1449 case SMU_SOCCLK:
1450 case SMU_MCLK:
1451 case SMU_UCLK:
1452 case SMU_FCLK:
1453 /* There is only 2 levels for fine grained DPM */
1454 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1455 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1456 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1457 }
1458
1459 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1460 if (ret)
1461 goto forec_level_out;
1462
1463 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1464 if (ret)
1465 goto forec_level_out;
1466
1467 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1468 if (ret)
1469 goto forec_level_out;
1470 break;
1471 case SMU_DCEFCLK:
1472 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1473 break;
1474 default:
1475 break;
1476 }
1477
1478 forec_level_out:
1479 return 0;
1480 }
1481
sienna_cichlid_populate_umd_state_clk(struct smu_context * smu)1482 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1483 {
1484 struct smu_11_0_dpm_context *dpm_context =
1485 smu->smu_dpm.dpm_context;
1486 struct smu_11_0_dpm_table *gfx_table =
1487 &dpm_context->dpm_tables.gfx_table;
1488 struct smu_11_0_dpm_table *mem_table =
1489 &dpm_context->dpm_tables.uclk_table;
1490 struct smu_11_0_dpm_table *soc_table =
1491 &dpm_context->dpm_tables.soc_table;
1492 struct smu_umd_pstate_table *pstate_table =
1493 &smu->pstate_table;
1494 struct amdgpu_device *adev = smu->adev;
1495
1496 pstate_table->gfxclk_pstate.min = gfx_table->min;
1497 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1498
1499 pstate_table->uclk_pstate.min = mem_table->min;
1500 pstate_table->uclk_pstate.peak = mem_table->max;
1501
1502 pstate_table->socclk_pstate.min = soc_table->min;
1503 pstate_table->socclk_pstate.peak = soc_table->max;
1504
1505 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1506 case IP_VERSION(11, 0, 7):
1507 case IP_VERSION(11, 0, 11):
1508 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1509 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1510 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1511 break;
1512 case IP_VERSION(11, 0, 12):
1513 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1514 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1515 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1516 break;
1517 case IP_VERSION(11, 0, 13):
1518 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1519 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1520 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1521 break;
1522 default:
1523 break;
1524 }
1525
1526 return 0;
1527 }
1528
sienna_cichlid_pre_display_config_changed(struct smu_context * smu)1529 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1530 {
1531 int ret = 0;
1532 uint32_t max_freq = 0;
1533
1534 /* Sienna_Cichlid do not support to change display num currently */
1535 return 0;
1536 #if 0
1537 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1538 if (ret)
1539 return ret;
1540 #endif
1541
1542 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1543 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1544 if (ret)
1545 return ret;
1546 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1547 if (ret)
1548 return ret;
1549 }
1550
1551 return ret;
1552 }
1553
sienna_cichlid_display_config_changed(struct smu_context * smu)1554 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1555 {
1556 int ret = 0;
1557
1558 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1559 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1560 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1561 #if 0
1562 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1563 smu->display_config->num_display,
1564 NULL);
1565 #endif
1566 if (ret)
1567 return ret;
1568 }
1569
1570 return ret;
1571 }
1572
sienna_cichlid_is_dpm_running(struct smu_context * smu)1573 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1574 {
1575 int ret = 0;
1576 uint64_t feature_enabled;
1577
1578 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1579 if (ret)
1580 return false;
1581
1582 return !!(feature_enabled & SMC_DPM_FEATURE);
1583 }
1584
sienna_cichlid_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1585 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1586 uint32_t *speed)
1587 {
1588 if (!speed)
1589 return -EINVAL;
1590
1591 /*
1592 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1593 * by pmfw is always trustable(even when the fan control feature
1594 * disabled or 0 RPM kicked in).
1595 */
1596 return sienna_cichlid_get_smu_metrics_data(smu,
1597 METRICS_CURR_FANSPEED,
1598 speed);
1599 }
1600
sienna_cichlid_get_fan_parameters(struct smu_context * smu)1601 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1602 {
1603 uint16_t *table_member;
1604
1605 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1606 smu->fan_max_rpm = *table_member;
1607
1608 return 0;
1609 }
1610
sienna_cichlid_get_power_profile_mode(struct smu_context * smu,char * buf)1611 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1612 {
1613 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1614 DpmActivityMonitorCoeffInt_t *activity_monitor =
1615 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1616 uint32_t i, size = 0;
1617 int16_t workload_type = 0;
1618 static const char *title[] = {
1619 "PROFILE_INDEX(NAME)",
1620 "CLOCK_TYPE(NAME)",
1621 "FPS",
1622 "MinFreqType",
1623 "MinActiveFreqType",
1624 "MinActiveFreq",
1625 "BoosterFreqType",
1626 "BoosterFreq",
1627 "PD_Data_limit_c",
1628 "PD_Data_error_coeff",
1629 "PD_Data_error_rate_coeff"};
1630 int result = 0;
1631
1632 if (!buf)
1633 return -EINVAL;
1634
1635 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1636 title[0], title[1], title[2], title[3], title[4], title[5],
1637 title[6], title[7], title[8], title[9], title[10]);
1638
1639 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1640 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1641 workload_type = smu_cmn_to_asic_specific_index(smu,
1642 CMN2ASIC_MAPPING_WORKLOAD,
1643 i);
1644 if (workload_type < 0)
1645 return -EINVAL;
1646
1647 result = smu_cmn_update_table(smu,
1648 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1649 (void *)(&activity_monitor_external), false);
1650 if (result) {
1651 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1652 return result;
1653 }
1654
1655 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1656 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1657
1658 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1659 " ",
1660 0,
1661 "GFXCLK",
1662 activity_monitor->Gfx_FPS,
1663 activity_monitor->Gfx_MinFreqStep,
1664 activity_monitor->Gfx_MinActiveFreqType,
1665 activity_monitor->Gfx_MinActiveFreq,
1666 activity_monitor->Gfx_BoosterFreqType,
1667 activity_monitor->Gfx_BoosterFreq,
1668 activity_monitor->Gfx_PD_Data_limit_c,
1669 activity_monitor->Gfx_PD_Data_error_coeff,
1670 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1671
1672 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1673 " ",
1674 1,
1675 "SOCCLK",
1676 activity_monitor->Fclk_FPS,
1677 activity_monitor->Fclk_MinFreqStep,
1678 activity_monitor->Fclk_MinActiveFreqType,
1679 activity_monitor->Fclk_MinActiveFreq,
1680 activity_monitor->Fclk_BoosterFreqType,
1681 activity_monitor->Fclk_BoosterFreq,
1682 activity_monitor->Fclk_PD_Data_limit_c,
1683 activity_monitor->Fclk_PD_Data_error_coeff,
1684 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1685
1686 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1687 " ",
1688 2,
1689 "MEMLK",
1690 activity_monitor->Mem_FPS,
1691 activity_monitor->Mem_MinFreqStep,
1692 activity_monitor->Mem_MinActiveFreqType,
1693 activity_monitor->Mem_MinActiveFreq,
1694 activity_monitor->Mem_BoosterFreqType,
1695 activity_monitor->Mem_BoosterFreq,
1696 activity_monitor->Mem_PD_Data_limit_c,
1697 activity_monitor->Mem_PD_Data_error_coeff,
1698 activity_monitor->Mem_PD_Data_error_rate_coeff);
1699 }
1700
1701 return size;
1702 }
1703
sienna_cichlid_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1704 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1705 {
1706
1707 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1708 DpmActivityMonitorCoeffInt_t *activity_monitor =
1709 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1710 int workload_type, ret = 0;
1711
1712 smu->power_profile_mode = input[size];
1713
1714 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1715 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1716 return -EINVAL;
1717 }
1718
1719 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1720
1721 ret = smu_cmn_update_table(smu,
1722 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1723 (void *)(&activity_monitor_external), false);
1724 if (ret) {
1725 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1726 return ret;
1727 }
1728
1729 switch (input[0]) {
1730 case 0: /* Gfxclk */
1731 activity_monitor->Gfx_FPS = input[1];
1732 activity_monitor->Gfx_MinFreqStep = input[2];
1733 activity_monitor->Gfx_MinActiveFreqType = input[3];
1734 activity_monitor->Gfx_MinActiveFreq = input[4];
1735 activity_monitor->Gfx_BoosterFreqType = input[5];
1736 activity_monitor->Gfx_BoosterFreq = input[6];
1737 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1738 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1739 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1740 break;
1741 case 1: /* Socclk */
1742 activity_monitor->Fclk_FPS = input[1];
1743 activity_monitor->Fclk_MinFreqStep = input[2];
1744 activity_monitor->Fclk_MinActiveFreqType = input[3];
1745 activity_monitor->Fclk_MinActiveFreq = input[4];
1746 activity_monitor->Fclk_BoosterFreqType = input[5];
1747 activity_monitor->Fclk_BoosterFreq = input[6];
1748 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1749 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1750 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1751 break;
1752 case 2: /* Memlk */
1753 activity_monitor->Mem_FPS = input[1];
1754 activity_monitor->Mem_MinFreqStep = input[2];
1755 activity_monitor->Mem_MinActiveFreqType = input[3];
1756 activity_monitor->Mem_MinActiveFreq = input[4];
1757 activity_monitor->Mem_BoosterFreqType = input[5];
1758 activity_monitor->Mem_BoosterFreq = input[6];
1759 activity_monitor->Mem_PD_Data_limit_c = input[7];
1760 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1761 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1762 break;
1763 }
1764
1765 ret = smu_cmn_update_table(smu,
1766 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1767 (void *)(&activity_monitor_external), true);
1768 if (ret) {
1769 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1770 return ret;
1771 }
1772 }
1773
1774 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1775 workload_type = smu_cmn_to_asic_specific_index(smu,
1776 CMN2ASIC_MAPPING_WORKLOAD,
1777 smu->power_profile_mode);
1778 if (workload_type < 0)
1779 return -EINVAL;
1780 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1781 1 << workload_type, NULL);
1782
1783 return ret;
1784 }
1785
sienna_cichlid_notify_smc_display_config(struct smu_context * smu)1786 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1787 {
1788 struct smu_clocks min_clocks = {0};
1789 struct pp_display_clock_request clock_req;
1790 int ret = 0;
1791
1792 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1793 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1794 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1795
1796 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1797 clock_req.clock_type = amd_pp_dcef_clock;
1798 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1799
1800 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1801 if (!ret) {
1802 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1803 ret = smu_cmn_send_smc_msg_with_param(smu,
1804 SMU_MSG_SetMinDeepSleepDcefclk,
1805 min_clocks.dcef_clock_in_sr/100,
1806 NULL);
1807 if (ret) {
1808 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1809 return ret;
1810 }
1811 }
1812 } else {
1813 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1814 }
1815 }
1816
1817 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1818 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1819 if (ret) {
1820 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1821 return ret;
1822 }
1823 }
1824
1825 return 0;
1826 }
1827
sienna_cichlid_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1828 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1829 struct pp_smu_wm_range_sets *clock_ranges)
1830 {
1831 Watermarks_t *table = smu->smu_table.watermarks_table;
1832 int ret = 0;
1833 int i;
1834
1835 if (clock_ranges) {
1836 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1837 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1838 return -EINVAL;
1839
1840 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1841 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1842 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1843 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1844 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1845 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1846 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1847 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1848 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1849
1850 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1851 clock_ranges->reader_wm_sets[i].wm_inst;
1852 }
1853
1854 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1855 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1856 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1857 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1858 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1859 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1860 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1861 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1862 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1863
1864 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1865 clock_ranges->writer_wm_sets[i].wm_inst;
1866 }
1867
1868 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1869 }
1870
1871 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1872 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1873 ret = smu_cmn_write_watermarks_table(smu);
1874 if (ret) {
1875 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1876 return ret;
1877 }
1878 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1879 }
1880
1881 return 0;
1882 }
1883
sienna_cichlid_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1884 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1885 enum amd_pp_sensors sensor,
1886 void *data, uint32_t *size)
1887 {
1888 int ret = 0;
1889 uint16_t *temp;
1890 struct amdgpu_device *adev = smu->adev;
1891
1892 if(!data || !size)
1893 return -EINVAL;
1894
1895 switch (sensor) {
1896 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1897 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1898 *(uint16_t *)data = *temp;
1899 *size = 4;
1900 break;
1901 case AMDGPU_PP_SENSOR_MEM_LOAD:
1902 ret = sienna_cichlid_get_smu_metrics_data(smu,
1903 METRICS_AVERAGE_MEMACTIVITY,
1904 (uint32_t *)data);
1905 *size = 4;
1906 break;
1907 case AMDGPU_PP_SENSOR_GPU_LOAD:
1908 ret = sienna_cichlid_get_smu_metrics_data(smu,
1909 METRICS_AVERAGE_GFXACTIVITY,
1910 (uint32_t *)data);
1911 *size = 4;
1912 break;
1913 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1914 ret = sienna_cichlid_get_smu_metrics_data(smu,
1915 METRICS_AVERAGE_SOCKETPOWER,
1916 (uint32_t *)data);
1917 *size = 4;
1918 break;
1919 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1920 ret = sienna_cichlid_get_smu_metrics_data(smu,
1921 METRICS_TEMPERATURE_HOTSPOT,
1922 (uint32_t *)data);
1923 *size = 4;
1924 break;
1925 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1926 ret = sienna_cichlid_get_smu_metrics_data(smu,
1927 METRICS_TEMPERATURE_EDGE,
1928 (uint32_t *)data);
1929 *size = 4;
1930 break;
1931 case AMDGPU_PP_SENSOR_MEM_TEMP:
1932 ret = sienna_cichlid_get_smu_metrics_data(smu,
1933 METRICS_TEMPERATURE_MEM,
1934 (uint32_t *)data);
1935 *size = 4;
1936 break;
1937 case AMDGPU_PP_SENSOR_GFX_MCLK:
1938 ret = sienna_cichlid_get_smu_metrics_data(smu,
1939 METRICS_CURR_UCLK,
1940 (uint32_t *)data);
1941 *(uint32_t *)data *= 100;
1942 *size = 4;
1943 break;
1944 case AMDGPU_PP_SENSOR_GFX_SCLK:
1945 ret = sienna_cichlid_get_smu_metrics_data(smu,
1946 METRICS_AVERAGE_GFXCLK,
1947 (uint32_t *)data);
1948 *(uint32_t *)data *= 100;
1949 *size = 4;
1950 break;
1951 case AMDGPU_PP_SENSOR_VDDGFX:
1952 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1953 *size = 4;
1954 break;
1955 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1956 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
1957 IP_VERSION(11, 0, 7)) {
1958 ret = sienna_cichlid_get_smu_metrics_data(smu,
1959 METRICS_SS_APU_SHARE, (uint32_t *)data);
1960 *size = 4;
1961 } else {
1962 ret = -EOPNOTSUPP;
1963 }
1964 break;
1965 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1966 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
1967 IP_VERSION(11, 0, 7)) {
1968 ret = sienna_cichlid_get_smu_metrics_data(smu,
1969 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1970 *size = 4;
1971 } else {
1972 ret = -EOPNOTSUPP;
1973 }
1974 break;
1975 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1976 default:
1977 ret = -EOPNOTSUPP;
1978 break;
1979 }
1980
1981 return ret;
1982 }
1983
sienna_cichlid_get_unique_id(struct smu_context * smu)1984 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1985 {
1986 struct amdgpu_device *adev = smu->adev;
1987 uint32_t upper32 = 0, lower32 = 0;
1988
1989 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1990 if (smu->smc_fw_version < 0x3A5300 ||
1991 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
1992 return;
1993
1994 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1995 goto out;
1996 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1997 goto out;
1998
1999 out:
2000
2001 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2002 }
2003
sienna_cichlid_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)2004 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2005 {
2006 uint32_t num_discrete_levels = 0;
2007 uint16_t *dpm_levels = NULL;
2008 uint16_t i = 0;
2009 struct smu_table_context *table_context = &smu->smu_table;
2010 DpmDescriptor_t *table_member1;
2011 uint16_t *table_member2;
2012
2013 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2014 return -EINVAL;
2015
2016 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2017 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2018 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2019 dpm_levels = table_member2;
2020
2021 if (num_discrete_levels == 0 || dpm_levels == NULL)
2022 return -EINVAL;
2023
2024 *num_states = num_discrete_levels;
2025 for (i = 0; i < num_discrete_levels; i++) {
2026 /* convert to khz */
2027 *clocks_in_khz = (*dpm_levels) * 1000;
2028 clocks_in_khz++;
2029 dpm_levels++;
2030 }
2031
2032 return 0;
2033 }
2034
sienna_cichlid_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2035 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2036 struct smu_temperature_range *range)
2037 {
2038 struct smu_table_context *table_context = &smu->smu_table;
2039 struct smu_11_0_7_powerplay_table *powerplay_table =
2040 table_context->power_play_table;
2041 uint16_t *table_member;
2042 uint16_t temp_edge, temp_hotspot, temp_mem;
2043
2044 if (!range)
2045 return -EINVAL;
2046
2047 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2048
2049 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2050 temp_edge = table_member[TEMP_EDGE];
2051 temp_hotspot = table_member[TEMP_HOTSPOT];
2052 temp_mem = table_member[TEMP_MEM];
2053
2054 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2055 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2056 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2057 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2058 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2060 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2061 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2062 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2063
2064 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2065
2066 return 0;
2067 }
2068
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)2069 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2070 bool disable_memory_clock_switch)
2071 {
2072 int ret = 0;
2073 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2074 (struct smu_11_0_max_sustainable_clocks *)
2075 smu->smu_table.max_sustainable_clocks;
2076 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2077 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2078
2079 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2080 return 0;
2081
2082 if(disable_memory_clock_switch)
2083 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2084 else
2085 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2086
2087 if(!ret)
2088 smu->disable_uclk_switch = disable_memory_clock_switch;
2089
2090 return ret;
2091 }
2092
sienna_cichlid_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2093 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2094 uint8_t pcie_gen_cap,
2095 uint8_t pcie_width_cap)
2096 {
2097 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2098 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2099 uint8_t *table_member1, *table_member2;
2100 uint8_t min_gen_speed, max_gen_speed;
2101 uint8_t min_lane_width, max_lane_width;
2102 uint32_t smu_pcie_arg;
2103 int ret, i;
2104
2105 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2106 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2107
2108 min_gen_speed = max_t(uint8_t, 0, table_member1[0]);
2109 max_gen_speed = min(pcie_gen_cap, table_member1[1]);
2110 min_gen_speed = min_gen_speed > max_gen_speed ?
2111 max_gen_speed : min_gen_speed;
2112 min_lane_width = max_t(uint8_t, 1, table_member2[0]);
2113 max_lane_width = min(pcie_width_cap, table_member2[1]);
2114 min_lane_width = min_lane_width > max_lane_width ?
2115 max_lane_width : min_lane_width;
2116
2117 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2118 pcie_table->pcie_gen[0] = max_gen_speed;
2119 pcie_table->pcie_lane[0] = max_lane_width;
2120 } else {
2121 pcie_table->pcie_gen[0] = min_gen_speed;
2122 pcie_table->pcie_lane[0] = min_lane_width;
2123 }
2124 pcie_table->pcie_gen[1] = max_gen_speed;
2125 pcie_table->pcie_lane[1] = max_lane_width;
2126
2127 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2128 smu_pcie_arg = (i << 16 |
2129 pcie_table->pcie_gen[i] << 8 |
2130 pcie_table->pcie_lane[i]);
2131
2132 ret = smu_cmn_send_smc_msg_with_param(smu,
2133 SMU_MSG_OverridePcieParameters,
2134 smu_pcie_arg,
2135 NULL);
2136 if (ret)
2137 return ret;
2138 }
2139
2140 return 0;
2141 }
2142
sienna_cichlid_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)2143 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2144 enum smu_clk_type clk_type,
2145 uint32_t *min, uint32_t *max)
2146 {
2147 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2148 }
2149
sienna_cichlid_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)2150 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2151 OverDriveTable_t *od_table)
2152 {
2153 struct amdgpu_device *adev = smu->adev;
2154
2155 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2156 od_table->GfxclkFmax);
2157 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2158 od_table->UclkFmax);
2159
2160 if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
2161 (smu->smc_fw_version < 0x003a2900)))
2162 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2163 }
2164
sienna_cichlid_set_default_od_settings(struct smu_context * smu)2165 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2166 {
2167 OverDriveTable_t *od_table =
2168 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2169 OverDriveTable_t *boot_od_table =
2170 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2171 OverDriveTable_t *user_od_table =
2172 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2173 OverDriveTable_t user_od_table_bak;
2174 int ret = 0;
2175
2176 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2177 0, (void *)boot_od_table, false);
2178 if (ret) {
2179 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2180 return ret;
2181 }
2182
2183 sienna_cichlid_dump_od_table(smu, boot_od_table);
2184
2185 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2186
2187 /*
2188 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2189 * but we have to preserve user defined values in "user_od_table".
2190 */
2191 if (!smu->adev->in_suspend) {
2192 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2193 smu->user_dpm_profile.user_od = false;
2194 } else if (smu->user_dpm_profile.user_od) {
2195 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2196 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2197 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2198 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2199 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2200 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2201 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2202 }
2203
2204 return 0;
2205 }
2206
sienna_cichlid_od_setting_check_range(struct smu_context * smu,struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t value)2207 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2208 struct smu_11_0_7_overdrive_table *od_table,
2209 enum SMU_11_0_7_ODSETTING_ID setting,
2210 uint32_t value)
2211 {
2212 if (value < od_table->min[setting]) {
2213 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2214 setting, value, od_table->min[setting]);
2215 return -EINVAL;
2216 }
2217 if (value > od_table->max[setting]) {
2218 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2219 setting, value, od_table->max[setting]);
2220 return -EINVAL;
2221 }
2222
2223 return 0;
2224 }
2225
sienna_cichlid_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2226 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2227 enum PP_OD_DPM_TABLE_COMMAND type,
2228 long input[], uint32_t size)
2229 {
2230 struct smu_table_context *table_context = &smu->smu_table;
2231 OverDriveTable_t *od_table =
2232 (OverDriveTable_t *)table_context->overdrive_table;
2233 struct smu_11_0_7_overdrive_table *od_settings =
2234 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2235 struct amdgpu_device *adev = smu->adev;
2236 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2237 uint16_t *freq_ptr;
2238 int i, ret = 0;
2239
2240 if (!smu->od_enabled) {
2241 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2242 return -EINVAL;
2243 }
2244
2245 if (!smu->od_settings) {
2246 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2247 return -ENOENT;
2248 }
2249
2250 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2251 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2252 return -EINVAL;
2253 }
2254
2255 switch (type) {
2256 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2257 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2258 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2259 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2260 return -ENOTSUPP;
2261 }
2262
2263 for (i = 0; i < size; i += 2) {
2264 if (i + 2 > size) {
2265 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2266 return -EINVAL;
2267 }
2268
2269 switch (input[i]) {
2270 case 0:
2271 if (input[i + 1] > od_table->GfxclkFmax) {
2272 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2273 input[i + 1], od_table->GfxclkFmax);
2274 return -EINVAL;
2275 }
2276
2277 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2278 freq_ptr = &od_table->GfxclkFmin;
2279 break;
2280
2281 case 1:
2282 if (input[i + 1] < od_table->GfxclkFmin) {
2283 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2284 input[i + 1], od_table->GfxclkFmin);
2285 return -EINVAL;
2286 }
2287
2288 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2289 freq_ptr = &od_table->GfxclkFmax;
2290 break;
2291
2292 default:
2293 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2294 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2295 return -EINVAL;
2296 }
2297
2298 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2299 freq_setting, input[i + 1]);
2300 if (ret)
2301 return ret;
2302
2303 *freq_ptr = (uint16_t)input[i + 1];
2304 }
2305 break;
2306
2307 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2308 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2309 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2310 return -ENOTSUPP;
2311 }
2312
2313 for (i = 0; i < size; i += 2) {
2314 if (i + 2 > size) {
2315 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2316 return -EINVAL;
2317 }
2318
2319 switch (input[i]) {
2320 case 0:
2321 if (input[i + 1] > od_table->UclkFmax) {
2322 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2323 input[i + 1], od_table->UclkFmax);
2324 return -EINVAL;
2325 }
2326
2327 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2328 freq_ptr = &od_table->UclkFmin;
2329 break;
2330
2331 case 1:
2332 if (input[i + 1] < od_table->UclkFmin) {
2333 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2334 input[i + 1], od_table->UclkFmin);
2335 return -EINVAL;
2336 }
2337
2338 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2339 freq_ptr = &od_table->UclkFmax;
2340 break;
2341
2342 default:
2343 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2344 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2345 return -EINVAL;
2346 }
2347
2348 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2349 freq_setting, input[i + 1]);
2350 if (ret)
2351 return ret;
2352
2353 *freq_ptr = (uint16_t)input[i + 1];
2354 }
2355 break;
2356
2357 case PP_OD_RESTORE_DEFAULT_TABLE:
2358 memcpy(table_context->overdrive_table,
2359 table_context->boot_overdrive_table,
2360 sizeof(OverDriveTable_t));
2361 fallthrough;
2362
2363 case PP_OD_COMMIT_DPM_TABLE:
2364 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2365 sienna_cichlid_dump_od_table(smu, od_table);
2366 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2367 if (ret) {
2368 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2369 return ret;
2370 }
2371 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2372 smu->user_dpm_profile.user_od = true;
2373
2374 if (!memcmp(table_context->user_overdrive_table,
2375 table_context->boot_overdrive_table,
2376 sizeof(OverDriveTable_t)))
2377 smu->user_dpm_profile.user_od = false;
2378 }
2379 break;
2380
2381 case PP_OD_EDIT_VDDGFX_OFFSET:
2382 if (size != 1) {
2383 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2384 return -EINVAL;
2385 }
2386
2387 /*
2388 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2389 * and onwards SMU firmwares.
2390 */
2391 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2392 IP_VERSION(11, 0, 7)) &&
2393 (smu->smc_fw_version < 0x003a2900)) {
2394 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2395 "only by 58.41.0 and onwards SMU firmwares!\n");
2396 return -EOPNOTSUPP;
2397 }
2398
2399 od_table->VddGfxOffset = (int16_t)input[0];
2400
2401 sienna_cichlid_dump_od_table(smu, od_table);
2402 break;
2403
2404 default:
2405 return -ENOSYS;
2406 }
2407
2408 return ret;
2409 }
2410
sienna_cichlid_restore_user_od_settings(struct smu_context * smu)2411 static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2412 {
2413 struct smu_table_context *table_context = &smu->smu_table;
2414 OverDriveTable_t *od_table = table_context->overdrive_table;
2415 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2416 int res;
2417
2418 res = smu_v11_0_restore_user_od_settings(smu);
2419 if (res == 0)
2420 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2421
2422 return res;
2423 }
2424
sienna_cichlid_run_btc(struct smu_context * smu)2425 static int sienna_cichlid_run_btc(struct smu_context *smu)
2426 {
2427 int res;
2428
2429 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2430 if (res)
2431 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2432
2433 return res;
2434 }
2435
sienna_cichlid_baco_enter(struct smu_context * smu)2436 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2437 {
2438 struct amdgpu_device *adev = smu->adev;
2439
2440 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2441 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2442 else
2443 return smu_v11_0_baco_enter(smu);
2444 }
2445
sienna_cichlid_baco_exit(struct smu_context * smu)2446 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2447 {
2448 struct amdgpu_device *adev = smu->adev;
2449
2450 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2451 /* Wait for PMFW handling for the Dstate change */
2452 msleep(10);
2453 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2454 } else {
2455 return smu_v11_0_baco_exit(smu);
2456 }
2457 }
2458
sienna_cichlid_is_mode1_reset_supported(struct smu_context * smu)2459 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2460 {
2461 struct amdgpu_device *adev = smu->adev;
2462 uint32_t val;
2463 uint32_t smu_version;
2464 int ret;
2465
2466 /**
2467 * SRIOV env will not support SMU mode1 reset
2468 * PM FW support mode1 reset from 58.26
2469 */
2470 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2471 if (ret)
2472 return false;
2473
2474 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2475 return false;
2476
2477 /**
2478 * mode1 reset relies on PSP, so we should check if
2479 * PSP is alive.
2480 */
2481 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2482 return val != 0x0;
2483 }
2484
beige_goby_dump_pptable(struct smu_context * smu)2485 static void beige_goby_dump_pptable(struct smu_context *smu)
2486 {
2487 struct smu_table_context *table_context = &smu->smu_table;
2488 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2489 int i;
2490
2491 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2492
2493 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2494 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2495 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2496
2497 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2498 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2499 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2500 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2501 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2502 }
2503
2504 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2505 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2506 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2507 }
2508
2509 for (i = 0; i < TEMP_COUNT; i++) {
2510 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2511 }
2512
2513 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2514 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2515 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2516 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2517 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2518
2519 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2520 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2521 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2522 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2523 }
2524 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2525
2526 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2527
2528 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2529 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2530 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2531 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2532
2533 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2534
2535 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2536
2537 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2538 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2539 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2540 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2541
2542 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2543 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2544
2545 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2546 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2547 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2548 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2549 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2550 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2551 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2552 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2553
2554 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2555 " .VoltageMode = 0x%02x\n"
2556 " .SnapToDiscrete = 0x%02x\n"
2557 " .NumDiscreteLevels = 0x%02x\n"
2558 " .padding = 0x%02x\n"
2559 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2560 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2561 " .SsFmin = 0x%04x\n"
2562 " .Padding_16 = 0x%04x\n",
2563 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2564 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2565 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2566 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2567 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2568 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2569 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2570 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2571 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2572 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2573 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2574
2575 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2576 " .VoltageMode = 0x%02x\n"
2577 " .SnapToDiscrete = 0x%02x\n"
2578 " .NumDiscreteLevels = 0x%02x\n"
2579 " .padding = 0x%02x\n"
2580 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2581 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2582 " .SsFmin = 0x%04x\n"
2583 " .Padding_16 = 0x%04x\n",
2584 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2585 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2586 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2587 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2588 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2589 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2590 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2591 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2592 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2593 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2594 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2595
2596 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2597 " .VoltageMode = 0x%02x\n"
2598 " .SnapToDiscrete = 0x%02x\n"
2599 " .NumDiscreteLevels = 0x%02x\n"
2600 " .padding = 0x%02x\n"
2601 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2602 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2603 " .SsFmin = 0x%04x\n"
2604 " .Padding_16 = 0x%04x\n",
2605 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2606 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2607 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2608 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2609 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2610 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2611 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2612 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2613 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2614 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2615 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2616
2617 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2618 " .VoltageMode = 0x%02x\n"
2619 " .SnapToDiscrete = 0x%02x\n"
2620 " .NumDiscreteLevels = 0x%02x\n"
2621 " .padding = 0x%02x\n"
2622 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2623 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2624 " .SsFmin = 0x%04x\n"
2625 " .Padding_16 = 0x%04x\n",
2626 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2627 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2628 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2629 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2630 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2631 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2632 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2633 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2634 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2635 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2636 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2637
2638 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2639 " .VoltageMode = 0x%02x\n"
2640 " .SnapToDiscrete = 0x%02x\n"
2641 " .NumDiscreteLevels = 0x%02x\n"
2642 " .padding = 0x%02x\n"
2643 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2644 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2645 " .SsFmin = 0x%04x\n"
2646 " .Padding_16 = 0x%04x\n",
2647 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2648 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2649 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2650 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2651 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2652 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2653 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2654 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2655 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2656 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2657 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2658
2659 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2660 " .VoltageMode = 0x%02x\n"
2661 " .SnapToDiscrete = 0x%02x\n"
2662 " .NumDiscreteLevels = 0x%02x\n"
2663 " .padding = 0x%02x\n"
2664 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2665 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2666 " .SsFmin = 0x%04x\n"
2667 " .Padding_16 = 0x%04x\n",
2668 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2669 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2670 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2671 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2672 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2673 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2674 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2675 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2676 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2677 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2678 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2679
2680 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2681 " .VoltageMode = 0x%02x\n"
2682 " .SnapToDiscrete = 0x%02x\n"
2683 " .NumDiscreteLevels = 0x%02x\n"
2684 " .padding = 0x%02x\n"
2685 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2686 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2687 " .SsFmin = 0x%04x\n"
2688 " .Padding_16 = 0x%04x\n",
2689 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2690 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2691 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2692 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2693 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2694 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2695 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2696 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2697 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2698 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2699 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2700
2701 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2702 " .VoltageMode = 0x%02x\n"
2703 " .SnapToDiscrete = 0x%02x\n"
2704 " .NumDiscreteLevels = 0x%02x\n"
2705 " .padding = 0x%02x\n"
2706 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2707 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2708 " .SsFmin = 0x%04x\n"
2709 " .Padding_16 = 0x%04x\n",
2710 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2711 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2712 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2713 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2714 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2715 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2716 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2717 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2718 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2719 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2720 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2721
2722 dev_info(smu->adev->dev, "FreqTableGfx\n");
2723 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2724 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2725
2726 dev_info(smu->adev->dev, "FreqTableVclk\n");
2727 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2728 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2729
2730 dev_info(smu->adev->dev, "FreqTableDclk\n");
2731 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2732 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2733
2734 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2735 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2736 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2737
2738 dev_info(smu->adev->dev, "FreqTableUclk\n");
2739 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2740 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2741
2742 dev_info(smu->adev->dev, "FreqTableFclk\n");
2743 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2744 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2745
2746 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2747 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2748 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2749 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2750 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2751 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2752 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2753 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2754 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2755
2756 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2757 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2758 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2759
2760 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2761 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2762
2763 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2764 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2765 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2766
2767 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2768 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2769 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2770
2771 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2772 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2773 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2774
2775 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2776 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2777 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2778
2779 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2780 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2781 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2782 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2783 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2784
2785 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2786
2787 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2788 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2789 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2790 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2791 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2792 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2793 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2794 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2795 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2796 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2797 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2798
2799 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2800 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2801 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2802 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2803 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2804 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2805
2806 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2807 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2808 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2809 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2810 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2811
2812 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2813 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2814 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2815
2816 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2817 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2818 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2819 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2820
2821 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2822 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2823 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2824
2825 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2826 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2827 pptable->UclkDpmSrcFreqRange.Fmin);
2828 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2829 pptable->UclkDpmSrcFreqRange.Fmax);
2830 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2831 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2832 pptable->UclkDpmTargFreqRange.Fmin);
2833 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2834 pptable->UclkDpmTargFreqRange.Fmax);
2835 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2836 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2837
2838 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2839 for (i = 0; i < NUM_LINK_LEVELS; i++)
2840 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2841
2842 dev_info(smu->adev->dev, "PcieLaneCount\n");
2843 for (i = 0; i < NUM_LINK_LEVELS; i++)
2844 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2845
2846 dev_info(smu->adev->dev, "LclkFreq\n");
2847 for (i = 0; i < NUM_LINK_LEVELS; i++)
2848 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2849
2850 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2851 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2852
2853 dev_info(smu->adev->dev, "FanGain\n");
2854 for (i = 0; i < TEMP_COUNT; i++)
2855 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2856
2857 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2858 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2859 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2860 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2861 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2862 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2863 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2864 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2865 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2866 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2867 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2868 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2869
2870 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2871 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2872 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2873 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2874
2875 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2876 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2877 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2878 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2879
2880 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2881 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2882 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2883 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2884 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2885 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2886 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2887 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2888 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2889 pptable->dBtcGbGfxPll.a,
2890 pptable->dBtcGbGfxPll.b,
2891 pptable->dBtcGbGfxPll.c);
2892 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2893 pptable->dBtcGbGfxDfll.a,
2894 pptable->dBtcGbGfxDfll.b,
2895 pptable->dBtcGbGfxDfll.c);
2896 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2897 pptable->dBtcGbSoc.a,
2898 pptable->dBtcGbSoc.b,
2899 pptable->dBtcGbSoc.c);
2900 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2901 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2902 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2903 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2904 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2905 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2906
2907 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2908 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2909 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2910 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2911 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2912 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2913 }
2914
2915 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2916 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2917 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2918 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2919 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2920 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2921 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2922 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2923
2924 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2925 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2926
2927 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2928 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2929 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2930 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2931
2932 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2933 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2934 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2935 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2936
2937 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2938 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2939
2940 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2941 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2942 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2943 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2944 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2945
2946 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2947 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2948 pptable->ReservedEquation0.a,
2949 pptable->ReservedEquation0.b,
2950 pptable->ReservedEquation0.c);
2951 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2952 pptable->ReservedEquation1.a,
2953 pptable->ReservedEquation1.b,
2954 pptable->ReservedEquation1.c);
2955 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2956 pptable->ReservedEquation2.a,
2957 pptable->ReservedEquation2.b,
2958 pptable->ReservedEquation2.c);
2959 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2960 pptable->ReservedEquation3.a,
2961 pptable->ReservedEquation3.b,
2962 pptable->ReservedEquation3.c);
2963
2964 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2965 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2966 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2967 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2968 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2969 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2970 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2971 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2972
2973 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2974 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2975 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2976 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2977 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2978 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2979
2980 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2981 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2982 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2983 pptable->I2cControllers[i].Enabled);
2984 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2985 pptable->I2cControllers[i].Speed);
2986 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2987 pptable->I2cControllers[i].SlaveAddress);
2988 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2989 pptable->I2cControllers[i].ControllerPort);
2990 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2991 pptable->I2cControllers[i].ControllerName);
2992 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2993 pptable->I2cControllers[i].ThermalThrotter);
2994 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2995 pptable->I2cControllers[i].I2cProtocol);
2996 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2997 pptable->I2cControllers[i].PaddingConfig);
2998 }
2999
3000 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3001 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3002 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3003 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3004
3005 dev_info(smu->adev->dev, "Board Parameters:\n");
3006 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3007 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3008 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3009 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3010 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3011 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3012 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3013 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3014
3015 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3016 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3017 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3018
3019 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3020 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3021 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3022
3023 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3024 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3025 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3026
3027 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3028 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3029 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3030
3031 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3032
3033 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3034 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3035 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3036 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3037 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3038 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3039 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3040 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3041 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3042 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3043 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3044 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3045 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3046 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3047 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3048 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3049
3050 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3051 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3052 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3053
3054 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3055 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3056 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3057
3058 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3059 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3060
3061 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3062 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3063 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3064
3065 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3066 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3067 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3068 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3069 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3070
3071 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3072 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3073
3074 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3075 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3076 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3077 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3078 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3079 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3080 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3081 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3082 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3083 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3084 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3085 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3086
3087 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3088 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3089 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3090 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3091
3092 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3093 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3094 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3095 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3096 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3097 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3098 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3099 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3100 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3101 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3102 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3103
3104 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3105 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3106 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3107 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3108 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3109 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3110 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3111 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3112 }
3113
sienna_cichlid_dump_pptable(struct smu_context * smu)3114 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3115 {
3116 struct smu_table_context *table_context = &smu->smu_table;
3117 PPTable_t *pptable = table_context->driver_pptable;
3118 int i;
3119
3120 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3121 IP_VERSION(11, 0, 13)) {
3122 beige_goby_dump_pptable(smu);
3123 return;
3124 }
3125
3126 dev_info(smu->adev->dev, "Dumped PPTable:\n");
3127
3128 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3129 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3130 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3131
3132 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3133 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3134 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3135 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3136 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3137 }
3138
3139 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3140 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3141 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3142 }
3143
3144 for (i = 0; i < TEMP_COUNT; i++) {
3145 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3146 }
3147
3148 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3149 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3150 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3151 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3152 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3153
3154 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3155 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3156 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3157 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3158 }
3159 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3160
3161 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3162
3163 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3164 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3165 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3166 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3167
3168 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3169 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3170
3171 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3172 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3173 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3174 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3175
3176 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3177 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3178 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3179 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3180
3181 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3182 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3183
3184 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3185 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3186 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3187 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3188 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3189 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3190 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3191 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3192
3193 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3194 " .VoltageMode = 0x%02x\n"
3195 " .SnapToDiscrete = 0x%02x\n"
3196 " .NumDiscreteLevels = 0x%02x\n"
3197 " .padding = 0x%02x\n"
3198 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3199 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3200 " .SsFmin = 0x%04x\n"
3201 " .Padding_16 = 0x%04x\n",
3202 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3203 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3204 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3205 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3206 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3207 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3208 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3209 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3210 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3211 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3212 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3213
3214 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3215 " .VoltageMode = 0x%02x\n"
3216 " .SnapToDiscrete = 0x%02x\n"
3217 " .NumDiscreteLevels = 0x%02x\n"
3218 " .padding = 0x%02x\n"
3219 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3220 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3221 " .SsFmin = 0x%04x\n"
3222 " .Padding_16 = 0x%04x\n",
3223 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3224 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3225 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3226 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3227 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3228 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3229 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3230 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3231 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3232 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3233 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3234
3235 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3236 " .VoltageMode = 0x%02x\n"
3237 " .SnapToDiscrete = 0x%02x\n"
3238 " .NumDiscreteLevels = 0x%02x\n"
3239 " .padding = 0x%02x\n"
3240 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3241 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3242 " .SsFmin = 0x%04x\n"
3243 " .Padding_16 = 0x%04x\n",
3244 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3245 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3246 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3247 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3248 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3249 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3250 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3251 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3252 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3253 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3254 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3255
3256 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3257 " .VoltageMode = 0x%02x\n"
3258 " .SnapToDiscrete = 0x%02x\n"
3259 " .NumDiscreteLevels = 0x%02x\n"
3260 " .padding = 0x%02x\n"
3261 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3262 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3263 " .SsFmin = 0x%04x\n"
3264 " .Padding_16 = 0x%04x\n",
3265 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3266 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3267 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3268 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3269 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3270 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3271 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3272 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3273 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3274 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3275 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3276
3277 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3278 " .VoltageMode = 0x%02x\n"
3279 " .SnapToDiscrete = 0x%02x\n"
3280 " .NumDiscreteLevels = 0x%02x\n"
3281 " .padding = 0x%02x\n"
3282 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3283 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3284 " .SsFmin = 0x%04x\n"
3285 " .Padding_16 = 0x%04x\n",
3286 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3287 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3288 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3289 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3290 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3291 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3292 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3293 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3294 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3295 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3296 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3297
3298 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3299 " .VoltageMode = 0x%02x\n"
3300 " .SnapToDiscrete = 0x%02x\n"
3301 " .NumDiscreteLevels = 0x%02x\n"
3302 " .padding = 0x%02x\n"
3303 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3304 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3305 " .SsFmin = 0x%04x\n"
3306 " .Padding_16 = 0x%04x\n",
3307 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3308 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3309 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3310 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3311 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3312 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3313 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3314 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3315 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3316 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3317 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3318
3319 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3320 " .VoltageMode = 0x%02x\n"
3321 " .SnapToDiscrete = 0x%02x\n"
3322 " .NumDiscreteLevels = 0x%02x\n"
3323 " .padding = 0x%02x\n"
3324 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3325 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3326 " .SsFmin = 0x%04x\n"
3327 " .Padding_16 = 0x%04x\n",
3328 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3329 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3330 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3331 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3332 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3333 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3334 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3335 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3336 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3337 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3338 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3339
3340 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3341 " .VoltageMode = 0x%02x\n"
3342 " .SnapToDiscrete = 0x%02x\n"
3343 " .NumDiscreteLevels = 0x%02x\n"
3344 " .padding = 0x%02x\n"
3345 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3346 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3347 " .SsFmin = 0x%04x\n"
3348 " .Padding_16 = 0x%04x\n",
3349 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3350 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3351 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3352 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3353 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3354 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3355 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3356 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3357 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3358 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3359 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3360
3361 dev_info(smu->adev->dev, "FreqTableGfx\n");
3362 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3363 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3364
3365 dev_info(smu->adev->dev, "FreqTableVclk\n");
3366 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3367 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3368
3369 dev_info(smu->adev->dev, "FreqTableDclk\n");
3370 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3371 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3372
3373 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3374 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3375 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3376
3377 dev_info(smu->adev->dev, "FreqTableUclk\n");
3378 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3379 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3380
3381 dev_info(smu->adev->dev, "FreqTableFclk\n");
3382 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3383 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3384
3385 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3386 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3387 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3388 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3389 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3390 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3391 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3392 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3393 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3394
3395 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3396 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3397 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3398
3399 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3400 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3401
3402 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3403 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3404 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3405
3406 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3407 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3408 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3409
3410 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3411 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3412 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3413
3414 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3415 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3416 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3417
3418 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3419 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3420 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3421 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3422 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3423
3424 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3425
3426 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3427 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3428 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3429 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3430 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3431 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3432 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3433 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3434 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3435 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3436 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3437
3438 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3439 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3440 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3441 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3442 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3443 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3444
3445 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3446 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3447 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3448 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3449 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3450
3451 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3452 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3453 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3454
3455 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3456 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3457 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3458 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3459
3460 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3461 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3462 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3463
3464 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3465 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3466 pptable->UclkDpmSrcFreqRange.Fmin);
3467 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3468 pptable->UclkDpmSrcFreqRange.Fmax);
3469 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3470 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3471 pptable->UclkDpmTargFreqRange.Fmin);
3472 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3473 pptable->UclkDpmTargFreqRange.Fmax);
3474 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3475 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3476
3477 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3478 for (i = 0; i < NUM_LINK_LEVELS; i++)
3479 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3480
3481 dev_info(smu->adev->dev, "PcieLaneCount\n");
3482 for (i = 0; i < NUM_LINK_LEVELS; i++)
3483 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3484
3485 dev_info(smu->adev->dev, "LclkFreq\n");
3486 for (i = 0; i < NUM_LINK_LEVELS; i++)
3487 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3488
3489 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3490 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3491
3492 dev_info(smu->adev->dev, "FanGain\n");
3493 for (i = 0; i < TEMP_COUNT; i++)
3494 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3495
3496 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3497 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3498 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3499 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3500 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3501 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3502 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3503 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3504 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3505 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3506 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3507 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3508
3509 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3510 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3511 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3512 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3513
3514 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3515 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3516 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3517 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3518
3519 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3520 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3521 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3522 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3523 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3524 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3525 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3526 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3527 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3528 pptable->dBtcGbGfxPll.a,
3529 pptable->dBtcGbGfxPll.b,
3530 pptable->dBtcGbGfxPll.c);
3531 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3532 pptable->dBtcGbGfxDfll.a,
3533 pptable->dBtcGbGfxDfll.b,
3534 pptable->dBtcGbGfxDfll.c);
3535 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3536 pptable->dBtcGbSoc.a,
3537 pptable->dBtcGbSoc.b,
3538 pptable->dBtcGbSoc.c);
3539 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3540 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3541 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3542 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3543 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3544 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3545
3546 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3547 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3548 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3549 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3550 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3551 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3552 }
3553
3554 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3555 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3556 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3557 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3558 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3559 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3560 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3561 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3562
3563 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3564 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3565
3566 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3567 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3568 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3569 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3570
3571 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3572 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3573 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3574 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3575
3576 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3577 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3578
3579 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3580 for (i = 0; i < NUM_XGMI_LEVELS; i++)
3581 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3582 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3583 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3584
3585 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3586 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3587 pptable->ReservedEquation0.a,
3588 pptable->ReservedEquation0.b,
3589 pptable->ReservedEquation0.c);
3590 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3591 pptable->ReservedEquation1.a,
3592 pptable->ReservedEquation1.b,
3593 pptable->ReservedEquation1.c);
3594 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3595 pptable->ReservedEquation2.a,
3596 pptable->ReservedEquation2.b,
3597 pptable->ReservedEquation2.c);
3598 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3599 pptable->ReservedEquation3.a,
3600 pptable->ReservedEquation3.b,
3601 pptable->ReservedEquation3.c);
3602
3603 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3604 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3605 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3606 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3607 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3608 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3609 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3610 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3611
3612 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3613 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3614 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3615 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3616 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3617 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3618
3619 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3620 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3621 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3622 pptable->I2cControllers[i].Enabled);
3623 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3624 pptable->I2cControllers[i].Speed);
3625 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3626 pptable->I2cControllers[i].SlaveAddress);
3627 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3628 pptable->I2cControllers[i].ControllerPort);
3629 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3630 pptable->I2cControllers[i].ControllerName);
3631 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3632 pptable->I2cControllers[i].ThermalThrotter);
3633 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3634 pptable->I2cControllers[i].I2cProtocol);
3635 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3636 pptable->I2cControllers[i].PaddingConfig);
3637 }
3638
3639 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3640 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3641 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3642 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3643
3644 dev_info(smu->adev->dev, "Board Parameters:\n");
3645 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3646 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3647 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3648 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3649 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3650 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3651 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3652 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3653
3654 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3655 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3656 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3657
3658 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3659 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3660 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3661
3662 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3663 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3664 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3665
3666 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3667 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3668 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3669
3670 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3671
3672 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3673 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3674 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3675 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3676 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3677 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3678 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3679 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3680 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3681 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3682 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3683 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3684 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3685 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3686 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3687 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3688
3689 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3690 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3691 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3692
3693 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3694 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3695 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3696
3697 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3698 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3699
3700 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3701 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3702 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3703
3704 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3705 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3706 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3707 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3708 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3709
3710 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3711 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3712
3713 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3714 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3715 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3716 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3717 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3718 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3719 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3720 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3721 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3722 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3723 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3724 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3725
3726 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3727 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3728 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3729 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3730
3731 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3732 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3733 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3734 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3735 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3736 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3737 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3738 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3739 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3740 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3741 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3742
3743 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3744 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3745 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3746 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3747 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3748 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3749 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3750 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3751 }
3752
sienna_cichlid_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)3753 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3754 struct i2c_msg *msg, int num_msgs)
3755 {
3756 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3757 struct amdgpu_device *adev = smu_i2c->adev;
3758 struct smu_context *smu = adev->powerplay.pp_handle;
3759 struct smu_table_context *smu_table = &smu->smu_table;
3760 struct smu_table *table = &smu_table->driver_table;
3761 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3762 int i, j, r, c;
3763 u16 dir;
3764
3765 if (!adev->pm.dpm_enabled)
3766 return -EBUSY;
3767
3768 req = kzalloc(sizeof(*req), GFP_KERNEL);
3769 if (!req)
3770 return -ENOMEM;
3771
3772 req->I2CcontrollerPort = smu_i2c->port;
3773 req->I2CSpeed = I2C_SPEED_FAST_400K;
3774 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3775 dir = msg[0].flags & I2C_M_RD;
3776
3777 for (c = i = 0; i < num_msgs; i++) {
3778 for (j = 0; j < msg[i].len; j++, c++) {
3779 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3780
3781 if (!(msg[i].flags & I2C_M_RD)) {
3782 /* write */
3783 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3784 cmd->ReadWriteData = msg[i].buf[j];
3785 }
3786
3787 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3788 /* The direction changes.
3789 */
3790 dir = msg[i].flags & I2C_M_RD;
3791 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3792 }
3793
3794 req->NumCmds++;
3795
3796 /*
3797 * Insert STOP if we are at the last byte of either last
3798 * message for the transaction or the client explicitly
3799 * requires a STOP at this particular message.
3800 */
3801 if ((j == msg[i].len - 1) &&
3802 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3803 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3804 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3805 }
3806 }
3807 }
3808 mutex_lock(&adev->pm.mutex);
3809 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3810 if (r)
3811 goto fail;
3812
3813 for (c = i = 0; i < num_msgs; i++) {
3814 if (!(msg[i].flags & I2C_M_RD)) {
3815 c += msg[i].len;
3816 continue;
3817 }
3818 for (j = 0; j < msg[i].len; j++, c++) {
3819 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3820
3821 msg[i].buf[j] = cmd->ReadWriteData;
3822 }
3823 }
3824 r = num_msgs;
3825 fail:
3826 mutex_unlock(&adev->pm.mutex);
3827 kfree(req);
3828 return r;
3829 }
3830
sienna_cichlid_i2c_func(struct i2c_adapter * adap)3831 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3832 {
3833 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3834 }
3835
3836
3837 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3838 .master_xfer = sienna_cichlid_i2c_xfer,
3839 .functionality = sienna_cichlid_i2c_func,
3840 };
3841
3842 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3843 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3844 .max_read_len = MAX_SW_I2C_COMMANDS,
3845 .max_write_len = MAX_SW_I2C_COMMANDS,
3846 .max_comb_1st_msg_len = 2,
3847 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3848 };
3849
sienna_cichlid_i2c_control_init(struct smu_context * smu)3850 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3851 {
3852 struct amdgpu_device *adev = smu->adev;
3853 int res, i;
3854
3855 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3856 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3857 struct i2c_adapter *control = &smu_i2c->adapter;
3858
3859 smu_i2c->adev = adev;
3860 smu_i2c->port = i;
3861 mutex_init(&smu_i2c->mutex);
3862 control->owner = THIS_MODULE;
3863 control->class = I2C_CLASS_HWMON;
3864 control->dev.parent = &adev->pdev->dev;
3865 control->algo = &sienna_cichlid_i2c_algo;
3866 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3867 control->quirks = &sienna_cichlid_i2c_control_quirks;
3868 i2c_set_adapdata(control, smu_i2c);
3869
3870 res = i2c_add_adapter(control);
3871 if (res) {
3872 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3873 goto Out_err;
3874 }
3875 }
3876 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3877 /* XXX ideally this would be something in a vbios data table */
3878 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3879 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3880
3881 return 0;
3882 Out_err:
3883 for ( ; i >= 0; i--) {
3884 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3885 struct i2c_adapter *control = &smu_i2c->adapter;
3886
3887 i2c_del_adapter(control);
3888 }
3889 return res;
3890 }
3891
sienna_cichlid_i2c_control_fini(struct smu_context * smu)3892 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3893 {
3894 struct amdgpu_device *adev = smu->adev;
3895 int i;
3896
3897 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3898 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3899 struct i2c_adapter *control = &smu_i2c->adapter;
3900
3901 i2c_del_adapter(control);
3902 }
3903 adev->pm.ras_eeprom_i2c_bus = NULL;
3904 adev->pm.fru_eeprom_i2c_bus = NULL;
3905 }
3906
sienna_cichlid_get_gpu_metrics(struct smu_context * smu,void ** table)3907 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3908 void **table)
3909 {
3910 struct smu_table_context *smu_table = &smu->smu_table;
3911 struct gpu_metrics_v1_3 *gpu_metrics =
3912 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3913 SmuMetricsExternal_t metrics_external;
3914 SmuMetrics_t *metrics =
3915 &(metrics_external.SmuMetrics);
3916 SmuMetrics_V2_t *metrics_v2 =
3917 &(metrics_external.SmuMetrics_V2);
3918 SmuMetrics_V3_t *metrics_v3 =
3919 &(metrics_external.SmuMetrics_V3);
3920 struct amdgpu_device *adev = smu->adev;
3921 bool use_metrics_v2 = false;
3922 bool use_metrics_v3 = false;
3923 uint16_t average_gfx_activity;
3924 int ret = 0;
3925
3926 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
3927 case IP_VERSION(11, 0, 7):
3928 if (smu->smc_fw_version >= 0x3A4900)
3929 use_metrics_v3 = true;
3930 else if (smu->smc_fw_version >= 0x3A4300)
3931 use_metrics_v2 = true;
3932 break;
3933 case IP_VERSION(11, 0, 11):
3934 if (smu->smc_fw_version >= 0x412D00)
3935 use_metrics_v2 = true;
3936 break;
3937 case IP_VERSION(11, 0, 12):
3938 if (smu->smc_fw_version >= 0x3B2300)
3939 use_metrics_v2 = true;
3940 break;
3941 case IP_VERSION(11, 0, 13):
3942 if (smu->smc_fw_version >= 0x491100)
3943 use_metrics_v2 = true;
3944 break;
3945 default:
3946 break;
3947 }
3948
3949 ret = smu_cmn_get_metrics_table(smu,
3950 &metrics_external,
3951 true);
3952 if (ret)
3953 return ret;
3954
3955 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3956
3957 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3958 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3959 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3960 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3961 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3962 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3963 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3964 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3965 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3966 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3967 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3968 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3969
3970 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3971 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3972 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3973 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3974 gpu_metrics->average_mm_activity = use_metrics_v3 ?
3975 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3976 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3977
3978 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3979 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3980 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3981 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3982
3983 if (metrics->CurrGfxVoltageOffset)
3984 gpu_metrics->voltage_gfx =
3985 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3986 if (metrics->CurrMemVidOffset)
3987 gpu_metrics->voltage_mem =
3988 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3989 if (metrics->CurrSocVoltageOffset)
3990 gpu_metrics->voltage_soc =
3991 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3992
3993 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3994 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3995 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3996 gpu_metrics->average_gfxclk_frequency =
3997 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3998 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3999 metrics->AverageGfxclkFrequencyPostDs;
4000 else
4001 gpu_metrics->average_gfxclk_frequency =
4002 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
4003 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
4004 metrics->AverageGfxclkFrequencyPreDs;
4005
4006 gpu_metrics->average_uclk_frequency =
4007 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
4008 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
4009 metrics->AverageUclkFrequencyPostDs;
4010 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
4011 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
4012 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
4013 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
4014 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
4015 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
4016 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
4017 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4018
4019 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
4020 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
4021 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
4022 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
4023 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
4024 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
4025 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
4026 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
4027 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
4028 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
4029 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
4030 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
4031 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
4032 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4033
4034 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
4035 gpu_metrics->indep_throttle_status =
4036 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
4037 sienna_cichlid_throttler_map);
4038
4039 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4040 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
4041
4042 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
4043 smu->smc_fw_version > 0x003A1E00) ||
4044 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) &&
4045 smu->smc_fw_version > 0x00410400)) {
4046 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4047 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4048 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4049 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
4050 } else {
4051 gpu_metrics->pcie_link_width =
4052 smu_v11_0_get_current_pcie_link_width(smu);
4053 gpu_metrics->pcie_link_speed =
4054 smu_v11_0_get_current_pcie_link_speed(smu);
4055 }
4056
4057 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4058
4059 *table = (void *)gpu_metrics;
4060
4061 return sizeof(struct gpu_metrics_v1_3);
4062 }
4063
sienna_cichlid_check_ecc_table_support(struct smu_context * smu)4064 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4065 {
4066 int ret = 0;
4067
4068 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
4069 ret = -EOPNOTSUPP;
4070
4071 return ret;
4072 }
4073
sienna_cichlid_get_ecc_info(struct smu_context * smu,void * table)4074 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4075 void *table)
4076 {
4077 struct smu_table_context *smu_table = &smu->smu_table;
4078 EccInfoTable_t *ecc_table = NULL;
4079 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4080 int i, ret = 0;
4081 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4082
4083 ret = sienna_cichlid_check_ecc_table_support(smu);
4084 if (ret)
4085 return ret;
4086
4087 ret = smu_cmn_update_table(smu,
4088 SMU_TABLE_ECCINFO,
4089 0,
4090 smu_table->ecc_table,
4091 false);
4092 if (ret) {
4093 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4094 return ret;
4095 }
4096
4097 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4098
4099 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4100 ecc_info_per_channel = &(eccinfo->ecc[i]);
4101 ecc_info_per_channel->ce_count_lo_chip =
4102 ecc_table->EccInfo[i].ce_count_lo_chip;
4103 ecc_info_per_channel->ce_count_hi_chip =
4104 ecc_table->EccInfo[i].ce_count_hi_chip;
4105 ecc_info_per_channel->mca_umc_status =
4106 ecc_table->EccInfo[i].mca_umc_status;
4107 ecc_info_per_channel->mca_umc_addr =
4108 ecc_table->EccInfo[i].mca_umc_addr;
4109 }
4110
4111 return ret;
4112 }
sienna_cichlid_enable_mgpu_fan_boost(struct smu_context * smu)4113 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4114 {
4115 uint16_t *mgpu_fan_boost_limit_rpm;
4116
4117 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4118 /*
4119 * Skip the MGpuFanBoost setting for those ASICs
4120 * which do not support it
4121 */
4122 if (*mgpu_fan_boost_limit_rpm == 0)
4123 return 0;
4124
4125 return smu_cmn_send_smc_msg_with_param(smu,
4126 SMU_MSG_SetMGpuFanBoostLimitRpm,
4127 0,
4128 NULL);
4129 }
4130
sienna_cichlid_gpo_control(struct smu_context * smu,bool enablement)4131 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4132 bool enablement)
4133 {
4134 int ret = 0;
4135
4136
4137 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4138
4139 if (enablement) {
4140 if (smu->smc_fw_version < 0x003a2500) {
4141 ret = smu_cmn_send_smc_msg_with_param(smu,
4142 SMU_MSG_SetGpoFeaturePMask,
4143 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4144 NULL);
4145 } else {
4146 ret = smu_cmn_send_smc_msg_with_param(smu,
4147 SMU_MSG_DisallowGpo,
4148 0,
4149 NULL);
4150 }
4151 } else {
4152 if (smu->smc_fw_version < 0x003a2500) {
4153 ret = smu_cmn_send_smc_msg_with_param(smu,
4154 SMU_MSG_SetGpoFeaturePMask,
4155 0,
4156 NULL);
4157 } else {
4158 ret = smu_cmn_send_smc_msg_with_param(smu,
4159 SMU_MSG_DisallowGpo,
4160 1,
4161 NULL);
4162 }
4163 }
4164 }
4165
4166 return ret;
4167 }
4168
sienna_cichlid_notify_2nd_usb20_port(struct smu_context * smu)4169 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4170 {
4171 /*
4172 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4173 * onwards PMFWs.
4174 */
4175 if (smu->smc_fw_version < 0x003A2D00)
4176 return 0;
4177
4178 return smu_cmn_send_smc_msg_with_param(smu,
4179 SMU_MSG_Enable2ndUSB20Port,
4180 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4181 1 : 0,
4182 NULL);
4183 }
4184
sienna_cichlid_system_features_control(struct smu_context * smu,bool en)4185 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4186 bool en)
4187 {
4188 int ret = 0;
4189
4190 if (en) {
4191 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4192 if (ret)
4193 return ret;
4194 }
4195
4196 return smu_v11_0_system_features_control(smu, en);
4197 }
4198
sienna_cichlid_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)4199 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4200 enum pp_mp1_state mp1_state)
4201 {
4202 int ret;
4203
4204 switch (mp1_state) {
4205 case PP_MP1_STATE_UNLOAD:
4206 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4207 break;
4208 default:
4209 /* Ignore others */
4210 ret = 0;
4211 }
4212
4213 return ret;
4214 }
4215
sienna_cichlid_stb_init(struct smu_context * smu)4216 static void sienna_cichlid_stb_init(struct smu_context *smu)
4217 {
4218 struct amdgpu_device *adev = smu->adev;
4219 uint32_t reg;
4220
4221 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4222 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4223
4224 /* STB is disabled */
4225 if (!smu->stb_context.enabled)
4226 return;
4227
4228 spin_lock_init(&smu->stb_context.lock);
4229
4230 /* STB buffer size in bytes as function of FIFO depth */
4231 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4232 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4233 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4234
4235 dev_info(smu->adev->dev, "STB initialized to %d entries",
4236 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4237
4238 }
4239
sienna_cichlid_get_default_config_table_settings(struct smu_context * smu,struct config_table_setting * table)4240 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4241 struct config_table_setting *table)
4242 {
4243 struct amdgpu_device *adev = smu->adev;
4244
4245 if (!table)
4246 return -EINVAL;
4247
4248 table->gfxclk_average_tau = 10;
4249 table->socclk_average_tau = 10;
4250 table->fclk_average_tau = 10;
4251 table->uclk_average_tau = 10;
4252 table->gfx_activity_average_tau = 10;
4253 table->mem_activity_average_tau = 10;
4254 table->socket_power_average_tau = 100;
4255 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
4256 table->apu_socket_power_average_tau = 100;
4257
4258 return 0;
4259 }
4260
sienna_cichlid_set_config_table(struct smu_context * smu,struct config_table_setting * table)4261 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4262 struct config_table_setting *table)
4263 {
4264 DriverSmuConfigExternal_t driver_smu_config_table;
4265
4266 if (!table)
4267 return -EINVAL;
4268
4269 memset(&driver_smu_config_table,
4270 0,
4271 sizeof(driver_smu_config_table));
4272 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4273 table->gfxclk_average_tau;
4274 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4275 table->fclk_average_tau;
4276 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4277 table->uclk_average_tau;
4278 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4279 table->gfx_activity_average_tau;
4280 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4281 table->mem_activity_average_tau;
4282 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4283 table->socket_power_average_tau;
4284
4285 return smu_cmn_update_table(smu,
4286 SMU_TABLE_DRIVER_SMU_CONFIG,
4287 0,
4288 (void *)&driver_smu_config_table,
4289 true);
4290 }
4291
sienna_cichlid_stb_get_data_direct(struct smu_context * smu,void * buf,uint32_t size)4292 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4293 void *buf,
4294 uint32_t size)
4295 {
4296 uint32_t *p = buf;
4297 struct amdgpu_device *adev = smu->adev;
4298
4299 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4300 spin_lock(&smu->stb_context.lock);
4301
4302 /*
4303 * Read the STB FIFO in units of 32bit since this is the accessor window
4304 * (register width) we have.
4305 */
4306 buf = ((char *) buf) + size;
4307 while ((void *)p < buf)
4308 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4309
4310 spin_unlock(&smu->stb_context.lock);
4311
4312 return 0;
4313 }
4314
sienna_cichlid_is_mode2_reset_supported(struct smu_context * smu)4315 static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4316 {
4317 return true;
4318 }
4319
sienna_cichlid_mode2_reset(struct smu_context * smu)4320 static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4321 {
4322 int ret = 0, index;
4323 struct amdgpu_device *adev = smu->adev;
4324 int timeout = 100;
4325
4326 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4327 SMU_MSG_DriverMode2Reset);
4328
4329 mutex_lock(&smu->message_lock);
4330
4331 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4332 SMU_RESET_MODE_2);
4333
4334 ret = smu_cmn_wait_for_response(smu);
4335 while (ret != 0 && timeout) {
4336 ret = smu_cmn_wait_for_response(smu);
4337 /* Wait a bit more time for getting ACK */
4338 if (ret != 0) {
4339 --timeout;
4340 usleep_range(500, 1000);
4341 continue;
4342 } else {
4343 break;
4344 }
4345 }
4346
4347 if (!timeout) {
4348 dev_err(adev->dev,
4349 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4350 SMU_RESET_MODE_2, ret);
4351 goto out;
4352 }
4353
4354 dev_info(smu->adev->dev, "restore config space...\n");
4355 /* Restore the config space saved during init */
4356 amdgpu_device_load_pci_state(adev->pdev);
4357 out:
4358 mutex_unlock(&smu->message_lock);
4359
4360 return ret;
4361 }
4362
4363 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4364 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4365 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4366 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4367 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4368 .i2c_init = sienna_cichlid_i2c_control_init,
4369 .i2c_fini = sienna_cichlid_i2c_control_fini,
4370 .print_clk_levels = sienna_cichlid_print_clk_levels,
4371 .force_clk_levels = sienna_cichlid_force_clk_levels,
4372 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4373 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4374 .display_config_changed = sienna_cichlid_display_config_changed,
4375 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4376 .is_dpm_running = sienna_cichlid_is_dpm_running,
4377 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4378 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4379 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4380 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4381 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4382 .read_sensor = sienna_cichlid_read_sensor,
4383 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4384 .set_performance_level = smu_v11_0_set_performance_level,
4385 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4386 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4387 .get_power_limit = sienna_cichlid_get_power_limit,
4388 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4389 .dump_pptable = sienna_cichlid_dump_pptable,
4390 .init_microcode = smu_v11_0_init_microcode,
4391 .load_microcode = smu_v11_0_load_microcode,
4392 .fini_microcode = smu_v11_0_fini_microcode,
4393 .init_smc_tables = sienna_cichlid_init_smc_tables,
4394 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4395 .init_power = smu_v11_0_init_power,
4396 .fini_power = smu_v11_0_fini_power,
4397 .check_fw_status = smu_v11_0_check_fw_status,
4398 .setup_pptable = sienna_cichlid_setup_pptable,
4399 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4400 .check_fw_version = smu_v11_0_check_fw_version,
4401 .write_pptable = smu_cmn_write_pptable,
4402 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4403 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4404 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4405 .system_features_control = sienna_cichlid_system_features_control,
4406 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4407 .send_smc_msg = smu_cmn_send_smc_msg,
4408 .init_display_count = NULL,
4409 .set_allowed_mask = smu_v11_0_set_allowed_mask,
4410 .get_enabled_mask = smu_cmn_get_enabled_mask,
4411 .feature_is_enabled = smu_cmn_feature_is_enabled,
4412 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4413 .notify_display_change = NULL,
4414 .set_power_limit = smu_v11_0_set_power_limit,
4415 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4416 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4417 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4418 .set_min_dcef_deep_sleep = NULL,
4419 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4420 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4421 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4422 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4423 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4424 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4425 .gfx_off_control = smu_v11_0_gfx_off_control,
4426 .register_irq_handler = smu_v11_0_register_irq_handler,
4427 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4428 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4429 .baco_is_support = smu_v11_0_baco_is_support,
4430 .baco_enter = sienna_cichlid_baco_enter,
4431 .baco_exit = sienna_cichlid_baco_exit,
4432 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4433 .mode1_reset = smu_v11_0_mode1_reset,
4434 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4435 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4436 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4437 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4438 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4439 .run_btc = sienna_cichlid_run_btc,
4440 .set_power_source = smu_v11_0_set_power_source,
4441 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4442 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4443 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4444 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4445 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4446 .deep_sleep_control = smu_v11_0_deep_sleep_control,
4447 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4448 .interrupt_work = smu_v11_0_interrupt_work,
4449 .gpo_control = sienna_cichlid_gpo_control,
4450 .set_mp1_state = sienna_cichlid_set_mp1_state,
4451 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4452 .get_ecc_info = sienna_cichlid_get_ecc_info,
4453 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4454 .set_config_table = sienna_cichlid_set_config_table,
4455 .get_unique_id = sienna_cichlid_get_unique_id,
4456 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4457 .mode2_reset = sienna_cichlid_mode2_reset,
4458 };
4459
sienna_cichlid_set_ppt_funcs(struct smu_context * smu)4460 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4461 {
4462 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4463 smu->message_map = sienna_cichlid_message_map;
4464 smu->clock_map = sienna_cichlid_clk_map;
4465 smu->feature_map = sienna_cichlid_feature_mask_map;
4466 smu->table_map = sienna_cichlid_table_map;
4467 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4468 smu->workload_map = sienna_cichlid_workload_map;
4469 smu_v11_0_set_smu_mailbox_registers(smu);
4470 }
4471