1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 */
6
7 #ifndef _SH_CSS_INTERNAL_H_
8 #define _SH_CSS_INTERNAL_H_
9
10 #include <linux/build_bug.h>
11 #include <linux/stdarg.h>
12
13 #include <system_global.h>
14 #include <math_support.h>
15 #include <type_support.h>
16 #include <platform_support.h>
17
18 #include "input_formatter.h"
19 #include "input_system.h"
20
21 #include "ia_css_types.h"
22 #include "ia_css_acc_types.h"
23 #include "ia_css_buffer.h"
24
25 #include "ia_css_binary.h"
26 #include "sh_css_firmware.h" /* not needed/desired on SP/ISP */
27 #include "sh_css_legacy.h"
28 #include "sh_css_defs.h"
29 #include "sh_css_uds.h"
30 #include "dma.h" /* N_DMA_CHANNEL_ID */
31 #include "ia_css_circbuf_comm.h" /* Circular buffer */
32 #include "ia_css_frame_comm.h"
33 #include "ia_css_3a.h"
34 #include "ia_css_dvs.h"
35 #include "ia_css_metadata.h"
36 #include "runtime/bufq/interface/ia_css_bufq.h"
37 #include "ia_css_timer.h"
38
39 /* TODO: Move to a more suitable place when sp pipeline design is done. */
40 #define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2
41 #define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1
42 #define IA_CSS_NUM_CBS 2
43 #define IA_CSS_CB_MAX_ELEMS 2
44
45 /* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or
46 * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively.
47 * TODO: Enforce the limitation above.
48 */
49 #define IA_CSS_COPYSINK_SEM_INDEX 0
50 #define IA_CSS_TAGGER_SEM_INDEX 1
51
52 /* Force generation of output event. Used by acceleration pipe. */
53 #define IA_CSS_POST_OUT_EVENT_FORCE 2
54
55 #define SH_CSS_MAX_BINARY_NAME 64
56
57 #define SP_DEBUG_NONE (0)
58 #define SP_DEBUG_DUMP (1)
59 #define SP_DEBUG_COPY (2)
60 #define SP_DEBUG_TRACE (3)
61 #define SP_DEBUG_MINIMAL (4)
62
63 #define SP_DEBUG SP_DEBUG_NONE
64 #define SP_DEBUG_MINIMAL_OVERWRITE 1
65
66 #define SH_CSS_TNR_BIT_DEPTH 8
67 #define SH_CSS_REF_BIT_DEPTH 8
68
69 /* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */
70 #define NUM_CONTINUOUS_FRAMES 15
71 #define NUM_MIPI_FRAMES_PER_STREAM 2
72
73 #define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2
74
75 #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */
76
77 #define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/
78 #define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF
79
80 #define SH_CSS_MAX_SP_THREADS 5
81
82 /**
83 * The C99 standard does not specify the exact object representation of structs;
84 * the representation is compiler dependent.
85 *
86 * The structs that are communicated between host and SP/ISP should have the
87 * exact same object representation. The compiler that is used to compile the
88 * firmware is hivecc.
89 *
90 * To check if a different compiler, used to compile a host application, uses
91 * another object representation, macros are defined specifying the size of
92 * the structs as expected by the firmware.
93 *
94 * A host application shall verify that a sizeof( ) of the struct is equal to
95 * the SIZE_OF_XXX macro of the corresponding struct. If they are not
96 * equal, functionality will break.
97 */
98 #define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x)
99 #define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32)
100
101 /* Number of SP's */
102 #define NUM_OF_SPS 1
103
104 #define NUM_OF_BLS 0
105
106 /* Enum for order of Binaries */
107 enum sh_css_order_binaries {
108 SP_FIRMWARE = 0,
109 ISP_FIRMWARE
110 };
111
112 /*
113 * JB: keep next enum in sync with thread id's
114 * and pipe id's
115 */
116 enum sh_css_pipe_config_override {
117 SH_CSS_PIPE_CONFIG_OVRD_NONE = 0,
118 SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff
119 };
120
121 enum host2sp_commands {
122 host2sp_cmd_error = 0,
123 /*
124 * The host2sp_cmd_ready command is the only command written by the SP
125 * It acknowledges that is previous command has been received.
126 * (this does not mean that the command has been executed)
127 * It also indicates that a new command can be send (it is a queue
128 * with depth 1).
129 */
130 host2sp_cmd_ready = 1,
131 /* Command written by the Host */
132 host2sp_cmd_dummy, /* No action, can be used as watchdog */
133 host2sp_cmd_start_flash, /* Request SP to start the flash */
134 host2sp_cmd_terminate, /* SP should terminate itself */
135 N_host2sp_cmd
136 };
137
138 /* Enumeration used to indicate the events that are produced by
139 * the SP and consumed by the Host.
140 *
141 * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC:
142 * 1) "enum ia_css_event_type" (ia_css_event_public.h)
143 * 2) "enum sh_css_sp_event_type" (sh_css_internal.h)
144 * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c)
145 * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c)
146 */
147 enum sh_css_sp_event_type {
148 SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE,
149 SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE,
150 SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE,
151 SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE,
152 SH_CSS_SP_EVENT_3A_STATISTICS_DONE,
153 SH_CSS_SP_EVENT_DIS_STATISTICS_DONE,
154 SH_CSS_SP_EVENT_PIPELINE_DONE,
155 SH_CSS_SP_EVENT_FRAME_TAGGED,
156 SH_CSS_SP_EVENT_INPUT_FRAME_DONE,
157 SH_CSS_SP_EVENT_METADATA_DONE,
158 SH_CSS_SP_EVENT_LACE_STATISTICS_DONE,
159 SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE,
160 SH_CSS_SP_EVENT_TIMER,
161 SH_CSS_SP_EVENT_PORT_EOF,
162 SH_CSS_SP_EVENT_FW_WARNING,
163 SH_CSS_SP_EVENT_FW_ASSERT,
164 SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */
165 };
166
167 /* xmem address map allocation per pipeline, css pointers */
168 /* Note that the struct below should only consist of ia_css_ptr-es
169 Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map
170 */
171 struct sh_css_ddr_address_map {
172 ia_css_ptr isp_param;
173 ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
174 ia_css_ptr macc_tbl;
175 ia_css_ptr fpn_tbl;
176 ia_css_ptr sc_tbl;
177 ia_css_ptr tetra_r_x;
178 ia_css_ptr tetra_r_y;
179 ia_css_ptr tetra_gr_x;
180 ia_css_ptr tetra_gr_y;
181 ia_css_ptr tetra_gb_x;
182 ia_css_ptr tetra_gb_y;
183 ia_css_ptr tetra_b_x;
184 ia_css_ptr tetra_b_y;
185 ia_css_ptr tetra_ratb_x;
186 ia_css_ptr tetra_ratb_y;
187 ia_css_ptr tetra_batr_x;
188 ia_css_ptr tetra_batr_y;
189 ia_css_ptr dvs_6axis_params_y;
190 };
191
192 #define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \
193 (SIZE_OF_HRT_VADDRESS + \
194 (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \
195 (16 * SIZE_OF_HRT_VADDRESS))
196
197 static_assert(sizeof(struct sh_css_ddr_address_map) == SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT);
198
199 /* xmem address map allocation per pipeline */
200 struct sh_css_ddr_address_map_size {
201 size_t isp_param;
202 size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
203 size_t macc_tbl;
204 size_t fpn_tbl;
205 size_t sc_tbl;
206 size_t tetra_r_x;
207 size_t tetra_r_y;
208 size_t tetra_gr_x;
209 size_t tetra_gr_y;
210 size_t tetra_gb_x;
211 size_t tetra_gb_y;
212 size_t tetra_b_x;
213 size_t tetra_b_y;
214 size_t tetra_ratb_x;
215 size_t tetra_ratb_y;
216 size_t tetra_batr_x;
217 size_t tetra_batr_y;
218 size_t dvs_6axis_params_y;
219 };
220
221 struct sh_css_ddr_address_map_compound {
222 struct sh_css_ddr_address_map map;
223 struct sh_css_ddr_address_map_size size;
224 };
225
226 struct ia_css_isp_parameter_set_info {
227 struct sh_css_ddr_address_map
228 mem_map;/** pointers to Parameters in ISP format IMPT:
229 This should be first member of this struct */
230 u32
231 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */
232 ia_css_ptr
233 output_frame_ptr;/** Output frame to which this config has to be applied (optional) */
234 };
235
236 /* this struct contains all arguments that can be passed to
237 a binary. It depends on the binary which ones are used. */
238 struct sh_css_binary_args {
239 struct ia_css_frame *in_frame; /* input frame */
240 const struct ia_css_frame
241 *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */
242 const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */
243 struct ia_css_frame
244 *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */
245 struct ia_css_frame *out_vf_frame; /* viewfinder output frame */
246 bool copy_vf;
247 bool copy_output;
248 unsigned int vf_downscale_log2;
249 };
250
251 #if SP_DEBUG == SP_DEBUG_DUMP
252
253 #define SH_CSS_NUM_SP_DEBUG 48
254
255 struct sh_css_sp_debug_state {
256 unsigned int error;
257 unsigned int debug[SH_CSS_NUM_SP_DEBUG];
258 };
259
260 #elif SP_DEBUG == SP_DEBUG_COPY
261
262 #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
263
264 struct sh_css_sp_debug_trace {
265 u16 frame;
266 u16 line;
267 u16 pixel_distance;
268 u16 mipi_used_dword;
269 u16 sp_index;
270 };
271
272 struct sh_css_sp_debug_state {
273 u16 if_start_line;
274 u16 if_start_column;
275 u16 if_cropped_height;
276 u16 if_cropped_width;
277 unsigned int index;
278 struct sh_css_sp_debug_trace
279 trace[SH_CSS_SP_DBG_TRACE_DEPTH];
280 };
281
282 #elif SP_DEBUG == SP_DEBUG_TRACE
283
284 /* Example of just one global trace */
285 #define SH_CSS_SP_DBG_NR_OF_TRACES (1)
286 #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
287
288 #define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13)
289
290 struct sh_css_sp_debug_trace {
291 u16 time_stamp;
292 u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */
293 u32 data;
294 };
295
296 struct sh_css_sp_debug_state {
297 struct sh_css_sp_debug_trace
298 trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH];
299 u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES];
300 u8 index[SH_CSS_SP_DBG_NR_OF_TRACES];
301 };
302
303 #elif SP_DEBUG == SP_DEBUG_MINIMAL
304
305 #define SH_CSS_NUM_SP_DEBUG 128
306
307 struct sh_css_sp_debug_state {
308 unsigned int error;
309 unsigned int debug[SH_CSS_NUM_SP_DEBUG];
310 };
311
312 #endif
313
314 struct sh_css_sp_debug_command {
315 /*
316 * The DMA software-mask,
317 * Bit 31...24: unused.
318 * Bit 23...16: unused.
319 * Bit 15...08: reading-request enabling bits for DMA channel 7..0
320 * Bit 07...00: writing-request enabling bits for DMA channel 7..0
321 *
322 * For example, "0...0 0...0 11111011 11111101" indicates that the
323 * writing request through DMA Channel 1 and the reading request
324 * through DMA channel 2 are both disabled. The others are enabled.
325 */
326 u32 dma_sw_reg;
327 };
328
329 /* SP input formatter configuration.*/
330 struct sh_css_sp_input_formatter_set {
331 u32 stream_format;
332 input_formatter_cfg_t config_a;
333 input_formatter_cfg_t config_b;
334 };
335
336 #define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3)
337
338 /*
339 * SP configuration information
340 *
341 * This struct is part of the atomisp firmware ABI and is directly copied
342 * to ISP DRAM by sh_css_store_sp_group_to_ddr()
343 *
344 * Do NOT change this struct's layout or remove seemingly unused fields!
345 */
346 struct sh_css_sp_config {
347 u8 no_isp_sync; /* Signal host immediately after start */
348 u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */
349 u8 lock_all;
350 /** If raw buffer locking is enabled, this flag indicates whether raw
351 frames are locked when their EOF event is successfully sent to the
352 host (true) or when they are passed to the preview/video pipe
353 (false). */
354
355 /*
356 * Note the fields below are only used on the ISP2400 not on the ISP2401,
357 * sh_css_store_sp_group_to_ddr() skip copying these when run on the ISP2401.
358 */
359 struct {
360 u8 a_changed;
361 u8 b_changed;
362 u8 isp_2ppc;
363 struct sh_css_sp_input_formatter_set
364 set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */
365 } input_formatter;
366
367 sync_generator_cfg_t sync_gen;
368 tpg_cfg_t tpg;
369 prbs_cfg_t prbs;
370 input_system_cfg_t input_circuit;
371 u8 input_circuit_cfg_changed;
372 u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT];
373 /* These last 2 fields are used on both the ISP2400 and the ISP2401 */
374 u8 enable_isys_event_queue;
375 u8 disable_cont_vf;
376 };
377
378 enum sh_css_stage_type {
379 SH_CSS_SP_STAGE_TYPE = 0,
380 SH_CSS_ISP_STAGE_TYPE = 1
381 };
382
383 #define SH_CSS_NUM_STAGE_TYPES 2
384
385 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0)
386 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \
387 ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1)
388
389 struct sh_css_sp_pipeline_terminal {
390 union {
391 /* Input System 2401 */
392 virtual_input_system_stream_t
393 virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
394 } context;
395 /*
396 * TODO
397 * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready.
398 */
399 union {
400 /* Input System 2401 */
401 virtual_input_system_stream_cfg_t
402 virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
403 } ctrl;
404 };
405
406 struct sh_css_sp_pipeline_io {
407 struct sh_css_sp_pipeline_terminal input;
408 /* pqiao: comment out temporarily to save dmem */
409 /*struct sh_css_sp_pipeline_terminal output;*/
410 };
411
412 /* This struct tracks how many streams are registered per CSI port.
413 * This is used to track which streams have already been configured.
414 * Only when all streams are configured, the CSI RX is started for that port.
415 */
416 struct sh_css_sp_pipeline_io_status {
417 u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */
418 u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */
419 };
420
421 enum sh_css_port_dir {
422 SH_CSS_PORT_INPUT = 0,
423 SH_CSS_PORT_OUTPUT = 1
424 };
425
426 enum sh_css_port_type {
427 SH_CSS_HOST_TYPE = 0,
428 SH_CSS_COPYSINK_TYPE = 1,
429 SH_CSS_TAGGERSINK_TYPE = 2
430 };
431
432 /* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */
433 #define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4)
434 #define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt))
435 #define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0)
436 #define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
437 #define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
438 #define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \
439 SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt))
440 #define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
441 #define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \
442 (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \
443 SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE)))
444
445 #define IA_CSS_ACQUIRE_ISP_POS 31
446
447 /* Flags for metadata processing */
448 #define SH_CSS_METADATA_ENABLED 0x01
449 #define SH_CSS_METADATA_PROCESSED 0x02
450 #define SH_CSS_METADATA_OFFLINE_MODE 0x04
451 #define SH_CSS_METADATA_WAIT_INPUT 0x08
452
453 /* @brief Free an array of metadata buffers.
454 *
455 * @param[in] num_bufs Number of metadata buffers to be freed.
456 * @param[in] bufs Pointer of array of metadata buffers.
457 *
458 * This function frees an array of metadata buffers.
459 */
460 void
461 ia_css_metadata_free_multiple(unsigned int num_bufs,
462 struct ia_css_metadata **bufs);
463
464 /* Macro for handling pipe_qos_config */
465 #define QOS_INVALID (~0U)
466
467 /* Information for a pipeline */
468 struct sh_css_sp_pipeline {
469 u32 pipe_id; /* the pipe ID */
470 u32 pipe_num; /* the dynamic pipe number */
471 u32 thread_id; /* the sp thread ID */
472 u32 pipe_config; /* the pipe config */
473 u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state.
474 (0xFFFFFFFF) indicates non QOS pipe.*/
475 u32 inout_port_config;
476 u32 required_bds_factor;
477 u32 dvs_frame_delay;
478 u32 input_system_mode; /* enum ia_css_input_mode */
479 u32 port_id; /* port_id for input system */
480 u32 num_stages; /* the pipe config */
481 u32 running; /* needed for pipe termination */
482 ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES];
483 ia_css_ptr scaler_pp_lut; /* Early bound LUT */
484 u32 dummy; /* stage ptr is only used on sp but lives in
485 this struct; needs cleanup */
486 s32 num_execs; /* number of times to run if this is
487 an acceleration pipe. */
488 struct {
489 u32 format; /* Metadata format in hrt format */
490 u32 width; /* Width of a line */
491 u32 height; /* Number of lines */
492 u32 stride; /* Stride (in bytes) per line */
493 u32 size; /* Total size (in bytes) */
494 ia_css_ptr cont_buf; /* Address of continuous buffer */
495 } metadata;
496 u32 output_frame_queue_id;
497 union {
498 struct {
499 u32 bytes_available;
500 } bin;
501 struct {
502 u32 height;
503 u32 width;
504 u32 padded_width;
505 u32 max_input_width;
506 u32 raw_bit_depth;
507 } raw;
508 } copy;
509 };
510
511 /*
512 * The first frames (with comment Dynamic) can be dynamic or static
513 * The other frames (ref_in and below) can only be static
514 * Static means that the data address will not change during the life time
515 * of the associated pipe. Dynamic means that the data address can
516 * change with every (frame) iteration of the associated pipe
517 *
518 * s3a and dis are now also dynamic but (still) handled separately
519 */
520 #define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3)
521
522 struct ia_css_frames_sp {
523 struct ia_css_frame_sp in;
524 struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
525 struct ia_css_resolution effective_in_res;
526 struct ia_css_frame_sp out_vf;
527 struct ia_css_frame_sp_info internal_frame_info;
528 struct ia_css_buffer_sp s3a_buf;
529 struct ia_css_buffer_sp dvs_buf;
530 struct ia_css_buffer_sp metadata_buf;
531 };
532
533 /* Information for a single pipeline stage for an ISP */
534 struct sh_css_isp_stage {
535 /*
536 * For compatibility and portabilty, only types
537 * from "stdint.h" are allowed
538 *
539 * Use of "enum" and "bool" is prohibited
540 * Multiple boolean flags can be stored in an
541 * integer
542 */
543 struct ia_css_blob_info blob_info;
544 struct ia_css_binary_info binary_info;
545 char binary_name[SH_CSS_MAX_BINARY_NAME];
546 struct ia_css_isp_param_css_segments mem_initializers;
547 };
548
549 /* Information for a single pipeline stage */
550 struct sh_css_sp_stage {
551 /*
552 * For compatibility and portabilty, only types
553 * from "stdint.h" are allowed
554 *
555 * Use of "enum" and "bool" is prohibited
556 * Multiple boolean flags can be stored in an
557 * integer
558 */
559 u8 num; /* Stage number */
560 u8 isp_online;
561 u8 isp_copy_vf;
562 u8 isp_copy_output;
563 u8 sp_enable_xnr;
564 u8 isp_deci_log_factor;
565 u8 isp_vf_downscale_bits;
566 u8 deinterleaved;
567 /*
568 * NOTE: Programming the input circuit can only be done at the
569 * start of a session. It is illegal to program it during execution
570 * The input circuit defines the connectivity
571 */
572 u8 program_input_circuit;
573 /* enum ia_css_pipeline_stage_sp_func func; */
574 u8 func;
575 /* The type of the pipe-stage */
576 /* enum sh_css_stage_type stage_type; */
577 u8 stage_type;
578 u8 num_stripes;
579 u8 isp_pipe_version;
580 struct {
581 u8 vf_output;
582 u8 s3a;
583 u8 sdis;
584 u8 dvs_stats;
585 u8 lace_stats;
586 } enable;
587 /* Add padding to come to a word boundary */
588 /* unsigned char padding[0]; */
589
590 struct sh_css_crop_pos sp_out_crop_pos;
591 struct ia_css_frames_sp frames;
592 struct ia_css_resolution dvs_envelope;
593 struct sh_css_uds_info uds;
594 ia_css_ptr isp_stage_addr;
595 ia_css_ptr xmem_bin_addr;
596 ia_css_ptr xmem_map_addr;
597
598 u16 top_cropping;
599 u16 row_stripes_height;
600 u16 row_stripes_overlap_lines;
601 u8 if_config_index; /* Which should be applied by this stage. */
602 };
603
604 /*
605 * Time: 2012-07-19, 17:40.
606 * Note: Add a new data member "debug" in "sh_css_sp_group". This
607 * data member is used to pass the debugging command from the
608 * Host to the SP.
609 *
610 * Time: Before 2012-07-19.
611 * Note:
612 * Group all host initialized SP variables into this struct.
613 * This is initialized every stage through dma.
614 * The stage part itself is transferred through sh_css_sp_stage.
615 */
616 struct sh_css_sp_group {
617 struct sh_css_sp_config config;
618 struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS];
619 struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS];
620 struct sh_css_sp_pipeline_io_status pipe_io_status;
621 struct sh_css_sp_debug_command debug;
622 };
623
624 /* Data in SP dmem that is set from the host every stage. */
625 struct sh_css_sp_per_frame_data {
626 /* ddr address of sp_group and sp_stage */
627 ia_css_ptr sp_group_addr;
628 };
629
630 #define SH_CSS_NUM_SDW_IRQS 3
631
632 /* Output data from SP to css */
633 struct sh_css_sp_output {
634 unsigned int bin_copy_bytes_copied;
635 #if SP_DEBUG != SP_DEBUG_NONE
636 struct sh_css_sp_debug_state debug;
637 #endif
638 unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS];
639 };
640
641 /**
642 * @brief Data structure for the circular buffer.
643 * The circular buffer is empty if "start == end". The
644 * circular buffer is full if "(end + 1) % size == start".
645 */
646 /* Variable Sized Buffer Queue Elements */
647
648 #define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6
649 #define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3
650 #define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6
651
652 /* sp-to-host queue is expected to be emptied in ISR since
653 * it is used instead of HW interrupts (due to HW design issue).
654 * We need one queue element per CSI port. */
655 #define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
656 /* The host-to-sp queue needs to allow for some delay
657 * in the emptying of this queue in the SP since there is no
658 * separate SP thread for this. */
659 #define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
660
661 #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13
662 #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19
663 #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */
664
665 struct sh_css_hmm_buffer {
666 union {
667 struct ia_css_isp_3a_statistics s3a;
668 struct ia_css_isp_dvs_statistics dis;
669 ia_css_ptr skc_dvs_statistics;
670 ia_css_ptr lace_stat;
671 struct ia_css_metadata metadata;
672 struct frame_data_wrapper {
673 ia_css_ptr frame_data;
674 u32 flashed;
675 u32 exp_id;
676 u32 isp_parameters_id; /** Unique ID to track which config was
677 actually applied to a particular frame */
678 } frame;
679 ia_css_ptr ddr_ptrs;
680 } payload;
681 /*
682 * kernel_ptr is present for host administration purposes only.
683 * type is uint64_t in order to be 64-bit host compatible.
684 * uint64_t does not exist on SP/ISP.
685 * Size of the struct is checked by sp.hive.c.
686 */
687 CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */
688 u64 kernel_ptr;
689 struct ia_css_time_meas timing_data;
690 clock_value_t isys_eof_clock_tick;
691 };
692
693 #define SIZE_OF_FRAME_STRUCT \
694 (SIZE_OF_HRT_VADDRESS + \
695 (3 * sizeof(uint32_t)))
696
697 #define SIZE_OF_PAYLOAD_UNION \
698 (MAX(MAX(MAX(MAX( \
699 SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \
700 SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \
701 SIZE_OF_IA_CSS_METADATA_STRUCT), \
702 SIZE_OF_FRAME_STRUCT), \
703 SIZE_OF_HRT_VADDRESS))
704
705 /* Do not use sizeof(uint64_t) since that does not exist of SP */
706 #define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \
707 (SIZE_OF_PAYLOAD_UNION + \
708 CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \
709 8 + \
710 8 + \
711 SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \
712 SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \
713 CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8))
714
715 static_assert(sizeof(struct sh_css_hmm_buffer) == SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT);
716
717 enum sh_css_queue_type {
718 sh_css_invalid_queue_type = -1,
719 sh_css_host2sp_buffer_queue,
720 sh_css_sp2host_buffer_queue,
721 sh_css_host2sp_psys_event_queue,
722 sh_css_sp2host_psys_event_queue,
723 sh_css_sp2host_isys_event_queue,
724 sh_css_host2sp_isys_event_queue,
725 sh_css_host2sp_tag_cmd_queue,
726 };
727
728 struct sh_css_event_irq_mask {
729 u16 or_mask;
730 u16 and_mask;
731 };
732
733 #define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \
734 (2 * sizeof(uint16_t))
735
736 static_assert(sizeof(struct sh_css_event_irq_mask) == SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT);
737
738 struct host_sp_communication {
739 /*
740 * Don't use enum host2sp_commands, because the sizeof an enum is
741 * compiler dependent and thus non-portable
742 */
743 u32 host2sp_command;
744
745 /*
746 * The frame buffers that are reused by the
747 * copy pipe in the offline preview mode.
748 *
749 * host2sp_offline_frames[0]: the input frame of the preview pipe.
750 * host2sp_offline_frames[1]: the output frame of the copy pipe.
751 *
752 * TODO:
753 * Remove it when the Host and the SP is decoupled.
754 */
755 ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES];
756 ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES];
757
758 ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
759 ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
760 u32 host2sp_num_mipi_frames[N_CSI_PORTS];
761 u32 host2sp_cont_avail_num_raw_frames;
762 u32 host2sp_cont_extra_num_raw_frames;
763 u32 host2sp_cont_target_num_raw_frames;
764 struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES];
765
766 };
767
768 #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \
769 (sizeof(uint32_t) + \
770 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \
771 (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \
772 ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \
773 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT))
774
775 static_assert(sizeof(struct host_sp_communication) == SIZE_OF_HOST_SP_COMMUNICATION_STRUCT);
776
777 struct host_sp_queues {
778 /*
779 * Queues for the dynamic frame information,
780 * i.e. the "in_frame" buffer, the "out_frame"
781 * buffer and the "vf_out_frame" buffer.
782 */
783 ia_css_circbuf_desc_t host2sp_buffer_queues_desc
784 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES];
785 ia_css_circbuf_elem_t host2sp_buffer_queues_elems
786 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]
787 [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE];
788 ia_css_circbuf_desc_t sp2host_buffer_queues_desc
789 [SH_CSS_MAX_NUM_QUEUES];
790 ia_css_circbuf_elem_t sp2host_buffer_queues_elems
791 [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE];
792
793 /*
794 * The queues for the events.
795 */
796 ia_css_circbuf_desc_t host2sp_psys_event_queue_desc;
797
798 ia_css_circbuf_elem_t host2sp_psys_event_queue_elems
799 [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE];
800 ia_css_circbuf_desc_t sp2host_psys_event_queue_desc;
801
802 ia_css_circbuf_elem_t sp2host_psys_event_queue_elems
803 [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE];
804
805 /*
806 * The queues for the ISYS events.
807 */
808 ia_css_circbuf_desc_t host2sp_isys_event_queue_desc;
809
810 ia_css_circbuf_elem_t host2sp_isys_event_queue_elems
811 [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE];
812 ia_css_circbuf_desc_t sp2host_isys_event_queue_desc;
813
814 ia_css_circbuf_elem_t sp2host_isys_event_queue_elems
815 [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE];
816 /*
817 * The queue for the tagger commands.
818 * CHECK: are these last two present on the 2401 ?
819 */
820 ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc;
821
822 ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems
823 [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE];
824 };
825
826 #define SIZE_OF_QUEUES_ELEMS \
827 (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \
828 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \
829 (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \
830 (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \
831 (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \
832 (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \
833 (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \
834 (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE)))
835
836 #define IA_CSS_NUM_CIRCBUF_DESCS 5
837
838 #define SIZE_OF_QUEUES_DESC \
839 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \
840 SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
841 (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
842 (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT))
843
844 #define SIZE_OF_HOST_SP_QUEUES_STRUCT \
845 (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC)
846
847 static_assert(sizeof(struct host_sp_queues) == SIZE_OF_HOST_SP_QUEUES_STRUCT);
848
849 extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args);
850
sh_css_print(const char * fmt,...)851 static inline void __printf(1, 2) sh_css_print(const char *fmt, ...)
852 {
853 va_list ap;
854
855 if (sh_css_printf) {
856 va_start(ap, fmt);
857 sh_css_printf(fmt, ap);
858 va_end(ap);
859 }
860 }
861
sh_css_vprint(const char * fmt,va_list args)862 static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args)
863 {
864 if (sh_css_printf)
865 sh_css_printf(fmt, args);
866 }
867
868 /* The following #if is there because this header file is also included
869 by SP and ISP code but they do not need this data and HIVECC has alignment
870 issue with the firmware struct/union's.
871 More permanent solution will be to refactor this include.
872 */
873 ia_css_ptr sh_css_params_ddr_address_map(void);
874
875 int
876 sh_css_params_init(void);
877
878 void
879 sh_css_params_uninit(void);
880
881 void
882 sh_css_binary_args_reset(struct sh_css_binary_args *args);
883
884 /* Check two frames for equality (format, resolution, bits per element) */
885 bool
886 sh_css_frame_equal_types(const struct ia_css_frame *frame_a,
887 const struct ia_css_frame *frame_b);
888
889 bool
890 sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a,
891 const struct ia_css_frame_info *info_b);
892
893 void
894 sh_css_capture_enable_bayer_downscaling(bool enable);
895
896 void
897 sh_css_binary_print(const struct ia_css_binary *binary);
898
899 /* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement.
900 When 0, no extra alignment is done. */
901 void
902 sh_css_frame_info_set_width(struct ia_css_frame_info *info,
903 unsigned int width,
904 unsigned int aligned);
905
906
907 unsigned int
908 sh_css_get_mipi_sizes_for_check(const unsigned int port,
909 const unsigned int idx);
910
911
912 ia_css_ptr
913 sh_css_store_sp_group_to_ddr(void);
914
915 ia_css_ptr
916 sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage);
917
918 ia_css_ptr
919 sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage);
920
921 void
922 sh_css_update_uds_and_crop_info(
923 const struct ia_css_binary_info *info,
924 const struct ia_css_frame_info *in_frame_info,
925 const struct ia_css_frame_info *out_frame_info,
926 const struct ia_css_resolution *dvs_env,
927 const struct ia_css_dz_config *zoom,
928 const struct ia_css_vector *motion_vector,
929 struct sh_css_uds_info *uds, /* out */
930 struct sh_css_crop_pos *sp_out_crop_pos, /* out */
931
932 bool enable_zoom
933 );
934
935 void
936 sh_css_invalidate_shading_tables(struct ia_css_stream *stream);
937
938 struct ia_css_pipeline *
939 ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe);
940
941 unsigned int
942 ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe);
943
944 unsigned int
945 ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe);
946
947 bool
948 sh_css_continuous_is_enabled(uint8_t pipe_num);
949
950 struct ia_css_pipe *
951 find_pipe_by_num(uint32_t pipe_num);
952
953 void
954 ia_css_get_crop_offsets(
955 struct ia_css_pipe *pipe,
956 struct ia_css_frame_info *in_frame);
957
958 #endif /* _SH_CSS_INTERNAL_H_ */
959