1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_LM_H 8 #define _DPU_HW_LM_H 9 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_util.h" 12 13 struct dpu_hw_mixer; 14 struct dpu_hw_stage_cfg; 15 16 struct dpu_hw_mixer_cfg { 17 u32 out_width; 18 u32 out_height; 19 bool right_mixer; 20 int flags; 21 }; 22 23 struct dpu_hw_color3_cfg { 24 u8 keep_fg[DPU_STAGE_MAX]; 25 }; 26 27 /** 28 * struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions 29 * Assumption is these functions will be called after clocks are enabled 30 */ 31 struct dpu_hw_lm_ops { 32 /** 33 * @setup_mixer_out: Sets up mixer output width and height 34 * and border color if enabled 35 */ 36 void (*setup_mixer_out)(struct dpu_hw_mixer *ctx, 37 struct dpu_hw_mixer_cfg *cfg); 38 39 /** 40 * @setup_blend_config: Alpha blending configuration 41 * for the specified stage 42 */ 43 void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage, 44 u16 fg_alpha, u16 bg_alpha, uint32_t blend_op); 45 46 /** 47 * @setup_alpha_out: Alpha color component selection from either fg or bg 48 */ 49 void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); 50 51 /** 52 * @clear_all_blendstages: Clear layer mixer to pipe configuration 53 * @ctx : mixer ctx pointer 54 * Returns: 0 on success or -error 55 */ 56 int (*clear_all_blendstages)(struct dpu_hw_mixer *ctx); 57 58 /** 59 * @setup_blendstage: Configure layer mixer to pipe configuration 60 * @ctx : mixer ctx pointer 61 * @lm : layer mixer enumeration 62 * @stage_cfg : blend stage configuration 63 * Returns: 0 on success or -error 64 */ 65 int (*setup_blendstage)(struct dpu_hw_mixer *ctx, enum dpu_lm lm, 66 struct dpu_hw_stage_cfg *stage_cfg); 67 68 /** 69 * @setup_border_color : enable/disable border color 70 */ 71 void (*setup_border_color)(struct dpu_hw_mixer *ctx, 72 struct dpu_mdss_color *color, 73 u8 border_en); 74 75 /** 76 * @setup_misr: Enable/disable MISR 77 */ 78 void (*setup_misr)(struct dpu_hw_mixer *ctx); 79 80 /** 81 * @collect_misr: Read MISR signature 82 */ 83 int (*collect_misr)(struct dpu_hw_mixer *ctx, u32 *misr_value); 84 }; 85 86 struct dpu_hw_mixer { 87 struct dpu_hw_blk base; 88 struct dpu_hw_blk_reg_map hw; 89 90 /* lm */ 91 enum dpu_lm idx; 92 const struct dpu_lm_cfg *cap; 93 const struct dpu_mdp_cfg *mdp; 94 const struct dpu_ctl_cfg *ctl; 95 96 /* ops */ 97 struct dpu_hw_lm_ops ops; 98 99 /* store mixer info specific to display */ 100 struct dpu_hw_mixer_cfg cfg; 101 }; 102 103 /** 104 * to_dpu_hw_mixer - convert base object dpu_hw_base to container 105 * @hw: Pointer to base hardware block 106 * return: Pointer to hardware block container 107 */ 108 static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) 109 { 110 return container_of(hw, struct dpu_hw_mixer, base); 111 } 112 113 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 114 const struct dpu_lm_cfg *cfg, 115 void __iomem *addr, 116 const struct dpu_mdss_version *mdss_ver); 117 118 #endif /*_DPU_HW_LM_H */ 119