1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3
4 #include <linux/acpi.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/iommu.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/seq_file.h>
15 #include <linux/topology.h>
16 #include <linux/uacce.h>
17 #include "sec.h"
18
19 #define CAP_FILE_PERMISSION 0444
20 #define SEC_VF_NUM 63
21 #define SEC_QUEUE_NUM_V1 4096
22 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
23
24 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
25 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
26 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
27
28 #define SEC_SQE_SIZE 128
29 #define SEC_PF_DEF_Q_NUM 256
30 #define SEC_PF_DEF_Q_BASE 0
31 #define SEC_CTX_Q_NUM_DEF 2
32 #define SEC_CTX_Q_NUM_MAX 32
33
34 #define SEC_CTRL_CNT_CLR_CE 0x301120
35 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
36 #define SEC_CORE_INT_SOURCE 0x301010
37 #define SEC_CORE_INT_MASK 0x301000
38 #define SEC_CORE_INT_STATUS 0x301008
39 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
40 #define SEC_ECC_NUM 16
41 #define SEC_ECC_MASH 0xFF
42 #define SEC_CORE_INT_DISABLE 0x0
43
44 #define SEC_RAS_CE_REG 0x301050
45 #define SEC_RAS_FE_REG 0x301054
46 #define SEC_RAS_NFE_REG 0x301058
47 #define SEC_RAS_FE_ENB_MSK 0x0
48 #define SEC_OOO_SHUTDOWN_SEL 0x301014
49 #define SEC_RAS_DISABLE 0x0
50 #define SEC_AXI_ERROR_MASK (BIT(0) | BIT(1))
51
52 #define SEC_MEM_START_INIT_REG 0x301100
53 #define SEC_MEM_INIT_DONE_REG 0x301104
54
55 /* clock gating */
56 #define SEC_CONTROL_REG 0x301200
57 #define SEC_DYNAMIC_GATE_REG 0x30121c
58 #define SEC_CORE_AUTO_GATE 0x30212c
59 #define SEC_DYNAMIC_GATE_EN 0x7fff
60 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)
61 #define SEC_CLK_GATE_ENABLE BIT(3)
62 #define SEC_CLK_GATE_DISABLE (~BIT(3))
63
64 #define SEC_TRNG_EN_SHIFT 8
65 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
66 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
67
68 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
69 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
70 #define SEC_SAA_EN_REG 0x301270
71 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
72 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
73 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
74
75 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
76 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
77 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24)
78 #define SEC_USER1_ENABLE_DATA_SSV BIT(16)
79 #define SEC_USER1_WB_CONTEXT_SSV BIT(8)
80 #define SEC_USER1_WB_DATA_SSV BIT(0)
81 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \
82 SEC_USER1_ENABLE_DATA_SSV | \
83 SEC_USER1_WB_CONTEXT_SSV | \
84 SEC_USER1_WB_DATA_SSV)
85 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
86 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
87 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220
88 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
89 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5))
90 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E
91 #define SEC_CORE_INT_STATUS_M_ECC BIT(2)
92
93 #define SEC_PREFETCH_CFG 0x301130
94 #define SEC_SVA_TRANS 0x301EC4
95 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11)))
96 #define SEC_PREFETCH_DISABLE BIT(1)
97 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11))
98 #define SEC_SVA_PREFETCH_INFO 0x301ED4
99 #define SEC_SVA_STALL_NUM GENMASK(23, 8)
100 #define SEC_SVA_PREFETCH_NUM GENMASK(2, 0)
101 #define SEC_WAIT_SVA_READY 500000
102 #define SEC_READ_SVA_STATUS_TIMES 3
103 #define SEC_WAIT_US_MIN 10
104 #define SEC_WAIT_US_MAX 20
105 #define SEC_WAIT_QP_US_MIN 1000
106 #define SEC_WAIT_QP_US_MAX 2000
107 #define SEC_MAX_WAIT_TIMES 2000
108
109 #define SEC_DELAY_10_US 10
110 #define SEC_POLL_TIMEOUT_US 1000
111 #define SEC_DBGFS_VAL_MAX_LEN 20
112 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060
113
114 #define SEC_SQE_MASK_OFFSET 16
115 #define SEC_SQE_MASK_LEN 108
116 #define SEC_SHAPER_TYPE_RATE 400
117
118 #define SEC_DFX_BASE 0x301000
119 #define SEC_DFX_CORE 0x302100
120 #define SEC_DFX_COMMON1 0x301600
121 #define SEC_DFX_COMMON2 0x301C00
122 #define SEC_DFX_BASE_LEN 0x9D
123 #define SEC_DFX_CORE_LEN 0x32B
124 #define SEC_DFX_COMMON1_LEN 0x45
125 #define SEC_DFX_COMMON2_LEN 0xBA
126
127 #define SEC_ALG_BITMAP_SHIFT 32
128
129 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \
130 GENMASK(24, 21))
131 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \
132 GENMASK_ULL(42, 25))
133 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \
134 GENMASK_ULL(45, 43))
135
136 #define SEC_MAX_CHANNEL_NUM 1
137
138 struct sec_hw_error {
139 u32 int_msk;
140 const char *msg;
141 };
142
143 struct sec_dfx_item {
144 const char *name;
145 u32 offset;
146 };
147
148 static const char sec_name[] = "hisi_sec2";
149 static struct dentry *sec_debugfs_root;
150
151 static struct hisi_qm_list sec_devices = {
152 .register_to_crypto = sec_register_to_crypto,
153 .unregister_from_crypto = sec_unregister_from_crypto,
154 };
155
156 static const struct hisi_qm_cap_info sec_basic_info[] = {
157 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77},
158 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77},
159 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
160 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
161 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177},
162 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177},
163 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177},
164 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088},
165 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1},
166 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1},
167 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},
168 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},
169 {SEC_CORE_ENABLE_BITMAP, 0x3140, 0, GENMASK(31, 0), 0x17F, 0x17F, 0xF},
170 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x18670CF},
171 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},
172 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
173 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
174 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
175 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
176 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
177 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
178 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
179 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
180 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
181 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
182 };
183
184 static const struct hisi_qm_cap_query_info sec_cap_query_info[] = {
185 {QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C77, 0x7C77},
186 {QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC77, 0x6C77},
187 {QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8},
188 {SEC_RAS_NFE_TYPE, "SEC_RAS_NFE_TYPE ", 0x3130, 0x0, 0x177, 0x60177},
189 {SEC_RAS_NFE_RESET, "SEC_RAS_NFE_RESET ", 0x3134, 0x0, 0x177, 0x177},
190 {SEC_RAS_CE_TYPE, "SEC_RAS_CE_TYPE ", 0x3138, 0x0, 0x88, 0xC088},
191 {SEC_CORE_INFO, "SEC_CORE_INFO ", 0x313c, 0x110404, 0x110404, 0x110404},
192 {SEC_CORE_EN, "SEC_CORE_EN ", 0x3140, 0x17F, 0x17F, 0xF},
193 {SEC_DRV_ALG_BITMAP_LOW_TB, "SEC_DRV_ALG_BITMAP_LOW ",
194 0x3144, 0x18050CB, 0x18050CB, 0x18670CF},
195 {SEC_DRV_ALG_BITMAP_HIGH_TB, "SEC_DRV_ALG_BITMAP_HIGH ",
196 0x3148, 0x395C, 0x395C, 0x395C},
197 {SEC_ALG_BITMAP_LOW, "SEC_ALG_BITMAP_LOW ",
198 0x314c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
199 {SEC_ALG_BITMAP_HIGH, "SEC_ALG_BITMAP_HIGH ", 0x3150, 0x3FFF, 0x3FFF, 0x3FFF},
200 {SEC_CORE1_BITMAP_LOW, "SEC_CORE1_BITMAP_LOW ",
201 0x3154, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
202 {SEC_CORE1_BITMAP_HIGH, "SEC_CORE1_BITMAP_HIGH ", 0x3158, 0x3FFF, 0x3FFF, 0x3FFF},
203 {SEC_CORE2_BITMAP_LOW, "SEC_CORE2_BITMAP_LOW ",
204 0x315c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
205 {SEC_CORE2_BITMAP_HIGH, "SEC_CORE2_BITMAP_HIGH ", 0x3160, 0x3FFF, 0x3FFF, 0x3FFF},
206 {SEC_CORE3_BITMAP_LOW, "SEC_CORE3_BITMAP_LOW ",
207 0x3164, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
208 {SEC_CORE3_BITMAP_HIGH, "SEC_CORE3_BITMAP_HIGH ", 0x3168, 0x3FFF, 0x3FFF, 0x3FFF},
209 {SEC_CORE4_BITMAP_LOW, "SEC_CORE4_BITMAP_LOW ",
210 0x316c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
211 {SEC_CORE4_BITMAP_HIGH, "SEC_CORE4_BITMAP_HIGH ", 0x3170, 0x3FFF, 0x3FFF, 0x3FFF},
212 };
213
214 static const struct qm_dev_alg sec_dev_algs[] = { {
215 .alg_msk = SEC_CIPHER_BITMAP,
216 .alg = "cipher\n",
217 }, {
218 .alg_msk = SEC_DIGEST_BITMAP,
219 .alg = "digest\n",
220 }, {
221 .alg_msk = SEC_AEAD_BITMAP,
222 .alg = "aead\n",
223 },
224 };
225
226 static const struct sec_hw_error sec_hw_errors[] = {
227 {
228 .int_msk = BIT(0),
229 .msg = "sec_axi_rresp_err_rint"
230 },
231 {
232 .int_msk = BIT(1),
233 .msg = "sec_axi_bresp_err_rint"
234 },
235 {
236 .int_msk = BIT(2),
237 .msg = "sec_ecc_2bit_err_rint"
238 },
239 {
240 .int_msk = BIT(3),
241 .msg = "sec_ecc_1bit_err_rint"
242 },
243 {
244 .int_msk = BIT(4),
245 .msg = "sec_req_trng_timeout_rint"
246 },
247 {
248 .int_msk = BIT(5),
249 .msg = "sec_fsm_hbeat_rint"
250 },
251 {
252 .int_msk = BIT(6),
253 .msg = "sec_channel_req_rng_timeout_rint"
254 },
255 {
256 .int_msk = BIT(7),
257 .msg = "sec_bd_err_rint"
258 },
259 {
260 .int_msk = BIT(8),
261 .msg = "sec_chain_buff_err_rint"
262 },
263 {
264 .int_msk = BIT(14),
265 .msg = "sec_no_secure_access"
266 },
267 {
268 .int_msk = BIT(15),
269 .msg = "sec_wrapping_key_auth_err"
270 },
271 {
272 .int_msk = BIT(16),
273 .msg = "sec_km_key_crc_fail"
274 },
275 {
276 .int_msk = BIT(17),
277 .msg = "sec_axi_poison_err"
278 },
279 {
280 .int_msk = BIT(18),
281 .msg = "sec_sva_err"
282 },
283 {}
284 };
285
286 static const char * const sec_dbg_file_name[] = {
287 [SEC_CLEAR_ENABLE] = "clear_enable",
288 };
289
290 static struct sec_dfx_item sec_dfx_labels[] = {
291 {"send_cnt", offsetof(struct sec_dfx, send_cnt)},
292 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)},
293 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)},
294 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)},
295 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)},
296 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)},
297 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)},
298 };
299
300 static const struct debugfs_reg32 sec_dfx_regs[] = {
301 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
302 {"SEC_SAA_EN ", 0x301270},
303 {"SEC_BD_LATENCY_MIN ", 0x301600},
304 {"SEC_BD_LATENCY_MAX ", 0x301608},
305 {"SEC_BD_LATENCY_AVG ", 0x30160C},
306 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
307 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
308 {"SEC_BD_NUM_IN_SEC ", 0x301680},
309 {"SEC_ECC_1BIT_CNT ", 0x301C00},
310 {"SEC_ECC_1BIT_INFO ", 0x301C04},
311 {"SEC_ECC_2BIT_CNT ", 0x301C10},
312 {"SEC_ECC_2BIT_INFO ", 0x301C14},
313 {"SEC_BD_SAA0 ", 0x301C20},
314 {"SEC_BD_SAA1 ", 0x301C24},
315 {"SEC_BD_SAA2 ", 0x301C28},
316 {"SEC_BD_SAA3 ", 0x301C2C},
317 {"SEC_BD_SAA4 ", 0x301C30},
318 {"SEC_BD_SAA5 ", 0x301C34},
319 {"SEC_BD_SAA6 ", 0x301C38},
320 {"SEC_BD_SAA7 ", 0x301C3C},
321 {"SEC_BD_SAA8 ", 0x301C40},
322 {"SEC_RAS_CE_ENABLE ", 0x301050},
323 {"SEC_RAS_FE_ENABLE ", 0x301054},
324 {"SEC_RAS_NFE_ENABLE ", 0x301058},
325 {"SEC_REQ_TRNG_TIME_TH ", 0x30112C},
326 {"SEC_CHANNEL_RNG_REQ_THLD ", 0x302110},
327 };
328
329 /* define the SEC's dfx regs region and region length */
330 static struct dfx_diff_registers sec_diff_regs[] = {
331 {
332 .reg_offset = SEC_DFX_BASE,
333 .reg_len = SEC_DFX_BASE_LEN,
334 }, {
335 .reg_offset = SEC_DFX_COMMON1,
336 .reg_len = SEC_DFX_COMMON1_LEN,
337 }, {
338 .reg_offset = SEC_DFX_COMMON2,
339 .reg_len = SEC_DFX_COMMON2_LEN,
340 }, {
341 .reg_offset = SEC_DFX_CORE,
342 .reg_len = SEC_DFX_CORE_LEN,
343 },
344 };
345
sec_diff_regs_show(struct seq_file * s,void * unused)346 static int sec_diff_regs_show(struct seq_file *s, void *unused)
347 {
348 struct hisi_qm *qm = s->private;
349
350 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
351 ARRAY_SIZE(sec_diff_regs));
352
353 return 0;
354 }
355 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs);
356
357 static bool pf_q_num_flag;
sec_pf_q_num_set(const char * val,const struct kernel_param * kp)358 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
359 {
360 pf_q_num_flag = true;
361
362 return hisi_qm_q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF);
363 }
364
365 static const struct kernel_param_ops sec_pf_q_num_ops = {
366 .set = sec_pf_q_num_set,
367 .get = param_get_int,
368 };
369
370 static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
371 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
372 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
373
sec_ctx_q_num_set(const char * val,const struct kernel_param * kp)374 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
375 {
376 u32 ctx_q_num;
377 int ret;
378
379 if (!val)
380 return -EINVAL;
381
382 ret = kstrtou32(val, 10, &ctx_q_num);
383 if (ret)
384 return -EINVAL;
385
386 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) {
387 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
388 return -EINVAL;
389 }
390
391 return param_set_int(val, kp);
392 }
393
394 static const struct kernel_param_ops sec_ctx_q_num_ops = {
395 .set = sec_ctx_q_num_set,
396 .get = param_get_int,
397 };
398 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
399 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
400 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
401
402 static const struct kernel_param_ops vfs_num_ops = {
403 .set = vfs_num_set,
404 .get = param_get_int,
405 };
406
407 static u32 vfs_num;
408 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
409 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
410
sec_destroy_qps(struct hisi_qp ** qps,int qp_num)411 void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
412 {
413 hisi_qm_free_qps(qps, qp_num);
414 kfree(qps);
415 }
416
sec_create_qps(void)417 struct hisi_qp **sec_create_qps(void)
418 {
419 int node = cpu_to_node(raw_smp_processor_id());
420 u32 ctx_num = ctx_q_num;
421 struct hisi_qp **qps;
422 u8 *type;
423 int ret;
424
425 qps = kzalloc_objs(struct hisi_qp *, ctx_num);
426 if (!qps)
427 return NULL;
428
429 /* The type of SEC is all 0, so just allocated by kcalloc */
430 type = kcalloc(ctx_num, sizeof(u8), GFP_KERNEL);
431 if (!type) {
432 kfree(qps);
433 return NULL;
434 }
435
436 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, type, node, qps);
437 if (ret) {
438 kfree(type);
439 kfree(qps);
440 return NULL;
441 }
442
443 kfree(type);
444 return qps;
445 }
446
sec_get_alg_bitmap(struct hisi_qm * qm,u32 high,u32 low)447 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low)
448 {
449 u32 cap_val_h, cap_val_l;
450
451 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val;
452 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val;
453
454 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;
455 }
456
457 static const struct kernel_param_ops sec_uacce_mode_ops = {
458 .set = uacce_mode_set,
459 .get = param_get_int,
460 };
461
462 /*
463 * uacce_mode = 0 means sec only register to crypto,
464 * uacce_mode = 1 means sec both register to crypto and uacce.
465 */
466 static u32 uacce_mode = UACCE_MODE_NOUACCE;
467 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444);
468 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
469
470 static const struct pci_device_id sec_dev_ids[] = {
471 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) },
472 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) },
473 { 0, }
474 };
475 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
476
sec_set_endian(struct hisi_qm * qm)477 static void sec_set_endian(struct hisi_qm *qm)
478 {
479 u32 reg;
480
481 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
482 reg &= ~(BIT(1) | BIT(0));
483 if (!IS_ENABLED(CONFIG_64BIT))
484 reg |= BIT(1);
485
486 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
487 reg |= BIT(0);
488
489 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
490 }
491
sec_wait_sva_ready(struct hisi_qm * qm,__u32 offset,__u32 mask)492 static int sec_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask)
493 {
494 u32 val, try_times = 0;
495 u8 count = 0;
496
497 /*
498 * Read the register value every 10-20us. If the value is 0 for three
499 * consecutive times, the SVA module is ready.
500 */
501 do {
502 val = readl(qm->io_base + offset);
503 if (val & mask)
504 count = 0;
505 else if (++count == SEC_READ_SVA_STATUS_TIMES)
506 break;
507
508 usleep_range(SEC_WAIT_US_MIN, SEC_WAIT_US_MAX);
509 } while (++try_times < SEC_WAIT_SVA_READY);
510
511 if (try_times == SEC_WAIT_SVA_READY) {
512 pci_err(qm->pdev, "failed to wait sva prefetch ready\n");
513 return -ETIMEDOUT;
514 }
515
516 return 0;
517 }
518
sec_close_sva_prefetch(struct hisi_qm * qm)519 static void sec_close_sva_prefetch(struct hisi_qm *qm)
520 {
521 u32 val;
522 int ret;
523
524 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
525 return;
526
527 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
528 val |= SEC_PREFETCH_DISABLE;
529 writel(val, qm->io_base + SEC_PREFETCH_CFG);
530
531 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,
532 val, !(val & SEC_SVA_DISABLE_READY),
533 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
534 if (ret)
535 pci_err(qm->pdev, "failed to close sva prefetch\n");
536
537 (void)sec_wait_sva_ready(qm, SEC_SVA_PREFETCH_INFO, SEC_SVA_STALL_NUM);
538 }
539
sec_open_sva_prefetch(struct hisi_qm * qm)540 static void sec_open_sva_prefetch(struct hisi_qm *qm)
541 {
542 u32 val;
543 int ret;
544
545 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
546 return;
547
548 /* Enable prefetch */
549 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
550 val &= SEC_PREFETCH_ENABLE;
551 writel(val, qm->io_base + SEC_PREFETCH_CFG);
552
553 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
554 val, !(val & SEC_PREFETCH_DISABLE),
555 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
556 if (ret) {
557 pci_err(qm->pdev, "failed to open sva prefetch\n");
558 sec_close_sva_prefetch(qm);
559 return;
560 }
561
562 ret = sec_wait_sva_ready(qm, SEC_SVA_TRANS, SEC_SVA_PREFETCH_NUM);
563 if (ret)
564 sec_close_sva_prefetch(qm);
565 }
566
sec_engine_sva_config(struct hisi_qm * qm)567 static void sec_engine_sva_config(struct hisi_qm *qm)
568 {
569 u32 reg;
570
571 if (qm->ver > QM_HW_V2) {
572 reg = readl_relaxed(qm->io_base +
573 SEC_INTERFACE_USER_CTRL0_REG_V3);
574 reg |= SEC_USER0_SMMU_NORMAL;
575 writel_relaxed(reg, qm->io_base +
576 SEC_INTERFACE_USER_CTRL0_REG_V3);
577
578 reg = readl_relaxed(qm->io_base +
579 SEC_INTERFACE_USER_CTRL1_REG_V3);
580 reg &= SEC_USER1_SMMU_MASK_V3;
581 reg |= SEC_USER1_SMMU_NORMAL_V3;
582 writel_relaxed(reg, qm->io_base +
583 SEC_INTERFACE_USER_CTRL1_REG_V3);
584 } else {
585 reg = readl_relaxed(qm->io_base +
586 SEC_INTERFACE_USER_CTRL0_REG);
587 reg |= SEC_USER0_SMMU_NORMAL;
588 writel_relaxed(reg, qm->io_base +
589 SEC_INTERFACE_USER_CTRL0_REG);
590 reg = readl_relaxed(qm->io_base +
591 SEC_INTERFACE_USER_CTRL1_REG);
592 reg &= SEC_USER1_SMMU_MASK;
593 if (qm->use_sva)
594 reg |= SEC_USER1_SMMU_SVA;
595 else
596 reg |= SEC_USER1_SMMU_NORMAL;
597 writel_relaxed(reg, qm->io_base +
598 SEC_INTERFACE_USER_CTRL1_REG);
599 }
600 sec_open_sva_prefetch(qm);
601 }
602
sec_enable_clock_gate(struct hisi_qm * qm)603 static void sec_enable_clock_gate(struct hisi_qm *qm)
604 {
605 u32 val;
606
607 if (qm->ver < QM_HW_V3)
608 return;
609
610 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
611 val |= SEC_CLK_GATE_ENABLE;
612 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
613
614 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);
615 val |= SEC_DYNAMIC_GATE_EN;
616 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);
617
618 val = readl(qm->io_base + SEC_CORE_AUTO_GATE);
619 val |= SEC_CORE_AUTO_GATE_EN;
620 writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
621 }
622
sec_disable_clock_gate(struct hisi_qm * qm)623 static void sec_disable_clock_gate(struct hisi_qm *qm)
624 {
625 u32 val;
626
627 /* Kunpeng920 needs to close clock gating */
628 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
629 val &= SEC_CLK_GATE_DISABLE;
630 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
631 }
632
sec_engine_init(struct hisi_qm * qm)633 static int sec_engine_init(struct hisi_qm *qm)
634 {
635 int ret;
636 u32 reg;
637
638 /* disable clock gate control before mem init */
639 sec_disable_clock_gate(qm);
640
641 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
642
643 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
644 reg, reg & 0x1, SEC_DELAY_10_US,
645 SEC_POLL_TIMEOUT_US);
646 if (ret) {
647 pci_err(qm->pdev, "fail to init sec mem\n");
648 return ret;
649 }
650
651 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
652 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
653 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
654
655 sec_engine_sva_config(qm);
656
657 writel(SEC_SINGLE_PORT_MAX_TRANS,
658 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
659
660 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver);
661 writel(reg, qm->io_base + SEC_SAA_EN_REG);
662
663 if (qm->ver < QM_HW_V3) {
664 /* HW V2 enable sm4 extra mode, as ctr/ecb */
665 writel_relaxed(SEC_BD_ERR_CHK_EN0,
666 qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
667
668 /* HW V2 enable sm4 xts mode multiple iv */
669 writel_relaxed(SEC_BD_ERR_CHK_EN1,
670 qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
671 writel_relaxed(SEC_BD_ERR_CHK_EN3,
672 qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
673 }
674
675 /* config endian */
676 sec_set_endian(qm);
677
678 sec_enable_clock_gate(qm);
679
680 return 0;
681 }
682
sec_set_user_domain_and_cache(struct hisi_qm * qm)683 static int sec_set_user_domain_and_cache(struct hisi_qm *qm)
684 {
685 /* qm user domain */
686 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
687 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
688 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
689 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
690 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
691
692 /* qm cache */
693 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
694 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
695
696 /* disable FLR triggered by BME(bus master enable) */
697 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
698 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
699
700 /* enable sqc,cqc writeback */
701 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
702 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
703 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
704
705 return sec_engine_init(qm);
706 }
707
708 /* sec_debug_regs_clear() - clear the sec debug regs */
sec_debug_regs_clear(struct hisi_qm * qm)709 static void sec_debug_regs_clear(struct hisi_qm *qm)
710 {
711 int i;
712
713 /* clear sec dfx regs */
714 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);
715 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
716 readl(qm->io_base + sec_dfx_regs[i].offset);
717
718 /* clear rdclr_en */
719 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
720
721 hisi_qm_debug_regs_clear(qm);
722 }
723
sec_master_ooo_ctrl(struct hisi_qm * qm,bool enable)724 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
725 {
726 u32 val1, val2;
727
728 val1 = readl(qm->io_base + SEC_CONTROL_REG);
729 if (enable) {
730 val1 |= SEC_AXI_SHUTDOWN_ENABLE;
731 val2 = qm->err_info.dev_err.shutdown_mask;
732 } else {
733 val1 &= SEC_AXI_SHUTDOWN_DISABLE;
734 val2 = 0x0;
735 }
736
737 if (qm->ver > QM_HW_V2)
738 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
739
740 writel(val1, qm->io_base + SEC_CONTROL_REG);
741 }
742
sec_hw_error_enable(struct hisi_qm * qm)743 static void sec_hw_error_enable(struct hisi_qm *qm)
744 {
745 struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;
746 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe;
747
748 if (qm->ver == QM_HW_V1) {
749 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
750 pci_info(qm->pdev, "V1 not support hw error handle\n");
751 return;
752 }
753
754 /* clear SEC hw error source if having */
755 writel(err_mask, qm->io_base + SEC_CORE_INT_SOURCE);
756
757 /* enable RAS int */
758 writel(dev_err->ce, qm->io_base + SEC_RAS_CE_REG);
759 writel(dev_err->fe, qm->io_base + SEC_RAS_FE_REG);
760 writel(dev_err->nfe, qm->io_base + SEC_RAS_NFE_REG);
761
762 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */
763 sec_master_ooo_ctrl(qm, true);
764
765 /* enable SEC hw error interrupts */
766 writel(err_mask, qm->io_base + SEC_CORE_INT_MASK);
767 }
768
sec_hw_error_disable(struct hisi_qm * qm)769 static void sec_hw_error_disable(struct hisi_qm *qm)
770 {
771 /* disable SEC hw error interrupts */
772 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
773
774 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
775 sec_master_ooo_ctrl(qm, false);
776
777 /* disable RAS int */
778 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
779 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
780 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
781 }
782
sec_clear_enable_read(struct hisi_qm * qm)783 static u32 sec_clear_enable_read(struct hisi_qm *qm)
784 {
785 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
786 SEC_CTRL_CNT_CLR_CE_BIT;
787 }
788
sec_clear_enable_write(struct hisi_qm * qm,u32 val)789 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
790 {
791 u32 tmp;
792
793 if (val != 1 && val)
794 return -EINVAL;
795
796 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
797 ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
798 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
799
800 return 0;
801 }
802
sec_debug_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)803 static ssize_t sec_debug_read(struct file *filp, char __user *buf,
804 size_t count, loff_t *pos)
805 {
806 struct sec_debug_file *file = filp->private_data;
807 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
808 struct hisi_qm *qm = file->qm;
809 u32 val;
810 int ret;
811
812 ret = hisi_qm_get_dfx_access(qm);
813 if (ret)
814 return ret;
815
816 spin_lock_irq(&file->lock);
817
818 switch (file->index) {
819 case SEC_CLEAR_ENABLE:
820 val = sec_clear_enable_read(qm);
821 break;
822 default:
823 goto err_input;
824 }
825
826 spin_unlock_irq(&file->lock);
827
828 hisi_qm_put_dfx_access(qm);
829 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
830 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
831
832 err_input:
833 spin_unlock_irq(&file->lock);
834 hisi_qm_put_dfx_access(qm);
835 return -EINVAL;
836 }
837
sec_debug_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)838 static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
839 size_t count, loff_t *pos)
840 {
841 struct sec_debug_file *file = filp->private_data;
842 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
843 struct hisi_qm *qm = file->qm;
844 unsigned long val;
845 int len, ret;
846
847 if (*pos != 0)
848 return 0;
849
850 if (count >= SEC_DBGFS_VAL_MAX_LEN)
851 return -ENOSPC;
852
853 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
854 pos, buf, count);
855 if (len < 0)
856 return len;
857
858 tbuf[len] = '\0';
859 if (kstrtoul(tbuf, 0, &val))
860 return -EFAULT;
861
862 ret = hisi_qm_get_dfx_access(qm);
863 if (ret)
864 return ret;
865
866 spin_lock_irq(&file->lock);
867
868 switch (file->index) {
869 case SEC_CLEAR_ENABLE:
870 ret = sec_clear_enable_write(qm, val);
871 if (ret)
872 goto err_input;
873 break;
874 default:
875 ret = -EINVAL;
876 goto err_input;
877 }
878
879 ret = count;
880
881 err_input:
882 spin_unlock_irq(&file->lock);
883 hisi_qm_put_dfx_access(qm);
884 return ret;
885 }
886
887 static const struct file_operations sec_dbg_fops = {
888 .owner = THIS_MODULE,
889 .open = simple_open,
890 .read = sec_debug_read,
891 .write = sec_debug_write,
892 };
893
sec_debugfs_atomic64_get(void * data,u64 * val)894 static int sec_debugfs_atomic64_get(void *data, u64 *val)
895 {
896 *val = atomic64_read((atomic64_t *)data);
897
898 return 0;
899 }
900
sec_debugfs_atomic64_set(void * data,u64 val)901 static int sec_debugfs_atomic64_set(void *data, u64 val)
902 {
903 if (val)
904 return -EINVAL;
905
906 atomic64_set((atomic64_t *)data, 0);
907
908 return 0;
909 }
910
911 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
912 sec_debugfs_atomic64_set, "%llu\n");
913
sec_regs_show(struct seq_file * s,void * unused)914 static int sec_regs_show(struct seq_file *s, void *unused)
915 {
916 hisi_qm_regs_dump(s, s->private);
917
918 return 0;
919 }
920
921 DEFINE_SHOW_ATTRIBUTE(sec_regs);
922
sec_cap_regs_show(struct seq_file * s,void * unused)923 static int sec_cap_regs_show(struct seq_file *s, void *unused)
924 {
925 struct hisi_qm *qm = s->private;
926 u32 i, size;
927
928 size = qm->cap_tables.qm_cap_size;
929 for (i = 0; i < size; i++)
930 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,
931 qm->cap_tables.qm_cap_table[i].cap_val);
932
933 size = qm->cap_tables.dev_cap_size;
934 for (i = 0; i < size; i++)
935 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,
936 qm->cap_tables.dev_cap_table[i].cap_val);
937
938 return 0;
939 }
940
941 DEFINE_SHOW_ATTRIBUTE(sec_cap_regs);
942
sec_core_debug_init(struct hisi_qm * qm)943 static int sec_core_debug_init(struct hisi_qm *qm)
944 {
945 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;
946 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
947 struct device *dev = &qm->pdev->dev;
948 struct sec_dfx *dfx = &sec->debug.dfx;
949 struct debugfs_regset32 *regset;
950 struct dentry *tmp_d;
951 int i;
952
953 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);
954
955 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
956 if (!regset)
957 return -ENOMEM;
958
959 regset->regs = sec_dfx_regs;
960 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
961 regset->base = qm->io_base;
962 regset->dev = dev;
963
964 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF)
965 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops);
966 if (qm->fun_type == QM_HW_PF && sec_regs)
967 debugfs_create_file("diff_regs", 0444, tmp_d,
968 qm, &sec_diff_regs_fops);
969
970 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) {
971 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx +
972 sec_dfx_labels[i].offset);
973 debugfs_create_file(sec_dfx_labels[i].name, 0644,
974 tmp_d, data, &sec_atomic64_ops);
975 }
976
977 debugfs_create_file("cap_regs", CAP_FILE_PERMISSION,
978 qm->debug.debug_root, qm, &sec_cap_regs_fops);
979
980 return 0;
981 }
982
sec_debug_init(struct hisi_qm * qm)983 static int sec_debug_init(struct hisi_qm *qm)
984 {
985 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
986 int i;
987
988 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) {
989 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) {
990 spin_lock_init(&sec->debug.files[i].lock);
991 sec->debug.files[i].index = i;
992 sec->debug.files[i].qm = qm;
993
994 debugfs_create_file(sec_dbg_file_name[i], 0600,
995 qm->debug.debug_root,
996 sec->debug.files + i,
997 &sec_dbg_fops);
998 }
999 }
1000
1001 return sec_core_debug_init(qm);
1002 }
1003
sec_debugfs_init(struct hisi_qm * qm)1004 static int sec_debugfs_init(struct hisi_qm *qm)
1005 {
1006 struct device *dev = &qm->pdev->dev;
1007 int ret;
1008
1009 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs));
1010 if (ret) {
1011 dev_warn(dev, "Failed to init SEC diff regs!\n");
1012 return ret;
1013 }
1014
1015 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
1016 sec_debugfs_root);
1017 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;
1018 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;
1019
1020 hisi_qm_debug_init(qm);
1021
1022 ret = sec_debug_init(qm);
1023 if (ret)
1024 goto debugfs_remove;
1025
1026 return 0;
1027
1028 debugfs_remove:
1029 debugfs_remove_recursive(qm->debug.debug_root);
1030 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
1031 return ret;
1032 }
1033
sec_debugfs_exit(struct hisi_qm * qm)1034 static void sec_debugfs_exit(struct hisi_qm *qm)
1035 {
1036 debugfs_remove_recursive(qm->debug.debug_root);
1037
1038 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
1039 }
1040
sec_show_last_regs_init(struct hisi_qm * qm)1041 static int sec_show_last_regs_init(struct hisi_qm *qm)
1042 {
1043 struct qm_debug *debug = &qm->debug;
1044 int i;
1045
1046 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs),
1047 sizeof(unsigned int), GFP_KERNEL);
1048 if (!debug->last_words)
1049 return -ENOMEM;
1050
1051 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
1052 debug->last_words[i] = readl_relaxed(qm->io_base +
1053 sec_dfx_regs[i].offset);
1054
1055 return 0;
1056 }
1057
sec_show_last_regs_uninit(struct hisi_qm * qm)1058 static void sec_show_last_regs_uninit(struct hisi_qm *qm)
1059 {
1060 struct qm_debug *debug = &qm->debug;
1061
1062 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1063 return;
1064
1065 kfree(debug->last_words);
1066 debug->last_words = NULL;
1067 }
1068
sec_show_last_dfx_regs(struct hisi_qm * qm)1069 static void sec_show_last_dfx_regs(struct hisi_qm *qm)
1070 {
1071 struct qm_debug *debug = &qm->debug;
1072 struct pci_dev *pdev = qm->pdev;
1073 u32 val;
1074 int i;
1075
1076 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1077 return;
1078
1079 /* dumps last word of the debugging registers during controller reset */
1080 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) {
1081 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset);
1082 if (val != debug->last_words[i])
1083 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n",
1084 sec_dfx_regs[i].name, debug->last_words[i], val);
1085 }
1086 }
1087
sec_log_hw_error(struct hisi_qm * qm,u32 err_sts)1088 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1089 {
1090 const struct sec_hw_error *errs = sec_hw_errors;
1091 struct device *dev = &qm->pdev->dev;
1092 u32 err_val;
1093
1094 while (errs->msg) {
1095 if (errs->int_msk & err_sts) {
1096 dev_err(dev, "%s [error status=0x%x] found\n",
1097 errs->msg, errs->int_msk);
1098
1099 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
1100 err_val = readl(qm->io_base +
1101 SEC_CORE_SRAM_ECC_ERR_INFO);
1102 dev_err(dev, "multi ecc sram num=0x%x\n",
1103 ((err_val) >> SEC_ECC_NUM) &
1104 SEC_ECC_MASH);
1105 }
1106 }
1107 errs++;
1108 }
1109 }
1110
sec_get_hw_err_status(struct hisi_qm * qm)1111 static u32 sec_get_hw_err_status(struct hisi_qm *qm)
1112 {
1113 return readl(qm->io_base + SEC_CORE_INT_STATUS);
1114 }
1115
sec_clear_hw_err_status(struct hisi_qm * qm,u32 err_sts)1116 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1117 {
1118 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
1119 }
1120
sec_disable_error_report(struct hisi_qm * qm,u32 err_type)1121 static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type)
1122 {
1123 u32 nfe_mask = qm->err_info.dev_err.nfe;
1124
1125 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);
1126 }
1127
sec_enable_error_report(struct hisi_qm * qm)1128 static void sec_enable_error_report(struct hisi_qm *qm)
1129 {
1130 u32 nfe_mask = qm->err_info.dev_err.nfe;
1131 u32 ce_mask = qm->err_info.dev_err.ce;
1132
1133 writel(nfe_mask, qm->io_base + SEC_RAS_NFE_REG);
1134 writel(ce_mask, qm->io_base + SEC_RAS_CE_REG);
1135 }
1136
sec_open_axi_master_ooo(struct hisi_qm * qm)1137 static void sec_open_axi_master_ooo(struct hisi_qm *qm)
1138 {
1139 u32 val;
1140
1141 val = readl(qm->io_base + SEC_CONTROL_REG);
1142 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
1143 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
1144 }
1145
sec_get_err_result(struct hisi_qm * qm)1146 static enum acc_err_result sec_get_err_result(struct hisi_qm *qm)
1147 {
1148 u32 err_status;
1149
1150 err_status = sec_get_hw_err_status(qm);
1151 if (err_status) {
1152 if (err_status & qm->err_info.dev_err.ecc_2bits_mask)
1153 qm->err_status.is_dev_ecc_mbit = true;
1154 sec_log_hw_error(qm, err_status);
1155
1156 if (err_status & qm->err_info.dev_err.reset_mask) {
1157 /* Disable the same error reporting until device is recovered. */
1158 sec_disable_error_report(qm, err_status);
1159 return ACC_ERR_NEED_RESET;
1160 }
1161 sec_clear_hw_err_status(qm, err_status);
1162 /* Avoid firmware disable error report, re-enable. */
1163 sec_enable_error_report(qm);
1164 }
1165
1166 return ACC_ERR_RECOVERED;
1167 }
1168
sec_dev_is_abnormal(struct hisi_qm * qm)1169 static bool sec_dev_is_abnormal(struct hisi_qm *qm)
1170 {
1171 u32 err_status;
1172
1173 err_status = sec_get_hw_err_status(qm);
1174 if (err_status & qm->err_info.dev_err.shutdown_mask)
1175 return true;
1176
1177 return false;
1178 }
1179
sec_disable_axi_error(struct hisi_qm * qm)1180 static void sec_disable_axi_error(struct hisi_qm *qm)
1181 {
1182 struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;
1183 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe;
1184
1185 writel(err_mask & ~SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_MASK);
1186
1187 if (qm->ver > QM_HW_V2)
1188 writel(dev_err->shutdown_mask & (~SEC_AXI_ERROR_MASK),
1189 qm->io_base + SEC_OOO_SHUTDOWN_SEL);
1190 }
1191
sec_enable_axi_error(struct hisi_qm * qm)1192 static void sec_enable_axi_error(struct hisi_qm *qm)
1193 {
1194 struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;
1195 u32 err_mask = dev_err->ce | dev_err->nfe | dev_err->fe;
1196
1197 /* clear axi error source */
1198 writel(SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_SOURCE);
1199
1200 writel(err_mask, qm->io_base + SEC_CORE_INT_MASK);
1201
1202 if (qm->ver > QM_HW_V2)
1203 writel(dev_err->shutdown_mask, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
1204 }
1205
sec_err_info_init(struct hisi_qm * qm)1206 static void sec_err_info_init(struct hisi_qm *qm)
1207 {
1208 struct hisi_qm_err_info *err_info = &qm->err_info;
1209 struct hisi_qm_err_mask *qm_err = &err_info->qm_err;
1210 struct hisi_qm_err_mask *dev_err = &err_info->dev_err;
1211
1212 qm_err->fe = SEC_RAS_FE_ENB_MSK;
1213 qm_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver);
1214 qm_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver);
1215 qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1216 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1217 qm_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1218 SEC_QM_RESET_MASK_CAP, qm->cap_ver);
1219 qm_err->ecc_2bits_mask = QM_ECC_MBIT;
1220
1221 dev_err->fe = SEC_RAS_FE_ENB_MSK;
1222 dev_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver);
1223 dev_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
1224 dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1225 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1226 dev_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1227 SEC_RESET_MASK_CAP, qm->cap_ver);
1228 dev_err->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;
1229
1230 err_info->msi_wr_port = BIT(0);
1231 err_info->acpi_rst = "SRST";
1232 }
1233
1234 static const struct hisi_qm_err_ini sec_err_ini = {
1235 .hw_init = sec_set_user_domain_and_cache,
1236 .hw_err_enable = sec_hw_error_enable,
1237 .hw_err_disable = sec_hw_error_disable,
1238 .get_dev_hw_err_status = sec_get_hw_err_status,
1239 .clear_dev_hw_err_status = sec_clear_hw_err_status,
1240 .open_axi_master_ooo = sec_open_axi_master_ooo,
1241 .open_sva_prefetch = sec_open_sva_prefetch,
1242 .close_sva_prefetch = sec_close_sva_prefetch,
1243 .show_last_dfx_regs = sec_show_last_dfx_regs,
1244 .err_info_init = sec_err_info_init,
1245 .get_err_result = sec_get_err_result,
1246 .dev_is_abnormal = sec_dev_is_abnormal,
1247 .disable_axi_error = sec_disable_axi_error,
1248 .enable_axi_error = sec_enable_axi_error,
1249 };
1250
sec_pf_probe_init(struct sec_dev * sec)1251 static int sec_pf_probe_init(struct sec_dev *sec)
1252 {
1253 struct hisi_qm *qm = &sec->qm;
1254 int ret;
1255
1256 ret = sec_set_user_domain_and_cache(qm);
1257 if (ret)
1258 return ret;
1259
1260 hisi_qm_dev_err_init(qm);
1261 sec_debug_regs_clear(qm);
1262 ret = sec_show_last_regs_init(qm);
1263 if (ret)
1264 pci_err(qm->pdev, "Failed to init last word regs!\n");
1265
1266 return ret;
1267 }
1268
sec_pre_store_cap_reg(struct hisi_qm * qm)1269 static int sec_pre_store_cap_reg(struct hisi_qm *qm)
1270 {
1271 struct hisi_qm_cap_record *sec_cap;
1272 struct pci_dev *pdev = qm->pdev;
1273 size_t i, size;
1274
1275 size = ARRAY_SIZE(sec_cap_query_info);
1276 sec_cap = devm_kcalloc(&pdev->dev, size, sizeof(*sec_cap), GFP_KERNEL);
1277 if (!sec_cap)
1278 return -ENOMEM;
1279
1280 for (i = 0; i < size; i++) {
1281 sec_cap[i].type = sec_cap_query_info[i].type;
1282 sec_cap[i].name = sec_cap_query_info[i].name;
1283 sec_cap[i].cap_val = hisi_qm_get_cap_value(qm, sec_cap_query_info,
1284 i, qm->cap_ver);
1285 }
1286
1287 qm->cap_tables.dev_cap_table = sec_cap;
1288 qm->cap_tables.dev_cap_size = size;
1289
1290 return 0;
1291 }
1292
sec_set_channels(struct hisi_qm * qm)1293 static void sec_set_channels(struct hisi_qm *qm)
1294 {
1295 struct qm_channel *channel_data = &qm->channel_data;
1296
1297 channel_data->channel_num = SEC_MAX_CHANNEL_NUM;
1298 channel_data->channel_name[0] = "SEC";
1299 }
1300
sec_qm_init(struct hisi_qm * qm,struct pci_dev * pdev)1301 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1302 {
1303 u64 alg_msk;
1304 int ret;
1305
1306 qm->pdev = pdev;
1307 qm->mode = uacce_mode;
1308 qm->sqe_size = SEC_SQE_SIZE;
1309 qm->dev_name = sec_name;
1310
1311 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?
1312 QM_HW_PF : QM_HW_VF;
1313 if (qm->fun_type == QM_HW_PF) {
1314 qm->qp_base = SEC_PF_DEF_Q_BASE;
1315 qm->qp_num = pf_q_num;
1316 qm->debug.curr_qm_qp_num = pf_q_num;
1317 qm->qm_list = &sec_devices;
1318 qm->err_ini = &sec_err_ini;
1319 if (pf_q_num_flag)
1320 set_bit(QM_MODULE_PARAM, &qm->misc_ctl);
1321 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
1322 /*
1323 * have no way to get qm configure in VM in v1 hardware,
1324 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
1325 * to trigger only one VF in v1 hardware.
1326 * v2 hardware has no such problem.
1327 */
1328 qm->qp_base = SEC_PF_DEF_Q_NUM;
1329 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
1330 }
1331
1332 ret = hisi_qm_init(qm);
1333 if (ret) {
1334 pci_err(qm->pdev, "Failed to init sec qm configures!\n");
1335 return ret;
1336 }
1337
1338 sec_set_channels(qm);
1339 /* Fetch and save the value of capability registers */
1340 ret = sec_pre_store_cap_reg(qm);
1341 if (ret) {
1342 pci_err(qm->pdev, "Failed to pre-store capability registers!\n");
1343 hisi_qm_uninit(qm);
1344 return ret;
1345 }
1346 alg_msk = sec_get_alg_bitmap(qm, SEC_ALG_BITMAP_HIGH, SEC_ALG_BITMAP_LOW);
1347 ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));
1348 if (ret) {
1349 pci_err(qm->pdev, "Failed to set sec algs!\n");
1350 hisi_qm_uninit(qm);
1351 }
1352
1353 return ret;
1354 }
1355
sec_qm_uninit(struct hisi_qm * qm)1356 static void sec_qm_uninit(struct hisi_qm *qm)
1357 {
1358 hisi_qm_uninit(qm);
1359 }
1360
sec_probe_init(struct sec_dev * sec)1361 static int sec_probe_init(struct sec_dev *sec)
1362 {
1363 u32 type_rate = SEC_SHAPER_TYPE_RATE;
1364 struct hisi_qm *qm = &sec->qm;
1365 int ret;
1366
1367 if (qm->fun_type == QM_HW_PF) {
1368 ret = sec_pf_probe_init(sec);
1369 if (ret)
1370 return ret;
1371 /* enable shaper type 0 */
1372 if (qm->ver >= QM_HW_V3) {
1373 type_rate |= QM_SHAPER_ENABLE;
1374 qm->type_rate = type_rate;
1375 }
1376 }
1377
1378 return 0;
1379 }
1380
sec_probe_uninit(struct hisi_qm * qm)1381 static void sec_probe_uninit(struct hisi_qm *qm)
1382 {
1383 if (qm->fun_type == QM_HW_VF)
1384 return;
1385
1386 sec_debug_regs_clear(qm);
1387 sec_show_last_regs_uninit(qm);
1388 sec_close_sva_prefetch(qm);
1389 hisi_qm_dev_err_uninit(qm);
1390 }
1391
sec_iommu_used_check(struct sec_dev * sec)1392 static void sec_iommu_used_check(struct sec_dev *sec)
1393 {
1394 struct iommu_domain *domain;
1395 struct device *dev = &sec->qm.pdev->dev;
1396
1397 domain = iommu_get_domain_for_dev(dev);
1398
1399 /* Check if iommu is used */
1400 sec->iommu_used = false;
1401 if (domain) {
1402 if (domain->type & __IOMMU_DOMAIN_PAGING)
1403 sec->iommu_used = true;
1404 dev_info(dev, "SMMU Opened, the iommu type = %u\n",
1405 domain->type);
1406 }
1407 }
1408
sec_probe(struct pci_dev * pdev,const struct pci_device_id * id)1409 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1410 {
1411 struct sec_dev *sec;
1412 struct hisi_qm *qm;
1413 int ret;
1414
1415 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
1416 if (!sec)
1417 return -ENOMEM;
1418
1419 qm = &sec->qm;
1420 ret = sec_qm_init(qm, pdev);
1421 if (ret) {
1422 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret);
1423 return ret;
1424 }
1425
1426 sec->ctx_q_num = ctx_q_num;
1427 sec_iommu_used_check(sec);
1428
1429 ret = sec_probe_init(sec);
1430 if (ret) {
1431 pci_err(pdev, "Failed to probe!\n");
1432 goto err_qm_uninit;
1433 }
1434
1435 ret = hisi_qm_start(qm);
1436 if (ret) {
1437 pci_err(pdev, "Failed to start sec qm!\n");
1438 goto err_probe_uninit;
1439 }
1440
1441 ret = sec_debugfs_init(qm);
1442 if (ret)
1443 pci_warn(pdev, "Failed to init debugfs!\n");
1444
1445 hisi_qm_add_list(qm, &sec_devices);
1446 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num);
1447 if (ret < 0) {
1448 pr_err("Failed to register driver to crypto.\n");
1449 goto err_qm_del_list;
1450 }
1451
1452 if (qm->uacce) {
1453 ret = uacce_register(qm->uacce);
1454 if (ret) {
1455 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1456 goto err_alg_unregister;
1457 }
1458 }
1459
1460 if (qm->fun_type == QM_HW_PF && vfs_num) {
1461 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1462 if (ret < 0)
1463 goto err_alg_unregister;
1464 }
1465
1466 hisi_qm_pm_init(qm);
1467
1468 return 0;
1469
1470 err_alg_unregister:
1471 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);
1472 err_qm_del_list:
1473 hisi_qm_del_list(qm, &sec_devices);
1474 sec_debugfs_exit(qm);
1475 hisi_qm_stop(qm, QM_NORMAL);
1476 err_probe_uninit:
1477 sec_probe_uninit(qm);
1478 err_qm_uninit:
1479 sec_qm_uninit(qm);
1480 return ret;
1481 }
1482
sec_remove(struct pci_dev * pdev)1483 static void sec_remove(struct pci_dev *pdev)
1484 {
1485 struct hisi_qm *qm = pci_get_drvdata(pdev);
1486
1487 hisi_qm_pm_uninit(qm);
1488 hisi_qm_wait_task_finish(qm, &sec_devices);
1489 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);
1490 hisi_qm_del_list(qm, &sec_devices);
1491
1492 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1493 hisi_qm_sriov_disable(pdev, true);
1494
1495 sec_debugfs_exit(qm);
1496
1497 (void)hisi_qm_stop(qm, QM_NORMAL);
1498 sec_probe_uninit(qm);
1499
1500 sec_qm_uninit(qm);
1501 }
1502
1503 static const struct dev_pm_ops sec_pm_ops = {
1504 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1505 };
1506
1507 static const struct pci_error_handlers sec_err_handler = {
1508 .error_detected = hisi_qm_dev_err_detected,
1509 .slot_reset = hisi_qm_dev_slot_reset,
1510 .reset_prepare = hisi_qm_reset_prepare,
1511 .reset_done = hisi_qm_reset_done,
1512 };
1513
1514 static struct pci_driver sec_pci_driver = {
1515 .name = "hisi_sec2",
1516 .id_table = sec_dev_ids,
1517 .probe = sec_probe,
1518 .remove = sec_remove,
1519 .err_handler = &sec_err_handler,
1520 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
1521 hisi_qm_sriov_configure : NULL,
1522 .shutdown = hisi_qm_dev_shutdown,
1523 .driver.pm = &sec_pm_ops,
1524 };
1525
hisi_sec_get_pf_driver(void)1526 struct pci_driver *hisi_sec_get_pf_driver(void)
1527 {
1528 return &sec_pci_driver;
1529 }
1530 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver);
1531
sec_register_debugfs(void)1532 static void sec_register_debugfs(void)
1533 {
1534 if (!debugfs_initialized())
1535 return;
1536
1537 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
1538 }
1539
sec_unregister_debugfs(void)1540 static void sec_unregister_debugfs(void)
1541 {
1542 debugfs_remove_recursive(sec_debugfs_root);
1543 }
1544
sec_init(void)1545 static int __init sec_init(void)
1546 {
1547 int ret;
1548
1549 hisi_qm_init_list(&sec_devices);
1550 sec_register_debugfs();
1551
1552 ret = pci_register_driver(&sec_pci_driver);
1553 if (ret < 0) {
1554 sec_unregister_debugfs();
1555 pr_err("Failed to register pci driver.\n");
1556 return ret;
1557 }
1558
1559 return 0;
1560 }
1561
sec_exit(void)1562 static void __exit sec_exit(void)
1563 {
1564 pci_unregister_driver(&sec_pci_driver);
1565 sec_unregister_debugfs();
1566 }
1567
1568 module_init(sec_init);
1569 module_exit(sec_exit);
1570
1571 MODULE_LICENSE("GPL v2");
1572 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1573 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
1574 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>");
1575 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>");
1576 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
1577