1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7280.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 13#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sc7280.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sc7280.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/mailbox/qcom-ipcc.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/sound/qcom,lpass.h> 31#include <dt-bindings/sound/qcom,q6afe.h> 32#include <dt-bindings/sound/qcom,q6asm.h> 33#include <dt-bindings/thermal/thermal.h> 34 35/ { 36 interrupt-parent = <&intc>; 37 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 chosen { }; 42 43 aliases { 44 i2c0 = &i2c0; 45 i2c1 = &i2c1; 46 i2c2 = &i2c2; 47 i2c3 = &i2c3; 48 i2c4 = &i2c4; 49 i2c5 = &i2c5; 50 i2c6 = &i2c6; 51 i2c7 = &i2c7; 52 i2c8 = &i2c8; 53 i2c9 = &i2c9; 54 i2c10 = &i2c10; 55 i2c11 = &i2c11; 56 i2c12 = &i2c12; 57 i2c13 = &i2c13; 58 i2c14 = &i2c14; 59 i2c15 = &i2c15; 60 mmc1 = &sdhc_1; 61 mmc2 = &sdhc_2; 62 spi0 = &spi0; 63 spi1 = &spi1; 64 spi2 = &spi2; 65 spi3 = &spi3; 66 spi4 = &spi4; 67 spi5 = &spi5; 68 spi6 = &spi6; 69 spi7 = &spi7; 70 spi8 = &spi8; 71 spi9 = &spi9; 72 spi10 = &spi10; 73 spi11 = &spi11; 74 spi12 = &spi12; 75 spi13 = &spi13; 76 spi14 = &spi14; 77 spi15 = &spi15; 78 }; 79 80 clocks { 81 xo_board: xo-board { 82 compatible = "fixed-clock"; 83 clock-frequency = <76800000>; 84 #clock-cells = <0>; 85 }; 86 87 sleep_clk: sleep-clk { 88 compatible = "fixed-clock"; 89 clock-frequency = <32764>; 90 #clock-cells = <0>; 91 }; 92 }; 93 94 reserved-memory { 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 wlan_ce_mem: wlan-ce@4cd000 { 100 no-map; 101 reg = <0x0 0x004cd000 0x0 0x1000>; 102 }; 103 104 hyp_mem: hyp@80000000 { 105 reg = <0x0 0x80000000 0x0 0x600000>; 106 no-map; 107 }; 108 109 xbl_mem: xbl@80600000 { 110 reg = <0x0 0x80600000 0x0 0x200000>; 111 no-map; 112 }; 113 114 aop_mem: aop@80800000 { 115 reg = <0x0 0x80800000 0x0 0x60000>; 116 no-map; 117 }; 118 119 aop_cmd_db_mem: aop-cmd-db@80860000 { 120 reg = <0x0 0x80860000 0x0 0x20000>; 121 compatible = "qcom,cmd-db"; 122 no-map; 123 }; 124 125 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 126 reg = <0x0 0x80884000 0x0 0x10000>; 127 no-map; 128 }; 129 130 sec_apps_mem: sec-apps@808ff000 { 131 reg = <0x0 0x808ff000 0x0 0x1000>; 132 no-map; 133 }; 134 135 smem_mem: smem@80900000 { 136 reg = <0x0 0x80900000 0x0 0x200000>; 137 no-map; 138 }; 139 140 cpucp_mem: cpucp@80b00000 { 141 no-map; 142 reg = <0x0 0x80b00000 0x0 0x100000>; 143 }; 144 145 wlan_fw_mem: wlan-fw@80c00000 { 146 reg = <0x0 0x80c00000 0x0 0xc00000>; 147 no-map; 148 }; 149 150 adsp_mem: adsp@86700000 { 151 reg = <0x0 0x86700000 0x0 0x2800000>; 152 no-map; 153 }; 154 155 video_mem: video@8b200000 { 156 reg = <0x0 0x8b200000 0x0 0x500000>; 157 no-map; 158 }; 159 160 cdsp_mem: cdsp@88f00000 { 161 reg = <0x0 0x88f00000 0x0 0x1e00000>; 162 no-map; 163 }; 164 165 ipa_fw_mem: ipa-fw@8b700000 { 166 reg = <0 0x8b700000 0 0x10000>; 167 no-map; 168 }; 169 170 gpu_zap_mem: zap@8b71a000 { 171 reg = <0 0x8b71a000 0 0x2000>; 172 no-map; 173 }; 174 175 mpss_mem: mpss@8b800000 { 176 reg = <0x0 0x8b800000 0x0 0xf600000>; 177 no-map; 178 }; 179 180 wpss_mem: wpss@9ae00000 { 181 reg = <0x0 0x9ae00000 0x0 0x1900000>; 182 no-map; 183 }; 184 185 rmtfs_mem: rmtfs@9c900000 { 186 compatible = "qcom,rmtfs-mem"; 187 reg = <0x0 0x9c900000 0x0 0x280000>; 188 no-map; 189 190 qcom,client-id = <1>; 191 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 192 }; 193 194 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 { 195 reg = <0x0 0x9cb80000 0x0 0x800000>; 196 no-map; 197 }; 198 }; 199 200 cpus { 201 #address-cells = <2>; 202 #size-cells = <0>; 203 204 cpu0: cpu@0 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo"; 207 reg = <0x0 0x0>; 208 clocks = <&cpufreq_hw 0>; 209 enable-method = "psci"; 210 power-domains = <&cpu_pd0>; 211 power-domain-names = "psci"; 212 next-level-cache = <&l2_0>; 213 operating-points-v2 = <&cpu0_opp_table>; 214 capacity-dmips-mhz = <1024>; 215 dynamic-power-coefficient = <100>; 216 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 217 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 qcom,freq-domain = <&cpufreq_hw 0>; 219 #cooling-cells = <2>; 220 l2_0: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&l3_0>; 225 l3_0: l3-cache { 226 compatible = "cache"; 227 cache-level = <3>; 228 cache-unified; 229 }; 230 }; 231 }; 232 233 cpu1: cpu@100 { 234 device_type = "cpu"; 235 compatible = "qcom,kryo"; 236 reg = <0x0 0x100>; 237 clocks = <&cpufreq_hw 0>; 238 enable-method = "psci"; 239 power-domains = <&cpu_pd1>; 240 power-domain-names = "psci"; 241 next-level-cache = <&l2_100>; 242 operating-points-v2 = <&cpu0_opp_table>; 243 capacity-dmips-mhz = <1024>; 244 dynamic-power-coefficient = <100>; 245 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 246 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 247 qcom,freq-domain = <&cpufreq_hw 0>; 248 #cooling-cells = <2>; 249 l2_100: l2-cache { 250 compatible = "cache"; 251 cache-level = <2>; 252 cache-unified; 253 next-level-cache = <&l3_0>; 254 }; 255 }; 256 257 cpu2: cpu@200 { 258 device_type = "cpu"; 259 compatible = "qcom,kryo"; 260 reg = <0x0 0x200>; 261 clocks = <&cpufreq_hw 0>; 262 enable-method = "psci"; 263 power-domains = <&cpu_pd2>; 264 power-domain-names = "psci"; 265 next-level-cache = <&l2_200>; 266 operating-points-v2 = <&cpu0_opp_table>; 267 capacity-dmips-mhz = <1024>; 268 dynamic-power-coefficient = <100>; 269 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 270 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 271 qcom,freq-domain = <&cpufreq_hw 0>; 272 #cooling-cells = <2>; 273 l2_200: l2-cache { 274 compatible = "cache"; 275 cache-level = <2>; 276 cache-unified; 277 next-level-cache = <&l3_0>; 278 }; 279 }; 280 281 cpu3: cpu@300 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x300>; 285 clocks = <&cpufreq_hw 0>; 286 enable-method = "psci"; 287 power-domains = <&cpu_pd3>; 288 power-domain-names = "psci"; 289 next-level-cache = <&l2_300>; 290 operating-points-v2 = <&cpu0_opp_table>; 291 capacity-dmips-mhz = <1024>; 292 dynamic-power-coefficient = <100>; 293 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 294 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 295 qcom,freq-domain = <&cpufreq_hw 0>; 296 #cooling-cells = <2>; 297 l2_300: l2-cache { 298 compatible = "cache"; 299 cache-level = <2>; 300 cache-unified; 301 next-level-cache = <&l3_0>; 302 }; 303 }; 304 305 cpu4: cpu@400 { 306 device_type = "cpu"; 307 compatible = "qcom,kryo"; 308 reg = <0x0 0x400>; 309 clocks = <&cpufreq_hw 1>; 310 enable-method = "psci"; 311 power-domains = <&cpu_pd4>; 312 power-domain-names = "psci"; 313 next-level-cache = <&l2_400>; 314 operating-points-v2 = <&cpu4_opp_table>; 315 capacity-dmips-mhz = <1946>; 316 dynamic-power-coefficient = <520>; 317 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 318 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 319 qcom,freq-domain = <&cpufreq_hw 1>; 320 #cooling-cells = <2>; 321 l2_400: l2-cache { 322 compatible = "cache"; 323 cache-level = <2>; 324 cache-unified; 325 next-level-cache = <&l3_0>; 326 }; 327 }; 328 329 cpu5: cpu@500 { 330 device_type = "cpu"; 331 compatible = "qcom,kryo"; 332 reg = <0x0 0x500>; 333 clocks = <&cpufreq_hw 1>; 334 enable-method = "psci"; 335 power-domains = <&cpu_pd5>; 336 power-domain-names = "psci"; 337 next-level-cache = <&l2_500>; 338 operating-points-v2 = <&cpu4_opp_table>; 339 capacity-dmips-mhz = <1946>; 340 dynamic-power-coefficient = <520>; 341 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 342 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 343 qcom,freq-domain = <&cpufreq_hw 1>; 344 #cooling-cells = <2>; 345 l2_500: l2-cache { 346 compatible = "cache"; 347 cache-level = <2>; 348 cache-unified; 349 next-level-cache = <&l3_0>; 350 }; 351 }; 352 353 cpu6: cpu@600 { 354 device_type = "cpu"; 355 compatible = "qcom,kryo"; 356 reg = <0x0 0x600>; 357 clocks = <&cpufreq_hw 1>; 358 enable-method = "psci"; 359 power-domains = <&cpu_pd6>; 360 power-domain-names = "psci"; 361 next-level-cache = <&l2_600>; 362 operating-points-v2 = <&cpu4_opp_table>; 363 capacity-dmips-mhz = <1946>; 364 dynamic-power-coefficient = <520>; 365 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 366 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 367 qcom,freq-domain = <&cpufreq_hw 1>; 368 #cooling-cells = <2>; 369 l2_600: l2-cache { 370 compatible = "cache"; 371 cache-level = <2>; 372 cache-unified; 373 next-level-cache = <&l3_0>; 374 }; 375 }; 376 377 cpu7: cpu@700 { 378 device_type = "cpu"; 379 compatible = "qcom,kryo"; 380 reg = <0x0 0x700>; 381 clocks = <&cpufreq_hw 2>; 382 enable-method = "psci"; 383 power-domains = <&cpu_pd7>; 384 power-domain-names = "psci"; 385 next-level-cache = <&l2_700>; 386 operating-points-v2 = <&cpu7_opp_table>; 387 capacity-dmips-mhz = <1985>; 388 dynamic-power-coefficient = <552>; 389 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 390 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 391 qcom,freq-domain = <&cpufreq_hw 2>; 392 #cooling-cells = <2>; 393 l2_700: l2-cache { 394 compatible = "cache"; 395 cache-level = <2>; 396 cache-unified; 397 next-level-cache = <&l3_0>; 398 }; 399 }; 400 401 cpu-map { 402 cluster0 { 403 core0 { 404 cpu = <&cpu0>; 405 }; 406 407 core1 { 408 cpu = <&cpu1>; 409 }; 410 411 core2 { 412 cpu = <&cpu2>; 413 }; 414 415 core3 { 416 cpu = <&cpu3>; 417 }; 418 419 core4 { 420 cpu = <&cpu4>; 421 }; 422 423 core5 { 424 cpu = <&cpu5>; 425 }; 426 427 core6 { 428 cpu = <&cpu6>; 429 }; 430 431 core7 { 432 cpu = <&cpu7>; 433 }; 434 }; 435 }; 436 437 idle-states { 438 entry-method = "psci"; 439 440 little_cpu_sleep_0: cpu-sleep-0-0 { 441 compatible = "arm,idle-state"; 442 idle-state-name = "little-power-down"; 443 arm,psci-suspend-param = <0x40000003>; 444 entry-latency-us = <549>; 445 exit-latency-us = <901>; 446 min-residency-us = <1774>; 447 local-timer-stop; 448 }; 449 450 little_cpu_sleep_1: cpu-sleep-0-1 { 451 compatible = "arm,idle-state"; 452 idle-state-name = "little-rail-power-down"; 453 arm,psci-suspend-param = <0x40000004>; 454 entry-latency-us = <702>; 455 exit-latency-us = <915>; 456 min-residency-us = <4001>; 457 local-timer-stop; 458 }; 459 460 big_cpu_sleep_0: cpu-sleep-1-0 { 461 compatible = "arm,idle-state"; 462 idle-state-name = "big-power-down"; 463 arm,psci-suspend-param = <0x40000003>; 464 entry-latency-us = <523>; 465 exit-latency-us = <1244>; 466 min-residency-us = <2207>; 467 local-timer-stop; 468 }; 469 470 big_cpu_sleep_1: cpu-sleep-1-1 { 471 compatible = "arm,idle-state"; 472 idle-state-name = "big-rail-power-down"; 473 arm,psci-suspend-param = <0x40000004>; 474 entry-latency-us = <526>; 475 exit-latency-us = <1854>; 476 min-residency-us = <5555>; 477 local-timer-stop; 478 }; 479 }; 480 481 domain_idle_states: domain-idle-states { 482 cluster_sleep_apss_off: cluster-sleep-0 { 483 compatible = "domain-idle-state"; 484 arm,psci-suspend-param = <0x41000044>; 485 entry-latency-us = <2752>; 486 exit-latency-us = <3048>; 487 min-residency-us = <6118>; 488 }; 489 490 cluster_sleep_cx_ret: cluster-sleep-1 { 491 compatible = "domain-idle-state"; 492 arm,psci-suspend-param = <0x41001344>; 493 entry-latency-us = <3263>; 494 exit-latency-us = <4562>; 495 min-residency-us = <8467>; 496 }; 497 498 cluster_sleep_llcc_off: cluster-sleep-2 { 499 compatible = "domain-idle-state"; 500 arm,psci-suspend-param = <0x4100b344>; 501 entry-latency-us = <3638>; 502 exit-latency-us = <6562>; 503 min-residency-us = <9826>; 504 }; 505 }; 506 }; 507 508 cpu0_opp_table: opp-table-cpu0 { 509 compatible = "operating-points-v2"; 510 opp-shared; 511 512 cpu0_opp_300mhz: opp-300000000 { 513 opp-hz = /bits/ 64 <300000000>; 514 opp-peak-kBps = <800000 9600000>; 515 }; 516 517 cpu0_opp_691mhz: opp-691200000 { 518 opp-hz = /bits/ 64 <691200000>; 519 opp-peak-kBps = <800000 17817600>; 520 }; 521 522 cpu0_opp_806mhz: opp-806400000 { 523 opp-hz = /bits/ 64 <806400000>; 524 opp-peak-kBps = <800000 20889600>; 525 }; 526 527 cpu0_opp_941mhz: opp-940800000 { 528 opp-hz = /bits/ 64 <940800000>; 529 opp-peak-kBps = <1804000 24576000>; 530 }; 531 532 cpu0_opp_1152mhz: opp-1152000000 { 533 opp-hz = /bits/ 64 <1152000000>; 534 opp-peak-kBps = <2188000 27033600>; 535 }; 536 537 cpu0_opp_1325mhz: opp-1324800000 { 538 opp-hz = /bits/ 64 <1324800000>; 539 opp-peak-kBps = <2188000 33792000>; 540 }; 541 542 cpu0_opp_1517mhz: opp-1516800000 { 543 opp-hz = /bits/ 64 <1516800000>; 544 opp-peak-kBps = <3072000 38092800>; 545 }; 546 547 cpu0_opp_1651mhz: opp-1651200000 { 548 opp-hz = /bits/ 64 <1651200000>; 549 opp-peak-kBps = <3072000 41779200>; 550 }; 551 552 cpu0_opp_1805mhz: opp-1804800000 { 553 opp-hz = /bits/ 64 <1804800000>; 554 opp-peak-kBps = <4068000 48537600>; 555 }; 556 557 cpu0_opp_1958mhz: opp-1958400000 { 558 opp-hz = /bits/ 64 <1958400000>; 559 opp-peak-kBps = <4068000 48537600>; 560 }; 561 562 cpu0_opp_2016mhz: opp-2016000000 { 563 opp-hz = /bits/ 64 <2016000000>; 564 opp-peak-kBps = <6220000 48537600>; 565 }; 566 }; 567 568 cpu4_opp_table: opp-table-cpu4 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu4_opp_691mhz: opp-691200000 { 573 opp-hz = /bits/ 64 <691200000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu4_opp_941mhz: opp-940800000 { 578 opp-hz = /bits/ 64 <940800000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu4_opp_1229mhz: opp-1228800000 { 583 opp-hz = /bits/ 64 <1228800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu4_opp_1344mhz: opp-1344000000 { 588 opp-hz = /bits/ 64 <1344000000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu4_opp_1517mhz: opp-1516800000 { 593 opp-hz = /bits/ 64 <1516800000>; 594 opp-peak-kBps = <4068000 24576000>; 595 }; 596 597 cpu4_opp_1651mhz: opp-1651200000 { 598 opp-hz = /bits/ 64 <1651200000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu4_opp_1901mhz: opp-1900800000 { 603 opp-hz = /bits/ 64 <1900800000>; 604 opp-peak-kBps = <6220000 44851200>; 605 }; 606 607 cpu4_opp_2054mhz: opp-2054400000 { 608 opp-hz = /bits/ 64 <2054400000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu4_opp_2112mhz: opp-2112000000 { 613 opp-hz = /bits/ 64 <2112000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu4_opp_2131mhz: opp-2131200000 { 618 opp-hz = /bits/ 64 <2131200000>; 619 opp-peak-kBps = <6220000 44851200>; 620 }; 621 622 cpu4_opp_2208mhz: opp-2208000000 { 623 opp-hz = /bits/ 64 <2208000000>; 624 opp-peak-kBps = <6220000 44851200>; 625 }; 626 627 cpu4_opp_2400mhz: opp-2400000000 { 628 opp-hz = /bits/ 64 <2400000000>; 629 opp-peak-kBps = <12787200 48537600>; 630 }; 631 632 cpu4_opp_2611mhz: opp-2611200000 { 633 opp-hz = /bits/ 64 <2611200000>; 634 opp-peak-kBps = <12787200 48537600>; 635 }; 636 }; 637 638 cpu7_opp_table: opp-table-cpu7 { 639 compatible = "operating-points-v2"; 640 opp-shared; 641 642 cpu7_opp_806mhz: opp-806400000 { 643 opp-hz = /bits/ 64 <806400000>; 644 opp-peak-kBps = <1804000 9600000>; 645 }; 646 647 cpu7_opp_1056mhz: opp-1056000000 { 648 opp-hz = /bits/ 64 <1056000000>; 649 opp-peak-kBps = <2188000 17817600>; 650 }; 651 652 cpu7_opp_1325mhz: opp-1324800000 { 653 opp-hz = /bits/ 64 <1324800000>; 654 opp-peak-kBps = <4068000 24576000>; 655 }; 656 657 cpu7_opp_1517mhz: opp-1516800000 { 658 opp-hz = /bits/ 64 <1516800000>; 659 opp-peak-kBps = <4068000 24576000>; 660 }; 661 662 cpu7_opp_1766mhz: opp-1766400000 { 663 opp-hz = /bits/ 64 <1766400000>; 664 opp-peak-kBps = <6220000 38092800>; 665 }; 666 667 cpu7_opp_1862mhz: opp-1862400000 { 668 opp-hz = /bits/ 64 <1862400000>; 669 opp-peak-kBps = <6220000 38092800>; 670 }; 671 672 cpu7_opp_2035mhz: opp-2035200000 { 673 opp-hz = /bits/ 64 <2035200000>; 674 opp-peak-kBps = <6220000 38092800>; 675 }; 676 677 cpu7_opp_2112mhz: opp-2112000000 { 678 opp-hz = /bits/ 64 <2112000000>; 679 opp-peak-kBps = <6220000 44851200>; 680 }; 681 682 cpu7_opp_2208mhz: opp-2208000000 { 683 opp-hz = /bits/ 64 <2208000000>; 684 opp-peak-kBps = <6220000 44851200>; 685 }; 686 687 cpu7_opp_2381mhz: opp-2380800000 { 688 opp-hz = /bits/ 64 <2380800000>; 689 opp-peak-kBps = <6832000 44851200>; 690 }; 691 692 cpu7_opp_2400mhz: opp-2400000000 { 693 opp-hz = /bits/ 64 <2400000000>; 694 opp-peak-kBps = <12787200 48537600>; 695 }; 696 697 cpu7_opp_2515mhz: opp-2515200000 { 698 opp-hz = /bits/ 64 <2515200000>; 699 opp-peak-kBps = <12787200 48537600>; 700 }; 701 702 cpu7_opp_2707mhz: opp-2707200000 { 703 opp-hz = /bits/ 64 <2707200000>; 704 opp-peak-kBps = <12787200 48537600>; 705 }; 706 707 cpu7_opp_3014mhz: opp-3014400000 { 708 opp-hz = /bits/ 64 <3014400000>; 709 opp-peak-kBps = <12787200 48537600>; 710 }; 711 }; 712 713 memory@80000000 { 714 device_type = "memory"; 715 /* We expect the bootloader to fill in the size */ 716 reg = <0 0x80000000 0 0>; 717 }; 718 719 firmware { 720 scm: scm { 721 compatible = "qcom,scm-sc7280", "qcom,scm"; 722 qcom,dload-mode = <&tcsr_2 0x13000>; 723 }; 724 }; 725 726 clk_virt: interconnect { 727 compatible = "qcom,sc7280-clk-virt"; 728 #interconnect-cells = <2>; 729 qcom,bcm-voters = <&apps_bcm_voter>; 730 }; 731 732 smem { 733 compatible = "qcom,smem"; 734 memory-region = <&smem_mem>; 735 hwlocks = <&tcsr_mutex 3>; 736 }; 737 738 smp2p-adsp { 739 compatible = "qcom,smp2p"; 740 qcom,smem = <443>, <429>; 741 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P 743 IRQ_TYPE_EDGE_RISING>; 744 mboxes = <&ipcc IPCC_CLIENT_LPASS 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,local-pid = <0>; 748 qcom,remote-pid = <2>; 749 750 adsp_smp2p_out: master-kernel { 751 qcom,entry-name = "master-kernel"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 adsp_smp2p_in: slave-kernel { 756 qcom,entry-name = "slave-kernel"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 }; 761 762 smp2p-cdsp { 763 compatible = "qcom,smp2p"; 764 qcom,smem = <94>, <432>; 765 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P 767 IRQ_TYPE_EDGE_RISING>; 768 mboxes = <&ipcc IPCC_CLIENT_CDSP 769 IPCC_MPROC_SIGNAL_SMP2P>; 770 771 qcom,local-pid = <0>; 772 qcom,remote-pid = <5>; 773 774 cdsp_smp2p_out: master-kernel { 775 qcom,entry-name = "master-kernel"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 cdsp_smp2p_in: slave-kernel { 780 qcom,entry-name = "slave-kernel"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 }; 785 786 smp2p-mpss { 787 compatible = "qcom,smp2p"; 788 qcom,smem = <435>, <428>; 789 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P 791 IRQ_TYPE_EDGE_RISING>; 792 mboxes = <&ipcc IPCC_CLIENT_MPSS 793 IPCC_MPROC_SIGNAL_SMP2P>; 794 795 qcom,local-pid = <0>; 796 qcom,remote-pid = <1>; 797 798 modem_smp2p_out: master-kernel { 799 qcom,entry-name = "master-kernel"; 800 #qcom,smem-state-cells = <1>; 801 }; 802 803 modem_smp2p_in: slave-kernel { 804 qcom,entry-name = "slave-kernel"; 805 interrupt-controller; 806 #interrupt-cells = <2>; 807 }; 808 809 ipa_smp2p_out: ipa-ap-to-modem { 810 qcom,entry-name = "ipa"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 ipa_smp2p_in: ipa-modem-to-ap { 815 qcom,entry-name = "ipa"; 816 interrupt-controller; 817 #interrupt-cells = <2>; 818 }; 819 }; 820 821 smp2p-wpss { 822 compatible = "qcom,smp2p"; 823 qcom,smem = <617>, <616>; 824 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 825 IPCC_MPROC_SIGNAL_SMP2P 826 IRQ_TYPE_EDGE_RISING>; 827 mboxes = <&ipcc IPCC_CLIENT_WPSS 828 IPCC_MPROC_SIGNAL_SMP2P>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <13>; 832 833 wpss_smp2p_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 wpss_smp2p_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 interrupt-controller; 841 #interrupt-cells = <2>; 842 }; 843 844 wlan_smp2p_out: wlan-ap-to-wpss { 845 qcom,entry-name = "wlan"; 846 #qcom,smem-state-cells = <1>; 847 }; 848 849 wlan_smp2p_in: wlan-wpss-to-ap { 850 qcom,entry-name = "wlan"; 851 interrupt-controller; 852 #interrupt-cells = <2>; 853 }; 854 }; 855 856 pmu-a55 { 857 compatible = "arm,cortex-a55-pmu"; 858 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 859 }; 860 861 pmu-a78 { 862 compatible = "arm,cortex-a78-pmu"; 863 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 864 }; 865 866 psci { 867 compatible = "arm,psci-1.0"; 868 method = "smc"; 869 870 cpu_pd0: power-domain-cpu0 { 871 #power-domain-cells = <0>; 872 power-domains = <&cluster_pd>; 873 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 874 }; 875 876 cpu_pd1: power-domain-cpu1 { 877 #power-domain-cells = <0>; 878 power-domains = <&cluster_pd>; 879 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 880 }; 881 882 cpu_pd2: power-domain-cpu2 { 883 #power-domain-cells = <0>; 884 power-domains = <&cluster_pd>; 885 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 886 }; 887 888 cpu_pd3: power-domain-cpu3 { 889 #power-domain-cells = <0>; 890 power-domains = <&cluster_pd>; 891 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 892 }; 893 894 cpu_pd4: power-domain-cpu4 { 895 #power-domain-cells = <0>; 896 power-domains = <&cluster_pd>; 897 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 898 }; 899 900 cpu_pd5: power-domain-cpu5 { 901 #power-domain-cells = <0>; 902 power-domains = <&cluster_pd>; 903 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 904 }; 905 906 cpu_pd6: power-domain-cpu6 { 907 #power-domain-cells = <0>; 908 power-domains = <&cluster_pd>; 909 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 910 }; 911 912 cpu_pd7: power-domain-cpu7 { 913 #power-domain-cells = <0>; 914 power-domains = <&cluster_pd>; 915 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 916 }; 917 918 cluster_pd: power-domain-cluster { 919 #power-domain-cells = <0>; 920 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 921 }; 922 }; 923 924 qspi_opp_table: opp-table-qspi { 925 compatible = "operating-points-v2"; 926 927 opp-75000000 { 928 opp-hz = /bits/ 64 <75000000>; 929 required-opps = <&rpmhpd_opp_low_svs>; 930 }; 931 932 opp-150000000 { 933 opp-hz = /bits/ 64 <150000000>; 934 required-opps = <&rpmhpd_opp_svs>; 935 }; 936 937 opp-200000000 { 938 opp-hz = /bits/ 64 <200000000>; 939 required-opps = <&rpmhpd_opp_svs_l1>; 940 }; 941 942 opp-300000000 { 943 opp-hz = /bits/ 64 <300000000>; 944 required-opps = <&rpmhpd_opp_nom>; 945 }; 946 }; 947 948 qup_opp_table: opp-table-qup { 949 compatible = "operating-points-v2"; 950 951 opp-75000000 { 952 opp-hz = /bits/ 64 <75000000>; 953 required-opps = <&rpmhpd_opp_low_svs>; 954 }; 955 956 opp-100000000 { 957 opp-hz = /bits/ 64 <100000000>; 958 required-opps = <&rpmhpd_opp_svs>; 959 }; 960 961 opp-128000000 { 962 opp-hz = /bits/ 64 <128000000>; 963 required-opps = <&rpmhpd_opp_nom>; 964 }; 965 }; 966 967 soc: soc@0 { 968 #address-cells = <2>; 969 #size-cells = <2>; 970 ranges = <0 0 0 0 0x10 0>; 971 dma-ranges = <0 0 0 0 0x10 0>; 972 compatible = "simple-bus"; 973 974 gcc: clock-controller@100000 { 975 compatible = "qcom,gcc-sc7280"; 976 reg = <0 0x00100000 0 0x1f0000>; 977 clocks = <&rpmhcc RPMH_CXO_CLK>, 978 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 979 <0>, <&pcie1_phy>, 980 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 981 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 982 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 983 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 984 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 985 "ufs_phy_tx_symbol_0_clk", 986 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 987 #clock-cells = <1>; 988 #reset-cells = <1>; 989 #power-domain-cells = <1>; 990 power-domains = <&rpmhpd SC7280_CX>; 991 }; 992 993 ipcc: mailbox@408000 { 994 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 995 reg = <0 0x00408000 0 0x1000>; 996 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-controller; 998 #interrupt-cells = <3>; 999 #mbox-cells = <2>; 1000 }; 1001 1002 qfprom: efuse@784000 { 1003 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 1004 reg = <0 0x00784000 0 0xa20>, 1005 <0 0x00780000 0 0xa20>, 1006 <0 0x00782000 0 0x120>, 1007 <0 0x00786000 0 0x1fff>; 1008 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1009 clock-names = "core"; 1010 power-domains = <&rpmhpd SC7280_MX>; 1011 #address-cells = <1>; 1012 #size-cells = <1>; 1013 1014 gpu_speed_bin: gpu-speed-bin@1e9 { 1015 reg = <0x1e9 0x2>; 1016 bits = <5 8>; 1017 }; 1018 }; 1019 1020 sdhc_1: mmc@7c4000 { 1021 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1022 pinctrl-names = "default", "sleep"; 1023 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1024 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1025 status = "disabled"; 1026 1027 reg = <0 0x007c4000 0 0x1000>, 1028 <0 0x007c5000 0 0x1000>; 1029 reg-names = "hc", "cqhci"; 1030 1031 iommus = <&apps_smmu 0xc0 0x0>; 1032 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1034 interrupt-names = "hc_irq", "pwr_irq"; 1035 1036 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1037 <&gcc GCC_SDCC1_APPS_CLK>, 1038 <&rpmhcc RPMH_CXO_CLK>; 1039 clock-names = "iface", "core", "xo"; 1040 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1042 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1043 power-domains = <&rpmhpd SC7280_CX>; 1044 operating-points-v2 = <&sdhc1_opp_table>; 1045 1046 bus-width = <8>; 1047 supports-cqe; 1048 dma-coherent; 1049 1050 qcom,dll-config = <0x0007642c>; 1051 qcom,ddr-config = <0x80040868>; 1052 1053 mmc-ddr-1_8v; 1054 mmc-hs200-1_8v; 1055 mmc-hs400-1_8v; 1056 mmc-hs400-enhanced-strobe; 1057 1058 resets = <&gcc GCC_SDCC1_BCR>; 1059 1060 sdhc1_opp_table: opp-table { 1061 compatible = "operating-points-v2"; 1062 1063 opp-100000000 { 1064 opp-hz = /bits/ 64 <100000000>; 1065 required-opps = <&rpmhpd_opp_low_svs>; 1066 opp-peak-kBps = <1800000 400000>; 1067 opp-avg-kBps = <100000 0>; 1068 }; 1069 1070 opp-384000000 { 1071 opp-hz = /bits/ 64 <384000000>; 1072 required-opps = <&rpmhpd_opp_nom>; 1073 opp-peak-kBps = <5400000 1600000>; 1074 opp-avg-kBps = <390000 0>; 1075 }; 1076 }; 1077 }; 1078 1079 gpi_dma0: dma-controller@900000 { 1080 #dma-cells = <3>; 1081 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1082 reg = <0 0x00900000 0 0x60000>; 1083 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1095 dma-channels = <12>; 1096 dma-channel-mask = <0x7f>; 1097 iommus = <&apps_smmu 0x0136 0x0>; 1098 status = "disabled"; 1099 }; 1100 1101 qupv3_id_0: geniqup@9c0000 { 1102 compatible = "qcom,geni-se-qup"; 1103 reg = <0 0x009c0000 0 0x2000>; 1104 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1105 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1106 clock-names = "m-ahb", "s-ahb"; 1107 #address-cells = <2>; 1108 #size-cells = <2>; 1109 ranges; 1110 iommus = <&apps_smmu 0x123 0x0>; 1111 status = "disabled"; 1112 1113 i2c0: i2c@980000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00980000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_i2c0_data_clk>; 1120 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1125 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1126 interconnect-names = "qup-core", "qup-config", 1127 "qup-memory"; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 required-opps = <&rpmhpd_opp_low_svs>; 1130 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1131 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1132 dma-names = "tx", "rx"; 1133 status = "disabled"; 1134 }; 1135 1136 spi0: spi@980000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00980000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1143 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 power-domains = <&rpmhpd SC7280_CX>; 1147 operating-points-v2 = <&qup_opp_table>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 status = "disabled"; 1155 }; 1156 1157 uart0: serial@980000 { 1158 compatible = "qcom,geni-uart"; 1159 reg = <0 0x00980000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1164 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&rpmhpd SC7280_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1169 interconnect-names = "qup-core", "qup-config"; 1170 status = "disabled"; 1171 }; 1172 1173 i2c1: i2c@984000 { 1174 compatible = "qcom,geni-i2c"; 1175 reg = <0 0x00984000 0 0x4000>; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1177 clock-names = "se"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&qup_i2c1_data_clk>; 1180 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1184 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1185 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1186 interconnect-names = "qup-core", "qup-config", 1187 "qup-memory"; 1188 power-domains = <&rpmhpd SC7280_CX>; 1189 required-opps = <&rpmhpd_opp_low_svs>; 1190 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1191 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1192 dma-names = "tx", "rx"; 1193 status = "disabled"; 1194 }; 1195 1196 spi1: spi@984000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x00984000 0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1200 clock-names = "se"; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1203 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 power-domains = <&rpmhpd SC7280_CX>; 1207 operating-points-v2 = <&qup_opp_table>; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1209 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1210 interconnect-names = "qup-core", "qup-config"; 1211 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 status = "disabled"; 1215 }; 1216 1217 uart1: serial@984000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x00984000 0 0x4000>; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1221 clock-names = "se"; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1224 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC7280_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c2: i2c@988000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00988000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_i2c2_data_clk>; 1240 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1245 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1246 interconnect-names = "qup-core", "qup-config", 1247 "qup-memory"; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 required-opps = <&rpmhpd_opp_low_svs>; 1250 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1251 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 status = "disabled"; 1254 }; 1255 1256 spi2: spi@988000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0 0x00988000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1263 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 power-domains = <&rpmhpd SC7280_CX>; 1267 operating-points-v2 = <&qup_opp_table>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1272 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1273 dma-names = "tx", "rx"; 1274 status = "disabled"; 1275 }; 1276 1277 uart2: serial@988000 { 1278 compatible = "qcom,geni-uart"; 1279 reg = <0 0x00988000 0 0x4000>; 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1281 clock-names = "se"; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1284 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SC7280_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1288 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1289 interconnect-names = "qup-core", "qup-config"; 1290 status = "disabled"; 1291 }; 1292 1293 i2c3: i2c@98c000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x0098c000 0 0x4000>; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1297 clock-names = "se"; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_i2c3_data_clk>; 1300 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1304 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1305 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1306 interconnect-names = "qup-core", "qup-config", 1307 "qup-memory"; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 required-opps = <&rpmhpd_opp_low_svs>; 1310 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1311 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 spi3: spi@98c000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x0098c000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1320 clock-names = "se"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1323 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 power-domains = <&rpmhpd SC7280_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1332 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1333 dma-names = "tx", "rx"; 1334 status = "disabled"; 1335 }; 1336 1337 uart3: serial@98c000 { 1338 compatible = "qcom,geni-uart"; 1339 reg = <0 0x0098c000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1344 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC7280_CX>; 1346 operating-points-v2 = <&qup_opp_table>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1349 interconnect-names = "qup-core", "qup-config"; 1350 status = "disabled"; 1351 }; 1352 1353 i2c4: i2c@990000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0 0x00990000 0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1357 clock-names = "se"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_i2c4_data_clk>; 1360 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", 1367 "qup-memory"; 1368 power-domains = <&rpmhpd SC7280_CX>; 1369 required-opps = <&rpmhpd_opp_low_svs>; 1370 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 status = "disabled"; 1374 }; 1375 1376 spi4: spi@990000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x00990000 0 0x4000>; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1380 clock-names = "se"; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1383 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 power-domains = <&rpmhpd SC7280_CX>; 1387 operating-points-v2 = <&qup_opp_table>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1390 interconnect-names = "qup-core", "qup-config"; 1391 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 status = "disabled"; 1395 }; 1396 1397 uart4: serial@990000 { 1398 compatible = "qcom,geni-uart"; 1399 reg = <0 0x00990000 0 0x4000>; 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1401 clock-names = "se"; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1404 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1405 power-domains = <&rpmhpd SC7280_CX>; 1406 operating-points-v2 = <&qup_opp_table>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1409 interconnect-names = "qup-core", "qup-config"; 1410 status = "disabled"; 1411 }; 1412 1413 i2c5: i2c@994000 { 1414 compatible = "qcom,geni-i2c"; 1415 reg = <0 0x00994000 0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1417 clock-names = "se"; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_i2c5_data_clk>; 1420 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1424 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1425 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1426 interconnect-names = "qup-core", "qup-config", 1427 "qup-memory"; 1428 power-domains = <&rpmhpd SC7280_CX>; 1429 required-opps = <&rpmhpd_opp_low_svs>; 1430 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1431 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1432 dma-names = "tx", "rx"; 1433 status = "disabled"; 1434 }; 1435 1436 spi5: spi@994000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00994000 0 0x4000>; 1439 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1440 clock-names = "se"; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1443 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 power-domains = <&rpmhpd SC7280_CX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1449 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1450 interconnect-names = "qup-core", "qup-config"; 1451 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1452 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1453 dma-names = "tx", "rx"; 1454 status = "disabled"; 1455 }; 1456 1457 uart5: serial@994000 { 1458 compatible = "qcom,geni-debug-uart"; 1459 reg = <0 0x00994000 0 0x4000>; 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1461 clock-names = "se"; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1464 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1465 power-domains = <&rpmhpd SC7280_CX>; 1466 operating-points-v2 = <&qup_opp_table>; 1467 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1468 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1469 interconnect-names = "qup-core", "qup-config"; 1470 status = "disabled"; 1471 }; 1472 1473 i2c6: i2c@998000 { 1474 compatible = "qcom,geni-i2c"; 1475 reg = <0 0x00998000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1477 clock-names = "se"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_i2c6_data_clk>; 1480 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1484 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1485 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1486 interconnect-names = "qup-core", "qup-config", 1487 "qup-memory"; 1488 power-domains = <&rpmhpd SC7280_CX>; 1489 required-opps = <&rpmhpd_opp_low_svs>; 1490 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1491 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 spi6: spi@998000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00998000 0 0x4000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1500 clock-names = "se"; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1503 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 power-domains = <&rpmhpd SC7280_CX>; 1507 operating-points-v2 = <&qup_opp_table>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1509 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1510 interconnect-names = "qup-core", "qup-config"; 1511 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1512 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1513 dma-names = "tx", "rx"; 1514 status = "disabled"; 1515 }; 1516 1517 uart6: serial@998000 { 1518 compatible = "qcom,geni-uart"; 1519 reg = <0 0x00998000 0 0x4000>; 1520 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1521 clock-names = "se"; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1524 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1525 power-domains = <&rpmhpd SC7280_CX>; 1526 operating-points-v2 = <&qup_opp_table>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1529 interconnect-names = "qup-core", "qup-config"; 1530 status = "disabled"; 1531 }; 1532 1533 i2c7: i2c@99c000 { 1534 compatible = "qcom,geni-i2c"; 1535 reg = <0 0x0099c000 0 0x4000>; 1536 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1537 clock-names = "se"; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_i2c7_data_clk>; 1540 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1545 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", 1547 "qup-memory"; 1548 power-domains = <&rpmhpd SC7280_CX>; 1549 required-opps = <&rpmhpd_opp_low_svs>; 1550 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1551 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1552 dma-names = "tx", "rx"; 1553 status = "disabled"; 1554 }; 1555 1556 spi7: spi@99c000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x0099c000 0 0x4000>; 1559 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1560 clock-names = "se"; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1563 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 power-domains = <&rpmhpd SC7280_CX>; 1567 operating-points-v2 = <&qup_opp_table>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1570 interconnect-names = "qup-core", "qup-config"; 1571 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1572 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1573 dma-names = "tx", "rx"; 1574 status = "disabled"; 1575 }; 1576 1577 uart7: serial@99c000 { 1578 compatible = "qcom,geni-uart"; 1579 reg = <0 0x0099c000 0 0x4000>; 1580 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1581 clock-names = "se"; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1584 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1585 power-domains = <&rpmhpd SC7280_CX>; 1586 operating-points-v2 = <&qup_opp_table>; 1587 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1588 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1589 interconnect-names = "qup-core", "qup-config"; 1590 status = "disabled"; 1591 }; 1592 }; 1593 1594 gpi_dma1: dma-controller@a00000 { 1595 #dma-cells = <3>; 1596 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1597 reg = <0 0x00a00000 0 0x60000>; 1598 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1610 dma-channels = <12>; 1611 dma-channel-mask = <0x1e>; 1612 iommus = <&apps_smmu 0x56 0x0>; 1613 status = "disabled"; 1614 }; 1615 1616 qupv3_id_1: geniqup@ac0000 { 1617 compatible = "qcom,geni-se-qup"; 1618 reg = <0 0x00ac0000 0 0x2000>; 1619 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1620 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1621 clock-names = "m-ahb", "s-ahb"; 1622 #address-cells = <2>; 1623 #size-cells = <2>; 1624 ranges; 1625 iommus = <&apps_smmu 0x43 0x0>; 1626 status = "disabled"; 1627 1628 i2c8: i2c@a80000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a80000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c8_data_clk>; 1635 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", 1642 "qup-memory"; 1643 power-domains = <&rpmhpd SC7280_CX>; 1644 required-opps = <&rpmhpd_opp_low_svs>; 1645 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1646 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1647 dma-names = "tx", "rx"; 1648 status = "disabled"; 1649 }; 1650 1651 spi8: spi@a80000 { 1652 compatible = "qcom,geni-spi"; 1653 reg = <0 0x00a80000 0 0x4000>; 1654 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1655 clock-names = "se"; 1656 pinctrl-names = "default"; 1657 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1658 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 power-domains = <&rpmhpd SC7280_CX>; 1662 operating-points-v2 = <&qup_opp_table>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1665 interconnect-names = "qup-core", "qup-config"; 1666 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1667 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1668 dma-names = "tx", "rx"; 1669 status = "disabled"; 1670 }; 1671 1672 uart8: serial@a80000 { 1673 compatible = "qcom,geni-uart"; 1674 reg = <0 0x00a80000 0 0x4000>; 1675 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1676 clock-names = "se"; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1679 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC7280_CX>; 1681 operating-points-v2 = <&qup_opp_table>; 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1683 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1684 interconnect-names = "qup-core", "qup-config"; 1685 status = "disabled"; 1686 }; 1687 1688 i2c9: i2c@a84000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0 0x00a84000 0 0x4000>; 1691 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1692 clock-names = "se"; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_i2c9_data_clk>; 1695 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1699 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1700 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1701 interconnect-names = "qup-core", "qup-config", 1702 "qup-memory"; 1703 power-domains = <&rpmhpd SC7280_CX>; 1704 required-opps = <&rpmhpd_opp_low_svs>; 1705 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1706 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1707 dma-names = "tx", "rx"; 1708 status = "disabled"; 1709 }; 1710 1711 spi9: spi@a84000 { 1712 compatible = "qcom,geni-spi"; 1713 reg = <0 0x00a84000 0 0x4000>; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1715 clock-names = "se"; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1718 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 power-domains = <&rpmhpd SC7280_CX>; 1722 operating-points-v2 = <&qup_opp_table>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1725 interconnect-names = "qup-core", "qup-config"; 1726 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1727 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1728 dma-names = "tx", "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 uart9: serial@a84000 { 1733 compatible = "qcom,geni-uart"; 1734 reg = <0 0x00a84000 0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1736 clock-names = "se"; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1739 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1740 power-domains = <&rpmhpd SC7280_CX>; 1741 operating-points-v2 = <&qup_opp_table>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1743 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1744 interconnect-names = "qup-core", "qup-config"; 1745 status = "disabled"; 1746 }; 1747 1748 i2c10: i2c@a88000 { 1749 compatible = "qcom,geni-i2c"; 1750 reg = <0 0x00a88000 0 0x4000>; 1751 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1752 clock-names = "se"; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&qup_i2c10_data_clk>; 1755 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1760 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1761 interconnect-names = "qup-core", "qup-config", 1762 "qup-memory"; 1763 power-domains = <&rpmhpd SC7280_CX>; 1764 required-opps = <&rpmhpd_opp_low_svs>; 1765 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1767 dma-names = "tx", "rx"; 1768 status = "disabled"; 1769 }; 1770 1771 spi10: spi@a88000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a88000 0 0x4000>; 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1775 clock-names = "se"; 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1778 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 power-domains = <&rpmhpd SC7280_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1784 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1785 interconnect-names = "qup-core", "qup-config"; 1786 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1787 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1788 dma-names = "tx", "rx"; 1789 status = "disabled"; 1790 }; 1791 1792 uart10: serial@a88000 { 1793 compatible = "qcom,geni-uart"; 1794 reg = <0 0x00a88000 0 0x4000>; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1796 clock-names = "se"; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1799 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1800 power-domains = <&rpmhpd SC7280_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1803 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1804 interconnect-names = "qup-core", "qup-config"; 1805 status = "disabled"; 1806 }; 1807 1808 i2c11: i2c@a8c000 { 1809 compatible = "qcom,geni-i2c"; 1810 reg = <0 0x00a8c000 0 0x4000>; 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1812 clock-names = "se"; 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&qup_i2c11_data_clk>; 1815 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1819 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1820 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1821 interconnect-names = "qup-core", "qup-config", 1822 "qup-memory"; 1823 power-domains = <&rpmhpd SC7280_CX>; 1824 required-opps = <&rpmhpd_opp_low_svs>; 1825 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1827 dma-names = "tx", "rx"; 1828 status = "disabled"; 1829 }; 1830 1831 spi11: spi@a8c000 { 1832 compatible = "qcom,geni-spi"; 1833 reg = <0 0x00a8c000 0 0x4000>; 1834 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1835 clock-names = "se"; 1836 pinctrl-names = "default"; 1837 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1838 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 power-domains = <&rpmhpd SC7280_CX>; 1842 operating-points-v2 = <&qup_opp_table>; 1843 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1844 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1845 interconnect-names = "qup-core", "qup-config"; 1846 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1847 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1848 dma-names = "tx", "rx"; 1849 status = "disabled"; 1850 }; 1851 1852 uart11: serial@a8c000 { 1853 compatible = "qcom,geni-uart"; 1854 reg = <0 0x00a8c000 0 0x4000>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1856 clock-names = "se"; 1857 pinctrl-names = "default"; 1858 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1859 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1860 power-domains = <&rpmhpd SC7280_CX>; 1861 operating-points-v2 = <&qup_opp_table>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1863 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1864 interconnect-names = "qup-core", "qup-config"; 1865 status = "disabled"; 1866 }; 1867 1868 i2c12: i2c@a90000 { 1869 compatible = "qcom,geni-i2c"; 1870 reg = <0 0x00a90000 0 0x4000>; 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1872 clock-names = "se"; 1873 pinctrl-names = "default"; 1874 pinctrl-0 = <&qup_i2c12_data_clk>; 1875 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1879 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1880 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1881 interconnect-names = "qup-core", "qup-config", 1882 "qup-memory"; 1883 power-domains = <&rpmhpd SC7280_CX>; 1884 required-opps = <&rpmhpd_opp_low_svs>; 1885 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1886 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1887 dma-names = "tx", "rx"; 1888 status = "disabled"; 1889 }; 1890 1891 spi12: spi@a90000 { 1892 compatible = "qcom,geni-spi"; 1893 reg = <0 0x00a90000 0 0x4000>; 1894 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1895 clock-names = "se"; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1898 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 power-domains = <&rpmhpd SC7280_CX>; 1902 operating-points-v2 = <&qup_opp_table>; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1904 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1905 interconnect-names = "qup-core", "qup-config"; 1906 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1907 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1908 dma-names = "tx", "rx"; 1909 status = "disabled"; 1910 }; 1911 1912 uart12: serial@a90000 { 1913 compatible = "qcom,geni-uart"; 1914 reg = <0 0x00a90000 0 0x4000>; 1915 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1916 clock-names = "se"; 1917 pinctrl-names = "default"; 1918 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1919 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1920 power-domains = <&rpmhpd SC7280_CX>; 1921 operating-points-v2 = <&qup_opp_table>; 1922 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1923 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1924 interconnect-names = "qup-core", "qup-config"; 1925 status = "disabled"; 1926 }; 1927 1928 i2c13: i2c@a94000 { 1929 compatible = "qcom,geni-i2c"; 1930 reg = <0 0x00a94000 0 0x4000>; 1931 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1932 clock-names = "se"; 1933 pinctrl-names = "default"; 1934 pinctrl-0 = <&qup_i2c13_data_clk>; 1935 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1936 #address-cells = <1>; 1937 #size-cells = <0>; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1939 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1940 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1941 interconnect-names = "qup-core", "qup-config", 1942 "qup-memory"; 1943 power-domains = <&rpmhpd SC7280_CX>; 1944 required-opps = <&rpmhpd_opp_low_svs>; 1945 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1946 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1947 dma-names = "tx", "rx"; 1948 status = "disabled"; 1949 }; 1950 1951 spi13: spi@a94000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0 0x00a94000 0 0x4000>; 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1955 clock-names = "se"; 1956 pinctrl-names = "default"; 1957 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1958 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 power-domains = <&rpmhpd SC7280_CX>; 1962 operating-points-v2 = <&qup_opp_table>; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1965 interconnect-names = "qup-core", "qup-config"; 1966 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1967 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1968 dma-names = "tx", "rx"; 1969 status = "disabled"; 1970 }; 1971 1972 uart13: serial@a94000 { 1973 compatible = "qcom,geni-uart"; 1974 reg = <0 0x00a94000 0 0x4000>; 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1976 clock-names = "se"; 1977 pinctrl-names = "default"; 1978 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1979 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1980 power-domains = <&rpmhpd SC7280_CX>; 1981 operating-points-v2 = <&qup_opp_table>; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1984 interconnect-names = "qup-core", "qup-config"; 1985 status = "disabled"; 1986 }; 1987 1988 i2c14: i2c@a98000 { 1989 compatible = "qcom,geni-i2c"; 1990 reg = <0 0x00a98000 0 0x4000>; 1991 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1992 clock-names = "se"; 1993 pinctrl-names = "default"; 1994 pinctrl-0 = <&qup_i2c14_data_clk>; 1995 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1999 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2000 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2001 interconnect-names = "qup-core", "qup-config", 2002 "qup-memory"; 2003 power-domains = <&rpmhpd SC7280_CX>; 2004 required-opps = <&rpmhpd_opp_low_svs>; 2005 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2006 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2007 dma-names = "tx", "rx"; 2008 status = "disabled"; 2009 }; 2010 2011 spi14: spi@a98000 { 2012 compatible = "qcom,geni-spi"; 2013 reg = <0 0x00a98000 0 0x4000>; 2014 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2015 clock-names = "se"; 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2018 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2019 #address-cells = <1>; 2020 #size-cells = <0>; 2021 power-domains = <&rpmhpd SC7280_CX>; 2022 operating-points-v2 = <&qup_opp_table>; 2023 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2025 interconnect-names = "qup-core", "qup-config"; 2026 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2027 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2028 dma-names = "tx", "rx"; 2029 status = "disabled"; 2030 }; 2031 2032 uart14: serial@a98000 { 2033 compatible = "qcom,geni-uart"; 2034 reg = <0 0x00a98000 0 0x4000>; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2036 clock-names = "se"; 2037 pinctrl-names = "default"; 2038 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2039 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2040 power-domains = <&rpmhpd SC7280_CX>; 2041 operating-points-v2 = <&qup_opp_table>; 2042 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2043 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2044 interconnect-names = "qup-core", "qup-config"; 2045 status = "disabled"; 2046 }; 2047 2048 i2c15: i2c@a9c000 { 2049 compatible = "qcom,geni-i2c"; 2050 reg = <0 0x00a9c000 0 0x4000>; 2051 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2052 clock-names = "se"; 2053 pinctrl-names = "default"; 2054 pinctrl-0 = <&qup_i2c15_data_clk>; 2055 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2056 #address-cells = <1>; 2057 #size-cells = <0>; 2058 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2059 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2060 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2061 interconnect-names = "qup-core", "qup-config", 2062 "qup-memory"; 2063 power-domains = <&rpmhpd SC7280_CX>; 2064 required-opps = <&rpmhpd_opp_low_svs>; 2065 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2067 dma-names = "tx", "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi15: spi@a9c000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0 0x00a9c000 0 0x4000>; 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2075 clock-names = "se"; 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2078 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 power-domains = <&rpmhpd SC7280_CX>; 2082 operating-points-v2 = <&qup_opp_table>; 2083 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2084 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2085 interconnect-names = "qup-core", "qup-config"; 2086 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2087 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2088 dma-names = "tx", "rx"; 2089 status = "disabled"; 2090 }; 2091 2092 uart15: serial@a9c000 { 2093 compatible = "qcom,geni-uart"; 2094 reg = <0 0x00a9c000 0 0x4000>; 2095 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2096 clock-names = "se"; 2097 pinctrl-names = "default"; 2098 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2099 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2100 power-domains = <&rpmhpd SC7280_CX>; 2101 operating-points-v2 = <&qup_opp_table>; 2102 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2104 interconnect-names = "qup-core", "qup-config"; 2105 status = "disabled"; 2106 }; 2107 }; 2108 2109 rng: rng@10d3000 { 2110 compatible = "qcom,sc7280-trng", "qcom,trng"; 2111 reg = <0 0x010d3000 0 0x1000>; 2112 }; 2113 2114 cnoc2: interconnect@1500000 { 2115 reg = <0 0x01500000 0 0x1000>; 2116 compatible = "qcom,sc7280-cnoc2"; 2117 #interconnect-cells = <2>; 2118 qcom,bcm-voters = <&apps_bcm_voter>; 2119 }; 2120 2121 cnoc3: interconnect@1502000 { 2122 reg = <0 0x01502000 0 0x1000>; 2123 compatible = "qcom,sc7280-cnoc3"; 2124 #interconnect-cells = <2>; 2125 qcom,bcm-voters = <&apps_bcm_voter>; 2126 }; 2127 2128 mc_virt: interconnect@1580000 { 2129 reg = <0 0x01580000 0 0x4>; 2130 compatible = "qcom,sc7280-mc-virt"; 2131 #interconnect-cells = <2>; 2132 qcom,bcm-voters = <&apps_bcm_voter>; 2133 }; 2134 2135 system_noc: interconnect@1680000 { 2136 reg = <0 0x01680000 0 0x15480>; 2137 compatible = "qcom,sc7280-system-noc"; 2138 #interconnect-cells = <2>; 2139 qcom,bcm-voters = <&apps_bcm_voter>; 2140 }; 2141 2142 aggre1_noc: interconnect@16e0000 { 2143 compatible = "qcom,sc7280-aggre1-noc"; 2144 reg = <0 0x016e0000 0 0x1c080>; 2145 #interconnect-cells = <2>; 2146 qcom,bcm-voters = <&apps_bcm_voter>; 2147 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2148 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2149 }; 2150 2151 aggre2_noc: interconnect@1700000 { 2152 reg = <0 0x01700000 0 0x2b080>; 2153 compatible = "qcom,sc7280-aggre2-noc"; 2154 #interconnect-cells = <2>; 2155 qcom,bcm-voters = <&apps_bcm_voter>; 2156 clocks = <&rpmhcc RPMH_IPA_CLK>; 2157 }; 2158 2159 mmss_noc: interconnect@1740000 { 2160 reg = <0 0x01740000 0 0x1e080>; 2161 compatible = "qcom,sc7280-mmss-noc"; 2162 #interconnect-cells = <2>; 2163 qcom,bcm-voters = <&apps_bcm_voter>; 2164 }; 2165 2166 wifi: wifi@17a10040 { 2167 compatible = "qcom,wcn6750-wifi"; 2168 reg = <0 0x17a10040 0 0x0>; 2169 iommus = <&apps_smmu 0x1c00 0x1>; 2170 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2196 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2197 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2198 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2199 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2200 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2201 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2202 qcom,rproc = <&remoteproc_wpss>; 2203 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2204 status = "disabled"; 2205 qcom,smem-states = <&wlan_smp2p_out 0>; 2206 qcom,smem-state-names = "wlan-smp2p-out"; 2207 }; 2208 2209 pcie0: pcie@1c00000 { 2210 compatible = "qcom,pcie-sc7280"; 2211 reg = <0 0x01c00000 0 0x3000>, 2212 <0 0x60000000 0 0xf1d>, 2213 <0 0x60000f20 0 0xa8>, 2214 <0 0x60001000 0 0x1000>, 2215 <0 0x60100000 0 0x100000>, 2216 <0 0x01c03000 0 0x1000>; 2217 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2218 device_type = "pci"; 2219 linux,pci-domain = <0>; 2220 bus-range = <0x00 0xff>; 2221 num-lanes = <1>; 2222 2223 #address-cells = <3>; 2224 #size-cells = <2>; 2225 2226 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2227 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2228 2229 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2238 interrupt-names = "msi0", 2239 "msi1", 2240 "msi2", 2241 "msi3", 2242 "msi4", 2243 "msi5", 2244 "msi6", 2245 "msi7", 2246 "global"; 2247 #interrupt-cells = <1>; 2248 interrupt-map-mask = <0 0 0 0x7>; 2249 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2250 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2251 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2252 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2253 2254 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2255 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2256 <&pcie0_phy>, 2257 <&rpmhcc RPMH_CXO_CLK>, 2258 <&gcc GCC_PCIE_0_AUX_CLK>, 2259 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2260 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2261 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2262 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2263 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2264 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2265 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2266 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 2267 clock-names = "pipe", 2268 "pipe_mux", 2269 "phy_pipe", 2270 "ref", 2271 "aux", 2272 "cfg", 2273 "bus_master", 2274 "bus_slave", 2275 "slave_q2a", 2276 "tbu", 2277 "ddrss_sf_tbu", 2278 "aggre0", 2279 "aggre1"; 2280 2281 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2282 <0x100 &apps_smmu 0x1c01 0x1>; 2283 2284 resets = <&gcc GCC_PCIE_0_BCR>; 2285 reset-names = "pci"; 2286 2287 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2288 2289 phys = <&pcie0_phy>; 2290 phy-names = "pciephy"; 2291 2292 pinctrl-names = "default"; 2293 pinctrl-0 = <&pcie0_clkreq_n>; 2294 dma-coherent; 2295 2296 status = "disabled"; 2297 2298 pcie0_port: pcie@0 { 2299 device_type = "pci"; 2300 reg = <0x0 0x0 0x0 0x0 0x0>; 2301 bus-range = <0x01 0xff>; 2302 2303 #address-cells = <3>; 2304 #size-cells = <2>; 2305 ranges; 2306 }; 2307 }; 2308 2309 pcie0_phy: phy@1c06000 { 2310 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2311 reg = <0 0x01c06000 0 0x1000>; 2312 2313 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2314 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2315 <&gcc GCC_PCIE_CLKREF_EN>, 2316 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 2317 <&gcc GCC_PCIE_0_PIPE_CLK>; 2318 clock-names = "aux", 2319 "cfg_ahb", 2320 "ref", 2321 "refgen", 2322 "pipe"; 2323 2324 clock-output-names = "pcie_0_pipe_clk"; 2325 #clock-cells = <0>; 2326 2327 #phy-cells = <0>; 2328 2329 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2330 reset-names = "phy"; 2331 2332 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 2333 assigned-clock-rates = <100000000>; 2334 2335 status = "disabled"; 2336 }; 2337 2338 pcie1: pcie@1c08000 { 2339 compatible = "qcom,pcie-sc7280"; 2340 reg = <0 0x01c08000 0 0x3000>, 2341 <0 0x40000000 0 0xf1d>, 2342 <0 0x40000f20 0 0xa8>, 2343 <0 0x40001000 0 0x1000>, 2344 <0 0x40100000 0 0x100000>; 2345 2346 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2347 device_type = "pci"; 2348 linux,pci-domain = <1>; 2349 bus-range = <0x00 0xff>; 2350 num-lanes = <2>; 2351 2352 #address-cells = <3>; 2353 #size-cells = <2>; 2354 2355 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2356 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2357 2358 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2367 interrupt-names = "msi0", 2368 "msi1", 2369 "msi2", 2370 "msi3", 2371 "msi4", 2372 "msi5", 2373 "msi6", 2374 "msi7", 2375 "global"; 2376 #interrupt-cells = <1>; 2377 interrupt-map-mask = <0 0 0 0x7>; 2378 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2379 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2380 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2381 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2382 2383 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2384 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2385 <&pcie1_phy>, 2386 <&rpmhcc RPMH_CXO_CLK>, 2387 <&gcc GCC_PCIE_1_AUX_CLK>, 2388 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2389 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2390 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2391 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2392 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2393 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2394 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2395 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2396 2397 clock-names = "pipe", 2398 "pipe_mux", 2399 "phy_pipe", 2400 "ref", 2401 "aux", 2402 "cfg", 2403 "bus_master", 2404 "bus_slave", 2405 "slave_q2a", 2406 "tbu", 2407 "ddrss_sf_tbu", 2408 "aggre0", 2409 "aggre1"; 2410 2411 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2412 assigned-clock-rates = <19200000>; 2413 2414 resets = <&gcc GCC_PCIE_1_BCR>; 2415 reset-names = "pci"; 2416 2417 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2418 2419 phys = <&pcie1_phy>; 2420 phy-names = "pciephy"; 2421 2422 pinctrl-names = "default"; 2423 pinctrl-0 = <&pcie1_clkreq_n>; 2424 2425 dma-coherent; 2426 2427 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2428 <0x100 &apps_smmu 0x1c81 0x1>; 2429 2430 status = "disabled"; 2431 2432 pcie1_port0: pcie@0 { 2433 device_type = "pci"; 2434 reg = <0x0 0x0 0x0 0x0 0x0>; 2435 bus-range = <0x01 0xff>; 2436 2437 #address-cells = <3>; 2438 #size-cells = <2>; 2439 ranges; 2440 }; 2441 }; 2442 2443 pcie1_phy: phy@1c0e000 { 2444 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2445 reg = <0 0x01c0e000 0 0x1000>; 2446 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2447 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2448 <&gcc GCC_PCIE_CLKREF_EN>, 2449 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2450 <&gcc GCC_PCIE_1_PIPE_CLK>; 2451 clock-names = "aux", 2452 "cfg_ahb", 2453 "ref", 2454 "refgen", 2455 "pipe"; 2456 2457 clock-output-names = "pcie_1_pipe_clk"; 2458 #clock-cells = <0>; 2459 2460 #phy-cells = <0>; 2461 2462 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2463 reset-names = "phy"; 2464 2465 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2466 assigned-clock-rates = <100000000>; 2467 2468 status = "disabled"; 2469 }; 2470 2471 ufs_mem_hc: ufshc@1d84000 { 2472 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2473 "jedec,ufs-2.0"; 2474 reg = <0x0 0x01d84000 0x0 0x3000>; 2475 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2476 phys = <&ufs_mem_phy>; 2477 phy-names = "ufsphy"; 2478 lanes-per-direction = <2>; 2479 #reset-cells = <1>; 2480 resets = <&gcc GCC_UFS_PHY_BCR>; 2481 reset-names = "rst"; 2482 2483 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2484 required-opps = <&rpmhpd_opp_nom>; 2485 2486 iommus = <&apps_smmu 0x80 0x0>; 2487 dma-coherent; 2488 2489 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2490 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2491 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2492 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2493 interconnect-names = "ufs-ddr", "cpu-ufs"; 2494 2495 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2496 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2497 <&gcc GCC_UFS_PHY_AHB_CLK>, 2498 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2499 <&rpmhcc RPMH_CXO_CLK>, 2500 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2501 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2502 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2503 clock-names = "core_clk", 2504 "bus_aggr_clk", 2505 "iface_clk", 2506 "core_clk_unipro", 2507 "ref_clk", 2508 "tx_lane0_sync_clk", 2509 "rx_lane0_sync_clk", 2510 "rx_lane1_sync_clk"; 2511 2512 operating-points-v2 = <&ufs_opp_table>; 2513 2514 qcom,ice = <&ice>; 2515 2516 status = "disabled"; 2517 2518 ufs_opp_table: opp-table { 2519 compatible = "operating-points-v2"; 2520 2521 opp-75000000 { 2522 opp-hz = /bits/ 64 <75000000>, 2523 /bits/ 64 <0>, 2524 /bits/ 64 <0>, 2525 /bits/ 64 <75000000>, 2526 /bits/ 64 <0>, 2527 /bits/ 64 <0>, 2528 /bits/ 64 <0>, 2529 /bits/ 64 <0>; 2530 required-opps = <&rpmhpd_opp_low_svs>; 2531 }; 2532 2533 opp-150000000 { 2534 opp-hz = /bits/ 64 <150000000>, 2535 /bits/ 64 <0>, 2536 /bits/ 64 <0>, 2537 /bits/ 64 <150000000>, 2538 /bits/ 64 <0>, 2539 /bits/ 64 <0>, 2540 /bits/ 64 <0>, 2541 /bits/ 64 <0>; 2542 required-opps = <&rpmhpd_opp_svs>; 2543 }; 2544 2545 opp-300000000 { 2546 opp-hz = /bits/ 64 <300000000>, 2547 /bits/ 64 <0>, 2548 /bits/ 64 <0>, 2549 /bits/ 64 <300000000>, 2550 /bits/ 64 <0>, 2551 /bits/ 64 <0>, 2552 /bits/ 64 <0>, 2553 /bits/ 64 <0>; 2554 required-opps = <&rpmhpd_opp_nom>; 2555 }; 2556 }; 2557 }; 2558 2559 ufs_mem_phy: phy@1d87000 { 2560 compatible = "qcom,sc7280-qmp-ufs-phy"; 2561 reg = <0x0 0x01d87000 0x0 0xe00>; 2562 clocks = <&rpmhcc RPMH_CXO_CLK>, 2563 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2564 <&gcc GCC_UFS_1_CLKREF_EN>; 2565 clock-names = "ref", "ref_aux", "qref"; 2566 2567 power-domains = <&rpmhpd SC7280_MX>; 2568 2569 resets = <&ufs_mem_hc 0>; 2570 reset-names = "ufsphy"; 2571 2572 #clock-cells = <1>; 2573 #phy-cells = <0>; 2574 2575 status = "disabled"; 2576 }; 2577 2578 ice: crypto@1d88000 { 2579 compatible = "qcom,sc7280-inline-crypto-engine", 2580 "qcom,inline-crypto-engine"; 2581 reg = <0 0x01d88000 0 0x8000>; 2582 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2583 }; 2584 2585 cryptobam: dma-controller@1dc4000 { 2586 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2587 reg = <0x0 0x01dc4000 0x0 0x28000>; 2588 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2589 #dma-cells = <1>; 2590 iommus = <&apps_smmu 0x4e4 0x0011>, 2591 <&apps_smmu 0x4e6 0x0011>; 2592 qcom,ee = <0>; 2593 qcom,controlled-remotely; 2594 num-channels = <16>; 2595 qcom,num-ees = <4>; 2596 }; 2597 2598 crypto: crypto@1dfa000 { 2599 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2600 reg = <0x0 0x01dfa000 0x0 0x6000>; 2601 dmas = <&cryptobam 4>, <&cryptobam 5>; 2602 dma-names = "rx", "tx"; 2603 iommus = <&apps_smmu 0x4e4 0x0011>, 2604 <&apps_smmu 0x4e4 0x0011>; 2605 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2606 interconnect-names = "memory"; 2607 }; 2608 2609 ipa: ipa@1e40000 { 2610 compatible = "qcom,sc7280-ipa"; 2611 2612 iommus = <&apps_smmu 0x480 0x0>, 2613 <&apps_smmu 0x482 0x0>; 2614 reg = <0 0x01e40000 0 0x8000>, 2615 <0 0x01e50000 0 0x4ad0>, 2616 <0 0x01e04000 0 0x23000>; 2617 reg-names = "ipa-reg", 2618 "ipa-shared", 2619 "gsi"; 2620 2621 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2622 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2623 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2624 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2625 interrupt-names = "ipa", 2626 "gsi", 2627 "ipa-clock-query", 2628 "ipa-setup-ready"; 2629 2630 clocks = <&rpmhcc RPMH_IPA_CLK>; 2631 clock-names = "core"; 2632 2633 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2635 interconnect-names = "memory", 2636 "config"; 2637 2638 qcom,qmp = <&aoss_qmp>; 2639 2640 qcom,smem-states = <&ipa_smp2p_out 0>, 2641 <&ipa_smp2p_out 1>; 2642 qcom,smem-state-names = "ipa-clock-enabled-valid", 2643 "ipa-clock-enabled"; 2644 2645 status = "disabled"; 2646 }; 2647 2648 tcsr_mutex: hwlock@1f40000 { 2649 compatible = "qcom,tcsr-mutex"; 2650 reg = <0 0x01f40000 0 0x20000>; 2651 #hwlock-cells = <1>; 2652 }; 2653 2654 tcsr_1: syscon@1f60000 { 2655 compatible = "qcom,sc7280-tcsr", "syscon"; 2656 reg = <0 0x01f60000 0 0x20000>; 2657 }; 2658 2659 tcsr_2: syscon@1fc0000 { 2660 compatible = "qcom,sc7280-tcsr", "syscon"; 2661 reg = <0 0x01fc0000 0 0x30000>; 2662 }; 2663 2664 lpasscc: lpasscc@3000000 { 2665 compatible = "qcom,sc7280-lpasscc"; 2666 reg = <0 0x03000000 0 0x40>, 2667 <0 0x03c04000 0 0x4>; 2668 reg-names = "qdsp6ss", "top_cc"; 2669 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2670 clock-names = "iface"; 2671 #clock-cells = <1>; 2672 status = "reserved"; /* Owned by ADSP firmware */ 2673 }; 2674 2675 lpass_rx_macro: codec@3200000 { 2676 compatible = "qcom,sc7280-lpass-rx-macro"; 2677 reg = <0 0x03200000 0 0x1000>; 2678 2679 pinctrl-names = "default"; 2680 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2681 2682 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2683 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2684 <&lpass_va_macro>; 2685 clock-names = "mclk", "npl", "fsgen"; 2686 2687 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2688 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2689 power-domain-names = "macro", "dcodec"; 2690 2691 #clock-cells = <0>; 2692 #sound-dai-cells = <1>; 2693 2694 status = "disabled"; 2695 }; 2696 2697 swr0: soundwire@3210000 { 2698 compatible = "qcom,soundwire-v1.6.0"; 2699 reg = <0 0x03210000 0 0x2000>; 2700 2701 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2702 clocks = <&lpass_rx_macro>; 2703 clock-names = "iface"; 2704 2705 qcom,din-ports = <0>; 2706 qcom,dout-ports = <5>; 2707 2708 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2709 reset-names = "swr_audio_cgcr"; 2710 2711 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2712 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2713 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2714 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2715 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2716 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2717 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2718 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2719 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2720 2721 #sound-dai-cells = <1>; 2722 #address-cells = <2>; 2723 #size-cells = <0>; 2724 2725 status = "disabled"; 2726 }; 2727 2728 lpass_tx_macro: codec@3220000 { 2729 compatible = "qcom,sc7280-lpass-tx-macro"; 2730 reg = <0 0x03220000 0 0x1000>; 2731 2732 pinctrl-names = "default"; 2733 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2734 2735 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2736 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2737 <&lpass_va_macro>; 2738 clock-names = "mclk", "npl", "fsgen"; 2739 2740 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2741 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2742 power-domain-names = "macro", "dcodec"; 2743 2744 #clock-cells = <0>; 2745 #sound-dai-cells = <1>; 2746 2747 status = "disabled"; 2748 }; 2749 2750 swr1: soundwire@3230000 { 2751 compatible = "qcom,soundwire-v1.6.0"; 2752 reg = <0 0x03230000 0 0x2000>; 2753 2754 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2755 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2756 clocks = <&lpass_tx_macro>; 2757 clock-names = "iface"; 2758 2759 qcom,din-ports = <3>; 2760 qcom,dout-ports = <0>; 2761 2762 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2763 reset-names = "swr_audio_cgcr"; 2764 2765 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2766 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2767 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2768 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2769 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2770 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2771 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2772 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2773 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2774 2775 #sound-dai-cells = <1>; 2776 #address-cells = <2>; 2777 #size-cells = <0>; 2778 2779 status = "disabled"; 2780 }; 2781 2782 lpass_wsa_macro: codec@3240000 { 2783 compatible = "qcom,sc7280-lpass-wsa-macro"; 2784 reg = <0x0 0x03240000 0x0 0x1000>; 2785 2786 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2787 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2788 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2789 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2790 <&lpass_va_macro>; 2791 clock-names = "mclk", 2792 "npl", 2793 "macro", 2794 "dcodec", 2795 "fsgen"; 2796 2797 pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; 2798 pinctrl-names = "default"; 2799 2800 #clock-cells = <0>; 2801 clock-output-names = "mclk"; 2802 #sound-dai-cells = <1>; 2803 2804 status = "disabled"; 2805 }; 2806 2807 swr2: soundwire@3250000 { 2808 compatible = "qcom,soundwire-v1.6.0"; 2809 reg = <0x0 0x03250000 0x0 0x2000>; 2810 2811 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2812 clocks = <&lpass_wsa_macro>; 2813 clock-names = "iface"; 2814 2815 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2816 reset-names = "swr_audio_cgcr"; 2817 2818 qcom,din-ports = <2>; 2819 qcom,dout-ports = <6>; 2820 2821 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 2822 0x1f 0x3f 0x0f 0x0f>; 2823 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2824 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2825 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2826 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2827 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2828 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 2829 0xff 0xff>; 2830 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2831 0xff 0xff>; 2832 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2833 0xff 0xff>; 2834 2835 #address-cells = <2>; 2836 #size-cells = <0>; 2837 #sound-dai-cells = <1>; 2838 2839 status = "disabled"; 2840 }; 2841 2842 lpass_audiocc: clock-controller@3300000 { 2843 compatible = "qcom,sc7280-lpassaudiocc"; 2844 reg = <0 0x03300000 0 0x30000>, 2845 <0 0x032a9000 0 0x1000>; 2846 clocks = <&rpmhcc RPMH_CXO_CLK>, 2847 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2848 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2849 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2850 #clock-cells = <1>; 2851 #power-domain-cells = <1>; 2852 #reset-cells = <1>; 2853 }; 2854 2855 lpass_va_macro: codec@3370000 { 2856 compatible = "qcom,sc7280-lpass-va-macro"; 2857 reg = <0 0x03370000 0 0x1000>; 2858 2859 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2860 clock-names = "mclk"; 2861 2862 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2863 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2864 power-domain-names = "macro", "dcodec"; 2865 2866 #clock-cells = <0>; 2867 #sound-dai-cells = <1>; 2868 2869 status = "disabled"; 2870 }; 2871 2872 lpass_aon: clock-controller@3380000 { 2873 compatible = "qcom,sc7280-lpassaoncc"; 2874 reg = <0 0x03380000 0 0x30000>; 2875 clocks = <&rpmhcc RPMH_CXO_CLK>, 2876 <&rpmhcc RPMH_CXO_CLK_A>, 2877 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2878 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2879 #clock-cells = <1>; 2880 #power-domain-cells = <1>; 2881 status = "reserved"; /* Owned by ADSP firmware */ 2882 }; 2883 2884 lpass_core: clock-controller@3900000 { 2885 compatible = "qcom,sc7280-lpasscorecc"; 2886 reg = <0 0x03900000 0 0x50000>; 2887 clocks = <&rpmhcc RPMH_CXO_CLK>; 2888 clock-names = "bi_tcxo"; 2889 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2890 #clock-cells = <1>; 2891 #power-domain-cells = <1>; 2892 status = "reserved"; /* Owned by ADSP firmware */ 2893 }; 2894 2895 lpass_cpu: audio@3987000 { 2896 compatible = "qcom,sc7280-lpass-cpu"; 2897 2898 reg = <0 0x03987000 0 0x68000>, 2899 <0 0x03b00000 0 0x29000>, 2900 <0 0x03260000 0 0xc000>, 2901 <0 0x03280000 0 0x29000>, 2902 <0 0x03340000 0 0x29000>, 2903 <0 0x0336c000 0 0x3000>; 2904 reg-names = "lpass-hdmiif", 2905 "lpass-lpaif", 2906 "lpass-rxtx-cdc-dma-lpm", 2907 "lpass-rxtx-lpaif", 2908 "lpass-va-lpaif", 2909 "lpass-va-cdc-dma-lpm"; 2910 2911 iommus = <&apps_smmu 0x1820 0>, 2912 <&apps_smmu 0x1821 0>, 2913 <&apps_smmu 0x1832 0>; 2914 2915 power-domains = <&rpmhpd SC7280_LCX>; 2916 power-domain-names = "lcx"; 2917 required-opps = <&rpmhpd_opp_nom>; 2918 2919 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2920 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2921 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2922 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2923 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2924 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2925 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2926 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2927 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2928 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2929 clock-names = "aon_cc_audio_hm_h", 2930 "audio_cc_ext_mclk0", 2931 "core_cc_sysnoc_mport_core", 2932 "core_cc_ext_if0_ibit", 2933 "core_cc_ext_if1_ibit", 2934 "audio_cc_codec_mem", 2935 "audio_cc_codec_mem0", 2936 "audio_cc_codec_mem1", 2937 "audio_cc_codec_mem2", 2938 "aon_cc_va_mem0"; 2939 2940 #sound-dai-cells = <1>; 2941 #address-cells = <1>; 2942 #size-cells = <0>; 2943 2944 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2948 interrupt-names = "lpass-irq-lpaif", 2949 "lpass-irq-hdmi", 2950 "lpass-irq-vaif", 2951 "lpass-irq-rxtxif"; 2952 2953 status = "disabled"; 2954 }; 2955 2956 slimbam: dma-controller@3a84000 { 2957 compatible = "qcom,bam-v1.7.0"; 2958 reg = <0 0x03a84000 0 0x20000>; 2959 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2960 #dma-cells = <1>; 2961 qcom,controlled-remotely; 2962 num-channels = <31>; 2963 qcom,ee = <1>; 2964 qcom,num-ees = <2>; 2965 iommus = <&apps_smmu 0x1826 0x0>; 2966 status = "disabled"; 2967 }; 2968 2969 slim: slim-ngd@3ac0000 { 2970 compatible = "qcom,slim-ngd-v1.5.0"; 2971 reg = <0 0x03ac0000 0 0x2c000>; 2972 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2973 dmas = <&slimbam 3>, <&slimbam 4>; 2974 dma-names = "rx", "tx"; 2975 iommus = <&apps_smmu 0x1826 0x0>; 2976 #address-cells = <1>; 2977 #size-cells = <0>; 2978 status = "disabled"; 2979 }; 2980 2981 lpass_hm: clock-controller@3c00000 { 2982 compatible = "qcom,sc7280-lpasshm"; 2983 reg = <0 0x03c00000 0 0x28>; 2984 clocks = <&rpmhcc RPMH_CXO_CLK>; 2985 clock-names = "bi_tcxo"; 2986 #clock-cells = <1>; 2987 #power-domain-cells = <1>; 2988 status = "reserved"; /* Owned by ADSP firmware */ 2989 }; 2990 2991 lpass_ag_noc: interconnect@3c40000 { 2992 reg = <0 0x03c40000 0 0xf080>; 2993 compatible = "qcom,sc7280-lpass-ag-noc"; 2994 #interconnect-cells = <2>; 2995 qcom,bcm-voters = <&apps_bcm_voter>; 2996 }; 2997 2998 lpass_tlmm: pinctrl@33c0000 { 2999 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 3000 reg = <0 0x033c0000 0x0 0x20000>, 3001 <0 0x03550000 0x0 0x10000>; 3002 3003 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3004 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3005 clock-names = "core", "audio"; 3006 3007 gpio-controller; 3008 #gpio-cells = <2>; 3009 gpio-ranges = <&lpass_tlmm 0 0 15>; 3010 3011 lpass_dmic01_clk: dmic01-clk-state { 3012 pins = "gpio6"; 3013 function = "dmic1_clk"; 3014 drive-strength = <8>; 3015 bias-disable; 3016 }; 3017 3018 lpass_dmic01_data: dmic01-data-state { 3019 pins = "gpio7"; 3020 function = "dmic1_data"; 3021 drive-strength = <8>; 3022 bias-pull-down; 3023 }; 3024 3025 lpass_dmic23_clk: dmic23-clk-state { 3026 pins = "gpio8"; 3027 function = "dmic2_clk"; 3028 drive-strength = <8>; 3029 bias-disable; 3030 }; 3031 3032 lpass_dmic23_data: dmic23-data-state { 3033 pins = "gpio9"; 3034 function = "dmic2_data"; 3035 drive-strength = <8>; 3036 bias-pull-down; 3037 }; 3038 3039 lpass_rx_swr_clk: rx-swr-clk-state { 3040 pins = "gpio3"; 3041 function = "swr_rx_clk"; 3042 drive-strength = <2>; 3043 slew-rate = <1>; 3044 bias-disable; 3045 }; 3046 3047 lpass_rx_swr_data: rx-swr-data-state { 3048 pins = "gpio4", "gpio5"; 3049 function = "swr_rx_data"; 3050 drive-strength = <2>; 3051 slew-rate = <1>; 3052 bias-bus-hold; 3053 }; 3054 3055 lpass_tx_swr_clk: tx-swr-clk-state { 3056 pins = "gpio0"; 3057 function = "swr_tx_clk"; 3058 drive-strength = <2>; 3059 slew-rate = <1>; 3060 bias-disable; 3061 }; 3062 3063 lpass_tx_swr_data: tx-swr-data-state { 3064 pins = "gpio1", "gpio2", "gpio14"; 3065 function = "swr_tx_data"; 3066 drive-strength = <2>; 3067 slew-rate = <1>; 3068 bias-bus-hold; 3069 }; 3070 3071 lpass_wsa_swr_clk: wsa-swr-clk-state { 3072 pins = "gpio10"; 3073 function = "wsa_swr_clk"; 3074 drive-strength = <2>; 3075 slew-rate = <1>; 3076 bias-disable; 3077 }; 3078 3079 lpass_wsa_swr_data: wsa-swr-data-state { 3080 pins = "gpio11"; 3081 function = "wsa_swr_data"; 3082 drive-strength = <2>; 3083 slew-rate = <1>; 3084 bias-bus-hold; 3085 }; 3086 }; 3087 3088 gpu: gpu@3d00000 { 3089 compatible = "qcom,adreno-635.0", "qcom,adreno"; 3090 reg = <0 0x03d00000 0 0x40000>, 3091 <0 0x03d9e000 0 0x1000>, 3092 <0 0x03d61000 0 0x800>; 3093 reg-names = "kgsl_3d0_reg_memory", 3094 "cx_mem", 3095 "cx_dbgc"; 3096 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3097 iommus = <&adreno_smmu 0 0x400>, 3098 <&adreno_smmu 1 0x400>; 3099 operating-points-v2 = <&gpu_opp_table>; 3100 qcom,gmu = <&gmu>; 3101 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3102 interconnect-names = "gfx-mem"; 3103 #cooling-cells = <2>; 3104 3105 nvmem-cells = <&gpu_speed_bin>; 3106 nvmem-cell-names = "speed_bin"; 3107 3108 status = "disabled"; 3109 3110 gpu_zap_shader: zap-shader { 3111 memory-region = <&gpu_zap_mem>; 3112 }; 3113 3114 gpu_opp_table: opp-table { 3115 compatible = "operating-points-v2"; 3116 3117 opp-315000000 { 3118 opp-hz = /bits/ 64 <315000000>; 3119 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3120 opp-peak-kBps = <1804000>; 3121 opp-supported-hw = <0x17>; 3122 }; 3123 3124 opp-450000000 { 3125 opp-hz = /bits/ 64 <450000000>; 3126 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3127 opp-peak-kBps = <4068000>; 3128 opp-supported-hw = <0x17>; 3129 }; 3130 3131 /* Only applicable for SKUs which has 550Mhz as Fmax */ 3132 opp-550000000-0 { 3133 opp-hz = /bits/ 64 <550000000>; 3134 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3135 opp-peak-kBps = <8368000>; 3136 opp-supported-hw = <0x01>; 3137 }; 3138 3139 opp-550000000-1 { 3140 opp-hz = /bits/ 64 <550000000>; 3141 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3142 opp-peak-kBps = <6832000>; 3143 opp-supported-hw = <0x16>; 3144 }; 3145 3146 opp-608000000 { 3147 opp-hz = /bits/ 64 <608000000>; 3148 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3149 opp-peak-kBps = <8368000>; 3150 opp-supported-hw = <0x16>; 3151 }; 3152 3153 opp-700000000 { 3154 opp-hz = /bits/ 64 <700000000>; 3155 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3156 opp-peak-kBps = <8532000>; 3157 opp-supported-hw = <0x06>; 3158 }; 3159 3160 opp-812000000 { 3161 opp-hz = /bits/ 64 <812000000>; 3162 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3163 opp-peak-kBps = <8532000>; 3164 opp-supported-hw = <0x06>; 3165 }; 3166 3167 opp-840000000 { 3168 opp-hz = /bits/ 64 <840000000>; 3169 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3170 opp-peak-kBps = <8532000>; 3171 opp-supported-hw = <0x02>; 3172 }; 3173 3174 opp-900000000 { 3175 opp-hz = /bits/ 64 <900000000>; 3176 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3177 opp-peak-kBps = <8532000>; 3178 opp-supported-hw = <0x02>; 3179 }; 3180 }; 3181 }; 3182 3183 gmu: gmu@3d6a000 { 3184 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 3185 reg = <0 0x03d6a000 0 0x34000>, 3186 <0 0x3de0000 0 0x10000>, 3187 <0 0x0b290000 0 0x10000>; 3188 reg-names = "gmu", "rscc", "gmu_pdc"; 3189 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3191 interrupt-names = "hfi", "gmu"; 3192 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3193 <&gpucc GPU_CC_CXO_CLK>, 3194 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3195 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3196 <&gpucc GPU_CC_AHB_CLK>, 3197 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3198 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3199 clock-names = "gmu", 3200 "cxo", 3201 "axi", 3202 "memnoc", 3203 "ahb", 3204 "hub", 3205 "smmu_vote"; 3206 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3207 <&gpucc GPU_CC_GX_GDSC>; 3208 power-domain-names = "cx", 3209 "gx"; 3210 iommus = <&adreno_smmu 5 0x400>; 3211 operating-points-v2 = <&gmu_opp_table>; 3212 3213 gmu_opp_table: opp-table { 3214 compatible = "operating-points-v2"; 3215 3216 opp-200000000 { 3217 opp-hz = /bits/ 64 <200000000>; 3218 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3219 }; 3220 }; 3221 }; 3222 3223 gpucc: clock-controller@3d90000 { 3224 compatible = "qcom,sc7280-gpucc"; 3225 reg = <0 0x03d90000 0 0x9000>; 3226 clocks = <&rpmhcc RPMH_CXO_CLK>, 3227 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3228 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3229 clock-names = "bi_tcxo", 3230 "gcc_gpu_gpll0_clk_src", 3231 "gcc_gpu_gpll0_div_clk_src"; 3232 #clock-cells = <1>; 3233 #reset-cells = <1>; 3234 #power-domain-cells = <1>; 3235 }; 3236 3237 dma@117f000 { 3238 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 3239 reg = <0x0 0x0117f000 0x0 0x1000>, 3240 <0x0 0x01112000 0x0 0x6000>; 3241 }; 3242 3243 adreno_smmu: iommu@3da0000 { 3244 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 3245 "qcom,smmu-500", "arm,mmu-500"; 3246 reg = <0 0x03da0000 0 0x20000>; 3247 #iommu-cells = <2>; 3248 #global-interrupts = <2>; 3249 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3261 3262 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3263 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3264 <&gpucc GPU_CC_AHB_CLK>, 3265 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3266 <&gpucc GPU_CC_CX_GMU_CLK>, 3267 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3268 <&gpucc GPU_CC_HUB_AON_CLK>; 3269 clock-names = "gcc_gpu_memnoc_gfx_clk", 3270 "gcc_gpu_snoc_dvm_gfx_clk", 3271 "gpu_cc_ahb_clk", 3272 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3273 "gpu_cc_cx_gmu_clk", 3274 "gpu_cc_hub_cx_int_clk", 3275 "gpu_cc_hub_aon_clk"; 3276 3277 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3278 dma-coherent; 3279 }; 3280 3281 gfx_0_tbu: tbu@3dd9000 { 3282 compatible = "qcom,sc7280-tbu"; 3283 reg = <0x0 0x3dd9000 0x0 0x1000>; 3284 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3285 }; 3286 3287 gfx_1_tbu: tbu@3ddd000 { 3288 compatible = "qcom,sc7280-tbu"; 3289 reg = <0x0 0x3ddd000 0x0 0x1000>; 3290 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3291 }; 3292 3293 remoteproc_mpss: remoteproc@4080000 { 3294 compatible = "qcom,sc7280-mpss-pas"; 3295 reg = <0 0x04080000 0 0x10000>; 3296 3297 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3298 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3299 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3300 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3301 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3302 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3303 interrupt-names = "wdog", "fatal", "ready", "handover", 3304 "stop-ack", "shutdown-ack"; 3305 3306 clocks = <&rpmhcc RPMH_CXO_CLK>; 3307 clock-names = "xo"; 3308 3309 power-domains = <&rpmhpd SC7280_CX>, 3310 <&rpmhpd SC7280_MSS>; 3311 power-domain-names = "cx", "mss"; 3312 3313 memory-region = <&mpss_mem>; 3314 3315 qcom,qmp = <&aoss_qmp>; 3316 3317 qcom,smem-states = <&modem_smp2p_out 0>; 3318 qcom,smem-state-names = "stop"; 3319 3320 status = "disabled"; 3321 3322 glink-edge { 3323 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3324 IPCC_MPROC_SIGNAL_GLINK_QMP 3325 IRQ_TYPE_EDGE_RISING>; 3326 mboxes = <&ipcc IPCC_CLIENT_MPSS 3327 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3328 label = "modem"; 3329 qcom,remote-pid = <1>; 3330 }; 3331 }; 3332 3333 stm@6002000 { 3334 compatible = "arm,coresight-stm", "arm,primecell"; 3335 reg = <0 0x06002000 0 0x1000>, 3336 <0 0x16280000 0 0x180000>; 3337 reg-names = "stm-base", "stm-stimulus-base"; 3338 3339 clocks = <&aoss_qmp>; 3340 clock-names = "apb_pclk"; 3341 3342 out-ports { 3343 port { 3344 stm_out: endpoint { 3345 remote-endpoint = <&funnel0_in7>; 3346 }; 3347 }; 3348 }; 3349 }; 3350 3351 tpda@6004000 { 3352 compatible = "qcom,coresight-tpda", "arm,primecell"; 3353 reg = <0x0 0x06004000 0x0 0x1000>; 3354 3355 clocks = <&aoss_qmp>; 3356 clock-names = "apb_pclk"; 3357 3358 in-ports { 3359 #address-cells = <1>; 3360 #size-cells = <0>; 3361 3362 port@1c { 3363 reg = <0x1c>; 3364 3365 qdss_tpda_in28: endpoint { 3366 remote-endpoint = <&spdm_tpdm_out>; 3367 }; 3368 }; 3369 }; 3370 3371 out-ports { 3372 port { 3373 qdss_tpda_out: endpoint { 3374 remote-endpoint = <&qdss_dl_funnel_in0>; 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 funnel@6005000 { 3381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3382 reg = <0x0 0x06005000 0x0 0x1000>; 3383 3384 clocks = <&aoss_qmp>; 3385 clock-names = "apb_pclk"; 3386 3387 in-ports { 3388 port { 3389 qdss_dl_funnel_in0: endpoint { 3390 remote-endpoint = <&qdss_tpda_out>; 3391 }; 3392 }; 3393 }; 3394 3395 out-ports { 3396 port { 3397 qdss_dl_funnel_out: endpoint { 3398 remote-endpoint = <&funnel0_in6>; 3399 }; 3400 }; 3401 }; 3402 }; 3403 3404 tpdm@600f000 { 3405 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3406 reg = <0x0 0x0600f000 0x0 0x1000>; 3407 3408 clocks = <&aoss_qmp>; 3409 clock-names = "apb_pclk"; 3410 3411 qcom,cmb-element-bits = <32>; 3412 qcom,cmb-msrs-num = <32>; 3413 3414 out-ports { 3415 port { 3416 spdm_tpdm_out: endpoint { 3417 remote-endpoint = <&qdss_tpda_in28>; 3418 }; 3419 }; 3420 }; 3421 }; 3422 3423 cti@6010000 { 3424 compatible = "arm,coresight-cti", "arm,primecell"; 3425 reg = <0x0 0x06010000 0x0 0x1000>; 3426 3427 clocks = <&aoss_qmp>; 3428 clock-names = "apb_pclk"; 3429 }; 3430 3431 funnel@6041000 { 3432 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3433 reg = <0 0x06041000 0 0x1000>; 3434 3435 clocks = <&aoss_qmp>; 3436 clock-names = "apb_pclk"; 3437 3438 out-ports { 3439 port { 3440 funnel0_out: endpoint { 3441 remote-endpoint = <&merge_funnel_in0>; 3442 }; 3443 }; 3444 }; 3445 3446 in-ports { 3447 #address-cells = <1>; 3448 #size-cells = <0>; 3449 3450 port@6 { 3451 reg = <6>; 3452 3453 funnel0_in6: endpoint { 3454 remote-endpoint = <&qdss_dl_funnel_out>; 3455 }; 3456 }; 3457 3458 port@7 { 3459 reg = <7>; 3460 funnel0_in7: endpoint { 3461 remote-endpoint = <&stm_out>; 3462 }; 3463 }; 3464 }; 3465 }; 3466 3467 funnel@6042000 { 3468 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3469 reg = <0 0x06042000 0 0x1000>; 3470 3471 clocks = <&aoss_qmp>; 3472 clock-names = "apb_pclk"; 3473 3474 out-ports { 3475 port { 3476 funnel1_out: endpoint { 3477 remote-endpoint = <&merge_funnel_in1>; 3478 }; 3479 }; 3480 }; 3481 3482 in-ports { 3483 #address-cells = <1>; 3484 #size-cells = <0>; 3485 3486 port@4 { 3487 reg = <4>; 3488 funnel1_in4: endpoint { 3489 remote-endpoint = <&apss_merge_funnel_out>; 3490 }; 3491 }; 3492 }; 3493 }; 3494 3495 funnel@6045000 { 3496 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3497 reg = <0 0x06045000 0 0x1000>; 3498 3499 clocks = <&aoss_qmp>; 3500 clock-names = "apb_pclk"; 3501 3502 out-ports { 3503 port { 3504 merge_funnel_out: endpoint { 3505 remote-endpoint = <&swao_funnel_in>; 3506 }; 3507 }; 3508 }; 3509 3510 in-ports { 3511 #address-cells = <1>; 3512 #size-cells = <0>; 3513 3514 port@0 { 3515 reg = <0>; 3516 merge_funnel_in0: endpoint { 3517 remote-endpoint = <&funnel0_out>; 3518 }; 3519 }; 3520 3521 port@1 { 3522 reg = <1>; 3523 merge_funnel_in1: endpoint { 3524 remote-endpoint = <&funnel1_out>; 3525 }; 3526 }; 3527 }; 3528 }; 3529 3530 replicator@6046000 { 3531 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3532 reg = <0 0x06046000 0 0x1000>; 3533 3534 clocks = <&aoss_qmp>; 3535 clock-names = "apb_pclk"; 3536 3537 out-ports { 3538 port { 3539 replicator_out: endpoint { 3540 remote-endpoint = <&etr_in>; 3541 }; 3542 }; 3543 }; 3544 3545 in-ports { 3546 port { 3547 replicator_in: endpoint { 3548 remote-endpoint = <&swao_replicator_out>; 3549 }; 3550 }; 3551 }; 3552 }; 3553 3554 etr@6048000 { 3555 compatible = "arm,coresight-tmc", "arm,primecell"; 3556 reg = <0 0x06048000 0 0x1000>; 3557 iommus = <&apps_smmu 0x04c0 0>; 3558 3559 clocks = <&aoss_qmp>; 3560 clock-names = "apb_pclk"; 3561 arm,scatter-gather; 3562 3563 in-ports { 3564 port { 3565 etr_in: endpoint { 3566 remote-endpoint = <&replicator_out>; 3567 }; 3568 }; 3569 }; 3570 }; 3571 3572 cti@6b00000 { 3573 compatible = "arm,coresight-cti", "arm,primecell"; 3574 reg = <0x0 0x06b00000 0x0 0x1000>; 3575 3576 clocks = <&aoss_qmp>; 3577 clock-names = "apb_pclk"; 3578 }; 3579 3580 cti@6b01000 { 3581 compatible = "arm,coresight-cti", "arm,primecell"; 3582 reg = <0x0 0x06b01000 0x0 0x1000>; 3583 3584 clocks = <&aoss_qmp>; 3585 clock-names = "apb_pclk"; 3586 }; 3587 3588 cti@6b02000 { 3589 compatible = "arm,coresight-cti", "arm,primecell"; 3590 reg = <0x0 0x06b02000 0x0 0x1000>; 3591 3592 clocks = <&aoss_qmp>; 3593 clock-names = "apb_pclk"; 3594 }; 3595 3596 cti@6b03000 { 3597 compatible = "arm,coresight-cti", "arm,primecell"; 3598 reg = <0x0 0x06b03000 0x0 0x1000>; 3599 3600 clocks = <&aoss_qmp>; 3601 clock-names = "apb_pclk"; 3602 }; 3603 3604 funnel@6b04000 { 3605 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3606 reg = <0 0x06b04000 0 0x1000>; 3607 3608 clocks = <&aoss_qmp>; 3609 clock-names = "apb_pclk"; 3610 3611 out-ports { 3612 port { 3613 swao_funnel_out: endpoint { 3614 remote-endpoint = <&etf_in>; 3615 }; 3616 }; 3617 }; 3618 3619 in-ports { 3620 #address-cells = <1>; 3621 #size-cells = <0>; 3622 3623 port@6 { 3624 reg = <6>; 3625 3626 swao_funnel_in6: endpoint { 3627 remote-endpoint = <&aoss_tpda_out>; 3628 }; 3629 }; 3630 3631 port@7 { 3632 reg = <7>; 3633 swao_funnel_in: endpoint { 3634 remote-endpoint = <&merge_funnel_out>; 3635 }; 3636 }; 3637 }; 3638 }; 3639 3640 etf@6b05000 { 3641 compatible = "arm,coresight-tmc", "arm,primecell"; 3642 reg = <0 0x06b05000 0 0x1000>; 3643 3644 clocks = <&aoss_qmp>; 3645 clock-names = "apb_pclk"; 3646 3647 out-ports { 3648 port { 3649 etf_out: endpoint { 3650 remote-endpoint = <&swao_replicator_in>; 3651 }; 3652 }; 3653 }; 3654 3655 in-ports { 3656 port { 3657 etf_in: endpoint { 3658 remote-endpoint = <&swao_funnel_out>; 3659 }; 3660 }; 3661 }; 3662 }; 3663 3664 replicator@6b06000 { 3665 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3666 reg = <0 0x06b06000 0 0x1000>; 3667 3668 clocks = <&aoss_qmp>; 3669 clock-names = "apb_pclk"; 3670 qcom,replicator-loses-context; 3671 3672 out-ports { 3673 port { 3674 swao_replicator_out: endpoint { 3675 remote-endpoint = <&replicator_in>; 3676 }; 3677 }; 3678 }; 3679 3680 in-ports { 3681 port { 3682 swao_replicator_in: endpoint { 3683 remote-endpoint = <&etf_out>; 3684 }; 3685 }; 3686 }; 3687 }; 3688 3689 tpda@6b08000 { 3690 compatible = "qcom,coresight-tpda", "arm,primecell"; 3691 reg = <0x0 0x06b08000 0x0 0x1000>; 3692 3693 clocks = <&aoss_qmp>; 3694 clock-names = "apb_pclk"; 3695 3696 in-ports { 3697 #address-cells = <1>; 3698 #size-cells = <0>; 3699 3700 port@0 { 3701 reg = <0>; 3702 3703 aoss_tpda_in0: endpoint { 3704 remote-endpoint = <&swao_prio0_tpdm_out>; 3705 }; 3706 }; 3707 3708 port@1 { 3709 reg = <1>; 3710 3711 aoss_tpda_in1: endpoint { 3712 remote-endpoint = <&swao_prio1_tpdm_out>; 3713 }; 3714 }; 3715 3716 port@2 { 3717 reg = <2>; 3718 3719 aoss_tpda_in2: endpoint { 3720 remote-endpoint = <&swao_prio2_tpdm_out>; 3721 }; 3722 }; 3723 3724 port@3 { 3725 reg = <3>; 3726 3727 aoss_tpda_in3: endpoint { 3728 remote-endpoint = <&swao_prio3_tpdm_out>; 3729 }; 3730 }; 3731 3732 port@4 { 3733 reg = <4>; 3734 3735 aoss_tpda_in4: endpoint { 3736 remote-endpoint = <&swao_tpdm_out>; 3737 }; 3738 }; 3739 }; 3740 3741 out-ports { 3742 port { 3743 aoss_tpda_out: endpoint { 3744 remote-endpoint = <&swao_funnel_in6>; 3745 }; 3746 }; 3747 }; 3748 }; 3749 3750 tpdm@6b09000 { 3751 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3752 reg = <0x0 0x06b09000 0x0 0x1000>; 3753 3754 clocks = <&aoss_qmp>; 3755 clock-names = "apb_pclk"; 3756 3757 qcom,cmb-element-bits = <64>; 3758 qcom,cmb-msrs-num = <32>; 3759 3760 out-ports { 3761 port { 3762 swao_prio0_tpdm_out: endpoint { 3763 remote-endpoint = <&aoss_tpda_in0>; 3764 }; 3765 }; 3766 }; 3767 }; 3768 3769 tpdm@6b0a000 { 3770 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3771 reg = <0x0 0x06b0a000 0x0 0x1000>; 3772 3773 clocks = <&aoss_qmp>; 3774 clock-names = "apb_pclk"; 3775 3776 qcom,cmb-element-bits = <64>; 3777 qcom,cmb-msrs-num = <32>; 3778 3779 out-ports { 3780 port { 3781 swao_prio1_tpdm_out: endpoint { 3782 remote-endpoint = <&aoss_tpda_in1>; 3783 }; 3784 }; 3785 }; 3786 }; 3787 3788 tpdm@6b0b000 { 3789 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3790 reg = <0x0 0x06b0b000 0x0 0x1000>; 3791 3792 clocks = <&aoss_qmp>; 3793 clock-names = "apb_pclk"; 3794 3795 qcom,cmb-element-bits = <64>; 3796 qcom,cmb-msrs-num = <32>; 3797 3798 out-ports { 3799 port { 3800 swao_prio2_tpdm_out: endpoint { 3801 remote-endpoint = <&aoss_tpda_in2>; 3802 }; 3803 }; 3804 }; 3805 }; 3806 3807 tpdm@6b0c000 { 3808 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3809 reg = <0x0 0x06b0c000 0x0 0x1000>; 3810 3811 clocks = <&aoss_qmp>; 3812 clock-names = "apb_pclk"; 3813 3814 qcom,cmb-element-bits = <64>; 3815 qcom,cmb-msrs-num = <32>; 3816 3817 out-ports { 3818 port { 3819 swao_prio3_tpdm_out: endpoint { 3820 remote-endpoint = <&aoss_tpda_in3>; 3821 }; 3822 }; 3823 }; 3824 }; 3825 3826 tpdm@6b0d000 { 3827 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3828 reg = <0x0 0x06b0d000 0x0 0x1000>; 3829 3830 clocks = <&aoss_qmp>; 3831 clock-names = "apb_pclk"; 3832 3833 qcom,dsb-element-bits = <32>; 3834 qcom,dsb-msrs-num = <32>; 3835 3836 out-ports { 3837 port { 3838 swao_tpdm_out: endpoint { 3839 remote-endpoint = <&aoss_tpda_in4>; 3840 }; 3841 }; 3842 }; 3843 }; 3844 3845 cti@6b11000 { 3846 compatible = "arm,coresight-cti", "arm,primecell"; 3847 reg = <0x0 0x06b11000 0x0 0x1000>; 3848 3849 clocks = <&aoss_qmp>; 3850 clock-names = "apb_pclk"; 3851 }; 3852 3853 etm@7040000 { 3854 compatible = "arm,coresight-etm4x", "arm,primecell"; 3855 reg = <0 0x07040000 0 0x1000>; 3856 3857 cpu = <&cpu0>; 3858 3859 clocks = <&aoss_qmp>; 3860 clock-names = "apb_pclk"; 3861 arm,coresight-loses-context-with-cpu; 3862 qcom,skip-power-up; 3863 3864 out-ports { 3865 port { 3866 etm0_out: endpoint { 3867 remote-endpoint = <&apss_funnel_in0>; 3868 }; 3869 }; 3870 }; 3871 }; 3872 3873 etm@7140000 { 3874 compatible = "arm,coresight-etm4x", "arm,primecell"; 3875 reg = <0 0x07140000 0 0x1000>; 3876 3877 cpu = <&cpu1>; 3878 3879 clocks = <&aoss_qmp>; 3880 clock-names = "apb_pclk"; 3881 arm,coresight-loses-context-with-cpu; 3882 qcom,skip-power-up; 3883 3884 out-ports { 3885 port { 3886 etm1_out: endpoint { 3887 remote-endpoint = <&apss_funnel_in1>; 3888 }; 3889 }; 3890 }; 3891 }; 3892 3893 etm@7240000 { 3894 compatible = "arm,coresight-etm4x", "arm,primecell"; 3895 reg = <0 0x07240000 0 0x1000>; 3896 3897 cpu = <&cpu2>; 3898 3899 clocks = <&aoss_qmp>; 3900 clock-names = "apb_pclk"; 3901 arm,coresight-loses-context-with-cpu; 3902 qcom,skip-power-up; 3903 3904 out-ports { 3905 port { 3906 etm2_out: endpoint { 3907 remote-endpoint = <&apss_funnel_in2>; 3908 }; 3909 }; 3910 }; 3911 }; 3912 3913 etm@7340000 { 3914 compatible = "arm,coresight-etm4x", "arm,primecell"; 3915 reg = <0 0x07340000 0 0x1000>; 3916 3917 cpu = <&cpu3>; 3918 3919 clocks = <&aoss_qmp>; 3920 clock-names = "apb_pclk"; 3921 arm,coresight-loses-context-with-cpu; 3922 qcom,skip-power-up; 3923 3924 out-ports { 3925 port { 3926 etm3_out: endpoint { 3927 remote-endpoint = <&apss_funnel_in3>; 3928 }; 3929 }; 3930 }; 3931 }; 3932 3933 etm@7440000 { 3934 compatible = "arm,coresight-etm4x", "arm,primecell"; 3935 reg = <0 0x07440000 0 0x1000>; 3936 3937 cpu = <&cpu4>; 3938 3939 clocks = <&aoss_qmp>; 3940 clock-names = "apb_pclk"; 3941 arm,coresight-loses-context-with-cpu; 3942 qcom,skip-power-up; 3943 3944 out-ports { 3945 port { 3946 etm4_out: endpoint { 3947 remote-endpoint = <&apss_funnel_in4>; 3948 }; 3949 }; 3950 }; 3951 }; 3952 3953 etm@7540000 { 3954 compatible = "arm,coresight-etm4x", "arm,primecell"; 3955 reg = <0 0x07540000 0 0x1000>; 3956 3957 cpu = <&cpu5>; 3958 3959 clocks = <&aoss_qmp>; 3960 clock-names = "apb_pclk"; 3961 arm,coresight-loses-context-with-cpu; 3962 qcom,skip-power-up; 3963 3964 out-ports { 3965 port { 3966 etm5_out: endpoint { 3967 remote-endpoint = <&apss_funnel_in5>; 3968 }; 3969 }; 3970 }; 3971 }; 3972 3973 etm@7640000 { 3974 compatible = "arm,coresight-etm4x", "arm,primecell"; 3975 reg = <0 0x07640000 0 0x1000>; 3976 3977 cpu = <&cpu6>; 3978 3979 clocks = <&aoss_qmp>; 3980 clock-names = "apb_pclk"; 3981 arm,coresight-loses-context-with-cpu; 3982 qcom,skip-power-up; 3983 3984 out-ports { 3985 port { 3986 etm6_out: endpoint { 3987 remote-endpoint = <&apss_funnel_in6>; 3988 }; 3989 }; 3990 }; 3991 }; 3992 3993 etm@7740000 { 3994 compatible = "arm,coresight-etm4x", "arm,primecell"; 3995 reg = <0 0x07740000 0 0x1000>; 3996 3997 cpu = <&cpu7>; 3998 3999 clocks = <&aoss_qmp>; 4000 clock-names = "apb_pclk"; 4001 arm,coresight-loses-context-with-cpu; 4002 qcom,skip-power-up; 4003 4004 out-ports { 4005 port { 4006 etm7_out: endpoint { 4007 remote-endpoint = <&apss_funnel_in7>; 4008 }; 4009 }; 4010 }; 4011 }; 4012 4013 funnel@7800000 { /* APSS Funnel */ 4014 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4015 reg = <0 0x07800000 0 0x1000>; 4016 4017 clocks = <&aoss_qmp>; 4018 clock-names = "apb_pclk"; 4019 4020 out-ports { 4021 port { 4022 apss_funnel_out: endpoint { 4023 remote-endpoint = <&apss_merge_funnel_in>; 4024 }; 4025 }; 4026 }; 4027 4028 in-ports { 4029 #address-cells = <1>; 4030 #size-cells = <0>; 4031 4032 port@0 { 4033 reg = <0>; 4034 apss_funnel_in0: endpoint { 4035 remote-endpoint = <&etm0_out>; 4036 }; 4037 }; 4038 4039 port@1 { 4040 reg = <1>; 4041 apss_funnel_in1: endpoint { 4042 remote-endpoint = <&etm1_out>; 4043 }; 4044 }; 4045 4046 port@2 { 4047 reg = <2>; 4048 apss_funnel_in2: endpoint { 4049 remote-endpoint = <&etm2_out>; 4050 }; 4051 }; 4052 4053 port@3 { 4054 reg = <3>; 4055 apss_funnel_in3: endpoint { 4056 remote-endpoint = <&etm3_out>; 4057 }; 4058 }; 4059 4060 port@4 { 4061 reg = <4>; 4062 apss_funnel_in4: endpoint { 4063 remote-endpoint = <&etm4_out>; 4064 }; 4065 }; 4066 4067 port@5 { 4068 reg = <5>; 4069 apss_funnel_in5: endpoint { 4070 remote-endpoint = <&etm5_out>; 4071 }; 4072 }; 4073 4074 port@6 { 4075 reg = <6>; 4076 apss_funnel_in6: endpoint { 4077 remote-endpoint = <&etm6_out>; 4078 }; 4079 }; 4080 4081 port@7 { 4082 reg = <7>; 4083 apss_funnel_in7: endpoint { 4084 remote-endpoint = <&etm7_out>; 4085 }; 4086 }; 4087 }; 4088 }; 4089 4090 funnel@7810000 { 4091 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4092 reg = <0 0x07810000 0 0x1000>; 4093 4094 clocks = <&aoss_qmp>; 4095 clock-names = "apb_pclk"; 4096 4097 out-ports { 4098 port { 4099 apss_merge_funnel_out: endpoint { 4100 remote-endpoint = <&funnel1_in4>; 4101 }; 4102 }; 4103 }; 4104 4105 in-ports { 4106 port { 4107 apss_merge_funnel_in: endpoint { 4108 remote-endpoint = <&apss_funnel_out>; 4109 }; 4110 }; 4111 }; 4112 }; 4113 4114 sdhc_2: mmc@8804000 { 4115 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 4116 pinctrl-names = "default", "sleep"; 4117 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 4118 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 4119 status = "disabled"; 4120 4121 reg = <0 0x08804000 0 0x1000>; 4122 4123 iommus = <&apps_smmu 0x100 0x0>; 4124 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4126 interrupt-names = "hc_irq", "pwr_irq"; 4127 4128 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4129 <&gcc GCC_SDCC2_APPS_CLK>, 4130 <&rpmhcc RPMH_CXO_CLK>; 4131 clock-names = "iface", "core", "xo"; 4132 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4133 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 4134 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4135 power-domains = <&rpmhpd SC7280_CX>; 4136 operating-points-v2 = <&sdhc2_opp_table>; 4137 4138 bus-width = <4>; 4139 dma-coherent; 4140 4141 qcom,dll-config = <0x0007642c>; 4142 4143 resets = <&gcc GCC_SDCC2_BCR>; 4144 4145 sdhc2_opp_table: opp-table { 4146 compatible = "operating-points-v2"; 4147 4148 opp-100000000 { 4149 opp-hz = /bits/ 64 <100000000>; 4150 required-opps = <&rpmhpd_opp_low_svs>; 4151 opp-peak-kBps = <1800000 400000>; 4152 opp-avg-kBps = <100000 0>; 4153 }; 4154 4155 opp-202000000 { 4156 opp-hz = /bits/ 64 <202000000>; 4157 required-opps = <&rpmhpd_opp_nom>; 4158 opp-peak-kBps = <5400000 1600000>; 4159 opp-avg-kBps = <200000 0>; 4160 }; 4161 }; 4162 }; 4163 4164 usb_1_hsphy: phy@88e3000 { 4165 compatible = "qcom,sc7280-usb-hs-phy", 4166 "qcom,usb-snps-hs-7nm-phy"; 4167 reg = <0 0x088e3000 0 0x400>; 4168 status = "disabled"; 4169 #phy-cells = <0>; 4170 4171 clocks = <&rpmhcc RPMH_CXO_CLK>; 4172 clock-names = "ref"; 4173 4174 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4175 }; 4176 4177 usb_2_hsphy: phy@88e4000 { 4178 compatible = "qcom,sc7280-usb-hs-phy", 4179 "qcom,usb-snps-hs-7nm-phy"; 4180 reg = <0 0x088e4000 0 0x400>; 4181 status = "disabled"; 4182 #phy-cells = <0>; 4183 4184 clocks = <&rpmhcc RPMH_CXO_CLK>; 4185 clock-names = "ref"; 4186 4187 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4188 }; 4189 4190 refgen: regulator@88e7000 { 4191 compatible = "qcom,sc7280-refgen-regulator", 4192 "qcom,sm8250-refgen-regulator"; 4193 reg = <0x0 0x088e7000 0x0 0x84>; 4194 }; 4195 4196 usb_1_qmpphy: phy@88e8000 { 4197 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 4198 reg = <0 0x088e8000 0 0x3000>; 4199 status = "disabled"; 4200 4201 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4202 <&rpmhcc RPMH_CXO_CLK>, 4203 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4204 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4205 clock-names = "aux", 4206 "ref", 4207 "com_aux", 4208 "usb3_pipe"; 4209 4210 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 4211 <&gcc GCC_USB3_PHY_PRIM_BCR>; 4212 reset-names = "phy", "common"; 4213 4214 #clock-cells = <1>; 4215 #phy-cells = <1>; 4216 4217 orientation-switch; 4218 4219 ports { 4220 #address-cells = <1>; 4221 #size-cells = <0>; 4222 4223 port@0 { 4224 reg = <0>; 4225 4226 usb_dp_qmpphy_out: endpoint { 4227 }; 4228 }; 4229 4230 port@1 { 4231 reg = <1>; 4232 4233 usb_dp_qmpphy_usb_ss_in: endpoint { 4234 remote-endpoint = <&usb_1_dwc3_ss>; 4235 }; 4236 }; 4237 4238 port@2 { 4239 reg = <2>; 4240 4241 usb_dp_qmpphy_dp_in: endpoint { 4242 remote-endpoint = <&mdss_dp_out>; 4243 }; 4244 }; 4245 }; 4246 }; 4247 4248 usb_2: usb@8c00000 { 4249 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4250 reg = <0 0x08c00000 0 0xfc100>; 4251 status = "disabled"; 4252 4253 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4254 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4255 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4256 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4257 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4258 clock-names = "cfg_noc", 4259 "core", 4260 "iface", 4261 "sleep", 4262 "mock_utmi"; 4263 4264 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4265 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4266 assigned-clock-rates = <19200000>, <200000000>; 4267 4268 interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 4269 <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 4270 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4271 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4272 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 4273 interrupt-names = "dwc_usb3", 4274 "pwr_event", 4275 "hs_phy_irq", 4276 "dp_hs_phy_irq", 4277 "dm_hs_phy_irq"; 4278 4279 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4280 required-opps = <&rpmhpd_opp_nom>; 4281 4282 resets = <&gcc GCC_USB30_SEC_BCR>; 4283 4284 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4285 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 4286 interconnect-names = "usb-ddr", "apps-usb"; 4287 4288 iommus = <&apps_smmu 0xa0 0x0>; 4289 snps,dis_u2_susphy_quirk; 4290 snps,dis_enblslpm_quirk; 4291 snps,dis-u1-entry-quirk; 4292 snps,dis-u2-entry-quirk; 4293 phys = <&usb_2_hsphy>; 4294 phy-names = "usb2-phy"; 4295 maximum-speed = "high-speed"; 4296 usb-role-switch; 4297 4298 port { 4299 usb2_role_switch: endpoint { 4300 remote-endpoint = <&eud_ep>; 4301 }; 4302 }; 4303 }; 4304 4305 qspi: spi@88dc000 { 4306 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 4307 reg = <0 0x088dc000 0 0x1000>; 4308 iommus = <&apps_smmu 0x20 0x0>; 4309 #address-cells = <1>; 4310 #size-cells = <0>; 4311 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 4312 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 4313 <&gcc GCC_QSPI_CORE_CLK>; 4314 clock-names = "iface", "core"; 4315 interconnects = <&gem_noc MASTER_APPSS_PROC 0 4316 &cnoc2 SLAVE_QSPI_0 0>; 4317 interconnect-names = "qspi-config"; 4318 power-domains = <&rpmhpd SC7280_CX>; 4319 operating-points-v2 = <&qspi_opp_table>; 4320 status = "disabled"; 4321 }; 4322 4323 remoteproc_adsp: remoteproc@3700000 { 4324 compatible = "qcom,sc7280-adsp-pas"; 4325 reg = <0 0x03700000 0 0x100>; 4326 4327 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4328 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4329 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4330 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4331 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4332 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4333 interrupt-names = "wdog", "fatal", "ready", "handover", 4334 "stop-ack", "shutdown-ack"; 4335 4336 clocks = <&rpmhcc RPMH_CXO_CLK>; 4337 clock-names = "xo"; 4338 4339 power-domains = <&rpmhpd SC7280_LCX>, 4340 <&rpmhpd SC7280_LMX>; 4341 power-domain-names = "lcx", "lmx"; 4342 4343 memory-region = <&adsp_mem>; 4344 4345 qcom,qmp = <&aoss_qmp>; 4346 4347 qcom,smem-states = <&adsp_smp2p_out 0>; 4348 qcom,smem-state-names = "stop"; 4349 4350 status = "disabled"; 4351 4352 remoteproc_adsp_glink: glink-edge { 4353 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4354 IPCC_MPROC_SIGNAL_GLINK_QMP 4355 IRQ_TYPE_EDGE_RISING>; 4356 4357 mboxes = <&ipcc IPCC_CLIENT_LPASS 4358 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4359 4360 label = "lpass"; 4361 qcom,remote-pid = <2>; 4362 4363 apr { 4364 compatible = "qcom,apr-v2"; 4365 qcom,glink-channels = "apr_audio_svc"; 4366 qcom,domain = <APR_DOMAIN_ADSP>; 4367 #address-cells = <1>; 4368 #size-cells = <0>; 4369 4370 service@3 { 4371 reg = <APR_SVC_ADSP_CORE>; 4372 compatible = "qcom,q6core"; 4373 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4374 }; 4375 4376 q6afe: service@4 { 4377 compatible = "qcom,q6afe"; 4378 reg = <APR_SVC_AFE>; 4379 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4380 4381 q6afedai: dais { 4382 compatible = "qcom,q6afe-dais"; 4383 #address-cells = <1>; 4384 #size-cells = <0>; 4385 #sound-dai-cells = <1>; 4386 }; 4387 4388 q6afecc: clock-controller { 4389 compatible = "qcom,q6afe-clocks"; 4390 #clock-cells = <2>; 4391 }; 4392 4393 q6usbdai: usbd { 4394 compatible = "qcom,q6usb"; 4395 iommus = <&apps_smmu 0x180f 0x0>; 4396 #sound-dai-cells = <1>; 4397 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 4398 }; 4399 }; 4400 4401 q6asm: service@7 { 4402 compatible = "qcom,q6asm"; 4403 reg = <APR_SVC_ASM>; 4404 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4405 4406 q6asmdai: dais { 4407 compatible = "qcom,q6asm-dais"; 4408 #address-cells = <1>; 4409 #size-cells = <0>; 4410 #sound-dai-cells = <1>; 4411 iommus = <&apps_smmu 0x1801 0x0>; 4412 4413 dai@0 { 4414 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 4415 }; 4416 4417 dai@1 { 4418 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 4419 }; 4420 4421 dai@2 { 4422 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 4423 }; 4424 }; 4425 }; 4426 4427 q6adm: service@8 { 4428 compatible = "qcom,q6adm"; 4429 reg = <APR_SVC_ADM>; 4430 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4431 4432 q6routing: routing { 4433 compatible = "qcom,q6adm-routing"; 4434 #sound-dai-cells = <0>; 4435 }; 4436 }; 4437 }; 4438 4439 fastrpc { 4440 compatible = "qcom,fastrpc"; 4441 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4442 label = "adsp"; 4443 qcom,non-secure-domain; 4444 memory-region = <&adsp_rpc_remote_heap_mem>; 4445 qcom,vmids = <QCOM_SCM_VMID_LPASS 4446 QCOM_SCM_VMID_ADSP_HEAP>; 4447 #address-cells = <1>; 4448 #size-cells = <0>; 4449 4450 compute-cb@3 { 4451 compatible = "qcom,fastrpc-compute-cb"; 4452 reg = <3>; 4453 iommus = <&apps_smmu 0x1803 0x0>; 4454 dma-coherent; 4455 }; 4456 4457 compute-cb@4 { 4458 compatible = "qcom,fastrpc-compute-cb"; 4459 reg = <4>; 4460 iommus = <&apps_smmu 0x1804 0x0>; 4461 dma-coherent; 4462 }; 4463 4464 compute-cb@5 { 4465 compatible = "qcom,fastrpc-compute-cb"; 4466 reg = <5>; 4467 iommus = <&apps_smmu 0x1805 0x0>; 4468 dma-coherent; 4469 }; 4470 }; 4471 }; 4472 }; 4473 4474 remoteproc_wpss: remoteproc@8a00000 { 4475 compatible = "qcom,sc7280-wpss-pas"; 4476 reg = <0 0x08a00000 0 0x10000>; 4477 4478 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 4479 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4480 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4481 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4482 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4483 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4484 interrupt-names = "wdog", "fatal", "ready", "handover", 4485 "stop-ack", "shutdown-ack"; 4486 4487 clocks = <&rpmhcc RPMH_CXO_CLK>; 4488 clock-names = "xo"; 4489 4490 power-domains = <&rpmhpd SC7280_CX>, 4491 <&rpmhpd SC7280_MX>; 4492 power-domain-names = "cx", "mx"; 4493 4494 memory-region = <&wpss_mem>; 4495 4496 qcom,qmp = <&aoss_qmp>; 4497 4498 qcom,smem-states = <&wpss_smp2p_out 0>; 4499 qcom,smem-state-names = "stop"; 4500 4501 4502 status = "disabled"; 4503 4504 glink-edge { 4505 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 4506 IPCC_MPROC_SIGNAL_GLINK_QMP 4507 IRQ_TYPE_EDGE_RISING>; 4508 mboxes = <&ipcc IPCC_CLIENT_WPSS 4509 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4510 4511 label = "wpss"; 4512 qcom,remote-pid = <13>; 4513 }; 4514 }; 4515 4516 pmu@9091000 { 4517 compatible = "qcom,sc7280-llcc-bwmon"; 4518 reg = <0 0x09091000 0 0x1000>; 4519 4520 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4521 4522 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4523 4524 operating-points-v2 = <&llcc_bwmon_opp_table>; 4525 4526 llcc_bwmon_opp_table: opp-table { 4527 compatible = "operating-points-v2"; 4528 4529 opp-0 { 4530 opp-peak-kBps = <800000>; 4531 }; 4532 opp-1 { 4533 opp-peak-kBps = <1804000>; 4534 }; 4535 opp-2 { 4536 opp-peak-kBps = <2188000>; 4537 }; 4538 opp-3 { 4539 opp-peak-kBps = <3072000>; 4540 }; 4541 opp-4 { 4542 opp-peak-kBps = <4068000>; 4543 }; 4544 opp-5 { 4545 opp-peak-kBps = <6220000>; 4546 }; 4547 opp-6 { 4548 opp-peak-kBps = <6832000>; 4549 }; 4550 opp-7 { 4551 opp-peak-kBps = <8532000>; 4552 }; 4553 opp-8 { 4554 opp-peak-kBps = <10944000>; 4555 }; 4556 opp-9 { 4557 opp-peak-kBps = <12787200>; 4558 }; 4559 }; 4560 }; 4561 4562 pmu@90b6400 { 4563 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 4564 reg = <0 0x090b6400 0 0x600>; 4565 4566 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4567 4568 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4569 operating-points-v2 = <&cpu_bwmon_opp_table>; 4570 4571 cpu_bwmon_opp_table: opp-table { 4572 compatible = "operating-points-v2"; 4573 4574 opp-0 { 4575 opp-peak-kBps = <2400000>; 4576 }; 4577 opp-1 { 4578 opp-peak-kBps = <4800000>; 4579 }; 4580 opp-2 { 4581 opp-peak-kBps = <7456000>; 4582 }; 4583 opp-3 { 4584 opp-peak-kBps = <9600000>; 4585 }; 4586 opp-4 { 4587 opp-peak-kBps = <12896000>; 4588 }; 4589 opp-5 { 4590 opp-peak-kBps = <14928000>; 4591 }; 4592 opp-6 { 4593 opp-peak-kBps = <17056000>; 4594 }; 4595 }; 4596 }; 4597 4598 dc_noc: interconnect@90e0000 { 4599 reg = <0 0x090e0000 0 0x5080>; 4600 compatible = "qcom,sc7280-dc-noc"; 4601 #interconnect-cells = <2>; 4602 qcom,bcm-voters = <&apps_bcm_voter>; 4603 }; 4604 4605 gem_noc: interconnect@9100000 { 4606 reg = <0 0x09100000 0 0xe2200>; 4607 compatible = "qcom,sc7280-gem-noc"; 4608 #interconnect-cells = <2>; 4609 qcom,bcm-voters = <&apps_bcm_voter>; 4610 }; 4611 4612 system-cache-controller@9200000 { 4613 compatible = "qcom,sc7280-llcc"; 4614 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4615 <0 0x09600000 0 0x58000>; 4616 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4617 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4618 }; 4619 4620 eud: eud@88e0000 { 4621 compatible = "qcom,sc7280-eud", "qcom,eud"; 4622 reg = <0 0x88e0000 0 0x2000>, 4623 <0 0x88e2000 0 0x1000>; 4624 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4625 4626 status = "disabled"; 4627 4628 ports { 4629 #address-cells = <1>; 4630 #size-cells = <0>; 4631 4632 port@0 { 4633 reg = <0>; 4634 eud_ep: endpoint { 4635 remote-endpoint = <&usb2_role_switch>; 4636 }; 4637 }; 4638 }; 4639 }; 4640 4641 nsp_noc: interconnect@a0c0000 { 4642 reg = <0 0x0a0c0000 0 0x10000>; 4643 compatible = "qcom,sc7280-nsp-noc"; 4644 #interconnect-cells = <2>; 4645 qcom,bcm-voters = <&apps_bcm_voter>; 4646 }; 4647 4648 remoteproc_cdsp: remoteproc@a300000 { 4649 compatible = "qcom,sc7280-cdsp-pas"; 4650 reg = <0 0x0a300000 0 0x10000>; 4651 4652 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4653 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4654 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4655 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4656 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4657 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4658 interrupt-names = "wdog", "fatal", "ready", "handover", 4659 "stop-ack", "shutdown-ack"; 4660 4661 clocks = <&rpmhcc RPMH_CXO_CLK>; 4662 clock-names = "xo"; 4663 4664 power-domains = <&rpmhpd SC7280_CX>, 4665 <&rpmhpd SC7280_MX>; 4666 power-domain-names = "cx", "mx"; 4667 4668 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4669 4670 memory-region = <&cdsp_mem>; 4671 4672 qcom,qmp = <&aoss_qmp>; 4673 4674 qcom,smem-states = <&cdsp_smp2p_out 0>; 4675 qcom,smem-state-names = "stop"; 4676 4677 status = "disabled"; 4678 4679 glink-edge { 4680 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4681 IPCC_MPROC_SIGNAL_GLINK_QMP 4682 IRQ_TYPE_EDGE_RISING>; 4683 mboxes = <&ipcc IPCC_CLIENT_CDSP 4684 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4685 4686 label = "cdsp"; 4687 qcom,remote-pid = <5>; 4688 4689 fastrpc { 4690 compatible = "qcom,fastrpc"; 4691 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4692 label = "cdsp"; 4693 qcom,non-secure-domain; 4694 #address-cells = <1>; 4695 #size-cells = <0>; 4696 4697 compute-cb@1 { 4698 compatible = "qcom,fastrpc-compute-cb"; 4699 reg = <1>; 4700 iommus = <&apps_smmu 0x11a1 0x0420>, 4701 <&apps_smmu 0x1181 0x0420>; 4702 dma-coherent; 4703 }; 4704 4705 compute-cb@2 { 4706 compatible = "qcom,fastrpc-compute-cb"; 4707 reg = <2>; 4708 iommus = <&apps_smmu 0x11a2 0x0420>, 4709 <&apps_smmu 0x1182 0x0420>; 4710 dma-coherent; 4711 }; 4712 4713 compute-cb@3 { 4714 compatible = "qcom,fastrpc-compute-cb"; 4715 reg = <3>; 4716 iommus = <&apps_smmu 0x11a3 0x0420>, 4717 <&apps_smmu 0x1183 0x0420>; 4718 dma-coherent; 4719 }; 4720 4721 compute-cb@4 { 4722 compatible = "qcom,fastrpc-compute-cb"; 4723 reg = <4>; 4724 iommus = <&apps_smmu 0x11a4 0x0420>, 4725 <&apps_smmu 0x1184 0x0420>; 4726 dma-coherent; 4727 }; 4728 4729 compute-cb@5 { 4730 compatible = "qcom,fastrpc-compute-cb"; 4731 reg = <5>; 4732 iommus = <&apps_smmu 0x11a5 0x0420>, 4733 <&apps_smmu 0x1185 0x0420>; 4734 dma-coherent; 4735 }; 4736 4737 compute-cb@6 { 4738 compatible = "qcom,fastrpc-compute-cb"; 4739 reg = <6>; 4740 iommus = <&apps_smmu 0x11a6 0x0420>, 4741 <&apps_smmu 0x1186 0x0420>; 4742 dma-coherent; 4743 }; 4744 4745 compute-cb@7 { 4746 compatible = "qcom,fastrpc-compute-cb"; 4747 reg = <7>; 4748 iommus = <&apps_smmu 0x11a7 0x0420>, 4749 <&apps_smmu 0x1187 0x0420>; 4750 dma-coherent; 4751 }; 4752 4753 compute-cb@8 { 4754 compatible = "qcom,fastrpc-compute-cb"; 4755 reg = <8>; 4756 iommus = <&apps_smmu 0x11a8 0x0420>, 4757 <&apps_smmu 0x1188 0x0420>; 4758 dma-coherent; 4759 }; 4760 4761 /* note: secure cb9 in downstream */ 4762 4763 compute-cb@11 { 4764 compatible = "qcom,fastrpc-compute-cb"; 4765 reg = <11>; 4766 iommus = <&apps_smmu 0x11ab 0x0420>, 4767 <&apps_smmu 0x118b 0x0420>; 4768 dma-coherent; 4769 }; 4770 4771 compute-cb@12 { 4772 compatible = "qcom,fastrpc-compute-cb"; 4773 reg = <12>; 4774 iommus = <&apps_smmu 0x11ac 0x0420>, 4775 <&apps_smmu 0x118c 0x0420>; 4776 dma-coherent; 4777 }; 4778 4779 compute-cb@13 { 4780 compatible = "qcom,fastrpc-compute-cb"; 4781 reg = <13>; 4782 iommus = <&apps_smmu 0x11ad 0x0420>, 4783 <&apps_smmu 0x118d 0x0420>; 4784 dma-coherent; 4785 }; 4786 4787 compute-cb@14 { 4788 compatible = "qcom,fastrpc-compute-cb"; 4789 reg = <14>; 4790 iommus = <&apps_smmu 0x11ae 0x0420>, 4791 <&apps_smmu 0x118e 0x0420>; 4792 dma-coherent; 4793 }; 4794 }; 4795 }; 4796 }; 4797 4798 usb_1: usb@a600000 { 4799 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4800 reg = <0 0x0a600000 0 0xfc100>; 4801 status = "disabled"; 4802 4803 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4804 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4805 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4806 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4807 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4808 clock-names = "cfg_noc", 4809 "core", 4810 "iface", 4811 "sleep", 4812 "mock_utmi"; 4813 4814 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4815 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4816 assigned-clock-rates = <19200000>, <200000000>; 4817 4818 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 4819 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4820 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4821 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4822 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4823 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4824 interrupt-names = "dwc_usb3", 4825 "pwr_event", 4826 "hs_phy_irq", 4827 "dp_hs_phy_irq", 4828 "dm_hs_phy_irq", 4829 "ss_phy_irq"; 4830 4831 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4832 required-opps = <&rpmhpd_opp_nom>; 4833 4834 resets = <&gcc GCC_USB30_PRIM_BCR>; 4835 4836 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4837 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4838 interconnect-names = "usb-ddr", "apps-usb"; 4839 4840 wakeup-source; 4841 4842 iommus = <&apps_smmu 0xe0 0x0>; 4843 snps,dis_u2_susphy_quirk; 4844 snps,dis_enblslpm_quirk; 4845 snps,parkmode-disable-ss-quirk; 4846 snps,dis-u1-entry-quirk; 4847 snps,dis-u2-entry-quirk; 4848 num-hc-interrupters = /bits/ 16 <3>; 4849 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4850 phy-names = "usb2-phy", "usb3-phy"; 4851 maximum-speed = "super-speed"; 4852 4853 ports { 4854 #address-cells = <1>; 4855 #size-cells = <0>; 4856 4857 port@0 { 4858 reg = <0>; 4859 4860 usb_1_dwc3_hs: endpoint { 4861 }; 4862 }; 4863 4864 port@1 { 4865 reg = <1>; 4866 4867 usb_1_dwc3_ss: endpoint { 4868 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4869 }; 4870 }; 4871 }; 4872 }; 4873 4874 venus: video-codec@aa00000 { 4875 compatible = "qcom,sc7280-venus"; 4876 reg = <0 0x0aa00000 0 0xd0600>; 4877 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4878 4879 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4880 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4881 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4882 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4883 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4884 clock-names = "core", "bus", "iface", 4885 "vcodec_core", "vcodec_bus"; 4886 4887 power-domains = <&videocc MVSC_GDSC>, 4888 <&videocc MVS0_GDSC>, 4889 <&rpmhpd SC7280_CX>; 4890 power-domain-names = "venus", "vcodec0", "cx"; 4891 operating-points-v2 = <&venus_opp_table>; 4892 4893 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4894 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4895 interconnect-names = "cpu-cfg", "video-mem"; 4896 4897 iommus = <&apps_smmu 0x2180 0x20>; 4898 memory-region = <&video_mem>; 4899 4900 status = "disabled"; 4901 4902 venus_opp_table: opp-table { 4903 compatible = "operating-points-v2"; 4904 4905 opp-133330000 { 4906 opp-hz = /bits/ 64 <133330000>; 4907 required-opps = <&rpmhpd_opp_low_svs>; 4908 }; 4909 4910 opp-240000000 { 4911 opp-hz = /bits/ 64 <240000000>; 4912 required-opps = <&rpmhpd_opp_svs>; 4913 }; 4914 4915 opp-335000000 { 4916 opp-hz = /bits/ 64 <335000000>; 4917 required-opps = <&rpmhpd_opp_svs_l1>; 4918 }; 4919 4920 opp-424000000 { 4921 opp-hz = /bits/ 64 <424000000>; 4922 required-opps = <&rpmhpd_opp_nom>; 4923 }; 4924 4925 opp-460000048 { 4926 opp-hz = /bits/ 64 <460000048>; 4927 required-opps = <&rpmhpd_opp_turbo>; 4928 }; 4929 }; 4930 }; 4931 4932 videocc: clock-controller@aaf0000 { 4933 compatible = "qcom,sc7280-videocc"; 4934 reg = <0 0x0aaf0000 0 0x10000>; 4935 clocks = <&rpmhcc RPMH_CXO_CLK>, 4936 <&rpmhcc RPMH_CXO_CLK_A>; 4937 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4938 #clock-cells = <1>; 4939 #reset-cells = <1>; 4940 #power-domain-cells = <1>; 4941 }; 4942 4943 cci0: cci@ac4a000 { 4944 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4945 reg = <0 0x0ac4a000 0 0x1000>; 4946 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4947 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4948 4949 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4950 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4951 <&camcc CAM_CC_CPAS_AHB_CLK>, 4952 <&camcc CAM_CC_CCI_0_CLK>, 4953 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4954 clock-names = "camnoc_axi", 4955 "slow_ahb_src", 4956 "cpas_ahb", 4957 "cci", 4958 "cci_src"; 4959 pinctrl-0 = <&cci0_default &cci1_default>; 4960 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4961 pinctrl-names = "default", "sleep"; 4962 4963 #address-cells = <1>; 4964 #size-cells = <0>; 4965 4966 status = "disabled"; 4967 4968 cci0_i2c0: i2c-bus@0 { 4969 reg = <0>; 4970 clock-frequency = <1000000>; 4971 #address-cells = <1>; 4972 #size-cells = <0>; 4973 }; 4974 4975 cci0_i2c1: i2c-bus@1 { 4976 reg = <1>; 4977 clock-frequency = <1000000>; 4978 #address-cells = <1>; 4979 #size-cells = <0>; 4980 }; 4981 }; 4982 4983 cci1: cci@ac4b000 { 4984 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4985 reg = <0 0x0ac4b000 0 0x1000>; 4986 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4987 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4988 4989 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4990 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4991 <&camcc CAM_CC_CPAS_AHB_CLK>, 4992 <&camcc CAM_CC_CCI_1_CLK>, 4993 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4994 clock-names = "camnoc_axi", 4995 "slow_ahb_src", 4996 "cpas_ahb", 4997 "cci", 4998 "cci_src"; 4999 pinctrl-0 = <&cci2_default &cci3_default>; 5000 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 5001 pinctrl-names = "default", "sleep"; 5002 5003 #address-cells = <1>; 5004 #size-cells = <0>; 5005 5006 status = "disabled"; 5007 5008 cci1_i2c0: i2c-bus@0 { 5009 reg = <0>; 5010 clock-frequency = <1000000>; 5011 #address-cells = <1>; 5012 #size-cells = <0>; 5013 }; 5014 5015 cci1_i2c1: i2c-bus@1 { 5016 reg = <1>; 5017 clock-frequency = <1000000>; 5018 #address-cells = <1>; 5019 #size-cells = <0>; 5020 }; 5021 }; 5022 5023 camss: isp@acb3000 { 5024 compatible = "qcom,sc7280-camss"; 5025 5026 reg = <0x0 0x0acb3000 0x0 0x1000>, 5027 <0x0 0x0acba000 0x0 0x1000>, 5028 <0x0 0x0acc1000 0x0 0x1000>, 5029 <0x0 0x0acc8000 0x0 0x1000>, 5030 <0x0 0x0accf000 0x0 0x1000>, 5031 <0x0 0x0ace0000 0x0 0x2000>, 5032 <0x0 0x0ace2000 0x0 0x2000>, 5033 <0x0 0x0ace4000 0x0 0x2000>, 5034 <0x0 0x0ace6000 0x0 0x2000>, 5035 <0x0 0x0ace8000 0x0 0x2000>, 5036 <0x0 0x0acaf000 0x0 0x4000>, 5037 <0x0 0x0acb6000 0x0 0x4000>, 5038 <0x0 0x0acbd000 0x0 0x4000>, 5039 <0x0 0x0acc4000 0x0 0x4000>, 5040 <0x0 0x0accb000 0x0 0x4000>; 5041 reg-names = "csid0", 5042 "csid1", 5043 "csid2", 5044 "csid_lite0", 5045 "csid_lite1", 5046 "csiphy0", 5047 "csiphy1", 5048 "csiphy2", 5049 "csiphy3", 5050 "csiphy4", 5051 "vfe0", 5052 "vfe1", 5053 "vfe2", 5054 "vfe_lite0", 5055 "vfe_lite1"; 5056 5057 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5058 <&camcc CAM_CC_CPAS_AHB_CLK>, 5059 <&camcc CAM_CC_CSIPHY0_CLK>, 5060 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5061 <&camcc CAM_CC_CSIPHY1_CLK>, 5062 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5063 <&camcc CAM_CC_CSIPHY2_CLK>, 5064 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5065 <&camcc CAM_CC_CSIPHY3_CLK>, 5066 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 5067 <&camcc CAM_CC_CSIPHY4_CLK>, 5068 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 5069 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5070 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5071 <&camcc CAM_CC_ICP_AHB_CLK>, 5072 <&camcc CAM_CC_IFE_0_CLK>, 5073 <&camcc CAM_CC_IFE_0_AXI_CLK>, 5074 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 5075 <&camcc CAM_CC_IFE_0_CSID_CLK>, 5076 <&camcc CAM_CC_IFE_1_CLK>, 5077 <&camcc CAM_CC_IFE_1_AXI_CLK>, 5078 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 5079 <&camcc CAM_CC_IFE_1_CSID_CLK>, 5080 <&camcc CAM_CC_IFE_2_CLK>, 5081 <&camcc CAM_CC_IFE_2_AXI_CLK>, 5082 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, 5083 <&camcc CAM_CC_IFE_2_CSID_CLK>, 5084 <&camcc CAM_CC_IFE_LITE_0_CLK>, 5085 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, 5086 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, 5087 <&camcc CAM_CC_IFE_LITE_1_CLK>, 5088 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, 5089 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; 5090 clock-names = "camnoc_axi", 5091 "cpas_ahb", 5092 "csiphy0", 5093 "csiphy0_timer", 5094 "csiphy1", 5095 "csiphy1_timer", 5096 "csiphy2", 5097 "csiphy2_timer", 5098 "csiphy3", 5099 "csiphy3_timer", 5100 "csiphy4", 5101 "csiphy4_timer", 5102 "gcc_axi_hf", 5103 "gcc_axi_sf", 5104 "icp_ahb", 5105 "vfe0", 5106 "vfe0_axi", 5107 "vfe0_cphy_rx", 5108 "vfe0_csid", 5109 "vfe1", 5110 "vfe1_axi", 5111 "vfe1_cphy_rx", 5112 "vfe1_csid", 5113 "vfe2", 5114 "vfe2_axi", 5115 "vfe2_cphy_rx", 5116 "vfe2_csid", 5117 "vfe_lite0", 5118 "vfe_lite0_cphy_rx", 5119 "vfe_lite0_csid", 5120 "vfe_lite1", 5121 "vfe_lite1_cphy_rx", 5122 "vfe_lite1_csid"; 5123 5124 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 5125 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 5126 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 5127 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5128 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5129 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5130 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5131 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5132 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 5133 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 5134 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5135 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5136 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 5137 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5138 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 5139 interrupt-names = "csid0", 5140 "csid1", 5141 "csid2", 5142 "csid_lite0", 5143 "csid_lite1", 5144 "csiphy0", 5145 "csiphy1", 5146 "csiphy2", 5147 "csiphy3", 5148 "csiphy4", 5149 "vfe0", 5150 "vfe1", 5151 "vfe2", 5152 "vfe_lite0", 5153 "vfe_lite1"; 5154 5155 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5156 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5157 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5159 interconnect-names = "ahb", 5160 "hf_0"; 5161 5162 iommus = <&apps_smmu 0x800 0x4e0>; 5163 5164 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 5165 <&camcc CAM_CC_IFE_1_GDSC>, 5166 <&camcc CAM_CC_IFE_2_GDSC>, 5167 <&camcc CAM_CC_TITAN_TOP_GDSC>; 5168 power-domain-names = "ife0", 5169 "ife1", 5170 "ife2", 5171 "top"; 5172 5173 status = "disabled"; 5174 5175 ports { 5176 #address-cells = <1>; 5177 #size-cells = <0>; 5178 5179 port@0 { 5180 reg = <0>; 5181 }; 5182 5183 port@1 { 5184 reg = <1>; 5185 }; 5186 5187 port@2 { 5188 reg = <2>; 5189 }; 5190 5191 port@3 { 5192 reg = <3>; 5193 }; 5194 5195 port@4 { 5196 reg = <4>; 5197 }; 5198 }; 5199 }; 5200 5201 camcc: clock-controller@ad00000 { 5202 compatible = "qcom,sc7280-camcc"; 5203 reg = <0 0x0ad00000 0 0x10000>; 5204 clocks = <&rpmhcc RPMH_CXO_CLK>, 5205 <&rpmhcc RPMH_CXO_CLK_A>, 5206 <&sleep_clk>; 5207 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 5208 #clock-cells = <1>; 5209 #reset-cells = <1>; 5210 #power-domain-cells = <1>; 5211 }; 5212 5213 dispcc: clock-controller@af00000 { 5214 compatible = "qcom,sc7280-dispcc"; 5215 reg = <0 0x0af00000 0 0x20000>; 5216 clocks = <&rpmhcc RPMH_CXO_CLK>, 5217 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 5218 <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5219 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, 5220 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5221 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5222 <&mdss_edp_phy 0>, 5223 <&mdss_edp_phy 1>; 5224 clock-names = "bi_tcxo", 5225 "gcc_disp_gpll0_clk", 5226 "dsi0_phy_pll_out_byteclk", 5227 "dsi0_phy_pll_out_dsiclk", 5228 "dp_phy_pll_link_clk", 5229 "dp_phy_pll_vco_div_clk", 5230 "edp_phy_pll_link_clk", 5231 "edp_phy_pll_vco_div_clk"; 5232 #clock-cells = <1>; 5233 #reset-cells = <1>; 5234 #power-domain-cells = <1>; 5235 }; 5236 5237 mdss: display-subsystem@ae00000 { 5238 compatible = "qcom,sc7280-mdss"; 5239 reg = <0 0x0ae00000 0 0x1000>; 5240 reg-names = "mdss"; 5241 5242 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 5243 5244 clocks = <&gcc GCC_DISP_AHB_CLK>, 5245 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5246 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5247 clock-names = "iface", 5248 "ahb", 5249 "core"; 5250 5251 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5252 interrupt-controller; 5253 #interrupt-cells = <1>; 5254 5255 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5256 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5257 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5258 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 5259 interconnect-names = "mdp0-mem", 5260 "cpu-cfg"; 5261 5262 iommus = <&apps_smmu 0x900 0x402>; 5263 5264 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5265 5266 #address-cells = <2>; 5267 #size-cells = <2>; 5268 ranges; 5269 5270 status = "disabled"; 5271 5272 mdss_mdp: display-controller@ae01000 { 5273 compatible = "qcom,sc7280-dpu"; 5274 reg = <0 0x0ae01000 0 0x8f030>, 5275 <0 0x0aeb0000 0 0x3000>; 5276 reg-names = "mdp", "vbif"; 5277 5278 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5279 <&gcc GCC_DISP_SF_AXI_CLK>, 5280 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5281 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5282 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5283 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5284 clock-names = "bus", 5285 "nrt_bus", 5286 "iface", 5287 "lut", 5288 "core", 5289 "vsync"; 5290 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 5291 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5292 assigned-clock-rates = <19200000>, 5293 <19200000>; 5294 operating-points-v2 = <&mdp_opp_table>; 5295 power-domains = <&rpmhpd SC7280_CX>; 5296 5297 interrupt-parent = <&mdss>; 5298 interrupts = <0>; 5299 5300 ports { 5301 #address-cells = <1>; 5302 #size-cells = <0>; 5303 5304 port@0 { 5305 reg = <0>; 5306 dpu_intf1_out: endpoint { 5307 remote-endpoint = <&mdss_dsi0_in>; 5308 }; 5309 }; 5310 5311 port@1 { 5312 reg = <1>; 5313 dpu_intf5_out: endpoint { 5314 remote-endpoint = <&edp_in>; 5315 }; 5316 }; 5317 5318 port@2 { 5319 reg = <2>; 5320 dpu_intf0_out: endpoint { 5321 remote-endpoint = <&dp_in>; 5322 }; 5323 }; 5324 }; 5325 5326 mdp_opp_table: opp-table { 5327 compatible = "operating-points-v2"; 5328 5329 opp-200000000 { 5330 opp-hz = /bits/ 64 <200000000>; 5331 required-opps = <&rpmhpd_opp_low_svs>; 5332 }; 5333 5334 opp-300000000 { 5335 opp-hz = /bits/ 64 <300000000>; 5336 required-opps = <&rpmhpd_opp_svs>; 5337 }; 5338 5339 opp-380000000 { 5340 opp-hz = /bits/ 64 <380000000>; 5341 required-opps = <&rpmhpd_opp_svs_l1>; 5342 }; 5343 5344 opp-506666667 { 5345 opp-hz = /bits/ 64 <506666667>; 5346 required-opps = <&rpmhpd_opp_nom>; 5347 }; 5348 5349 opp-608000000 { 5350 opp-hz = /bits/ 64 <608000000>; 5351 required-opps = <&rpmhpd_opp_turbo>; 5352 }; 5353 }; 5354 }; 5355 5356 mdss_dsi: dsi@ae94000 { 5357 compatible = "qcom,sc7280-dsi-ctrl", 5358 "qcom,mdss-dsi-ctrl"; 5359 reg = <0 0x0ae94000 0 0x400>; 5360 reg-names = "dsi_ctrl"; 5361 5362 interrupt-parent = <&mdss>; 5363 interrupts = <4>; 5364 5365 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5366 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5367 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5368 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5369 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5370 <&gcc GCC_DISP_HF_AXI_CLK>; 5371 clock-names = "byte", 5372 "byte_intf", 5373 "pixel", 5374 "core", 5375 "iface", 5376 "bus"; 5377 5378 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5379 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5380 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5381 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; 5382 5383 operating-points-v2 = <&dsi_opp_table>; 5384 power-domains = <&rpmhpd SC7280_CX>; 5385 5386 phys = <&mdss_dsi_phy>; 5387 5388 refgen-supply = <&refgen>; 5389 5390 #address-cells = <1>; 5391 #size-cells = <0>; 5392 5393 status = "disabled"; 5394 5395 ports { 5396 #address-cells = <1>; 5397 #size-cells = <0>; 5398 5399 port@0 { 5400 reg = <0>; 5401 mdss_dsi0_in: endpoint { 5402 remote-endpoint = <&dpu_intf1_out>; 5403 }; 5404 }; 5405 5406 port@1 { 5407 reg = <1>; 5408 mdss_dsi0_out: endpoint { 5409 }; 5410 }; 5411 }; 5412 5413 dsi_opp_table: opp-table { 5414 compatible = "operating-points-v2"; 5415 5416 opp-187500000 { 5417 opp-hz = /bits/ 64 <187500000>; 5418 required-opps = <&rpmhpd_opp_low_svs>; 5419 }; 5420 5421 opp-300000000 { 5422 opp-hz = /bits/ 64 <300000000>; 5423 required-opps = <&rpmhpd_opp_svs>; 5424 }; 5425 5426 opp-358000000 { 5427 opp-hz = /bits/ 64 <358000000>; 5428 required-opps = <&rpmhpd_opp_svs_l1>; 5429 }; 5430 }; 5431 }; 5432 5433 mdss_dsi_phy: phy@ae94400 { 5434 compatible = "qcom,sc7280-dsi-phy-7nm"; 5435 reg = <0 0x0ae94400 0 0x200>, 5436 <0 0x0ae94600 0 0x280>, 5437 <0 0x0ae94900 0 0x280>; 5438 reg-names = "dsi_phy", 5439 "dsi_phy_lane", 5440 "dsi_pll"; 5441 5442 #clock-cells = <1>; 5443 #phy-cells = <0>; 5444 5445 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5446 <&rpmhcc RPMH_CXO_CLK>; 5447 clock-names = "iface", "ref"; 5448 5449 status = "disabled"; 5450 }; 5451 5452 mdss_edp: edp@aea0000 { 5453 compatible = "qcom,sc7280-edp"; 5454 pinctrl-names = "default"; 5455 pinctrl-0 = <&edp_hot_plug_det>; 5456 5457 reg = <0 0x0aea0000 0 0x200>, 5458 <0 0x0aea0200 0 0x200>, 5459 <0 0x0aea0400 0 0xc00>, 5460 <0 0x0aea1000 0 0x400>, 5461 <0 0x0aea1400 0 0x400>; 5462 5463 interrupt-parent = <&mdss>; 5464 interrupts = <14>; 5465 5466 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5467 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 5468 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 5469 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 5470 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 5471 clock-names = "core_iface", 5472 "core_aux", 5473 "ctrl_link", 5474 "ctrl_link_iface", 5475 "stream_pixel"; 5476 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 5477 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 5478 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 5479 5480 phys = <&mdss_edp_phy>; 5481 phy-names = "dp"; 5482 5483 operating-points-v2 = <&edp_opp_table>; 5484 power-domains = <&rpmhpd SC7280_CX>; 5485 5486 status = "disabled"; 5487 5488 ports { 5489 #address-cells = <1>; 5490 #size-cells = <0>; 5491 5492 port@0 { 5493 reg = <0>; 5494 edp_in: endpoint { 5495 remote-endpoint = <&dpu_intf5_out>; 5496 }; 5497 }; 5498 5499 port@1 { 5500 reg = <1>; 5501 mdss_edp_out: endpoint { }; 5502 }; 5503 }; 5504 5505 edp_opp_table: opp-table { 5506 compatible = "operating-points-v2"; 5507 5508 opp-160000000 { 5509 opp-hz = /bits/ 64 <160000000>; 5510 required-opps = <&rpmhpd_opp_low_svs>; 5511 }; 5512 5513 opp-270000000 { 5514 opp-hz = /bits/ 64 <270000000>; 5515 required-opps = <&rpmhpd_opp_svs>; 5516 }; 5517 5518 opp-540000000 { 5519 opp-hz = /bits/ 64 <540000000>; 5520 required-opps = <&rpmhpd_opp_nom>; 5521 }; 5522 5523 opp-810000000 { 5524 opp-hz = /bits/ 64 <810000000>; 5525 required-opps = <&rpmhpd_opp_nom>; 5526 }; 5527 }; 5528 }; 5529 5530 mdss_edp_phy: phy@aec2a00 { 5531 compatible = "qcom,sc7280-edp-phy"; 5532 5533 reg = <0 0x0aec2a00 0 0x19c>, 5534 <0 0x0aec2200 0 0xa0>, 5535 <0 0x0aec2600 0 0xa0>, 5536 <0 0x0aec2000 0 0x1c0>; 5537 5538 clocks = <&rpmhcc RPMH_CXO_CLK>, 5539 <&gcc GCC_EDP_CLKREF_EN>; 5540 clock-names = "aux", 5541 "cfg_ahb"; 5542 5543 #clock-cells = <1>; 5544 #phy-cells = <0>; 5545 5546 status = "disabled"; 5547 }; 5548 5549 mdss_dp: displayport-controller@ae90000 { 5550 compatible = "qcom,sc7280-dp"; 5551 5552 reg = <0 0x0ae90000 0 0x200>, 5553 <0 0x0ae90200 0 0x200>, 5554 <0 0x0ae90400 0 0xc00>, 5555 <0 0x0ae91000 0 0x400>, 5556 <0 0x0ae91400 0 0x400>; 5557 5558 interrupt-parent = <&mdss>; 5559 interrupts = <12>; 5560 5561 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5562 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 5563 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 5564 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 5565 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 5566 clock-names = "core_iface", 5567 "core_aux", 5568 "ctrl_link", 5569 "ctrl_link_iface", 5570 "stream_pixel"; 5571 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 5572 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 5573 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5574 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5575 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5576 phy-names = "dp"; 5577 5578 operating-points-v2 = <&dp_opp_table>; 5579 power-domains = <&rpmhpd SC7280_CX>; 5580 5581 #sound-dai-cells = <0>; 5582 5583 status = "disabled"; 5584 5585 ports { 5586 #address-cells = <1>; 5587 #size-cells = <0>; 5588 5589 port@0 { 5590 reg = <0>; 5591 dp_in: endpoint { 5592 remote-endpoint = <&dpu_intf0_out>; 5593 }; 5594 }; 5595 5596 port@1 { 5597 reg = <1>; 5598 mdss_dp_out: endpoint { 5599 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5600 }; 5601 }; 5602 }; 5603 5604 dp_opp_table: opp-table { 5605 compatible = "operating-points-v2"; 5606 5607 opp-160000000 { 5608 opp-hz = /bits/ 64 <160000000>; 5609 required-opps = <&rpmhpd_opp_low_svs>; 5610 }; 5611 5612 opp-270000000 { 5613 opp-hz = /bits/ 64 <270000000>; 5614 required-opps = <&rpmhpd_opp_svs>; 5615 }; 5616 5617 opp-540000000 { 5618 opp-hz = /bits/ 64 <540000000>; 5619 required-opps = <&rpmhpd_opp_svs_l1>; 5620 }; 5621 5622 opp-810000000 { 5623 opp-hz = /bits/ 64 <810000000>; 5624 required-opps = <&rpmhpd_opp_nom>; 5625 }; 5626 }; 5627 }; 5628 }; 5629 5630 pdc: interrupt-controller@b220000 { 5631 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 5632 reg = <0 0x0b220000 0 0x30000>; 5633 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 5634 <55 306 4>, <59 312 3>, <62 374 2>, 5635 <64 434 2>, <66 438 3>, <69 86 1>, 5636 <70 520 54>, <124 609 31>, <155 63 1>, 5637 <156 716 12>; 5638 #interrupt-cells = <2>; 5639 interrupt-parent = <&intc>; 5640 interrupt-controller; 5641 }; 5642 5643 pdc_reset: reset-controller@b5e0000 { 5644 compatible = "qcom,sc7280-pdc-global"; 5645 reg = <0 0x0b5e0000 0 0x20000>; 5646 #reset-cells = <1>; 5647 status = "reserved"; /* Owned by firmware */ 5648 }; 5649 5650 tsens0: thermal-sensor@c263000 { 5651 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5652 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5653 <0 0x0c222000 0 0x1ff>; /* SROT */ 5654 #qcom,sensors = <15>; 5655 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5657 interrupt-names = "uplow","critical"; 5658 #thermal-sensor-cells = <1>; 5659 }; 5660 5661 tsens1: thermal-sensor@c265000 { 5662 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5663 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5664 <0 0x0c223000 0 0x1ff>; /* SROT */ 5665 #qcom,sensors = <12>; 5666 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5667 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5668 interrupt-names = "uplow","critical"; 5669 #thermal-sensor-cells = <1>; 5670 }; 5671 5672 aoss_reset: reset-controller@c2a0000 { 5673 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 5674 reg = <0 0x0c2a0000 0 0x31000>; 5675 #reset-cells = <1>; 5676 }; 5677 5678 aoss_qmp: power-management@c300000 { 5679 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 5680 reg = <0 0x0c300000 0 0x400>; 5681 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5682 IPCC_MPROC_SIGNAL_GLINK_QMP 5683 IRQ_TYPE_EDGE_RISING>; 5684 mboxes = <&ipcc IPCC_CLIENT_AOP 5685 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5686 5687 #clock-cells = <0>; 5688 }; 5689 5690 sram@c3f0000 { 5691 compatible = "qcom,rpmh-stats"; 5692 reg = <0 0x0c3f0000 0 0x400>; 5693 }; 5694 5695 spmi_bus: spmi@c440000 { 5696 compatible = "qcom,spmi-pmic-arb"; 5697 reg = <0 0x0c440000 0 0x1100>, 5698 <0 0x0c600000 0 0x2000000>, 5699 <0 0x0e600000 0 0x100000>, 5700 <0 0x0e700000 0 0xa0000>, 5701 <0 0x0c40a000 0 0x26000>; 5702 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5703 interrupt-names = "periph_irq"; 5704 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5705 qcom,ee = <0>; 5706 qcom,channel = <0>; 5707 #address-cells = <2>; 5708 #size-cells = <0>; 5709 interrupt-controller; 5710 #interrupt-cells = <4>; 5711 }; 5712 5713 tlmm: pinctrl@f100000 { 5714 compatible = "qcom,sc7280-pinctrl"; 5715 reg = <0 0x0f100000 0 0x300000>; 5716 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5717 gpio-controller; 5718 #gpio-cells = <2>; 5719 interrupt-controller; 5720 #interrupt-cells = <2>; 5721 gpio-ranges = <&tlmm 0 0 175>; 5722 wakeup-parent = <&pdc>; 5723 5724 cci0_default: cci0-default-state { 5725 pins = "gpio69", "gpio70"; 5726 function = "cci_i2c"; 5727 drive-strength = <2>; 5728 bias-pull-up; 5729 }; 5730 5731 cci0_sleep: cci0-sleep-state { 5732 pins = "gpio69", "gpio70"; 5733 function = "cci_i2c"; 5734 drive-strength = <2>; 5735 bias-pull-down; 5736 }; 5737 5738 cci1_default: cci1-default-state { 5739 pins = "gpio71", "gpio72"; 5740 function = "cci_i2c"; 5741 drive-strength = <2>; 5742 bias-pull-up; 5743 }; 5744 5745 cci1_sleep: cci1-sleep-state { 5746 pins = "gpio71", "gpio72"; 5747 function = "cci_i2c"; 5748 drive-strength = <2>; 5749 bias-pull-down; 5750 }; 5751 5752 cci2_default: cci2-default-state { 5753 pins = "gpio73", "gpio74"; 5754 function = "cci_i2c"; 5755 drive-strength = <2>; 5756 bias-pull-up; 5757 }; 5758 5759 cci2_sleep: cci2-sleep-state { 5760 pins = "gpio73", "gpio74"; 5761 function = "cci_i2c"; 5762 drive-strength = <2>; 5763 bias-pull-down; 5764 }; 5765 5766 cci3_default: cci3-default-state { 5767 pins = "gpio75", "gpio76"; 5768 function = "cci_i2c"; 5769 drive-strength = <2>; 5770 bias-pull-up; 5771 }; 5772 5773 cci3_sleep: cci3-sleep-state { 5774 pins = "gpio75", "gpio76"; 5775 function = "cci_i2c"; 5776 drive-strength = <2>; 5777 bias-pull-down; 5778 }; 5779 5780 dp_hot_plug_det: dp-hot-plug-det-state { 5781 pins = "gpio47"; 5782 function = "dp_hot"; 5783 }; 5784 5785 edp_hot_plug_det: edp-hot-plug-det-state { 5786 pins = "gpio60"; 5787 function = "edp_hot"; 5788 }; 5789 5790 mi2s0_data0: mi2s0-data0-state { 5791 pins = "gpio98"; 5792 function = "mi2s0_data0"; 5793 }; 5794 5795 mi2s0_data1: mi2s0-data1-state { 5796 pins = "gpio99"; 5797 function = "mi2s0_data1"; 5798 }; 5799 5800 mi2s0_mclk: mi2s0-mclk-state { 5801 pins = "gpio96"; 5802 function = "pri_mi2s"; 5803 }; 5804 5805 mi2s0_sclk: mi2s0-sclk-state { 5806 pins = "gpio97"; 5807 function = "mi2s0_sck"; 5808 }; 5809 5810 mi2s0_ws: mi2s0-ws-state { 5811 pins = "gpio100"; 5812 function = "mi2s0_ws"; 5813 }; 5814 5815 mi2s1_data0: mi2s1-data0-state { 5816 pins = "gpio107"; 5817 function = "mi2s1_data0"; 5818 }; 5819 5820 mi2s1_sclk: mi2s1-sclk-state { 5821 pins = "gpio106"; 5822 function = "mi2s1_sck"; 5823 }; 5824 5825 mi2s1_ws: mi2s1-ws-state { 5826 pins = "gpio108"; 5827 function = "mi2s1_ws"; 5828 }; 5829 5830 pcie0_clkreq_n: pcie0-clkreq-n-state { 5831 pins = "gpio88"; 5832 function = "pcie0_clkreqn"; 5833 }; 5834 5835 pcie1_clkreq_n: pcie1-clkreq-n-state { 5836 pins = "gpio79"; 5837 function = "pcie1_clkreqn"; 5838 }; 5839 5840 qspi_clk: qspi-clk-state { 5841 pins = "gpio14"; 5842 function = "qspi_clk"; 5843 }; 5844 5845 qspi_cs0: qspi-cs0-state { 5846 pins = "gpio15"; 5847 function = "qspi_cs"; 5848 }; 5849 5850 qspi_cs1: qspi-cs1-state { 5851 pins = "gpio19"; 5852 function = "qspi_cs"; 5853 }; 5854 5855 qspi_data0: qspi-data0-state { 5856 pins = "gpio12"; 5857 function = "qspi_data"; 5858 }; 5859 5860 qspi_data1: qspi-data1-state { 5861 pins = "gpio13"; 5862 function = "qspi_data"; 5863 }; 5864 5865 qspi_data23: qspi-data23-state { 5866 pins = "gpio16", "gpio17"; 5867 function = "qspi_data"; 5868 }; 5869 5870 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5871 pins = "gpio0", "gpio1"; 5872 function = "qup00"; 5873 }; 5874 5875 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5876 pins = "gpio4", "gpio5"; 5877 function = "qup01"; 5878 }; 5879 5880 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5881 pins = "gpio8", "gpio9"; 5882 function = "qup02"; 5883 }; 5884 5885 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5886 pins = "gpio12", "gpio13"; 5887 function = "qup03"; 5888 }; 5889 5890 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5891 pins = "gpio16", "gpio17"; 5892 function = "qup04"; 5893 }; 5894 5895 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5896 pins = "gpio20", "gpio21"; 5897 function = "qup05"; 5898 }; 5899 5900 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5901 pins = "gpio24", "gpio25"; 5902 function = "qup06"; 5903 }; 5904 5905 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5906 pins = "gpio28", "gpio29"; 5907 function = "qup07"; 5908 }; 5909 5910 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5911 pins = "gpio32", "gpio33"; 5912 function = "qup10"; 5913 }; 5914 5915 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5916 pins = "gpio36", "gpio37"; 5917 function = "qup11"; 5918 }; 5919 5920 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5921 pins = "gpio40", "gpio41"; 5922 function = "qup12"; 5923 }; 5924 5925 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5926 pins = "gpio44", "gpio45"; 5927 function = "qup13"; 5928 }; 5929 5930 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5931 pins = "gpio48", "gpio49"; 5932 function = "qup14"; 5933 }; 5934 5935 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5936 pins = "gpio52", "gpio53"; 5937 function = "qup15"; 5938 }; 5939 5940 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5941 pins = "gpio56", "gpio57"; 5942 function = "qup16"; 5943 }; 5944 5945 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5946 pins = "gpio60", "gpio61"; 5947 function = "qup17"; 5948 }; 5949 5950 qup_spi0_data_clk: qup-spi0-data-clk-state { 5951 pins = "gpio0", "gpio1", "gpio2"; 5952 function = "qup00"; 5953 }; 5954 5955 qup_spi0_cs: qup-spi0-cs-state { 5956 pins = "gpio3"; 5957 function = "qup00"; 5958 }; 5959 5960 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5961 pins = "gpio3"; 5962 function = "gpio"; 5963 }; 5964 5965 qup_spi1_data_clk: qup-spi1-data-clk-state { 5966 pins = "gpio4", "gpio5", "gpio6"; 5967 function = "qup01"; 5968 }; 5969 5970 qup_spi1_cs: qup-spi1-cs-state { 5971 pins = "gpio7"; 5972 function = "qup01"; 5973 }; 5974 5975 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5976 pins = "gpio7"; 5977 function = "gpio"; 5978 }; 5979 5980 qup_spi2_data_clk: qup-spi2-data-clk-state { 5981 pins = "gpio8", "gpio9", "gpio10"; 5982 function = "qup02"; 5983 }; 5984 5985 qup_spi2_cs: qup-spi2-cs-state { 5986 pins = "gpio11"; 5987 function = "qup02"; 5988 }; 5989 5990 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5991 pins = "gpio11"; 5992 function = "gpio"; 5993 }; 5994 5995 qup_spi3_data_clk: qup-spi3-data-clk-state { 5996 pins = "gpio12", "gpio13", "gpio14"; 5997 function = "qup03"; 5998 }; 5999 6000 qup_spi3_cs: qup-spi3-cs-state { 6001 pins = "gpio15"; 6002 function = "qup03"; 6003 }; 6004 6005 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6006 pins = "gpio15"; 6007 function = "gpio"; 6008 }; 6009 6010 qup_spi4_data_clk: qup-spi4-data-clk-state { 6011 pins = "gpio16", "gpio17", "gpio18"; 6012 function = "qup04"; 6013 }; 6014 6015 qup_spi4_cs: qup-spi4-cs-state { 6016 pins = "gpio19"; 6017 function = "qup04"; 6018 }; 6019 6020 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6021 pins = "gpio19"; 6022 function = "gpio"; 6023 }; 6024 6025 qup_spi5_data_clk: qup-spi5-data-clk-state { 6026 pins = "gpio20", "gpio21", "gpio22"; 6027 function = "qup05"; 6028 }; 6029 6030 qup_spi5_cs: qup-spi5-cs-state { 6031 pins = "gpio23"; 6032 function = "qup05"; 6033 }; 6034 6035 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6036 pins = "gpio23"; 6037 function = "gpio"; 6038 }; 6039 6040 qup_spi6_data_clk: qup-spi6-data-clk-state { 6041 pins = "gpio24", "gpio25", "gpio26"; 6042 function = "qup06"; 6043 }; 6044 6045 qup_spi6_cs: qup-spi6-cs-state { 6046 pins = "gpio27"; 6047 function = "qup06"; 6048 }; 6049 6050 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6051 pins = "gpio27"; 6052 function = "gpio"; 6053 }; 6054 6055 qup_spi7_data_clk: qup-spi7-data-clk-state { 6056 pins = "gpio28", "gpio29", "gpio30"; 6057 function = "qup07"; 6058 }; 6059 6060 qup_spi7_cs: qup-spi7-cs-state { 6061 pins = "gpio31"; 6062 function = "qup07"; 6063 }; 6064 6065 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 6066 pins = "gpio31"; 6067 function = "gpio"; 6068 }; 6069 6070 qup_spi8_data_clk: qup-spi8-data-clk-state { 6071 pins = "gpio32", "gpio33", "gpio34"; 6072 function = "qup10"; 6073 }; 6074 6075 qup_spi8_cs: qup-spi8-cs-state { 6076 pins = "gpio35"; 6077 function = "qup10"; 6078 }; 6079 6080 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6081 pins = "gpio35"; 6082 function = "gpio"; 6083 }; 6084 6085 qup_spi9_data_clk: qup-spi9-data-clk-state { 6086 pins = "gpio36", "gpio37", "gpio38"; 6087 function = "qup11"; 6088 }; 6089 6090 qup_spi9_cs: qup-spi9-cs-state { 6091 pins = "gpio39"; 6092 function = "qup11"; 6093 }; 6094 6095 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6096 pins = "gpio39"; 6097 function = "gpio"; 6098 }; 6099 6100 qup_spi10_data_clk: qup-spi10-data-clk-state { 6101 pins = "gpio40", "gpio41", "gpio42"; 6102 function = "qup12"; 6103 }; 6104 6105 qup_spi10_cs: qup-spi10-cs-state { 6106 pins = "gpio43"; 6107 function = "qup12"; 6108 }; 6109 6110 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6111 pins = "gpio43"; 6112 function = "gpio"; 6113 }; 6114 6115 qup_spi11_data_clk: qup-spi11-data-clk-state { 6116 pins = "gpio44", "gpio45", "gpio46"; 6117 function = "qup13"; 6118 }; 6119 6120 qup_spi11_cs: qup-spi11-cs-state { 6121 pins = "gpio47"; 6122 function = "qup13"; 6123 }; 6124 6125 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 6126 pins = "gpio47"; 6127 function = "gpio"; 6128 }; 6129 6130 qup_spi12_data_clk: qup-spi12-data-clk-state { 6131 pins = "gpio48", "gpio49", "gpio50"; 6132 function = "qup14"; 6133 }; 6134 6135 qup_spi12_cs: qup-spi12-cs-state { 6136 pins = "gpio51"; 6137 function = "qup14"; 6138 }; 6139 6140 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6141 pins = "gpio51"; 6142 function = "gpio"; 6143 }; 6144 6145 qup_spi13_data_clk: qup-spi13-data-clk-state { 6146 pins = "gpio52", "gpio53", "gpio54"; 6147 function = "qup15"; 6148 }; 6149 6150 qup_spi13_cs: qup-spi13-cs-state { 6151 pins = "gpio55"; 6152 function = "qup15"; 6153 }; 6154 6155 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6156 pins = "gpio55"; 6157 function = "gpio"; 6158 }; 6159 6160 qup_spi14_data_clk: qup-spi14-data-clk-state { 6161 pins = "gpio56", "gpio57", "gpio58"; 6162 function = "qup16"; 6163 }; 6164 6165 qup_spi14_cs: qup-spi14-cs-state { 6166 pins = "gpio59"; 6167 function = "qup16"; 6168 }; 6169 6170 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6171 pins = "gpio59"; 6172 function = "gpio"; 6173 }; 6174 6175 qup_spi15_data_clk: qup-spi15-data-clk-state { 6176 pins = "gpio60", "gpio61", "gpio62"; 6177 function = "qup17"; 6178 }; 6179 6180 qup_spi15_cs: qup-spi15-cs-state { 6181 pins = "gpio63"; 6182 function = "qup17"; 6183 }; 6184 6185 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6186 pins = "gpio63"; 6187 function = "gpio"; 6188 }; 6189 6190 qup_uart0_cts: qup-uart0-cts-state { 6191 pins = "gpio0"; 6192 function = "qup00"; 6193 }; 6194 6195 qup_uart0_rts: qup-uart0-rts-state { 6196 pins = "gpio1"; 6197 function = "qup00"; 6198 }; 6199 6200 qup_uart0_tx: qup-uart0-tx-state { 6201 pins = "gpio2"; 6202 function = "qup00"; 6203 }; 6204 6205 qup_uart0_rx: qup-uart0-rx-state { 6206 pins = "gpio3"; 6207 function = "qup00"; 6208 }; 6209 6210 qup_uart1_cts: qup-uart1-cts-state { 6211 pins = "gpio4"; 6212 function = "qup01"; 6213 }; 6214 6215 qup_uart1_rts: qup-uart1-rts-state { 6216 pins = "gpio5"; 6217 function = "qup01"; 6218 }; 6219 6220 qup_uart1_tx: qup-uart1-tx-state { 6221 pins = "gpio6"; 6222 function = "qup01"; 6223 }; 6224 6225 qup_uart1_rx: qup-uart1-rx-state { 6226 pins = "gpio7"; 6227 function = "qup01"; 6228 }; 6229 6230 qup_uart2_cts: qup-uart2-cts-state { 6231 pins = "gpio8"; 6232 function = "qup02"; 6233 }; 6234 6235 qup_uart2_rts: qup-uart2-rts-state { 6236 pins = "gpio9"; 6237 function = "qup02"; 6238 }; 6239 6240 qup_uart2_tx: qup-uart2-tx-state { 6241 pins = "gpio10"; 6242 function = "qup02"; 6243 }; 6244 6245 qup_uart2_rx: qup-uart2-rx-state { 6246 pins = "gpio11"; 6247 function = "qup02"; 6248 }; 6249 6250 qup_uart3_cts: qup-uart3-cts-state { 6251 pins = "gpio12"; 6252 function = "qup03"; 6253 }; 6254 6255 qup_uart3_rts: qup-uart3-rts-state { 6256 pins = "gpio13"; 6257 function = "qup03"; 6258 }; 6259 6260 qup_uart3_tx: qup-uart3-tx-state { 6261 pins = "gpio14"; 6262 function = "qup03"; 6263 }; 6264 6265 qup_uart3_rx: qup-uart3-rx-state { 6266 pins = "gpio15"; 6267 function = "qup03"; 6268 }; 6269 6270 qup_uart4_cts: qup-uart4-cts-state { 6271 pins = "gpio16"; 6272 function = "qup04"; 6273 }; 6274 6275 qup_uart4_rts: qup-uart4-rts-state { 6276 pins = "gpio17"; 6277 function = "qup04"; 6278 }; 6279 6280 qup_uart4_tx: qup-uart4-tx-state { 6281 pins = "gpio18"; 6282 function = "qup04"; 6283 }; 6284 6285 qup_uart4_rx: qup-uart4-rx-state { 6286 pins = "gpio19"; 6287 function = "qup04"; 6288 }; 6289 6290 qup_uart5_tx: qup-uart5-tx-state { 6291 pins = "gpio22"; 6292 function = "qup05"; 6293 }; 6294 6295 qup_uart5_rx: qup-uart5-rx-state { 6296 pins = "gpio23"; 6297 function = "qup05"; 6298 }; 6299 6300 qup_uart6_cts: qup-uart6-cts-state { 6301 pins = "gpio24"; 6302 function = "qup06"; 6303 }; 6304 6305 qup_uart6_rts: qup-uart6-rts-state { 6306 pins = "gpio25"; 6307 function = "qup06"; 6308 }; 6309 6310 qup_uart6_tx: qup-uart6-tx-state { 6311 pins = "gpio26"; 6312 function = "qup06"; 6313 }; 6314 6315 qup_uart6_rx: qup-uart6-rx-state { 6316 pins = "gpio27"; 6317 function = "qup06"; 6318 }; 6319 6320 qup_uart7_cts: qup-uart7-cts-state { 6321 pins = "gpio28"; 6322 function = "qup07"; 6323 }; 6324 6325 qup_uart7_rts: qup-uart7-rts-state { 6326 pins = "gpio29"; 6327 function = "qup07"; 6328 }; 6329 6330 qup_uart7_tx: qup-uart7-tx-state { 6331 pins = "gpio30"; 6332 function = "qup07"; 6333 }; 6334 6335 qup_uart7_rx: qup-uart7-rx-state { 6336 pins = "gpio31"; 6337 function = "qup07"; 6338 }; 6339 6340 qup_uart8_cts: qup-uart8-cts-state { 6341 pins = "gpio32"; 6342 function = "qup10"; 6343 }; 6344 6345 qup_uart8_rts: qup-uart8-rts-state { 6346 pins = "gpio33"; 6347 function = "qup10"; 6348 }; 6349 6350 qup_uart8_tx: qup-uart8-tx-state { 6351 pins = "gpio34"; 6352 function = "qup10"; 6353 }; 6354 6355 qup_uart8_rx: qup-uart8-rx-state { 6356 pins = "gpio35"; 6357 function = "qup10"; 6358 }; 6359 6360 qup_uart9_cts: qup-uart9-cts-state { 6361 pins = "gpio36"; 6362 function = "qup11"; 6363 }; 6364 6365 qup_uart9_rts: qup-uart9-rts-state { 6366 pins = "gpio37"; 6367 function = "qup11"; 6368 }; 6369 6370 qup_uart9_tx: qup-uart9-tx-state { 6371 pins = "gpio38"; 6372 function = "qup11"; 6373 }; 6374 6375 qup_uart9_rx: qup-uart9-rx-state { 6376 pins = "gpio39"; 6377 function = "qup11"; 6378 }; 6379 6380 qup_uart10_cts: qup-uart10-cts-state { 6381 pins = "gpio40"; 6382 function = "qup12"; 6383 }; 6384 6385 qup_uart10_rts: qup-uart10-rts-state { 6386 pins = "gpio41"; 6387 function = "qup12"; 6388 }; 6389 6390 qup_uart10_tx: qup-uart10-tx-state { 6391 pins = "gpio42"; 6392 function = "qup12"; 6393 }; 6394 6395 qup_uart10_rx: qup-uart10-rx-state { 6396 pins = "gpio43"; 6397 function = "qup12"; 6398 }; 6399 6400 qup_uart11_cts: qup-uart11-cts-state { 6401 pins = "gpio44"; 6402 function = "qup13"; 6403 }; 6404 6405 qup_uart11_rts: qup-uart11-rts-state { 6406 pins = "gpio45"; 6407 function = "qup13"; 6408 }; 6409 6410 qup_uart11_tx: qup-uart11-tx-state { 6411 pins = "gpio46"; 6412 function = "qup13"; 6413 }; 6414 6415 qup_uart11_rx: qup-uart11-rx-state { 6416 pins = "gpio47"; 6417 function = "qup13"; 6418 }; 6419 6420 qup_uart12_cts: qup-uart12-cts-state { 6421 pins = "gpio48"; 6422 function = "qup14"; 6423 }; 6424 6425 qup_uart12_rts: qup-uart12-rts-state { 6426 pins = "gpio49"; 6427 function = "qup14"; 6428 }; 6429 6430 qup_uart12_tx: qup-uart12-tx-state { 6431 pins = "gpio50"; 6432 function = "qup14"; 6433 }; 6434 6435 qup_uart12_rx: qup-uart12-rx-state { 6436 pins = "gpio51"; 6437 function = "qup14"; 6438 }; 6439 6440 qup_uart13_cts: qup-uart13-cts-state { 6441 pins = "gpio52"; 6442 function = "qup15"; 6443 }; 6444 6445 qup_uart13_rts: qup-uart13-rts-state { 6446 pins = "gpio53"; 6447 function = "qup15"; 6448 }; 6449 6450 qup_uart13_tx: qup-uart13-tx-state { 6451 pins = "gpio54"; 6452 function = "qup15"; 6453 }; 6454 6455 qup_uart13_rx: qup-uart13-rx-state { 6456 pins = "gpio55"; 6457 function = "qup15"; 6458 }; 6459 6460 qup_uart14_cts: qup-uart14-cts-state { 6461 pins = "gpio56"; 6462 function = "qup16"; 6463 }; 6464 6465 qup_uart14_rts: qup-uart14-rts-state { 6466 pins = "gpio57"; 6467 function = "qup16"; 6468 }; 6469 6470 qup_uart14_tx: qup-uart14-tx-state { 6471 pins = "gpio58"; 6472 function = "qup16"; 6473 }; 6474 6475 qup_uart14_rx: qup-uart14-rx-state { 6476 pins = "gpio59"; 6477 function = "qup16"; 6478 }; 6479 6480 qup_uart15_cts: qup-uart15-cts-state { 6481 pins = "gpio60"; 6482 function = "qup17"; 6483 }; 6484 6485 qup_uart15_rts: qup-uart15-rts-state { 6486 pins = "gpio61"; 6487 function = "qup17"; 6488 }; 6489 6490 qup_uart15_tx: qup-uart15-tx-state { 6491 pins = "gpio62"; 6492 function = "qup17"; 6493 }; 6494 6495 qup_uart15_rx: qup-uart15-rx-state { 6496 pins = "gpio63"; 6497 function = "qup17"; 6498 }; 6499 6500 sdc1_clk: sdc1-clk-state { 6501 pins = "sdc1_clk"; 6502 }; 6503 6504 sdc1_cmd: sdc1-cmd-state { 6505 pins = "sdc1_cmd"; 6506 }; 6507 6508 sdc1_data: sdc1-data-state { 6509 pins = "sdc1_data"; 6510 }; 6511 6512 sdc1_rclk: sdc1-rclk-state { 6513 pins = "sdc1_rclk"; 6514 }; 6515 6516 sdc1_clk_sleep: sdc1-clk-sleep-state { 6517 pins = "sdc1_clk"; 6518 drive-strength = <2>; 6519 bias-bus-hold; 6520 }; 6521 6522 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 6523 pins = "sdc1_cmd"; 6524 drive-strength = <2>; 6525 bias-bus-hold; 6526 }; 6527 6528 sdc1_data_sleep: sdc1-data-sleep-state { 6529 pins = "sdc1_data"; 6530 drive-strength = <2>; 6531 bias-bus-hold; 6532 }; 6533 6534 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 6535 pins = "sdc1_rclk"; 6536 drive-strength = <2>; 6537 bias-bus-hold; 6538 }; 6539 6540 sdc2_clk: sdc2-clk-state { 6541 pins = "sdc2_clk"; 6542 }; 6543 6544 sdc2_cmd: sdc2-cmd-state { 6545 pins = "sdc2_cmd"; 6546 }; 6547 6548 sdc2_data: sdc2-data-state { 6549 pins = "sdc2_data"; 6550 }; 6551 6552 sdc2_clk_sleep: sdc2-clk-sleep-state { 6553 pins = "sdc2_clk"; 6554 drive-strength = <2>; 6555 bias-bus-hold; 6556 }; 6557 6558 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 6559 pins = "sdc2_cmd"; 6560 drive-strength = <2>; 6561 bias-bus-hold; 6562 }; 6563 6564 sdc2_data_sleep: sdc2-data-sleep-state { 6565 pins = "sdc2_data"; 6566 drive-strength = <2>; 6567 bias-bus-hold; 6568 }; 6569 }; 6570 6571 sram@146a5000 { 6572 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 6573 reg = <0 0x146a5000 0 0x6000>; 6574 6575 #address-cells = <1>; 6576 #size-cells = <1>; 6577 6578 ranges = <0 0 0x146a5000 0x6000>; 6579 6580 pil-reloc@594c { 6581 compatible = "qcom,pil-reloc-info"; 6582 reg = <0x594c 0xc8>; 6583 }; 6584 }; 6585 6586 apps_smmu: iommu@15000000 { 6587 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 6588 reg = <0 0x15000000 0 0x100000>; 6589 #iommu-cells = <2>; 6590 #global-interrupts = <1>; 6591 dma-coherent; 6592 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6593 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 6594 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6595 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6596 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6597 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6599 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6600 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6601 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6602 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6603 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6604 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6605 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6606 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6607 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6608 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6609 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6610 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6611 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6612 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6613 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6614 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6615 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6616 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6617 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6618 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6619 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6620 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6621 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6622 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6623 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6624 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6625 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6626 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6627 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6628 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6630 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6631 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6632 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6633 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6634 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6635 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6636 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6637 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6638 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6639 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6640 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6641 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6642 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6643 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6644 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6645 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6646 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6647 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6648 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6649 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6650 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6651 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6652 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6653 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6654 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6655 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6656 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6657 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6658 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6660 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6661 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6662 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6663 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6664 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6665 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6666 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6667 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6668 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6669 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6670 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6671 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6672 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 6673 }; 6674 6675 anoc_1_tbu: tbu@151dd000 { 6676 compatible = "qcom,sc7280-tbu"; 6677 reg = <0x0 0x151dd000 0x0 0x1000>; 6678 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6679 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6680 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 6681 }; 6682 6683 anoc_2_tbu: tbu@151e1000 { 6684 compatible = "qcom,sc7280-tbu"; 6685 reg = <0x0 0x151e1000 0x0 0x1000>; 6686 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6687 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6688 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 6689 }; 6690 6691 mnoc_hf_0_tbu: tbu@151e5000 { 6692 compatible = "qcom,sc7280-tbu"; 6693 reg = <0x0 0x151e5000 0x0 0x1000>; 6694 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6696 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 6697 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 6698 }; 6699 6700 mnoc_hf_1_tbu: tbu@151e9000 { 6701 compatible = "qcom,sc7280-tbu"; 6702 reg = <0x0 0x151e9000 0x0 0x1000>; 6703 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6705 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 6706 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 6707 }; 6708 6709 compute_dsp_1_tbu: tbu@151ed000 { 6710 compatible = "qcom,sc7280-tbu"; 6711 reg = <0x0 0x151ed000 0x0 0x1000>; 6712 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6713 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6714 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 6715 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 6716 }; 6717 6718 compute_dsp_0_tbu: tbu@151f1000 { 6719 compatible = "qcom,sc7280-tbu"; 6720 reg = <0x0 0x151f1000 0x0 0x1000>; 6721 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6722 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6723 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 6724 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 6725 }; 6726 6727 adsp_tbu: tbu@151f5000 { 6728 compatible = "qcom,sc7280-tbu"; 6729 reg = <0x0 0x151f5000 0x0 0x1000>; 6730 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6731 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 6732 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 6733 }; 6734 6735 anoc_1_pcie_tbu: tbu@151f9000 { 6736 compatible = "qcom,sc7280-tbu"; 6737 reg = <0x0 0x151f9000 0x0 0x1000>; 6738 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6739 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6740 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 6741 }; 6742 6743 mnoc_sf_0_tbu: tbu@151fd000 { 6744 compatible = "qcom,sc7280-tbu"; 6745 reg = <0x0 0x151fd000 0x0 0x1000>; 6746 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 6747 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6748 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 6749 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 6750 }; 6751 6752 intc: interrupt-controller@17a00000 { 6753 compatible = "arm,gic-v3"; 6754 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 6755 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 6756 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 6757 #interrupt-cells = <3>; 6758 interrupt-controller; 6759 #address-cells = <2>; 6760 #size-cells = <2>; 6761 ranges; 6762 6763 msi-controller@17a40000 { 6764 compatible = "arm,gic-v3-its"; 6765 reg = <0 0x17a40000 0 0x20000>; 6766 msi-controller; 6767 #msi-cells = <1>; 6768 status = "disabled"; 6769 }; 6770 }; 6771 6772 watchdog: watchdog@17c10000 { 6773 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 6774 reg = <0 0x17c10000 0 0x1000>; 6775 clocks = <&sleep_clk>; 6776 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6777 status = "reserved"; /* Owned by Gunyah hyp */ 6778 }; 6779 6780 timer@17c20000 { 6781 #address-cells = <1>; 6782 #size-cells = <1>; 6783 ranges = <0 0 0 0x20000000>; 6784 compatible = "arm,armv7-timer-mem"; 6785 reg = <0 0x17c20000 0 0x1000>; 6786 6787 frame@17c21000 { 6788 frame-number = <0>; 6789 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6790 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6791 reg = <0x17c21000 0x1000>, 6792 <0x17c22000 0x1000>; 6793 }; 6794 6795 frame@17c23000 { 6796 frame-number = <1>; 6797 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6798 reg = <0x17c23000 0x1000>; 6799 status = "disabled"; 6800 }; 6801 6802 frame@17c25000 { 6803 frame-number = <2>; 6804 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6805 reg = <0x17c25000 0x1000>; 6806 status = "disabled"; 6807 }; 6808 6809 frame@17c27000 { 6810 frame-number = <3>; 6811 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6812 reg = <0x17c27000 0x1000>; 6813 status = "disabled"; 6814 }; 6815 6816 frame@17c29000 { 6817 frame-number = <4>; 6818 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6819 reg = <0x17c29000 0x1000>; 6820 status = "disabled"; 6821 }; 6822 6823 frame@17c2b000 { 6824 frame-number = <5>; 6825 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6826 reg = <0x17c2b000 0x1000>; 6827 status = "disabled"; 6828 }; 6829 6830 frame@17c2d000 { 6831 frame-number = <6>; 6832 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6833 reg = <0x17c2d000 0x1000>; 6834 status = "disabled"; 6835 }; 6836 }; 6837 6838 apps_rsc: rsc@18200000 { 6839 compatible = "qcom,rpmh-rsc"; 6840 reg = <0 0x18200000 0 0x10000>, 6841 <0 0x18210000 0 0x10000>, 6842 <0 0x18220000 0 0x10000>; 6843 reg-names = "drv-0", "drv-1", "drv-2"; 6844 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6845 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6846 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6847 qcom,tcs-offset = <0xd00>; 6848 qcom,drv-id = <2>; 6849 qcom,tcs-config = <ACTIVE_TCS 2>, 6850 <SLEEP_TCS 3>, 6851 <WAKE_TCS 3>, 6852 <CONTROL_TCS 1>; 6853 power-domains = <&cluster_pd>; 6854 6855 apps_bcm_voter: bcm-voter { 6856 compatible = "qcom,bcm-voter"; 6857 }; 6858 6859 rpmhpd: power-controller { 6860 compatible = "qcom,sc7280-rpmhpd"; 6861 #power-domain-cells = <1>; 6862 operating-points-v2 = <&rpmhpd_opp_table>; 6863 6864 rpmhpd_opp_table: opp-table { 6865 compatible = "operating-points-v2"; 6866 6867 rpmhpd_opp_ret: opp1 { 6868 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6869 }; 6870 6871 rpmhpd_opp_low_svs: opp2 { 6872 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6873 }; 6874 6875 rpmhpd_opp_svs: opp3 { 6876 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6877 }; 6878 6879 rpmhpd_opp_svs_l1: opp4 { 6880 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6881 }; 6882 6883 rpmhpd_opp_svs_l2: opp5 { 6884 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6885 }; 6886 6887 rpmhpd_opp_nom: opp6 { 6888 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6889 }; 6890 6891 rpmhpd_opp_nom_l1: opp7 { 6892 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6893 }; 6894 6895 rpmhpd_opp_turbo: opp8 { 6896 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6897 }; 6898 6899 rpmhpd_opp_turbo_l1: opp9 { 6900 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6901 }; 6902 }; 6903 }; 6904 6905 rpmhcc: clock-controller { 6906 compatible = "qcom,sc7280-rpmh-clk"; 6907 clocks = <&xo_board>; 6908 clock-names = "xo"; 6909 #clock-cells = <1>; 6910 }; 6911 }; 6912 6913 epss_l3: interconnect@18590000 { 6914 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6915 reg = <0 0x18590000 0 0x1000>; 6916 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6917 clock-names = "xo", "alternate"; 6918 #interconnect-cells = <1>; 6919 }; 6920 6921 cpufreq_hw: cpufreq@18591000 { 6922 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6923 reg = <0 0x18591000 0 0x1000>, 6924 <0 0x18592000 0 0x1000>, 6925 <0 0x18593000 0 0x1000>; 6926 6927 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6928 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6929 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6930 interrupt-names = "dcvsh-irq-0", 6931 "dcvsh-irq-1", 6932 "dcvsh-irq-2"; 6933 6934 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6935 clock-names = "xo", "alternate"; 6936 #freq-domain-cells = <1>; 6937 #clock-cells = <1>; 6938 }; 6939 }; 6940 6941 sound: sound { 6942 }; 6943 6944 thermal_zones: thermal-zones { 6945 cpu0-thermal { 6946 polling-delay-passive = <250>; 6947 6948 thermal-sensors = <&tsens0 1>; 6949 6950 trips { 6951 cpu0_alert0: trip-point0 { 6952 temperature = <90000>; 6953 hysteresis = <2000>; 6954 type = "passive"; 6955 }; 6956 6957 cpu0_alert1: trip-point1 { 6958 temperature = <95000>; 6959 hysteresis = <2000>; 6960 type = "passive"; 6961 }; 6962 6963 cpu0_crit: cpu-crit { 6964 temperature = <110000>; 6965 hysteresis = <0>; 6966 type = "critical"; 6967 }; 6968 }; 6969 6970 cooling-maps { 6971 map0 { 6972 trip = <&cpu0_alert0>; 6973 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6974 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6975 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6976 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6977 }; 6978 map1 { 6979 trip = <&cpu0_alert1>; 6980 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6981 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6982 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6983 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6984 }; 6985 }; 6986 }; 6987 6988 cpu1-thermal { 6989 polling-delay-passive = <250>; 6990 6991 thermal-sensors = <&tsens0 2>; 6992 6993 trips { 6994 cpu1_alert0: trip-point0 { 6995 temperature = <90000>; 6996 hysteresis = <2000>; 6997 type = "passive"; 6998 }; 6999 7000 cpu1_alert1: trip-point1 { 7001 temperature = <95000>; 7002 hysteresis = <2000>; 7003 type = "passive"; 7004 }; 7005 7006 cpu1_crit: cpu-crit { 7007 temperature = <110000>; 7008 hysteresis = <0>; 7009 type = "critical"; 7010 }; 7011 }; 7012 7013 cooling-maps { 7014 map0 { 7015 trip = <&cpu1_alert0>; 7016 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7017 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7018 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7019 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7020 }; 7021 map1 { 7022 trip = <&cpu1_alert1>; 7023 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7024 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7025 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7026 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7027 }; 7028 }; 7029 }; 7030 7031 cpu2-thermal { 7032 polling-delay-passive = <250>; 7033 7034 thermal-sensors = <&tsens0 3>; 7035 7036 trips { 7037 cpu2_alert0: trip-point0 { 7038 temperature = <90000>; 7039 hysteresis = <2000>; 7040 type = "passive"; 7041 }; 7042 7043 cpu2_alert1: trip-point1 { 7044 temperature = <95000>; 7045 hysteresis = <2000>; 7046 type = "passive"; 7047 }; 7048 7049 cpu2_crit: cpu-crit { 7050 temperature = <110000>; 7051 hysteresis = <0>; 7052 type = "critical"; 7053 }; 7054 }; 7055 7056 cooling-maps { 7057 map0 { 7058 trip = <&cpu2_alert0>; 7059 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7060 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7061 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7062 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7063 }; 7064 map1 { 7065 trip = <&cpu2_alert1>; 7066 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7067 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7068 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7069 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7070 }; 7071 }; 7072 }; 7073 7074 cpu3-thermal { 7075 polling-delay-passive = <250>; 7076 7077 thermal-sensors = <&tsens0 4>; 7078 7079 trips { 7080 cpu3_alert0: trip-point0 { 7081 temperature = <90000>; 7082 hysteresis = <2000>; 7083 type = "passive"; 7084 }; 7085 7086 cpu3_alert1: trip-point1 { 7087 temperature = <95000>; 7088 hysteresis = <2000>; 7089 type = "passive"; 7090 }; 7091 7092 cpu3_crit: cpu-crit { 7093 temperature = <110000>; 7094 hysteresis = <0>; 7095 type = "critical"; 7096 }; 7097 }; 7098 7099 cooling-maps { 7100 map0 { 7101 trip = <&cpu3_alert0>; 7102 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7103 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7104 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7105 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7106 }; 7107 map1 { 7108 trip = <&cpu3_alert1>; 7109 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7110 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7111 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7112 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7113 }; 7114 }; 7115 }; 7116 7117 cpu4-thermal { 7118 polling-delay-passive = <250>; 7119 7120 thermal-sensors = <&tsens0 7>; 7121 7122 trips { 7123 cpu4_alert0: trip-point0 { 7124 temperature = <90000>; 7125 hysteresis = <2000>; 7126 type = "passive"; 7127 }; 7128 7129 cpu4_alert1: trip-point1 { 7130 temperature = <95000>; 7131 hysteresis = <2000>; 7132 type = "passive"; 7133 }; 7134 7135 cpu4_crit: cpu-crit { 7136 temperature = <110000>; 7137 hysteresis = <0>; 7138 type = "critical"; 7139 }; 7140 }; 7141 7142 cooling-maps { 7143 map0 { 7144 trip = <&cpu4_alert0>; 7145 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7146 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7147 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7148 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7149 }; 7150 map1 { 7151 trip = <&cpu4_alert1>; 7152 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7153 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7154 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7155 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7156 }; 7157 }; 7158 }; 7159 7160 cpu5-thermal { 7161 polling-delay-passive = <250>; 7162 7163 thermal-sensors = <&tsens0 8>; 7164 7165 trips { 7166 cpu5_alert0: trip-point0 { 7167 temperature = <90000>; 7168 hysteresis = <2000>; 7169 type = "passive"; 7170 }; 7171 7172 cpu5_alert1: trip-point1 { 7173 temperature = <95000>; 7174 hysteresis = <2000>; 7175 type = "passive"; 7176 }; 7177 7178 cpu5_crit: cpu-crit { 7179 temperature = <110000>; 7180 hysteresis = <0>; 7181 type = "critical"; 7182 }; 7183 }; 7184 7185 cooling-maps { 7186 map0 { 7187 trip = <&cpu5_alert0>; 7188 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7189 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7190 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7191 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7192 }; 7193 map1 { 7194 trip = <&cpu5_alert1>; 7195 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7196 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7197 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7198 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7199 }; 7200 }; 7201 }; 7202 7203 cpu6-thermal { 7204 polling-delay-passive = <250>; 7205 7206 thermal-sensors = <&tsens0 9>; 7207 7208 trips { 7209 cpu6_alert0: trip-point0 { 7210 temperature = <90000>; 7211 hysteresis = <2000>; 7212 type = "passive"; 7213 }; 7214 7215 cpu6_alert1: trip-point1 { 7216 temperature = <95000>; 7217 hysteresis = <2000>; 7218 type = "passive"; 7219 }; 7220 7221 cpu6_crit: cpu-crit { 7222 temperature = <110000>; 7223 hysteresis = <0>; 7224 type = "critical"; 7225 }; 7226 }; 7227 7228 cooling-maps { 7229 map0 { 7230 trip = <&cpu6_alert0>; 7231 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7232 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7233 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7234 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7235 }; 7236 map1 { 7237 trip = <&cpu6_alert1>; 7238 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7239 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7240 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7241 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7242 }; 7243 }; 7244 }; 7245 7246 cpu7-thermal { 7247 polling-delay-passive = <250>; 7248 7249 thermal-sensors = <&tsens0 10>; 7250 7251 trips { 7252 cpu7_alert0: trip-point0 { 7253 temperature = <90000>; 7254 hysteresis = <2000>; 7255 type = "passive"; 7256 }; 7257 7258 cpu7_alert1: trip-point1 { 7259 temperature = <95000>; 7260 hysteresis = <2000>; 7261 type = "passive"; 7262 }; 7263 7264 cpu7_crit: cpu-crit { 7265 temperature = <110000>; 7266 hysteresis = <0>; 7267 type = "critical"; 7268 }; 7269 }; 7270 7271 cooling-maps { 7272 map0 { 7273 trip = <&cpu7_alert0>; 7274 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7275 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7276 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7277 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7278 }; 7279 map1 { 7280 trip = <&cpu7_alert1>; 7281 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7282 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7283 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7284 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7285 }; 7286 }; 7287 }; 7288 7289 cpu8-thermal { 7290 polling-delay-passive = <250>; 7291 7292 thermal-sensors = <&tsens0 11>; 7293 7294 trips { 7295 cpu8_alert0: trip-point0 { 7296 temperature = <90000>; 7297 hysteresis = <2000>; 7298 type = "passive"; 7299 }; 7300 7301 cpu8_alert1: trip-point1 { 7302 temperature = <95000>; 7303 hysteresis = <2000>; 7304 type = "passive"; 7305 }; 7306 7307 cpu8_crit: cpu-crit { 7308 temperature = <110000>; 7309 hysteresis = <0>; 7310 type = "critical"; 7311 }; 7312 }; 7313 7314 cooling-maps { 7315 map0 { 7316 trip = <&cpu8_alert0>; 7317 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7318 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7319 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7320 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7321 }; 7322 map1 { 7323 trip = <&cpu8_alert1>; 7324 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7325 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7326 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7327 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7328 }; 7329 }; 7330 }; 7331 7332 cpu9-thermal { 7333 polling-delay-passive = <250>; 7334 7335 thermal-sensors = <&tsens0 12>; 7336 7337 trips { 7338 cpu9_alert0: trip-point0 { 7339 temperature = <90000>; 7340 hysteresis = <2000>; 7341 type = "passive"; 7342 }; 7343 7344 cpu9_alert1: trip-point1 { 7345 temperature = <95000>; 7346 hysteresis = <2000>; 7347 type = "passive"; 7348 }; 7349 7350 cpu9_crit: cpu-crit { 7351 temperature = <110000>; 7352 hysteresis = <0>; 7353 type = "critical"; 7354 }; 7355 }; 7356 7357 cooling-maps { 7358 map0 { 7359 trip = <&cpu9_alert0>; 7360 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7361 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7362 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7363 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7364 }; 7365 map1 { 7366 trip = <&cpu9_alert1>; 7367 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7368 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7369 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7370 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7371 }; 7372 }; 7373 }; 7374 7375 cpu10-thermal { 7376 polling-delay-passive = <250>; 7377 7378 thermal-sensors = <&tsens0 13>; 7379 7380 trips { 7381 cpu10_alert0: trip-point0 { 7382 temperature = <90000>; 7383 hysteresis = <2000>; 7384 type = "passive"; 7385 }; 7386 7387 cpu10_alert1: trip-point1 { 7388 temperature = <95000>; 7389 hysteresis = <2000>; 7390 type = "passive"; 7391 }; 7392 7393 cpu10_crit: cpu-crit { 7394 temperature = <110000>; 7395 hysteresis = <0>; 7396 type = "critical"; 7397 }; 7398 }; 7399 7400 cooling-maps { 7401 map0 { 7402 trip = <&cpu10_alert0>; 7403 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7404 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7405 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7406 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7407 }; 7408 map1 { 7409 trip = <&cpu10_alert1>; 7410 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7411 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7412 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7413 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7414 }; 7415 }; 7416 }; 7417 7418 cpu11-thermal { 7419 polling-delay-passive = <250>; 7420 7421 thermal-sensors = <&tsens0 14>; 7422 7423 trips { 7424 cpu11_alert0: trip-point0 { 7425 temperature = <90000>; 7426 hysteresis = <2000>; 7427 type = "passive"; 7428 }; 7429 7430 cpu11_alert1: trip-point1 { 7431 temperature = <95000>; 7432 hysteresis = <2000>; 7433 type = "passive"; 7434 }; 7435 7436 cpu11_crit: cpu-crit { 7437 temperature = <110000>; 7438 hysteresis = <0>; 7439 type = "critical"; 7440 }; 7441 }; 7442 7443 cooling-maps { 7444 map0 { 7445 trip = <&cpu11_alert0>; 7446 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7447 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7448 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7449 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7450 }; 7451 map1 { 7452 trip = <&cpu11_alert1>; 7453 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7454 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7455 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7456 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7457 }; 7458 }; 7459 }; 7460 7461 aoss0-thermal { 7462 polling-delay-passive = <0>; 7463 7464 thermal-sensors = <&tsens0 0>; 7465 7466 trips { 7467 aoss0_alert0: trip-point0 { 7468 temperature = <90000>; 7469 hysteresis = <2000>; 7470 type = "hot"; 7471 }; 7472 7473 aoss0_crit: aoss0-crit { 7474 temperature = <110000>; 7475 hysteresis = <0>; 7476 type = "critical"; 7477 }; 7478 }; 7479 }; 7480 7481 aoss1-thermal { 7482 polling-delay-passive = <0>; 7483 7484 thermal-sensors = <&tsens1 0>; 7485 7486 trips { 7487 aoss1_alert0: trip-point0 { 7488 temperature = <90000>; 7489 hysteresis = <2000>; 7490 type = "hot"; 7491 }; 7492 7493 aoss1_crit: aoss1-crit { 7494 temperature = <110000>; 7495 hysteresis = <0>; 7496 type = "critical"; 7497 }; 7498 }; 7499 }; 7500 7501 cpuss0-thermal { 7502 polling-delay-passive = <0>; 7503 7504 thermal-sensors = <&tsens0 5>; 7505 7506 trips { 7507 cpuss0_alert0: trip-point0 { 7508 temperature = <90000>; 7509 hysteresis = <2000>; 7510 type = "hot"; 7511 }; 7512 cpuss0_crit: cluster0-crit { 7513 temperature = <110000>; 7514 hysteresis = <0>; 7515 type = "critical"; 7516 }; 7517 }; 7518 }; 7519 7520 cpuss1-thermal { 7521 polling-delay-passive = <0>; 7522 7523 thermal-sensors = <&tsens0 6>; 7524 7525 trips { 7526 cpuss1_alert0: trip-point0 { 7527 temperature = <90000>; 7528 hysteresis = <2000>; 7529 type = "hot"; 7530 }; 7531 cpuss1_crit: cluster0-crit { 7532 temperature = <110000>; 7533 hysteresis = <0>; 7534 type = "critical"; 7535 }; 7536 }; 7537 }; 7538 7539 gpuss0-thermal { 7540 polling-delay-passive = <100>; 7541 7542 thermal-sensors = <&tsens1 1>; 7543 7544 trips { 7545 gpuss0_alert0: trip-point0 { 7546 temperature = <95000>; 7547 hysteresis = <2000>; 7548 type = "passive"; 7549 }; 7550 7551 gpuss0_crit: gpuss0-crit { 7552 temperature = <110000>; 7553 hysteresis = <0>; 7554 type = "critical"; 7555 }; 7556 }; 7557 7558 cooling-maps { 7559 map0 { 7560 trip = <&gpuss0_alert0>; 7561 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7562 }; 7563 }; 7564 }; 7565 7566 gpuss1-thermal { 7567 polling-delay-passive = <100>; 7568 7569 thermal-sensors = <&tsens1 2>; 7570 7571 trips { 7572 gpuss1_alert0: trip-point0 { 7573 temperature = <95000>; 7574 hysteresis = <2000>; 7575 type = "passive"; 7576 }; 7577 7578 gpuss1_crit: gpuss1-crit { 7579 temperature = <110000>; 7580 hysteresis = <0>; 7581 type = "critical"; 7582 }; 7583 }; 7584 7585 cooling-maps { 7586 map0 { 7587 trip = <&gpuss1_alert0>; 7588 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7589 }; 7590 }; 7591 }; 7592 7593 nspss0-thermal { 7594 thermal-sensors = <&tsens1 3>; 7595 7596 trips { 7597 nspss0_alert0: trip-point0 { 7598 temperature = <90000>; 7599 hysteresis = <2000>; 7600 type = "hot"; 7601 }; 7602 7603 nspss0_crit: nspss0-crit { 7604 temperature = <110000>; 7605 hysteresis = <0>; 7606 type = "critical"; 7607 }; 7608 }; 7609 }; 7610 7611 nspss1-thermal { 7612 thermal-sensors = <&tsens1 4>; 7613 7614 trips { 7615 nspss1_alert0: trip-point0 { 7616 temperature = <90000>; 7617 hysteresis = <2000>; 7618 type = "hot"; 7619 }; 7620 7621 nspss1_crit: nspss1-crit { 7622 temperature = <110000>; 7623 hysteresis = <0>; 7624 type = "critical"; 7625 }; 7626 }; 7627 }; 7628 7629 video-thermal { 7630 thermal-sensors = <&tsens1 5>; 7631 7632 trips { 7633 video_alert0: trip-point0 { 7634 temperature = <90000>; 7635 hysteresis = <2000>; 7636 type = "hot"; 7637 }; 7638 7639 video_crit: video-crit { 7640 temperature = <110000>; 7641 hysteresis = <0>; 7642 type = "critical"; 7643 }; 7644 }; 7645 }; 7646 7647 ddr-thermal { 7648 thermal-sensors = <&tsens1 6>; 7649 7650 trips { 7651 ddr_alert0: trip-point0 { 7652 temperature = <90000>; 7653 hysteresis = <2000>; 7654 type = "hot"; 7655 }; 7656 7657 ddr_crit: ddr-crit { 7658 temperature = <110000>; 7659 hysteresis = <0>; 7660 type = "critical"; 7661 }; 7662 }; 7663 }; 7664 7665 mdmss0-thermal { 7666 thermal-sensors = <&tsens1 7>; 7667 7668 trips { 7669 mdmss0_alert0: trip-point0 { 7670 temperature = <90000>; 7671 hysteresis = <2000>; 7672 type = "hot"; 7673 }; 7674 7675 mdmss0_crit: mdmss0-crit { 7676 temperature = <110000>; 7677 hysteresis = <0>; 7678 type = "critical"; 7679 }; 7680 }; 7681 }; 7682 7683 mdmss1-thermal { 7684 thermal-sensors = <&tsens1 8>; 7685 7686 trips { 7687 mdmss1_alert0: trip-point0 { 7688 temperature = <90000>; 7689 hysteresis = <2000>; 7690 type = "hot"; 7691 }; 7692 7693 mdmss1_crit: mdmss1-crit { 7694 temperature = <110000>; 7695 hysteresis = <0>; 7696 type = "critical"; 7697 }; 7698 }; 7699 }; 7700 7701 mdmss2-thermal { 7702 thermal-sensors = <&tsens1 9>; 7703 7704 trips { 7705 mdmss2_alert0: trip-point0 { 7706 temperature = <90000>; 7707 hysteresis = <2000>; 7708 type = "hot"; 7709 }; 7710 7711 mdmss2_crit: mdmss2-crit { 7712 temperature = <110000>; 7713 hysteresis = <0>; 7714 type = "critical"; 7715 }; 7716 }; 7717 }; 7718 7719 mdmss3-thermal { 7720 thermal-sensors = <&tsens1 10>; 7721 7722 trips { 7723 mdmss3_alert0: trip-point0 { 7724 temperature = <90000>; 7725 hysteresis = <2000>; 7726 type = "hot"; 7727 }; 7728 7729 mdmss3_crit: mdmss3-crit { 7730 temperature = <110000>; 7731 hysteresis = <0>; 7732 type = "critical"; 7733 }; 7734 }; 7735 }; 7736 7737 camera0-thermal { 7738 thermal-sensors = <&tsens1 11>; 7739 7740 trips { 7741 camera0_alert0: trip-point0 { 7742 temperature = <90000>; 7743 hysteresis = <2000>; 7744 type = "hot"; 7745 }; 7746 7747 camera0_crit: camera0-crit { 7748 temperature = <110000>; 7749 hysteresis = <0>; 7750 type = "critical"; 7751 }; 7752 }; 7753 }; 7754 }; 7755 7756 timer { 7757 compatible = "arm,armv8-timer"; 7758 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7759 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7760 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7761 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7762 }; 7763}; 7764