1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #include "isci.h"
57 #include "host.h"
58 #include "phy.h"
59 #include "scu_event_codes.h"
60 #include "probe_roms.h"
61
62 /* Maximum arbitration wait time in micro-seconds */
63 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME (700)
64
sci_phy_linkrate(struct isci_phy * iphy)65 enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy)
66 {
67 return iphy->max_negotiated_speed;
68 }
69
70 static enum sci_status
sci_phy_transport_layer_initialization(struct isci_phy * iphy,struct scu_transport_layer_registers __iomem * reg)71 sci_phy_transport_layer_initialization(struct isci_phy *iphy,
72 struct scu_transport_layer_registers __iomem *reg)
73 {
74 u32 tl_control;
75
76 iphy->transport_layer_registers = reg;
77
78 writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
79 &iphy->transport_layer_registers->stp_rni);
80
81 /*
82 * Hardware team recommends that we enable the STP prefetch for all
83 * transports
84 */
85 tl_control = readl(&iphy->transport_layer_registers->control);
86 tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
87 writel(tl_control, &iphy->transport_layer_registers->control);
88
89 return SCI_SUCCESS;
90 }
91
92 static enum sci_status
sci_phy_link_layer_initialization(struct isci_phy * iphy,struct scu_link_layer_registers __iomem * llr)93 sci_phy_link_layer_initialization(struct isci_phy *iphy,
94 struct scu_link_layer_registers __iomem *llr)
95 {
96 struct isci_host *ihost = iphy->owning_port->owning_controller;
97 struct sci_phy_user_params *phy_user;
98 struct sci_phy_oem_params *phy_oem;
99 int phy_idx = iphy->phy_index;
100 struct sci_phy_cap phy_cap;
101 u32 phy_configuration;
102 u32 parity_check = 0;
103 u32 parity_count = 0;
104 u32 llctl, link_rate;
105 u32 clksm_value = 0;
106 u32 sp_timeouts = 0;
107
108 phy_user = &ihost->user_parameters.phys[phy_idx];
109 phy_oem = &ihost->oem_parameters.phys[phy_idx];
110 iphy->link_layer_registers = llr;
111
112 /* Set our IDENTIFY frame data */
113 #define SCI_END_DEVICE 0x01
114
115 writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
116 SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
117 SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
118 SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
119 SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
120 &llr->transmit_identification);
121
122 /* Write the device SAS Address */
123 writel(0xFEDCBA98, &llr->sas_device_name_high);
124 writel(phy_idx, &llr->sas_device_name_low);
125
126 /* Write the source SAS Address */
127 writel(phy_oem->sas_address.high, &llr->source_sas_address_high);
128 writel(phy_oem->sas_address.low, &llr->source_sas_address_low);
129
130 /* Clear and Set the PHY Identifier */
131 writel(0, &llr->identify_frame_phy_id);
132 writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id);
133
134 /* Change the initial state of the phy configuration register */
135 phy_configuration = readl(&llr->phy_configuration);
136
137 /* Hold OOB state machine in reset */
138 phy_configuration |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
139 writel(phy_configuration, &llr->phy_configuration);
140
141 /* Configure the SNW capabilities */
142 phy_cap.all = 0;
143 phy_cap.start = 1;
144 phy_cap.gen3_no_ssc = 1;
145 phy_cap.gen2_no_ssc = 1;
146 phy_cap.gen1_no_ssc = 1;
147 if (ihost->oem_parameters.controller.do_enable_ssc) {
148 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
149 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_idx];
150 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
151 bool en_sas = false;
152 bool en_sata = false;
153 u32 sas_type = 0;
154 u32 sata_spread = 0x2;
155 u32 sas_spread = 0x2;
156
157 phy_cap.gen3_ssc = 1;
158 phy_cap.gen2_ssc = 1;
159 phy_cap.gen1_ssc = 1;
160
161 if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1)
162 en_sas = en_sata = true;
163 else {
164 sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level;
165 sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level;
166
167 if (sata_spread)
168 en_sata = true;
169
170 if (sas_spread) {
171 en_sas = true;
172 sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type;
173 }
174
175 }
176
177 if (en_sas) {
178 u32 reg;
179
180 reg = readl(&xcvr->afe_xcvr_control0);
181 reg |= (0x00100000 | (sas_type << 19));
182 writel(reg, &xcvr->afe_xcvr_control0);
183
184 reg = readl(&xcvr->afe_tx_ssc_control);
185 reg |= sas_spread << 8;
186 writel(reg, &xcvr->afe_tx_ssc_control);
187 }
188
189 if (en_sata) {
190 u32 reg;
191
192 reg = readl(&xcvr->afe_tx_ssc_control);
193 reg |= sata_spread;
194 writel(reg, &xcvr->afe_tx_ssc_control);
195
196 reg = readl(&llr->stp_control);
197 reg |= 1 << 12;
198 writel(reg, &llr->stp_control);
199 }
200 }
201
202 /* The SAS specification indicates that the phy_capabilities that
203 * are transmitted shall have an even parity. Calculate the parity.
204 */
205 parity_check = phy_cap.all;
206 while (parity_check != 0) {
207 if (parity_check & 0x1)
208 parity_count++;
209 parity_check >>= 1;
210 }
211
212 /* If parity indicates there are an odd number of bits set, then
213 * set the parity bit to 1 in the phy capabilities.
214 */
215 if ((parity_count % 2) != 0)
216 phy_cap.parity = 1;
217
218 writel(phy_cap.all, &llr->phy_capabilities);
219
220 /* Set the enable spinup period but disable the ability to send
221 * notify enable spinup
222 */
223 writel(SCU_ENSPINUP_GEN_VAL(COUNT,
224 phy_user->notify_enable_spin_up_insertion_frequency),
225 &llr->notify_enable_spinup_control);
226
227 /* Write the ALIGN Insertion Ferequency for connected phy and
228 * inpendent of connected state
229 */
230 clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
231 phy_user->in_connection_align_insertion_frequency);
232
233 clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
234 phy_user->align_insertion_frequency);
235
236 writel(clksm_value, &llr->clock_skew_management);
237
238 if (is_c0(ihost->pdev) || is_c1(ihost->pdev)) {
239 writel(0x04210400, &llr->afe_lookup_table_control);
240 writel(0x020A7C05, &llr->sas_primitive_timeout);
241 } else
242 writel(0x02108421, &llr->afe_lookup_table_control);
243
244 llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
245 (u8)ihost->user_parameters.no_outbound_task_timeout);
246
247 switch (phy_user->max_speed_generation) {
248 case SCIC_SDS_PARM_GEN3_SPEED:
249 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
250 break;
251 case SCIC_SDS_PARM_GEN2_SPEED:
252 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
253 break;
254 default:
255 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
256 break;
257 }
258 llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
259 writel(llctl, &llr->link_layer_control);
260
261 sp_timeouts = readl(&llr->sas_phy_timeouts);
262
263 /* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */
264 sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF);
265
266 /* Set RATE_CHANGE timeout value to 0x3B (59us). This ensures SCU can
267 * lock with 3Gb drive when SCU max rate is set to 1.5Gb.
268 */
269 sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B);
270
271 writel(sp_timeouts, &llr->sas_phy_timeouts);
272
273 if (is_a2(ihost->pdev)) {
274 /* Program the max ARB time for the PHY to 700us so we
275 * inter-operate with the PMC expander which shuts down
276 * PHYs if the expander PHY generates too many breaks.
277 * This time value will guarantee that the initiator PHY
278 * will generate the break.
279 */
280 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
281 &llr->maximum_arbitration_wait_timer_timeout);
282 }
283
284 /* Disable link layer hang detection, rely on the OS timeout for
285 * I/O timeouts.
286 */
287 writel(0, &llr->link_layer_hang_detection_timeout);
288
289 /* We can exit the initial state to the stopped state */
290 sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
291
292 return SCI_SUCCESS;
293 }
294
phy_sata_timeout(unsigned long data)295 static void phy_sata_timeout(unsigned long data)
296 {
297 struct sci_timer *tmr = (struct sci_timer *)data;
298 struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer);
299 struct isci_host *ihost = iphy->owning_port->owning_controller;
300 unsigned long flags;
301
302 spin_lock_irqsave(&ihost->scic_lock, flags);
303
304 if (tmr->cancel)
305 goto done;
306
307 dev_dbg(sciphy_to_dev(iphy),
308 "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
309 "timeout.\n",
310 __func__,
311 iphy);
312
313 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
314 done:
315 spin_unlock_irqrestore(&ihost->scic_lock, flags);
316 }
317
318 /**
319 * This method returns the port currently containing this phy. If the phy is
320 * currently contained by the dummy port, then the phy is considered to not
321 * be part of a port.
322 * @sci_phy: This parameter specifies the phy for which to retrieve the
323 * containing port.
324 *
325 * This method returns a handle to a port that contains the supplied phy.
326 * NULL This value is returned if the phy is not part of a real
327 * port (i.e. it's contained in the dummy port). !NULL All other
328 * values indicate a handle/pointer to the port containing the phy.
329 */
phy_get_non_dummy_port(struct isci_phy * iphy)330 struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy)
331 {
332 struct isci_port *iport = iphy->owning_port;
333
334 if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT)
335 return NULL;
336
337 return iphy->owning_port;
338 }
339
340 /**
341 * This method will assign a port to the phy object.
342 * @out]: iphy This parameter specifies the phy for which to assign a port
343 * object.
344 *
345 *
346 */
sci_phy_set_port(struct isci_phy * iphy,struct isci_port * iport)347 void sci_phy_set_port(
348 struct isci_phy *iphy,
349 struct isci_port *iport)
350 {
351 iphy->owning_port = iport;
352
353 if (iphy->bcn_received_while_port_unassigned) {
354 iphy->bcn_received_while_port_unassigned = false;
355 sci_port_broadcast_change_received(iphy->owning_port, iphy);
356 }
357 }
358
sci_phy_initialize(struct isci_phy * iphy,struct scu_transport_layer_registers __iomem * tl,struct scu_link_layer_registers __iomem * ll)359 enum sci_status sci_phy_initialize(struct isci_phy *iphy,
360 struct scu_transport_layer_registers __iomem *tl,
361 struct scu_link_layer_registers __iomem *ll)
362 {
363 /* Perfrom the initialization of the TL hardware */
364 sci_phy_transport_layer_initialization(iphy, tl);
365
366 /* Perofrm the initialization of the PE hardware */
367 sci_phy_link_layer_initialization(iphy, ll);
368
369 /* There is nothing that needs to be done in this state just
370 * transition to the stopped state
371 */
372 sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
373
374 return SCI_SUCCESS;
375 }
376
377 /**
378 * This method assigns the direct attached device ID for this phy.
379 *
380 * @iphy The phy for which the direct attached device id is to
381 * be assigned.
382 * @device_id The direct attached device ID to assign to the phy.
383 * This will either be the RNi for the device or an invalid RNi if there
384 * is no current device assigned to the phy.
385 */
sci_phy_setup_transport(struct isci_phy * iphy,u32 device_id)386 void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id)
387 {
388 u32 tl_control;
389
390 writel(device_id, &iphy->transport_layer_registers->stp_rni);
391
392 /*
393 * The read should guarantee that the first write gets posted
394 * before the next write
395 */
396 tl_control = readl(&iphy->transport_layer_registers->control);
397 tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
398 writel(tl_control, &iphy->transport_layer_registers->control);
399 }
400
sci_phy_suspend(struct isci_phy * iphy)401 static void sci_phy_suspend(struct isci_phy *iphy)
402 {
403 u32 scu_sas_pcfg_value;
404
405 scu_sas_pcfg_value =
406 readl(&iphy->link_layer_registers->phy_configuration);
407 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
408 writel(scu_sas_pcfg_value,
409 &iphy->link_layer_registers->phy_configuration);
410
411 sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
412 }
413
sci_phy_resume(struct isci_phy * iphy)414 void sci_phy_resume(struct isci_phy *iphy)
415 {
416 u32 scu_sas_pcfg_value;
417
418 scu_sas_pcfg_value =
419 readl(&iphy->link_layer_registers->phy_configuration);
420 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
421 writel(scu_sas_pcfg_value,
422 &iphy->link_layer_registers->phy_configuration);
423 }
424
sci_phy_get_sas_address(struct isci_phy * iphy,struct sci_sas_address * sas)425 void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
426 {
427 sas->high = readl(&iphy->link_layer_registers->source_sas_address_high);
428 sas->low = readl(&iphy->link_layer_registers->source_sas_address_low);
429 }
430
sci_phy_get_attached_sas_address(struct isci_phy * iphy,struct sci_sas_address * sas)431 void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
432 {
433 struct sas_identify_frame *iaf;
434
435 iaf = &iphy->frame_rcvd.iaf;
436 memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE);
437 }
438
sci_phy_get_protocols(struct isci_phy * iphy,struct sci_phy_proto * proto)439 void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto)
440 {
441 proto->all = readl(&iphy->link_layer_registers->transmit_identification);
442 }
443
sci_phy_start(struct isci_phy * iphy)444 enum sci_status sci_phy_start(struct isci_phy *iphy)
445 {
446 enum sci_phy_states state = iphy->sm.current_state_id;
447
448 if (state != SCI_PHY_STOPPED) {
449 dev_dbg(sciphy_to_dev(iphy),
450 "%s: in wrong state: %d\n", __func__, state);
451 return SCI_FAILURE_INVALID_STATE;
452 }
453
454 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
455 return SCI_SUCCESS;
456 }
457
sci_phy_stop(struct isci_phy * iphy)458 enum sci_status sci_phy_stop(struct isci_phy *iphy)
459 {
460 enum sci_phy_states state = iphy->sm.current_state_id;
461
462 switch (state) {
463 case SCI_PHY_SUB_INITIAL:
464 case SCI_PHY_SUB_AWAIT_OSSP_EN:
465 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
466 case SCI_PHY_SUB_AWAIT_SAS_POWER:
467 case SCI_PHY_SUB_AWAIT_SATA_POWER:
468 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
469 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
470 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
471 case SCI_PHY_SUB_FINAL:
472 case SCI_PHY_READY:
473 break;
474 default:
475 dev_dbg(sciphy_to_dev(iphy),
476 "%s: in wrong state: %d\n", __func__, state);
477 return SCI_FAILURE_INVALID_STATE;
478 }
479
480 sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
481 return SCI_SUCCESS;
482 }
483
sci_phy_reset(struct isci_phy * iphy)484 enum sci_status sci_phy_reset(struct isci_phy *iphy)
485 {
486 enum sci_phy_states state = iphy->sm.current_state_id;
487
488 if (state != SCI_PHY_READY) {
489 dev_dbg(sciphy_to_dev(iphy),
490 "%s: in wrong state: %d\n", __func__, state);
491 return SCI_FAILURE_INVALID_STATE;
492 }
493
494 sci_change_state(&iphy->sm, SCI_PHY_RESETTING);
495 return SCI_SUCCESS;
496 }
497
sci_phy_consume_power_handler(struct isci_phy * iphy)498 enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy)
499 {
500 enum sci_phy_states state = iphy->sm.current_state_id;
501
502 switch (state) {
503 case SCI_PHY_SUB_AWAIT_SAS_POWER: {
504 u32 enable_spinup;
505
506 enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
507 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
508 writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
509
510 /* Change state to the final state this substate machine has run to completion */
511 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
512
513 return SCI_SUCCESS;
514 }
515 case SCI_PHY_SUB_AWAIT_SATA_POWER: {
516 u32 scu_sas_pcfg_value;
517
518 /* Release the spinup hold state and reset the OOB state machine */
519 scu_sas_pcfg_value =
520 readl(&iphy->link_layer_registers->phy_configuration);
521 scu_sas_pcfg_value &=
522 ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
523 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
524 writel(scu_sas_pcfg_value,
525 &iphy->link_layer_registers->phy_configuration);
526
527 /* Now restart the OOB operation */
528 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
529 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
530 writel(scu_sas_pcfg_value,
531 &iphy->link_layer_registers->phy_configuration);
532
533 /* Change state to the final state this substate machine has run to completion */
534 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
535
536 return SCI_SUCCESS;
537 }
538 default:
539 dev_dbg(sciphy_to_dev(iphy),
540 "%s: in wrong state: %d\n", __func__, state);
541 return SCI_FAILURE_INVALID_STATE;
542 }
543 }
544
sci_phy_start_sas_link_training(struct isci_phy * iphy)545 static void sci_phy_start_sas_link_training(struct isci_phy *iphy)
546 {
547 /* continue the link training for the phy as if it were a SAS PHY
548 * instead of a SATA PHY. This is done because the completion queue had a SAS
549 * PHY DETECTED event when the state machine was expecting a SATA PHY event.
550 */
551 u32 phy_control;
552
553 phy_control = readl(&iphy->link_layer_registers->phy_configuration);
554 phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
555 writel(phy_control,
556 &iphy->link_layer_registers->phy_configuration);
557
558 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
559
560 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
561 }
562
sci_phy_start_sata_link_training(struct isci_phy * iphy)563 static void sci_phy_start_sata_link_training(struct isci_phy *iphy)
564 {
565 /* This method continues the link training for the phy as if it were a SATA PHY
566 * instead of a SAS PHY. This is done because the completion queue had a SATA
567 * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
568 */
569 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
570
571 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
572 }
573
574 /**
575 * sci_phy_complete_link_training - perform processing common to
576 * all protocols upon completion of link training.
577 * @sci_phy: This parameter specifies the phy object for which link training
578 * has completed.
579 * @max_link_rate: This parameter specifies the maximum link rate to be
580 * associated with this phy.
581 * @next_state: This parameter specifies the next state for the phy's starting
582 * sub-state machine.
583 *
584 */
sci_phy_complete_link_training(struct isci_phy * iphy,enum sas_linkrate max_link_rate,u32 next_state)585 static void sci_phy_complete_link_training(struct isci_phy *iphy,
586 enum sas_linkrate max_link_rate,
587 u32 next_state)
588 {
589 iphy->max_negotiated_speed = max_link_rate;
590
591 sci_change_state(&iphy->sm, next_state);
592 }
593
sci_phy_event_handler(struct isci_phy * iphy,u32 event_code)594 enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code)
595 {
596 enum sci_phy_states state = iphy->sm.current_state_id;
597
598 switch (state) {
599 case SCI_PHY_SUB_AWAIT_OSSP_EN:
600 switch (scu_get_event_code(event_code)) {
601 case SCU_EVENT_SAS_PHY_DETECTED:
602 sci_phy_start_sas_link_training(iphy);
603 iphy->is_in_link_training = true;
604 break;
605 case SCU_EVENT_SATA_SPINUP_HOLD:
606 sci_phy_start_sata_link_training(iphy);
607 iphy->is_in_link_training = true;
608 break;
609 default:
610 dev_dbg(sciphy_to_dev(iphy),
611 "%s: PHY starting substate machine received "
612 "unexpected event_code %x\n",
613 __func__,
614 event_code);
615 return SCI_FAILURE;
616 }
617 return SCI_SUCCESS;
618 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
619 switch (scu_get_event_code(event_code)) {
620 case SCU_EVENT_SAS_PHY_DETECTED:
621 /*
622 * Why is this being reported again by the controller?
623 * We would re-enter this state so just stay here */
624 break;
625 case SCU_EVENT_SAS_15:
626 case SCU_EVENT_SAS_15_SSC:
627 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
628 SCI_PHY_SUB_AWAIT_IAF_UF);
629 break;
630 case SCU_EVENT_SAS_30:
631 case SCU_EVENT_SAS_30_SSC:
632 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
633 SCI_PHY_SUB_AWAIT_IAF_UF);
634 break;
635 case SCU_EVENT_SAS_60:
636 case SCU_EVENT_SAS_60_SSC:
637 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
638 SCI_PHY_SUB_AWAIT_IAF_UF);
639 break;
640 case SCU_EVENT_SATA_SPINUP_HOLD:
641 /*
642 * We were doing SAS PHY link training and received a SATA PHY event
643 * continue OOB/SN as if this were a SATA PHY */
644 sci_phy_start_sata_link_training(iphy);
645 break;
646 case SCU_EVENT_LINK_FAILURE:
647 /* Link failure change state back to the starting state */
648 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
649 break;
650 default:
651 dev_warn(sciphy_to_dev(iphy),
652 "%s: PHY starting substate machine received "
653 "unexpected event_code %x\n",
654 __func__, event_code);
655
656 return SCI_FAILURE;
657 break;
658 }
659 return SCI_SUCCESS;
660 case SCI_PHY_SUB_AWAIT_IAF_UF:
661 switch (scu_get_event_code(event_code)) {
662 case SCU_EVENT_SAS_PHY_DETECTED:
663 /* Backup the state machine */
664 sci_phy_start_sas_link_training(iphy);
665 break;
666 case SCU_EVENT_SATA_SPINUP_HOLD:
667 /* We were doing SAS PHY link training and received a
668 * SATA PHY event continue OOB/SN as if this were a
669 * SATA PHY
670 */
671 sci_phy_start_sata_link_training(iphy);
672 break;
673 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
674 case SCU_EVENT_LINK_FAILURE:
675 case SCU_EVENT_HARD_RESET_RECEIVED:
676 /* Start the oob/sn state machine over again */
677 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
678 break;
679 default:
680 dev_warn(sciphy_to_dev(iphy),
681 "%s: PHY starting substate machine received "
682 "unexpected event_code %x\n",
683 __func__, event_code);
684 return SCI_FAILURE;
685 }
686 return SCI_SUCCESS;
687 case SCI_PHY_SUB_AWAIT_SAS_POWER:
688 switch (scu_get_event_code(event_code)) {
689 case SCU_EVENT_LINK_FAILURE:
690 /* Link failure change state back to the starting state */
691 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
692 break;
693 default:
694 dev_warn(sciphy_to_dev(iphy),
695 "%s: PHY starting substate machine received unexpected "
696 "event_code %x\n",
697 __func__,
698 event_code);
699 return SCI_FAILURE;
700 }
701 return SCI_SUCCESS;
702 case SCI_PHY_SUB_AWAIT_SATA_POWER:
703 switch (scu_get_event_code(event_code)) {
704 case SCU_EVENT_LINK_FAILURE:
705 /* Link failure change state back to the starting state */
706 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
707 break;
708 case SCU_EVENT_SATA_SPINUP_HOLD:
709 /* These events are received every 10ms and are
710 * expected while in this state
711 */
712 break;
713
714 case SCU_EVENT_SAS_PHY_DETECTED:
715 /* There has been a change in the phy type before OOB/SN for the
716 * SATA finished start down the SAS link traning path.
717 */
718 sci_phy_start_sas_link_training(iphy);
719 break;
720
721 default:
722 dev_warn(sciphy_to_dev(iphy),
723 "%s: PHY starting substate machine received "
724 "unexpected event_code %x\n",
725 __func__, event_code);
726
727 return SCI_FAILURE;
728 }
729 return SCI_SUCCESS;
730 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
731 switch (scu_get_event_code(event_code)) {
732 case SCU_EVENT_LINK_FAILURE:
733 /* Link failure change state back to the starting state */
734 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
735 break;
736 case SCU_EVENT_SATA_SPINUP_HOLD:
737 /* These events might be received since we dont know how many may be in
738 * the completion queue while waiting for power
739 */
740 break;
741 case SCU_EVENT_SATA_PHY_DETECTED:
742 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
743
744 /* We have received the SATA PHY notification change state */
745 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
746 break;
747 case SCU_EVENT_SAS_PHY_DETECTED:
748 /* There has been a change in the phy type before OOB/SN for the
749 * SATA finished start down the SAS link traning path.
750 */
751 sci_phy_start_sas_link_training(iphy);
752 break;
753 default:
754 dev_warn(sciphy_to_dev(iphy),
755 "%s: PHY starting substate machine received "
756 "unexpected event_code %x\n",
757 __func__,
758 event_code);
759
760 return SCI_FAILURE;
761 }
762 return SCI_SUCCESS;
763 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
764 switch (scu_get_event_code(event_code)) {
765 case SCU_EVENT_SATA_PHY_DETECTED:
766 /*
767 * The hardware reports multiple SATA PHY detected events
768 * ignore the extras */
769 break;
770 case SCU_EVENT_SATA_15:
771 case SCU_EVENT_SATA_15_SSC:
772 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
773 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
774 break;
775 case SCU_EVENT_SATA_30:
776 case SCU_EVENT_SATA_30_SSC:
777 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
778 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
779 break;
780 case SCU_EVENT_SATA_60:
781 case SCU_EVENT_SATA_60_SSC:
782 sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
783 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
784 break;
785 case SCU_EVENT_LINK_FAILURE:
786 /* Link failure change state back to the starting state */
787 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
788 break;
789 case SCU_EVENT_SAS_PHY_DETECTED:
790 /*
791 * There has been a change in the phy type before OOB/SN for the
792 * SATA finished start down the SAS link traning path. */
793 sci_phy_start_sas_link_training(iphy);
794 break;
795 default:
796 dev_warn(sciphy_to_dev(iphy),
797 "%s: PHY starting substate machine received "
798 "unexpected event_code %x\n",
799 __func__, event_code);
800
801 return SCI_FAILURE;
802 }
803
804 return SCI_SUCCESS;
805 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
806 switch (scu_get_event_code(event_code)) {
807 case SCU_EVENT_SATA_PHY_DETECTED:
808 /* Backup the state machine */
809 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
810 break;
811
812 case SCU_EVENT_LINK_FAILURE:
813 /* Link failure change state back to the starting state */
814 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
815 break;
816
817 default:
818 dev_warn(sciphy_to_dev(iphy),
819 "%s: PHY starting substate machine received "
820 "unexpected event_code %x\n",
821 __func__,
822 event_code);
823
824 return SCI_FAILURE;
825 }
826 return SCI_SUCCESS;
827 case SCI_PHY_READY:
828 switch (scu_get_event_code(event_code)) {
829 case SCU_EVENT_LINK_FAILURE:
830 /* Link failure change state back to the starting state */
831 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
832 break;
833 case SCU_EVENT_BROADCAST_CHANGE:
834 /* Broadcast change received. Notify the port. */
835 if (phy_get_non_dummy_port(iphy) != NULL)
836 sci_port_broadcast_change_received(iphy->owning_port, iphy);
837 else
838 iphy->bcn_received_while_port_unassigned = true;
839 break;
840 default:
841 dev_warn(sciphy_to_dev(iphy),
842 "%sP SCIC PHY 0x%p ready state machine received "
843 "unexpected event_code %x\n",
844 __func__, iphy, event_code);
845 return SCI_FAILURE_INVALID_STATE;
846 }
847 return SCI_SUCCESS;
848 case SCI_PHY_RESETTING:
849 switch (scu_get_event_code(event_code)) {
850 case SCU_EVENT_HARD_RESET_TRANSMITTED:
851 /* Link failure change state back to the starting state */
852 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
853 break;
854 default:
855 dev_warn(sciphy_to_dev(iphy),
856 "%s: SCIC PHY 0x%p resetting state machine received "
857 "unexpected event_code %x\n",
858 __func__, iphy, event_code);
859
860 return SCI_FAILURE_INVALID_STATE;
861 break;
862 }
863 return SCI_SUCCESS;
864 default:
865 dev_dbg(sciphy_to_dev(iphy),
866 "%s: in wrong state: %d\n", __func__, state);
867 return SCI_FAILURE_INVALID_STATE;
868 }
869 }
870
sci_phy_frame_handler(struct isci_phy * iphy,u32 frame_index)871 enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index)
872 {
873 enum sci_phy_states state = iphy->sm.current_state_id;
874 struct isci_host *ihost = iphy->owning_port->owning_controller;
875 enum sci_status result;
876 unsigned long flags;
877
878 switch (state) {
879 case SCI_PHY_SUB_AWAIT_IAF_UF: {
880 u32 *frame_words;
881 struct sas_identify_frame iaf;
882
883 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
884 frame_index,
885 (void **)&frame_words);
886
887 if (result != SCI_SUCCESS)
888 return result;
889
890 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
891 if (iaf.frame_type == 0) {
892 u32 state;
893
894 spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
895 memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
896 spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
897 if (iaf.smp_tport) {
898 /* We got the IAF for an expander PHY go to the final
899 * state since there are no power requirements for
900 * expander phys.
901 */
902 state = SCI_PHY_SUB_FINAL;
903 } else {
904 /* We got the IAF we can now go to the await spinup
905 * semaphore state
906 */
907 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
908 }
909 sci_change_state(&iphy->sm, state);
910 result = SCI_SUCCESS;
911 } else
912 dev_warn(sciphy_to_dev(iphy),
913 "%s: PHY starting substate machine received "
914 "unexpected frame id %x\n",
915 __func__, frame_index);
916
917 sci_controller_release_frame(ihost, frame_index);
918 return result;
919 }
920 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
921 struct dev_to_host_fis *frame_header;
922 u32 *fis_frame_data;
923
924 result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
925 frame_index,
926 (void **)&frame_header);
927
928 if (result != SCI_SUCCESS)
929 return result;
930
931 if ((frame_header->fis_type == FIS_REGD2H) &&
932 !(frame_header->status & ATA_BUSY)) {
933 sci_unsolicited_frame_control_get_buffer(&ihost->uf_control,
934 frame_index,
935 (void **)&fis_frame_data);
936
937 spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
938 sci_controller_copy_sata_response(&iphy->frame_rcvd.fis,
939 frame_header,
940 fis_frame_data);
941 spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
942
943 /* got IAF we can now go to the await spinup semaphore state */
944 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
945
946 result = SCI_SUCCESS;
947 } else
948 dev_warn(sciphy_to_dev(iphy),
949 "%s: PHY starting substate machine received "
950 "unexpected frame id %x\n",
951 __func__, frame_index);
952
953 /* Regardless of the result we are done with this frame with it */
954 sci_controller_release_frame(ihost, frame_index);
955
956 return result;
957 }
958 default:
959 dev_dbg(sciphy_to_dev(iphy),
960 "%s: in wrong state: %d\n", __func__, state);
961 return SCI_FAILURE_INVALID_STATE;
962 }
963
964 }
965
sci_phy_starting_initial_substate_enter(struct sci_base_state_machine * sm)966 static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
967 {
968 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
969
970 /* This is just an temporary state go off to the starting state */
971 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
972 }
973
sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine * sm)974 static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
975 {
976 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
977 struct isci_host *ihost = iphy->owning_port->owning_controller;
978
979 sci_controller_power_control_queue_insert(ihost, iphy);
980 }
981
sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine * sm)982 static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
983 {
984 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
985 struct isci_host *ihost = iphy->owning_port->owning_controller;
986
987 sci_controller_power_control_queue_remove(ihost, iphy);
988 }
989
sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine * sm)990 static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
991 {
992 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
993 struct isci_host *ihost = iphy->owning_port->owning_controller;
994
995 sci_controller_power_control_queue_insert(ihost, iphy);
996 }
997
sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine * sm)998 static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
999 {
1000 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1001 struct isci_host *ihost = iphy->owning_port->owning_controller;
1002
1003 sci_controller_power_control_queue_remove(ihost, iphy);
1004 }
1005
sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine * sm)1006 static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1007 {
1008 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1009
1010 sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1011 }
1012
sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine * sm)1013 static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1014 {
1015 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1016
1017 sci_del_timer(&iphy->sata_timer);
1018 }
1019
sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine * sm)1020 static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1021 {
1022 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1023
1024 sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1025 }
1026
sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine * sm)1027 static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1028 {
1029 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1030
1031 sci_del_timer(&iphy->sata_timer);
1032 }
1033
sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine * sm)1034 static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1035 {
1036 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1037
1038 if (sci_port_link_detected(iphy->owning_port, iphy)) {
1039
1040 /*
1041 * Clear the PE suspend condition so we can actually
1042 * receive SIG FIS
1043 * The hardware will not respond to the XRDY until the PE
1044 * suspend condition is cleared.
1045 */
1046 sci_phy_resume(iphy);
1047
1048 sci_mod_timer(&iphy->sata_timer,
1049 SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1050 } else
1051 iphy->is_in_link_training = false;
1052 }
1053
sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine * sm)1054 static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1055 {
1056 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1057
1058 sci_del_timer(&iphy->sata_timer);
1059 }
1060
sci_phy_starting_final_substate_enter(struct sci_base_state_machine * sm)1061 static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1062 {
1063 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1064
1065 /* State machine has run to completion so exit out and change
1066 * the base state machine to the ready state
1067 */
1068 sci_change_state(&iphy->sm, SCI_PHY_READY);
1069 }
1070
1071 /**
1072 *
1073 * @sci_phy: This is the struct isci_phy object to stop.
1074 *
1075 * This method will stop the struct isci_phy object. This does not reset the
1076 * protocol engine it just suspends it and places it in a state where it will
1077 * not cause the end device to power up. none
1078 */
scu_link_layer_stop_protocol_engine(struct isci_phy * iphy)1079 static void scu_link_layer_stop_protocol_engine(
1080 struct isci_phy *iphy)
1081 {
1082 u32 scu_sas_pcfg_value;
1083 u32 enable_spinup_value;
1084
1085 /* Suspend the protocol engine and place it in a sata spinup hold state */
1086 scu_sas_pcfg_value =
1087 readl(&iphy->link_layer_registers->phy_configuration);
1088 scu_sas_pcfg_value |=
1089 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1090 SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1091 SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1092 writel(scu_sas_pcfg_value,
1093 &iphy->link_layer_registers->phy_configuration);
1094
1095 /* Disable the notify enable spinup primitives */
1096 enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
1097 enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1098 writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
1099 }
1100
scu_link_layer_start_oob(struct isci_phy * iphy)1101 static void scu_link_layer_start_oob(struct isci_phy *iphy)
1102 {
1103 struct scu_link_layer_registers __iomem *ll = iphy->link_layer_registers;
1104 u32 val;
1105
1106 /** Reset OOB sequence - start */
1107 val = readl(&ll->phy_configuration);
1108 val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1109 SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1110 writel(val, &ll->phy_configuration);
1111 readl(&ll->phy_configuration); /* flush */
1112 /** Reset OOB sequence - end */
1113
1114 /** Start OOB sequence - start */
1115 val = readl(&ll->phy_configuration);
1116 val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1117 writel(val, &ll->phy_configuration);
1118 readl(&ll->phy_configuration); /* flush */
1119 /** Start OOB sequence - end */
1120 }
1121
1122 /**
1123 *
1124 *
1125 * This method will transmit a hard reset request on the specified phy. The SCU
1126 * hardware requires that we reset the OOB state machine and set the hard reset
1127 * bit in the phy configuration register. We then must start OOB over with the
1128 * hard reset bit set.
1129 */
scu_link_layer_tx_hard_reset(struct isci_phy * iphy)1130 static void scu_link_layer_tx_hard_reset(
1131 struct isci_phy *iphy)
1132 {
1133 u32 phy_configuration_value;
1134
1135 /*
1136 * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1137 * to the starting state. */
1138 phy_configuration_value =
1139 readl(&iphy->link_layer_registers->phy_configuration);
1140 phy_configuration_value |=
1141 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1142 SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1143 writel(phy_configuration_value,
1144 &iphy->link_layer_registers->phy_configuration);
1145
1146 /* Now take the OOB state machine out of reset */
1147 phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1148 phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1149 writel(phy_configuration_value,
1150 &iphy->link_layer_registers->phy_configuration);
1151 }
1152
sci_phy_stopped_state_enter(struct sci_base_state_machine * sm)1153 static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1154 {
1155 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1156 struct isci_port *iport = iphy->owning_port;
1157 struct isci_host *ihost = iport->owning_controller;
1158
1159 /*
1160 * @todo We need to get to the controller to place this PE in a
1161 * reset state
1162 */
1163 sci_del_timer(&iphy->sata_timer);
1164
1165 scu_link_layer_stop_protocol_engine(iphy);
1166
1167 if (iphy->sm.previous_state_id != SCI_PHY_INITIAL)
1168 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1169 }
1170
sci_phy_starting_state_enter(struct sci_base_state_machine * sm)1171 static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm)
1172 {
1173 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1174 struct isci_port *iport = iphy->owning_port;
1175 struct isci_host *ihost = iport->owning_controller;
1176
1177 scu_link_layer_stop_protocol_engine(iphy);
1178 scu_link_layer_start_oob(iphy);
1179
1180 /* We don't know what kind of phy we are going to be just yet */
1181 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1182 iphy->bcn_received_while_port_unassigned = false;
1183
1184 if (iphy->sm.previous_state_id == SCI_PHY_READY)
1185 sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1186
1187 sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL);
1188 }
1189
sci_phy_ready_state_enter(struct sci_base_state_machine * sm)1190 static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm)
1191 {
1192 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1193 struct isci_port *iport = iphy->owning_port;
1194 struct isci_host *ihost = iport->owning_controller;
1195
1196 sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy);
1197 }
1198
sci_phy_ready_state_exit(struct sci_base_state_machine * sm)1199 static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm)
1200 {
1201 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1202
1203 sci_phy_suspend(iphy);
1204 }
1205
sci_phy_resetting_state_enter(struct sci_base_state_machine * sm)1206 static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1207 {
1208 struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1209
1210 /* The phy is being reset, therefore deactivate it from the port. In
1211 * the resetting state we don't notify the user regarding link up and
1212 * link down notifications
1213 */
1214 sci_port_deactivate_phy(iphy->owning_port, iphy, false);
1215
1216 if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1217 scu_link_layer_tx_hard_reset(iphy);
1218 } else {
1219 /* The SCU does not need to have a discrete reset state so
1220 * just go back to the starting state.
1221 */
1222 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
1223 }
1224 }
1225
1226 static const struct sci_base_state sci_phy_state_table[] = {
1227 [SCI_PHY_INITIAL] = { },
1228 [SCI_PHY_STOPPED] = {
1229 .enter_state = sci_phy_stopped_state_enter,
1230 },
1231 [SCI_PHY_STARTING] = {
1232 .enter_state = sci_phy_starting_state_enter,
1233 },
1234 [SCI_PHY_SUB_INITIAL] = {
1235 .enter_state = sci_phy_starting_initial_substate_enter,
1236 },
1237 [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1238 [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1239 [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1240 [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1241 .enter_state = sci_phy_starting_await_sas_power_substate_enter,
1242 .exit_state = sci_phy_starting_await_sas_power_substate_exit,
1243 },
1244 [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1245 .enter_state = sci_phy_starting_await_sata_power_substate_enter,
1246 .exit_state = sci_phy_starting_await_sata_power_substate_exit
1247 },
1248 [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1249 .enter_state = sci_phy_starting_await_sata_phy_substate_enter,
1250 .exit_state = sci_phy_starting_await_sata_phy_substate_exit
1251 },
1252 [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1253 .enter_state = sci_phy_starting_await_sata_speed_substate_enter,
1254 .exit_state = sci_phy_starting_await_sata_speed_substate_exit
1255 },
1256 [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1257 .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter,
1258 .exit_state = sci_phy_starting_await_sig_fis_uf_substate_exit
1259 },
1260 [SCI_PHY_SUB_FINAL] = {
1261 .enter_state = sci_phy_starting_final_substate_enter,
1262 },
1263 [SCI_PHY_READY] = {
1264 .enter_state = sci_phy_ready_state_enter,
1265 .exit_state = sci_phy_ready_state_exit,
1266 },
1267 [SCI_PHY_RESETTING] = {
1268 .enter_state = sci_phy_resetting_state_enter,
1269 },
1270 [SCI_PHY_FINAL] = { },
1271 };
1272
sci_phy_construct(struct isci_phy * iphy,struct isci_port * iport,u8 phy_index)1273 void sci_phy_construct(struct isci_phy *iphy,
1274 struct isci_port *iport, u8 phy_index)
1275 {
1276 sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL);
1277
1278 /* Copy the rest of the input data to our locals */
1279 iphy->owning_port = iport;
1280 iphy->phy_index = phy_index;
1281 iphy->bcn_received_while_port_unassigned = false;
1282 iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1283 iphy->link_layer_registers = NULL;
1284 iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1285
1286 /* Create the SIGNATURE FIS Timeout timer for this phy */
1287 sci_init_timer(&iphy->sata_timer, phy_sata_timeout);
1288 }
1289
isci_phy_init(struct isci_phy * iphy,struct isci_host * ihost,int index)1290 void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1291 {
1292 struct sci_oem_params *oem = &ihost->oem_parameters;
1293 u64 sci_sas_addr;
1294 __be64 sas_addr;
1295
1296 sci_sas_addr = oem->phys[index].sas_address.high;
1297 sci_sas_addr <<= 32;
1298 sci_sas_addr |= oem->phys[index].sas_address.low;
1299 sas_addr = cpu_to_be64(sci_sas_addr);
1300 memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1301
1302 iphy->isci_port = NULL;
1303 iphy->sas_phy.enabled = 0;
1304 iphy->sas_phy.id = index;
1305 iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1306 iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1307 iphy->sas_phy.ha = &ihost->sas_ha;
1308 iphy->sas_phy.lldd_phy = iphy;
1309 iphy->sas_phy.enabled = 1;
1310 iphy->sas_phy.class = SAS;
1311 iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1312 iphy->sas_phy.tproto = 0;
1313 iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1314 iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1315 iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1316 iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1317 memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1318 }
1319
1320
1321 /**
1322 * isci_phy_control() - This function is one of the SAS Domain Template
1323 * functions. This is a phy management function.
1324 * @phy: This parameter specifies the sphy being controlled.
1325 * @func: This parameter specifies the phy control function being invoked.
1326 * @buf: This parameter is specific to the phy function being invoked.
1327 *
1328 * status, zero indicates success.
1329 */
isci_phy_control(struct asd_sas_phy * sas_phy,enum phy_func func,void * buf)1330 int isci_phy_control(struct asd_sas_phy *sas_phy,
1331 enum phy_func func,
1332 void *buf)
1333 {
1334 int ret = 0;
1335 struct isci_phy *iphy = sas_phy->lldd_phy;
1336 struct isci_port *iport = iphy->isci_port;
1337 struct isci_host *ihost = sas_phy->ha->lldd_ha;
1338 unsigned long flags;
1339
1340 dev_dbg(&ihost->pdev->dev,
1341 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1342 __func__, sas_phy, func, buf, iphy, iport);
1343
1344 switch (func) {
1345 case PHY_FUNC_DISABLE:
1346 spin_lock_irqsave(&ihost->scic_lock, flags);
1347 sci_phy_stop(iphy);
1348 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1349 break;
1350
1351 case PHY_FUNC_LINK_RESET:
1352 spin_lock_irqsave(&ihost->scic_lock, flags);
1353 sci_phy_stop(iphy);
1354 sci_phy_start(iphy);
1355 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1356 break;
1357
1358 case PHY_FUNC_HARD_RESET:
1359 if (!iport)
1360 return -ENODEV;
1361
1362 /* Perform the port reset. */
1363 ret = isci_port_perform_hard_reset(ihost, iport, iphy);
1364
1365 break;
1366 case PHY_FUNC_GET_EVENTS: {
1367 struct scu_link_layer_registers __iomem *r;
1368 struct sas_phy *phy = sas_phy->phy;
1369
1370 r = iphy->link_layer_registers;
1371 phy->running_disparity_error_count = readl(&r->running_disparity_error_count);
1372 phy->loss_of_dword_sync_count = readl(&r->loss_of_sync_error_count);
1373 phy->phy_reset_problem_count = readl(&r->phy_reset_problem_count);
1374 phy->invalid_dword_count = readl(&r->invalid_dword_counter);
1375 break;
1376 }
1377
1378 default:
1379 dev_dbg(&ihost->pdev->dev,
1380 "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1381 __func__, sas_phy, func);
1382 ret = -ENOSYS;
1383 break;
1384 }
1385 return ret;
1386 }
1387