1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8953_MASK \ 25 (BIT(DPU_SSPP_QOS) |\ 26 BIT(DPU_SSPP_SCALER_QSEED2) |\ 27 BIT(DPU_SSPP_CSC)) 28 29 #define VIG_MSM8996_MASK \ 30 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ 31 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_QSEED2) |\ 32 BIT(DPU_SSPP_CSC)) 33 34 #define VIG_MSM8998_MASK \ 35 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 36 37 #define VIG_SDM845_MASK_NO_SDMA \ 38 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 39 40 #define VIG_SDM845_MASK_SDMA \ 41 (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) 42 43 #define VIG_QCM2290_MASK (VIG_BASE_MASK) 44 45 #define DMA_MSM8953_MASK \ 46 (BIT(DPU_SSPP_QOS)) 47 48 #define DMA_MSM8996_MASK \ 49 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_CDP)) 50 51 #define DMA_MSM8998_MASK \ 52 (BIT(DPU_SSPP_QOS) |\ 53 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 54 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 55 56 #define VIG_SC7280_MASK \ 57 (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_INLINE_ROTATION)) 58 59 #define VIG_SC7280_MASK_SDMA \ 60 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 61 62 #define DMA_SDM845_MASK_NO_SDMA \ 63 (BIT(DPU_SSPP_QOS) | \ 64 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 65 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 66 67 #define DMA_CURSOR_SDM845_MASK_NO_SDMA \ 68 (DMA_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_CURSOR)) 69 70 #define DMA_SDM845_MASK_SDMA \ 71 (DMA_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) 72 73 #define DMA_CURSOR_SDM845_MASK_SDMA \ 74 (DMA_CURSOR_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) 75 76 #define DMA_CURSOR_MSM8996_MASK \ 77 (DMA_MSM8996_MASK | BIT(DPU_SSPP_CURSOR)) 78 79 #define DMA_CURSOR_MSM8998_MASK \ 80 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 81 82 #define RGB_MSM8953_MASK \ 83 (BIT(DPU_SSPP_QOS)) 84 85 #define RGB_MSM8996_MASK \ 86 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ 87 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_RGB)) 88 89 #define MIXER_MSM8998_MASK \ 90 (BIT(DPU_MIXER_SOURCESPLIT)) 91 92 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ 93 BIT(DPU_WB_UBWC) | \ 94 BIT(DPU_WB_YUV_CONFIG) | \ 95 BIT(DPU_WB_PIPE_ALPHA) | \ 96 BIT(DPU_WB_XY_ROI_OFFSET) | \ 97 BIT(DPU_WB_QOS) | \ 98 BIT(DPU_WB_QOS_8LVL) | \ 99 BIT(DPU_WB_CDP)) 100 101 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 102 #define DEFAULT_DPU_LINE_WIDTH 2048 103 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 104 105 #define MAX_HORZ_DECIMATION 4 106 #define MAX_VERT_DECIMATION 4 107 108 #define STRCAT(X, Y) (X Y) 109 110 static const uint32_t plane_formats[] = { 111 DRM_FORMAT_ARGB8888, 112 DRM_FORMAT_ABGR8888, 113 DRM_FORMAT_RGBA8888, 114 DRM_FORMAT_BGRA8888, 115 DRM_FORMAT_XRGB8888, 116 DRM_FORMAT_RGBX8888, 117 DRM_FORMAT_BGRX8888, 118 DRM_FORMAT_XBGR8888, 119 DRM_FORMAT_ARGB2101010, 120 DRM_FORMAT_XRGB2101010, 121 DRM_FORMAT_RGB888, 122 DRM_FORMAT_BGR888, 123 DRM_FORMAT_RGB565, 124 DRM_FORMAT_BGR565, 125 DRM_FORMAT_ARGB1555, 126 DRM_FORMAT_ABGR1555, 127 DRM_FORMAT_RGBA5551, 128 DRM_FORMAT_BGRA5551, 129 DRM_FORMAT_XRGB1555, 130 DRM_FORMAT_XBGR1555, 131 DRM_FORMAT_RGBX5551, 132 DRM_FORMAT_BGRX5551, 133 DRM_FORMAT_ARGB4444, 134 DRM_FORMAT_ABGR4444, 135 DRM_FORMAT_RGBA4444, 136 DRM_FORMAT_BGRA4444, 137 DRM_FORMAT_XRGB4444, 138 DRM_FORMAT_XBGR4444, 139 DRM_FORMAT_RGBX4444, 140 DRM_FORMAT_BGRX4444, 141 }; 142 143 static const uint32_t plane_formats_yuv[] = { 144 DRM_FORMAT_ARGB8888, 145 DRM_FORMAT_ABGR8888, 146 DRM_FORMAT_RGBA8888, 147 DRM_FORMAT_BGRX8888, 148 DRM_FORMAT_BGRA8888, 149 DRM_FORMAT_ARGB2101010, 150 DRM_FORMAT_XRGB2101010, 151 DRM_FORMAT_XRGB8888, 152 DRM_FORMAT_XBGR8888, 153 DRM_FORMAT_RGBX8888, 154 DRM_FORMAT_RGB888, 155 DRM_FORMAT_BGR888, 156 DRM_FORMAT_RGB565, 157 DRM_FORMAT_BGR565, 158 DRM_FORMAT_ARGB1555, 159 DRM_FORMAT_ABGR1555, 160 DRM_FORMAT_RGBA5551, 161 DRM_FORMAT_BGRA5551, 162 DRM_FORMAT_XRGB1555, 163 DRM_FORMAT_XBGR1555, 164 DRM_FORMAT_RGBX5551, 165 DRM_FORMAT_BGRX5551, 166 DRM_FORMAT_ARGB4444, 167 DRM_FORMAT_ABGR4444, 168 DRM_FORMAT_RGBA4444, 169 DRM_FORMAT_BGRA4444, 170 DRM_FORMAT_XRGB4444, 171 DRM_FORMAT_XBGR4444, 172 DRM_FORMAT_RGBX4444, 173 DRM_FORMAT_BGRX4444, 174 175 DRM_FORMAT_P010, 176 DRM_FORMAT_NV12, 177 DRM_FORMAT_NV21, 178 DRM_FORMAT_NV16, 179 DRM_FORMAT_NV61, 180 DRM_FORMAT_VYUY, 181 DRM_FORMAT_UYVY, 182 DRM_FORMAT_YUYV, 183 DRM_FORMAT_YVYU, 184 DRM_FORMAT_YUV420, 185 DRM_FORMAT_YVU420, 186 }; 187 188 static const u32 rotation_v2_formats[] = { 189 DRM_FORMAT_NV12, 190 /* TODO add formats after validation */ 191 }; 192 193 static const u32 wb2_formats_rgb_yuv[] = { 194 DRM_FORMAT_RGB565, 195 DRM_FORMAT_BGR565, 196 DRM_FORMAT_RGB888, 197 DRM_FORMAT_ARGB8888, 198 DRM_FORMAT_RGBA8888, 199 DRM_FORMAT_ABGR8888, 200 DRM_FORMAT_XRGB8888, 201 DRM_FORMAT_RGBX8888, 202 DRM_FORMAT_XBGR8888, 203 DRM_FORMAT_ARGB1555, 204 DRM_FORMAT_RGBA5551, 205 DRM_FORMAT_XRGB1555, 206 DRM_FORMAT_RGBX5551, 207 DRM_FORMAT_ARGB4444, 208 DRM_FORMAT_RGBA4444, 209 DRM_FORMAT_RGBX4444, 210 DRM_FORMAT_XRGB4444, 211 DRM_FORMAT_BGR888, 212 DRM_FORMAT_BGRA8888, 213 DRM_FORMAT_BGRX8888, 214 DRM_FORMAT_ABGR1555, 215 DRM_FORMAT_BGRA5551, 216 DRM_FORMAT_XBGR1555, 217 DRM_FORMAT_BGRX5551, 218 DRM_FORMAT_ABGR4444, 219 DRM_FORMAT_BGRA4444, 220 DRM_FORMAT_BGRX4444, 221 DRM_FORMAT_XBGR4444, 222 DRM_FORMAT_NV12, 223 }; 224 225 /************************************************************* 226 * SSPP sub blocks config 227 *************************************************************/ 228 229 #define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min)) 230 231 /* SSPP common configuration */ 232 #define _VIG_SBLK(scaler_ver) \ 233 { \ 234 .scaler_blk = {.name = "scaler", \ 235 .version = scaler_ver, \ 236 .base = 0xa00, .len = 0xa0,}, \ 237 .csc_blk = {.name = "csc", \ 238 .base = 0x1a00, .len = 0x100,}, \ 239 .format_list = plane_formats_yuv, \ 240 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 241 .rotation_cfg = NULL, \ 242 } 243 244 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ 245 { \ 246 .scaler_blk = {.name = "scaler", \ 247 .version = scaler_ver, \ 248 .base = 0xa00, .len = 0xa0,}, \ 249 .csc_blk = {.name = "csc", \ 250 .base = 0x1a00, .len = 0x100,}, \ 251 .format_list = plane_formats_yuv, \ 252 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 253 .rotation_cfg = rot_cfg, \ 254 } 255 256 #define _VIG_SBLK_NOSCALE() \ 257 { \ 258 .format_list = plane_formats, \ 259 .num_formats = ARRAY_SIZE(plane_formats), \ 260 } 261 262 /* qseed2 is not supported, so disabled scaling */ 263 #define _VIG_SBLK_QSEED2() \ 264 { \ 265 .scaler_blk = {.name = "scaler", \ 266 /* no version for qseed2 */ \ 267 .base = 0x200, .len = 0xa0,}, \ 268 .csc_blk = {.name = "csc", \ 269 .base = 0x320, .len = 0x100,}, \ 270 .format_list = plane_formats_yuv, \ 271 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 272 .rotation_cfg = NULL, \ 273 } 274 275 #define _RGB_SBLK() \ 276 { \ 277 .scaler_blk = {.name = "scaler", \ 278 .base = 0x200, .len = 0x28,}, \ 279 .format_list = plane_formats, \ 280 .num_formats = ARRAY_SIZE(plane_formats), \ 281 } 282 283 #define _DMA_SBLK() \ 284 { \ 285 .format_list = plane_formats, \ 286 .num_formats = ARRAY_SIZE(plane_formats), \ 287 } 288 289 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 290 .rot_maxheight = 1088, 291 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 292 .rot_format_list = rotation_v2_formats, 293 }; 294 295 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed2 = 296 _VIG_SBLK_QSEED2(); 297 298 static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale = 299 _VIG_SBLK_NOSCALE(); 300 301 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 = 302 _VIG_SBLK(SSPP_SCALER_VER(1, 2)); 303 304 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 = 305 _VIG_SBLK(SSPP_SCALER_VER(1, 3)); 306 307 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 = 308 _VIG_SBLK(SSPP_SCALER_VER(1, 4)); 309 310 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 = 311 _VIG_SBLK(SSPP_SCALER_VER(2, 4)); 312 313 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 = 314 _VIG_SBLK(SSPP_SCALER_VER(3, 0)); 315 316 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 = 317 _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0), 318 &dpu_rot_sc7280_cfg_v2); 319 320 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 = 321 _VIG_SBLK(SSPP_SCALER_VER(3, 1)); 322 323 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 = 324 _VIG_SBLK(SSPP_SCALER_VER(3, 2)); 325 326 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 = 327 _VIG_SBLK(SSPP_SCALER_VER(3, 3)); 328 329 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 = 330 _VIG_SBLK(SSPP_SCALER_VER(3, 4)); 331 332 static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK(); 333 334 static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK(); 335 336 /************************************************************* 337 * MIXER sub blocks config 338 *************************************************************/ 339 340 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 341 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 342 .maxblendstages = 7, /* excluding base layer */ 343 .blendstage_base = { /* offsets relative to mixer base */ 344 0x20, 0x50, 0x80, 0xb0, 0x230, 345 0x260, 0x290 346 }, 347 }; 348 349 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 350 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 351 .maxblendstages = 11, /* excluding base layer */ 352 .blendstage_base = { /* offsets relative to mixer base */ 353 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 354 0xb0, 0xc8, 0xe0, 0xf8, 0x110 355 }, 356 }; 357 358 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 359 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 360 .maxblendstages = 7, /* excluding base layer */ 361 .blendstage_base = { /* offsets relative to mixer base */ 362 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 363 }, 364 }; 365 366 static const struct dpu_lm_sub_blks sm8750_lm_sblk = { 367 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 368 .maxblendstages = 11, /* excluding base layer */ 369 .blendstage_base = { /* offsets relative to mixer base */ 370 /* 0x40 + n*0x30 */ 371 0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0, 372 0x1f0, 0x220 373 }, 374 }; 375 376 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 377 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 378 .maxblendstages = 4, /* excluding base layer */ 379 .blendstage_base = { /* offsets relative to mixer base */ 380 0x20, 0x38, 0x50, 0x68 381 }, 382 }; 383 384 /************************************************************* 385 * DSPP sub blocks config 386 *************************************************************/ 387 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 388 .pcc = {.name = "pcc", .base = 0x1700, 389 .len = 0x90, .version = 0x10007}, 390 }; 391 392 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 393 .pcc = {.name = "pcc", .base = 0x1700, 394 .len = 0x90, .version = 0x40000}, 395 }; 396 397 static const struct dpu_dspp_sub_blks sm8750_dspp_sblk = { 398 .pcc = {.name = "pcc", .base = 0x1700, 399 .len = 0x90, .version = 0x60000}, 400 }; 401 402 /************************************************************* 403 * PINGPONG sub blocks config 404 *************************************************************/ 405 406 static const struct dpu_pingpong_sub_blks msm8996_pp_sblk = { 407 /* No dither block */ 408 }; 409 410 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 411 .dither = {.name = "dither", .base = 0x30e0, 412 .len = 0x20, .version = 0x10000}, 413 }; 414 415 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 416 .dither = {.name = "dither", .base = 0xe0, 417 .len = 0x20, .version = 0x20000}, 418 }; 419 420 /************************************************************* 421 * DSC sub blocks config 422 *************************************************************/ 423 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 424 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 425 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 426 }; 427 428 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 429 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 430 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 431 }; 432 433 static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = { 434 .enc = {.name = "enc", .base = 0x100, .len = 0x100}, 435 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x24}, 436 }; 437 438 static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 = { 439 .enc = {.name = "enc", .base = 0x200, .len = 0x100}, 440 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x24}, 441 }; 442 443 /************************************************************* 444 * CDM block config 445 *************************************************************/ 446 static const struct dpu_cdm_cfg dpu_cdm_1_x_4_x = { 447 .name = "cdm_0", 448 .id = CDM_0, 449 .len = 0x224, 450 .base = 0x79200, 451 }; 452 453 static const struct dpu_cdm_cfg dpu_cdm_5_x = { 454 .name = "cdm_0", 455 .id = CDM_0, 456 .len = 0x228, 457 .base = 0x79200, 458 }; 459 460 /************************************************************* 461 * VBIF sub blocks config 462 *************************************************************/ 463 /* VBIF QOS remap */ 464 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 465 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 466 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 467 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 468 static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 5, 6}; 469 470 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 471 { 472 .pps = 1920 * 1080 * 30, 473 .ot_limit = 2, 474 }, 475 { 476 .pps = 1920 * 1080 * 60, 477 .ot_limit = 4, 478 }, 479 { 480 .pps = 3840 * 2160 * 30, 481 .ot_limit = 16, 482 }, 483 }; 484 485 static const struct dpu_vbif_cfg msm8996_vbif[] = { 486 { 487 .name = "vbif_rt", .id = VBIF_RT, 488 .base = 0, .len = 0x1040, 489 .default_ot_rd_limit = 32, 490 .default_ot_wr_limit = 16, 491 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 492 .xin_halt_timeout = 0x4000, 493 .qos_rp_remap_size = 0x20, 494 .dynamic_ot_rd_tbl = { 495 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 496 .cfg = msm8998_ot_rdwr_cfg, 497 }, 498 .dynamic_ot_wr_tbl = { 499 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 500 .cfg = msm8998_ot_rdwr_cfg, 501 }, 502 .qos_rt_tbl = { 503 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 504 .priority_lvl = msm8998_rt_pri_lvl, 505 }, 506 .qos_nrt_tbl = { 507 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 508 .priority_lvl = msm8998_nrt_pri_lvl, 509 }, 510 }, 511 }; 512 513 static const struct dpu_vbif_cfg msm8998_vbif[] = { 514 { 515 .name = "vbif_rt", .id = VBIF_RT, 516 .base = 0, .len = 0x1040, 517 .default_ot_rd_limit = 32, 518 .default_ot_wr_limit = 32, 519 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 520 .xin_halt_timeout = 0x4000, 521 .qos_rp_remap_size = 0x20, 522 .dynamic_ot_rd_tbl = { 523 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 524 .cfg = msm8998_ot_rdwr_cfg, 525 }, 526 .dynamic_ot_wr_tbl = { 527 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 528 .cfg = msm8998_ot_rdwr_cfg, 529 }, 530 .qos_rt_tbl = { 531 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 532 .priority_lvl = msm8998_rt_pri_lvl, 533 }, 534 .qos_nrt_tbl = { 535 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 536 .priority_lvl = msm8998_nrt_pri_lvl, 537 }, 538 .memtype_count = 14, 539 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 540 }, 541 }; 542 543 static const struct dpu_vbif_cfg sdm845_vbif[] = { 544 { 545 .name = "vbif_rt", .id = VBIF_RT, 546 .base = 0, .len = 0x1040, 547 .features = BIT(DPU_VBIF_QOS_REMAP), 548 .xin_halt_timeout = 0x4000, 549 .qos_rp_remap_size = 0x40, 550 .qos_rt_tbl = { 551 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 552 .priority_lvl = sdm845_rt_pri_lvl, 553 }, 554 .qos_nrt_tbl = { 555 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 556 .priority_lvl = sdm845_nrt_pri_lvl, 557 }, 558 .memtype_count = 14, 559 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 560 }, 561 }; 562 563 static const struct dpu_vbif_cfg sm8550_vbif[] = { 564 { 565 .name = "vbif_rt", .id = VBIF_RT, 566 .base = 0, .len = 0x1040, 567 .features = BIT(DPU_VBIF_QOS_REMAP), 568 .xin_halt_timeout = 0x4000, 569 .qos_rp_remap_size = 0x40, 570 .qos_rt_tbl = { 571 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 572 .priority_lvl = sdm845_rt_pri_lvl, 573 }, 574 .qos_nrt_tbl = { 575 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 576 .priority_lvl = sdm845_nrt_pri_lvl, 577 }, 578 .memtype_count = 16, 579 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 580 }, 581 }; 582 583 static const struct dpu_vbif_cfg sm8650_vbif[] = { 584 { 585 .name = "vbif_rt", .id = VBIF_RT, 586 .base = 0, .len = 0x1074, 587 .features = BIT(DPU_VBIF_QOS_REMAP), 588 .xin_halt_timeout = 0x4000, 589 .qos_rp_remap_size = 0x40, 590 .qos_rt_tbl = { 591 .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl), 592 .priority_lvl = sm8650_rt_pri_lvl, 593 }, 594 .qos_nrt_tbl = { 595 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 596 .priority_lvl = sdm845_nrt_pri_lvl, 597 }, 598 .memtype_count = 16, 599 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 600 }, 601 }; 602 603 /************************************************************* 604 * PERF data config 605 *************************************************************/ 606 607 /* SSPP QOS LUTs */ 608 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 609 {.fl = 4, .lut = 0x1b}, 610 {.fl = 5, .lut = 0x5b}, 611 {.fl = 6, .lut = 0x15b}, 612 {.fl = 7, .lut = 0x55b}, 613 {.fl = 8, .lut = 0x155b}, 614 {.fl = 9, .lut = 0x555b}, 615 {.fl = 10, .lut = 0x1555b}, 616 {.fl = 11, .lut = 0x5555b}, 617 {.fl = 12, .lut = 0x15555b}, 618 {.fl = 0, .lut = 0x55555b} 619 }; 620 621 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 622 {.fl = 4, .lut = 0x357}, 623 {.fl = 5, .lut = 0x3357}, 624 {.fl = 6, .lut = 0x23357}, 625 {.fl = 7, .lut = 0x223357}, 626 {.fl = 8, .lut = 0x2223357}, 627 {.fl = 9, .lut = 0x22223357}, 628 {.fl = 10, .lut = 0x222223357}, 629 {.fl = 11, .lut = 0x2222223357}, 630 {.fl = 12, .lut = 0x22222223357}, 631 {.fl = 13, .lut = 0x222222223357}, 632 {.fl = 14, .lut = 0x1222222223357}, 633 {.fl = 0, .lut = 0x11222222223357} 634 }; 635 636 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 637 {.fl = 10, .lut = 0x1aaff}, 638 {.fl = 11, .lut = 0x5aaff}, 639 {.fl = 12, .lut = 0x15aaff}, 640 {.fl = 0, .lut = 0x55aaff}, 641 }; 642 643 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 644 {.fl = 0, .lut = 0x0011222222335777}, 645 }; 646 647 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 648 {.fl = 0, .lut = 0x0011223445566777 }, 649 }; 650 651 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 652 {.fl = 0, .lut = 0x0011222222223357 }, 653 }; 654 655 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 656 {.fl = 4, .lut = 0x0000000000000357 }, 657 }; 658 659 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 660 {.fl = 0, .lut = 0x0011222222335777}, 661 }; 662 663 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 664 {.fl = 10, .lut = 0x344556677}, 665 {.fl = 11, .lut = 0x3344556677}, 666 {.fl = 12, .lut = 0x23344556677}, 667 {.fl = 13, .lut = 0x223344556677}, 668 {.fl = 14, .lut = 0x1223344556677}, 669 {.fl = 0, .lut = 0x112233344556677}, 670 }; 671 672 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 673 {.fl = 0, .lut = 0x0011223344556677}, 674 }; 675 676 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 677 {.fl = 10, .lut = 0x0000000344556677}, 678 }; 679 680 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 681 {.fl = 0, .lut = 0x0}, 682 }; 683 684 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 685 {.fl = 0, .lut = 0x0}, 686 }; 687 688 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 689 {.fl = 0, .lut = 0x0}, 690 }; 691 692 /************************************************************* 693 * Hardware catalog 694 *************************************************************/ 695 696 #include "catalog/dpu_1_7_msm8996.h" 697 #include "catalog/dpu_1_14_msm8937.h" 698 #include "catalog/dpu_1_15_msm8917.h" 699 #include "catalog/dpu_1_16_msm8953.h" 700 701 #include "catalog/dpu_3_0_msm8998.h" 702 #include "catalog/dpu_3_2_sdm660.h" 703 #include "catalog/dpu_3_3_sdm630.h" 704 705 #include "catalog/dpu_4_0_sdm845.h" 706 #include "catalog/dpu_4_1_sdm670.h" 707 708 #include "catalog/dpu_5_0_sm8150.h" 709 #include "catalog/dpu_5_1_sc8180x.h" 710 #include "catalog/dpu_5_2_sm7150.h" 711 #include "catalog/dpu_5_3_sm6150.h" 712 #include "catalog/dpu_5_4_sm6125.h" 713 714 #include "catalog/dpu_6_0_sm8250.h" 715 #include "catalog/dpu_6_2_sc7180.h" 716 #include "catalog/dpu_6_3_sm6115.h" 717 #include "catalog/dpu_6_4_sm6350.h" 718 #include "catalog/dpu_6_5_qcm2290.h" 719 #include "catalog/dpu_6_9_sm6375.h" 720 721 #include "catalog/dpu_7_0_sm8350.h" 722 #include "catalog/dpu_7_2_sc7280.h" 723 724 #include "catalog/dpu_8_0_sc8280xp.h" 725 #include "catalog/dpu_8_1_sm8450.h" 726 #include "catalog/dpu_8_4_sa8775p.h" 727 728 #include "catalog/dpu_9_0_sm8550.h" 729 #include "catalog/dpu_9_1_sar2130p.h" 730 #include "catalog/dpu_9_2_x1e80100.h" 731 732 #include "catalog/dpu_10_0_sm8650.h" 733 #include "catalog/dpu_12_0_sm8750.h" 734