1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dccg.h"
32 #include "dce/dce_hwseq.h"
33 #include "dcn30/dcn30_cm_common.h"
34 #include "reg_helper.h"
35 #include "abm.h"
36 #include "hubp.h"
37 #include "dchubbub.h"
38 #include "timing_generator.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "mpc.h"
42 #include "mcif_wb.h"
43 #include "dc_dmub_srv.h"
44 #include "link_hwss.h"
45 #include "dpcd_defs.h"
46 #include "dcn32_hwseq.h"
47 #include "clk_mgr.h"
48 #include "dsc.h"
49 #include "dcn20/dcn20_optc.h"
50 #include "dce/dmub_hw_lock_mgr.h"
51 #include "dcn32/dcn32_resource.h"
52 #include "link.h"
53 #include "../dcn20/dcn20_hwseq.h"
54 #include "dc_state_priv.h"
55
56 #define DC_LOGGER_INIT(logger)
57
58 #define CTX \
59 hws->ctx
60 #define REG(reg)\
61 hws->regs->reg
62 #define DC_LOGGER \
63 dc->ctx->logger
64
65 #undef FN
66 #define FN(reg_name, field_name) \
67 hws->shifts->field_name, hws->masks->field_name
68
dcn32_dsc_pg_control(struct dce_hwseq * hws,unsigned int dsc_inst,bool power_on)69 void dcn32_dsc_pg_control(
70 struct dce_hwseq *hws,
71 unsigned int dsc_inst,
72 bool power_on)
73 {
74 uint32_t power_gate = power_on ? 0 : 1;
75 uint32_t pwr_status = power_on ? 0 : 2;
76 uint32_t org_ip_request_cntl = 0;
77 struct dc *dc = hws->ctx->dc;
78
79 if (dc->debug.disable_dsc_power_gate)
80 return;
81
82 if (!dc->debug.enable_double_buffered_dsc_pg_support)
83 return;
84
85 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
86 if (org_ip_request_cntl == 0)
87 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
88
89 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst);
90 switch (dsc_inst) {
91 case 0: /* DSC0 */
92 REG_UPDATE(DOMAIN16_PG_CONFIG,
93 DOMAIN_POWER_GATE, power_gate);
94
95 REG_WAIT(DOMAIN16_PG_STATUS,
96 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
97 1, 1000);
98 break;
99 case 1: /* DSC1 */
100 REG_UPDATE(DOMAIN17_PG_CONFIG,
101 DOMAIN_POWER_GATE, power_gate);
102
103 REG_WAIT(DOMAIN17_PG_STATUS,
104 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
105 1, 1000);
106 break;
107 case 2: /* DSC2 */
108 REG_UPDATE(DOMAIN18_PG_CONFIG,
109 DOMAIN_POWER_GATE, power_gate);
110
111 REG_WAIT(DOMAIN18_PG_STATUS,
112 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
113 1, 1000);
114 break;
115 case 3: /* DSC3 */
116 REG_UPDATE(DOMAIN19_PG_CONFIG,
117 DOMAIN_POWER_GATE, power_gate);
118
119 REG_WAIT(DOMAIN19_PG_STATUS,
120 DOMAIN_PGFSM_PWR_STATUS, pwr_status,
121 1, 1000);
122 break;
123 default:
124 BREAK_TO_DEBUGGER();
125 break;
126 }
127
128 if (org_ip_request_cntl == 0)
129 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
130 }
131
132
dcn32_enable_power_gating_plane(struct dce_hwseq * hws,bool enable)133 void dcn32_enable_power_gating_plane(
134 struct dce_hwseq *hws,
135 bool enable)
136 {
137 bool force_on = true; /* disable power gating */
138 uint32_t org_ip_request_cntl = 0;
139
140 if (enable)
141 force_on = false;
142
143 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
144 if (org_ip_request_cntl == 0)
145 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
146
147 /* DCHUBP0/1/2/3 */
148 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
149 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
150 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
151 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
152
153 /* DCS0/1/2/3 */
154 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
155 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
156 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
157 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
158
159 if (org_ip_request_cntl == 0)
160 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
161 }
162
dcn32_hubp_pg_control(struct dce_hwseq * hws,unsigned int hubp_inst,bool power_on)163 void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
164 {
165 uint32_t power_gate = power_on ? 0 : 1;
166 uint32_t pwr_status = power_on ? 0 : 2;
167
168 if (hws->ctx->dc->debug.disable_hubp_power_gate)
169 return;
170
171 if (REG(DOMAIN0_PG_CONFIG) == 0)
172 return;
173
174 switch (hubp_inst) {
175 case 0:
176 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
177 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
178 break;
179 case 1:
180 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
181 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
182 break;
183 case 2:
184 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
185 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
186 break;
187 case 3:
188 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
189 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
190 break;
191 default:
192 BREAK_TO_DEBUGGER();
193 break;
194 }
195 }
196
dcn32_check_no_memory_request_for_cab(struct dc * dc)197 static bool dcn32_check_no_memory_request_for_cab(struct dc *dc)
198 {
199 int i;
200
201 /* First, check no-memory-request case */
202 for (i = 0; i < dc->current_state->stream_count; i++) {
203 if ((dc->current_state->stream_status[i].plane_count) &&
204 (dc->current_state->streams[i]->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED))
205 /* Fail eligibility on a visible stream */
206 break;
207 }
208
209 if (i == dc->current_state->stream_count)
210 return true;
211
212 return false;
213 }
214
215
216 /* This function loops through every surface that needs to be cached in CAB for SS,
217 * and calculates the total number of ways required to store all surfaces (primary,
218 * meta, cursor).
219 */
dcn32_calculate_cab_allocation(struct dc * dc,struct dc_state * ctx)220 static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
221 {
222 int i;
223 uint32_t num_ways = 0;
224 uint32_t mall_ss_size_bytes = 0;
225
226 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
227 // TODO add additional logic for PSR active stream exclusion optimization
228 // mall_ss_psr_active_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes;
229
230 // Include cursor size for CAB allocation
231 for (i = 0; i < dc->res_pool->pipe_count; i++) {
232 struct pipe_ctx *pipe = &ctx->res_ctx.pipe_ctx[i];
233
234 if (!pipe->stream || !pipe->plane_state)
235 continue;
236
237 mall_ss_size_bytes += dcn32_helper_calculate_mall_bytes_for_cursor(dc, pipe, false);
238 }
239
240 // Convert number of cache lines required to number of ways
241 if (dc->debug.force_mall_ss_num_ways > 0) {
242 num_ways = dc->debug.force_mall_ss_num_ways;
243 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) {
244 num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes);
245 } else {
246 num_ways = 0;
247 }
248
249 return num_ways;
250 }
251
dcn32_apply_idle_power_optimizations(struct dc * dc,bool enable)252 bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable)
253 {
254 union dmub_rb_cmd cmd;
255 uint8_t i;
256 uint32_t ways;
257 int j;
258 bool mall_ss_unsupported = false;
259 struct dc_plane_state *plane = NULL;
260
261 if (!dc->ctx->dmub_srv)
262 return false;
263
264 for (i = 0; i < dc->current_state->stream_count; i++) {
265 /* MALL SS messaging is not supported with PSR at this time */
266 if (dc->current_state->streams[i] != NULL &&
267 dc->current_state->streams[i]->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
268 (dc->current_state->stream_count > 1 || (!dc->current_state->streams[i]->dpms_off &&
269 dc->current_state->stream_status[i].plane_count > 0)))
270 return false;
271 }
272
273 if (enable) {
274 /* 1. Check no memory request case for CAB.
275 * If no memory request case, send CAB_ACTION NO_DF_REQ DMUB message
276 */
277 if (dcn32_check_no_memory_request_for_cab(dc)) {
278 /* Enable no-memory-requests case */
279 memset(&cmd, 0, sizeof(cmd));
280 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
281 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_DCN_REQ;
282 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
283
284 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
285
286 return true;
287 }
288
289 /* 2. Check if all surfaces can fit in CAB.
290 * If surfaces can fit into CAB, send CAB_ACTION_ALLOW DMUB message
291 * and configure HUBP's to fetch from MALL
292 */
293 ways = dcn32_calculate_cab_allocation(dc, dc->current_state);
294
295 /* MALL not supported with Stereo3D or TMZ surface. If any plane is using stereo,
296 * or TMZ surface, don't try to enter MALL.
297 */
298 for (i = 0; i < dc->current_state->stream_count; i++) {
299 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
300 plane = dc->current_state->stream_status[i].plane_states[j];
301
302 if (plane->address.type == PLN_ADDR_TYPE_GRPH_STEREO ||
303 plane->address.tmz_surface) {
304 mall_ss_unsupported = true;
305 break;
306 }
307 }
308 if (mall_ss_unsupported)
309 break;
310 }
311 if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
312 memset(&cmd, 0, sizeof(cmd));
313 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
314 cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
315 cmd.cab.header.payload_bytes = sizeof(cmd.cab) - sizeof(cmd.cab.header);
316 cmd.cab.cab_alloc_ways = (uint8_t)ways;
317
318 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
319 DC_LOG_MALL("enable scanout from MALL");
320
321 return true;
322 }
323
324 DC_LOG_MALL("surface cannot fit in CAB, disabling scanout from MALL\n");
325 return false;
326 }
327
328 /* Disable CAB */
329 memset(&cmd, 0, sizeof(cmd));
330 cmd.cab.header.type = DMUB_CMD__CAB_FOR_SS;
331 cmd.cab.header.sub_type = DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION;
332 cmd.cab.header.payload_bytes =
333 sizeof(cmd.cab) - sizeof(cmd.cab.header);
334
335 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
336
337 return true;
338 }
339
340 /* Send DMCUB message with SubVP pipe info
341 * - For each pipe in context, populate payload with required SubVP information
342 * if the pipe is using SubVP for MCLK switch
343 * - This function must be called while the DMUB HW lock is acquired by driver
344 */
dcn32_commit_subvp_config(struct dc * dc,struct dc_state * context)345 void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context)
346 {
347 int i;
348 bool enable_subvp = false;
349
350 if (!dc->ctx || !dc->ctx->dmub_srv)
351 return;
352
353 for (i = 0; i < dc->res_pool->pipe_count; i++) {
354 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
355
356 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) {
357 // There is at least 1 SubVP pipe, so enable SubVP
358 enable_subvp = true;
359 break;
360 }
361 }
362 dc_dmub_setup_subvp_dmub_command(dc, context, enable_subvp);
363 }
364
365 /* Sub-Viewport DMUB lock needs to be acquired by driver whenever SubVP is active and:
366 * 1. Any full update for any SubVP main pipe
367 * 2. Any immediate flip for any SubVP pipe
368 * 3. Any flip for DRR pipe
369 * 4. If SubVP was previously in use (i.e. in old context)
370 */
dcn32_subvp_pipe_control_lock(struct dc * dc,struct dc_state * context,bool lock,bool should_lock_all_pipes,struct pipe_ctx * top_pipe_to_program,bool subvp_prev_use)371 void dcn32_subvp_pipe_control_lock(struct dc *dc,
372 struct dc_state *context,
373 bool lock,
374 bool should_lock_all_pipes,
375 struct pipe_ctx *top_pipe_to_program,
376 bool subvp_prev_use)
377 {
378 unsigned int i = 0;
379 bool subvp_immediate_flip = false;
380 bool subvp_in_use = false;
381 struct pipe_ctx *pipe;
382 enum mall_stream_type pipe_mall_type = SUBVP_NONE;
383
384 for (i = 0; i < dc->res_pool->pipe_count; i++) {
385 pipe = &context->res_ctx.pipe_ctx[i];
386 pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe);
387
388 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN) {
389 subvp_in_use = true;
390 break;
391 }
392 }
393
394 if (top_pipe_to_program && top_pipe_to_program->stream && top_pipe_to_program->plane_state) {
395 if (dc_state_get_pipe_subvp_type(context, top_pipe_to_program) == SUBVP_MAIN &&
396 top_pipe_to_program->plane_state->flip_immediate)
397 subvp_immediate_flip = true;
398 }
399
400 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
401 if ((subvp_in_use && (should_lock_all_pipes || subvp_immediate_flip)) || (!subvp_in_use && subvp_prev_use)) {
402 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
403
404 if (!lock) {
405 for (i = 0; i < dc->res_pool->pipe_count; i++) {
406 pipe = &context->res_ctx.pipe_ctx[i];
407 if (pipe->stream && pipe->plane_state && pipe_mall_type == SUBVP_MAIN &&
408 should_lock_all_pipes)
409 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
410 }
411 }
412
413 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
414 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
415 hw_lock_cmd.bits.lock = lock;
416 hw_lock_cmd.bits.should_release = !lock;
417 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
418 }
419 }
420
dcn32_subvp_pipe_control_lock_fast(union block_sequence_params * params)421 void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)
422 {
423 struct dc *dc = params->subvp_pipe_control_lock_fast_params.dc;
424 bool lock = params->subvp_pipe_control_lock_fast_params.lock;
425 bool subvp_immediate_flip = params->subvp_pipe_control_lock_fast_params.subvp_immediate_flip;
426
427 // Don't need to lock for DRR VSYNC flips -- FW will wait for DRR pending update cleared.
428 if (subvp_immediate_flip) {
429 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 };
430
431 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK;
432 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER;
433 hw_lock_cmd.bits.lock = lock;
434 hw_lock_cmd.bits.should_release = !lock;
435 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);
436 }
437 }
438
dcn32_set_mpc_shaper_3dlut(struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)439 bool dcn32_set_mpc_shaper_3dlut(
440 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
441 {
442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
443 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
444 struct dc *dc = pipe_ctx->stream->ctx->dc;
445 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
446 bool result = false;
447
448 const struct pwl_params *shaper_lut = NULL;
449 //get the shaper lut params
450 if (stream->func_shaper) {
451 if (stream->func_shaper->type == TF_TYPE_HWPWL)
452 shaper_lut = &stream->func_shaper->pwl;
453 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
454 cm_helper_translate_curve_to_hw_format(stream->ctx,
455 stream->func_shaper,
456 &dpp_base->shaper_params, true);
457 shaper_lut = &dpp_base->shaper_params;
458 }
459 }
460
461 if (stream->lut3d_func &&
462 stream->lut3d_func->state.bits.initialized == 1) {
463
464 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, mpcc_id);
465 if (!result)
466 DC_LOG_ERROR("%s: program_3dlut failed\n", __func__);
467
468 result = mpc->funcs->program_shaper(mpc, shaper_lut, mpcc_id);
469 if (!result)
470 DC_LOG_ERROR("%s: program_shaper failed\n", __func__);
471 }
472
473 return result;
474 }
475
dcn32_set_mcm_luts(struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)476 bool dcn32_set_mcm_luts(
477 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
478 {
479 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
480 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
481 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
482 bool result = true;
483 const struct pwl_params *lut_params = NULL;
484
485 // 1D LUT
486 if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
487 lut_params = &plane_state->blend_tf.pwl;
488 else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
489 result = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
490 &dpp_base->regamma_params, false);
491 if (!result)
492 return result;
493
494 lut_params = &dpp_base->regamma_params;
495 }
496 mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
497 lut_params = NULL;
498
499 // Shaper
500 if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)
501 lut_params = &plane_state->in_shaper_func.pwl;
502 else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
503 // TODO: dpp_base replace
504 ASSERT(false);
505 cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
506 &dpp_base->shaper_params, true);
507 lut_params = &dpp_base->shaper_params;
508 }
509
510 mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
511
512 // 3D
513 if (plane_state->lut3d_func.state.bits.initialized == 1)
514 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);
515 else
516 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
517
518 return result;
519 }
520
dcn32_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)521 bool dcn32_set_input_transfer_func(struct dc *dc,
522 struct pipe_ctx *pipe_ctx,
523 const struct dc_plane_state *plane_state)
524 {
525 struct dce_hwseq *hws = dc->hwseq;
526 struct mpc *mpc = dc->res_pool->mpc;
527 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
528
529 enum dc_transfer_func_predefined tf;
530 bool result = true;
531 const struct pwl_params *params = NULL;
532
533 if (mpc == NULL || plane_state == NULL)
534 return false;
535
536 tf = TRANSFER_FUNCTION_UNITY;
537
538 if (plane_state->in_transfer_func.type == TF_TYPE_PREDEFINED)
539 tf = plane_state->in_transfer_func.tf;
540
541 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
542
543 if (plane_state->in_transfer_func.type == TF_TYPE_HWPWL)
544 params = &plane_state->in_transfer_func.pwl;
545 else if (plane_state->in_transfer_func.type == TF_TYPE_DISTRIBUTED_POINTS &&
546 cm3_helper_translate_curve_to_hw_format(&plane_state->in_transfer_func,
547 &dpp_base->degamma_params, false))
548 params = &dpp_base->degamma_params;
549
550 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
551
552 if (pipe_ctx->stream_res.opp &&
553 pipe_ctx->stream_res.opp->ctx &&
554 hws->funcs.set_mcm_luts)
555 result = hws->funcs.set_mcm_luts(pipe_ctx, plane_state);
556
557 return result;
558 }
559
dcn32_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)560 bool dcn32_set_output_transfer_func(struct dc *dc,
561 struct pipe_ctx *pipe_ctx,
562 const struct dc_stream_state *stream)
563 {
564 int mpcc_id = pipe_ctx->plane_res.hubp->inst;
565 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
566 const struct pwl_params *params = NULL;
567 bool ret = false;
568
569 /* program OGAM or 3DLUT only for the top pipe*/
570 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
571 /*program shaper and 3dlut in MPC*/
572 ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
573 if (ret == false && mpc->funcs->set_output_gamma) {
574 if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
575 params = &stream->out_transfer_func.pwl;
576 else if (pipe_ctx->stream->out_transfer_func.type ==
577 TF_TYPE_DISTRIBUTED_POINTS &&
578 cm3_helper_translate_curve_to_hw_format(
579 &stream->out_transfer_func,
580 &mpc->blender_params, false))
581 params = &mpc->blender_params;
582 /* there are no ROM LUTs in OUTGAM */
583 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED)
584 BREAK_TO_DEBUGGER();
585 }
586 }
587
588 if (mpc->funcs->set_output_gamma)
589 mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
590
591 return ret;
592 }
593
594 /* Program P-State force value according to if pipe is using SubVP / FPO or not:
595 * 1. Reset P-State force on all pipes first
596 * 2. For each main pipe, force P-State disallow (P-State allow moderated by DMUB)
597 */
dcn32_update_force_pstate(struct dc * dc,struct dc_state * context)598 void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context)
599 {
600 int i;
601
602 /* Unforce p-state for each pipe if it is not FPO or SubVP.
603 * For FPO and SubVP, if it's already forced disallow, leave
604 * it as disallow.
605 */
606 for (i = 0; i < dc->res_pool->pipe_count; i++) {
607 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
608 struct hubp *hubp = pipe->plane_res.hubp;
609 struct dc_stream_status *stream_status = NULL;
610
611 if (pipe->stream)
612 stream_status = dc_state_get_stream_status(context, pipe->stream);
613
614 if (!pipe->stream || !(dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
615 (stream_status && stream_status->fpo_in_use))) {
616 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
617 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false);
618 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
619 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, false);
620 }
621 }
622
623 /* Loop through each pipe -- for each subvp main pipe force p-state allow equal to false.
624 */
625 for (i = 0; i < dc->res_pool->pipe_count; i++) {
626 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
627 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
628 struct hubp *hubp = pipe->plane_res.hubp;
629 struct dc_stream_status *stream_status = NULL;
630 struct dc_stream_status *old_stream_status = NULL;
631
632 /* Today for MED update type we do not call update clocks. However, for FPO
633 * the assumption is that update clocks should be called to disable P-State
634 * switch before any HW programming since FPO in FW and driver are not
635 * synchronized. This causes an issue where on a MED update, an FPO P-State
636 * switch could be taking place, then driver forces P-State disallow in the below
637 * code and prevents FPO from completing the sequence. In this case we add a check
638 * to avoid re-programming (and thus re-setting) the P-State force register by
639 * only reprogramming if the pipe was not previously Subvp or FPO. The assumption
640 * is that the P-State force register should be programmed correctly the first
641 * time SubVP / FPO was enabled, so there's no need to update / reset it if the
642 * pipe config has never exited SubVP / FPO.
643 */
644 if (pipe->stream)
645 stream_status = dc_state_get_stream_status(context, pipe->stream);
646 if (old_pipe->stream)
647 old_stream_status = dc_state_get_stream_status(dc->current_state, old_pipe->stream);
648
649 if (pipe->stream && (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN ||
650 (stream_status && stream_status->fpo_in_use)) &&
651 (!old_pipe->stream || (dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_MAIN &&
652 (old_stream_status && !old_stream_status->fpo_in_use)))) {
653 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow)
654 hubp->funcs->hubp_update_force_pstate_disallow(hubp, true);
655 if (hubp && hubp->funcs->hubp_update_force_cursor_pstate_disallow)
656 hubp->funcs->hubp_update_force_cursor_pstate_disallow(hubp, true);
657 }
658 }
659 }
660
661 /* Update MALL_SEL register based on if pipe / plane
662 * is a phantom pipe, main pipe, and if using MALL
663 * for SS.
664 */
dcn32_update_mall_sel(struct dc * dc,struct dc_state * context)665 void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context)
666 {
667 int i;
668 unsigned int num_ways = dcn32_calculate_cab_allocation(dc, context);
669 bool cache_cursor = false;
670
671 for (i = 0; i < dc->res_pool->pipe_count; i++) {
672 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
673 struct hubp *hubp = pipe->plane_res.hubp;
674
675 if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) {
676 int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
677
678 switch (hubp->curs_attr.color_format) {
679 case CURSOR_MODE_MONO:
680 cursor_size /= 2;
681 break;
682 case CURSOR_MODE_COLOR_1BIT_AND:
683 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
684 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
685 cursor_size *= 4;
686 break;
687
688 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
689 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
690 default:
691 cursor_size *= 8;
692 break;
693 }
694
695 if (cursor_size > 16384)
696 cache_cursor = true;
697
698 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
699 hubp->funcs->hubp_update_mall_sel(hubp, 1, false);
700 } else {
701 // MALL not supported with Stereo3D
702 hubp->funcs->hubp_update_mall_sel(hubp,
703 num_ways <= dc->caps.cache_num_ways &&
704 pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
705 pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO &&
706 !pipe->plane_state->address.tmz_surface ? 2 : 0,
707 cache_cursor);
708 }
709 }
710 }
711 }
712
713 /* Program the sub-viewport pipe configuration after the main / phantom pipes
714 * have been programmed in hardware.
715 * 1. Update force P-State for all the main pipes (disallow P-state)
716 * 2. Update MALL_SEL register
717 * 3. Program FORCE_ONE_ROW_FOR_FRAME for main subvp pipes
718 */
dcn32_program_mall_pipe_config(struct dc * dc,struct dc_state * context)719 void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context)
720 {
721 int i;
722 struct dce_hwseq *hws = dc->hwseq;
723
724 // Don't force p-state disallow -- can't block dummy p-state
725
726 // Update MALL_SEL register for each pipe
727 if (hws && hws->funcs.update_mall_sel)
728 hws->funcs.update_mall_sel(dc, context);
729
730 // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes
731 for (i = 0; i < dc->res_pool->pipe_count; i++) {
732 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
733 struct hubp *hubp = pipe->plane_res.hubp;
734
735 if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) {
736 /* TODO - remove setting CURSOR_REQ_MODE to 0 for legacy cases
737 * - need to investigate single pipe MPO + SubVP case to
738 * see if CURSOR_REQ_MODE will be back to 1 for SubVP
739 * when it should be 0 for MPO
740 */
741 if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
742 hubp->funcs->hubp_prepare_subvp_buffering(hubp, true);
743 }
744 }
745 }
746
dcn32_initialize_min_clocks(struct dc * dc)747 static void dcn32_initialize_min_clocks(struct dc *dc)
748 {
749 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk;
750
751 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
752 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
753 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
754 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
755 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
756 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
757 clocks->fclk_p_state_change_support = true;
758 clocks->p_state_change_support = true;
759 if (dc->debug.disable_boot_optimizations) {
760 clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000;
761 } else {
762 /* Even though DPG_EN = 1 for the connected display, it still requires the
763 * correct timing so we cannot set DISPCLK to min freq or it could cause
764 * audio corruption. Read current DISPCLK from DENTIST and request the same
765 * freq to ensure that the timing is valid and unchanged.
766 */
767 clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
768 }
769
770 dc->clk_mgr->funcs->update_clocks(
771 dc->clk_mgr,
772 dc->current_state,
773 true);
774 }
775
dcn32_init_hw(struct dc * dc)776 void dcn32_init_hw(struct dc *dc)
777 {
778 struct abm **abms = dc->res_pool->multiple_abms;
779 struct dce_hwseq *hws = dc->hwseq;
780 struct dc_bios *dcb = dc->ctx->dc_bios;
781 struct resource_pool *res_pool = dc->res_pool;
782 int i;
783 int edp_num;
784 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
785 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
786
787 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks)
788 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
789
790 // Initialize the dccg
791 if (res_pool->dccg->funcs->dccg_init)
792 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
793
794 if (!dcb->funcs->is_accelerated_mode(dcb)) {
795 hws->funcs.bios_golden_init(dc);
796 hws->funcs.disable_vga(dc->hwseq);
797 }
798
799 // Set default OPTC memory power states
800 if (dc->debug.enable_mem_low_power.bits.optc) {
801 // Shutdown when unassigned and light sleep in VBLANK
802 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
803 }
804
805 if (dc->debug.enable_mem_low_power.bits.vga) {
806 // Power down VGA memory
807 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
808 }
809
810 if (dc->ctx->dc_bios->fw_info_valid) {
811 res_pool->ref_clocks.xtalin_clock_inKhz =
812 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
813
814 if (res_pool->hubbub) {
815 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
816 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
817 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
818
819 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
820 res_pool->ref_clocks.dccg_ref_clock_inKhz,
821 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
822 } else {
823 // Not all ASICs have DCCG sw component
824 res_pool->ref_clocks.dccg_ref_clock_inKhz =
825 res_pool->ref_clocks.xtalin_clock_inKhz;
826 res_pool->ref_clocks.dchub_ref_clock_inKhz =
827 res_pool->ref_clocks.xtalin_clock_inKhz;
828 }
829 } else
830 ASSERT_CRITICAL(false);
831
832 for (i = 0; i < dc->link_count; i++) {
833 /* Power up AND update implementation according to the
834 * required signal (which may be different from the
835 * default signal on connector).
836 */
837 struct dc_link *link = dc->links[i];
838
839 link->link_enc->funcs->hw_init(link->link_enc);
840
841 /* Check for enabled DIG to identify enabled display */
842 if (link->link_enc->funcs->is_dig_enabled &&
843 link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
844 link->link_status.link_active = true;
845 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
846 if (link->link_enc->funcs->fec_is_active &&
847 link->link_enc->funcs->fec_is_active(link->link_enc))
848 link->fec_state = dc_link_fec_enabled;
849 }
850 }
851
852 /* enable_power_gating_plane before dsc_pg_control because
853 * FORCEON = 1 with hw default value on bootup, resume from s3
854 */
855 if (hws->funcs.enable_power_gating_plane)
856 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
857
858 /* we want to turn off all dp displays before doing detection */
859 dc->link_srv->blank_all_dp_displays(dc);
860
861 /* If taking control over from VBIOS, we may want to optimize our first
862 * mode set, so we need to skip powering down pipes until we know which
863 * pipes we want to use.
864 * Otherwise, if taking control is not possible, we need to power
865 * everything down.
866 */
867 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
868 /* Disable boot optimizations means power down everything including PHY, DIG,
869 * and OTG (i.e. the boot is not optimized because we do a full power down).
870 */
871 if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
872 dc->hwss.enable_accelerated_mode(dc, dc->current_state);
873 else
874 hws->funcs.init_pipes(dc, dc->current_state);
875
876 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
877 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
878 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
879
880 dcn32_initialize_min_clocks(dc);
881
882 /* On HW init, allow idle optimizations after pipes have been turned off.
883 *
884 * In certain D3 cases (i.e. BOCO / BOMACO) it's possible that hardware state
885 * is reset (i.e. not in idle at the time hw init is called), but software state
886 * still has idle_optimizations = true, so we must disable idle optimizations first
887 * (i.e. set false), then re-enable (set true).
888 */
889 dc_allow_idle_optimizations(dc, false);
890 dc_allow_idle_optimizations(dc, true);
891 }
892
893 /* In headless boot cases, DIG may be turned
894 * on which causes HW/SW discrepancies.
895 * To avoid this, power down hardware on boot
896 * if DIG is turned on and seamless boot not enabled
897 */
898 if (!dc->config.seamless_boot_edp_requested) {
899 struct dc_link *edp_links[MAX_NUM_EDP];
900 struct dc_link *edp_link;
901
902 dc_get_edp_links(dc, edp_links, &edp_num);
903 if (edp_num) {
904 for (i = 0; i < edp_num; i++) {
905 edp_link = edp_links[i];
906 if (edp_link->link_enc->funcs->is_dig_enabled &&
907 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
908 dc->hwss.edp_backlight_control &&
909 hws->funcs.power_down &&
910 dc->hwss.edp_power_control) {
911 dc->hwss.edp_backlight_control(edp_link, false);
912 hws->funcs.power_down(dc);
913 dc->hwss.edp_power_control(edp_link, false);
914 }
915 }
916 } else {
917 for (i = 0; i < dc->link_count; i++) {
918 struct dc_link *link = dc->links[i];
919
920 if (link->link_enc->funcs->is_dig_enabled &&
921 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
922 hws->funcs.power_down) {
923 hws->funcs.power_down(dc);
924 break;
925 }
926
927 }
928 }
929 }
930
931 for (i = 0; i < res_pool->audio_count; i++) {
932 struct audio *audio = res_pool->audios[i];
933
934 audio->funcs->hw_init(audio);
935 }
936
937 for (i = 0; i < dc->link_count; i++) {
938 struct dc_link *link = dc->links[i];
939
940 if (link->panel_cntl) {
941 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
942 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
943 }
944 }
945
946 for (i = 0; i < dc->res_pool->pipe_count; i++) {
947 if (abms[i] != NULL && abms[i]->funcs != NULL)
948 abms[i]->funcs->abm_init(abms[i], backlight, user_level);
949 }
950
951 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
952 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
953
954 if (!dc->debug.disable_clock_gate) {
955 /* enable all DCN clock gating */
956 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
957
958 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
959
960 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
961 }
962
963 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
964 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
965
966 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges)
967 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
968
969 if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->set_hard_max_memclk &&
970 !dc->clk_mgr->dc_mode_softmax_enabled)
971 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
972
973 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
974 dc->res_pool->hubbub->funcs->force_pstate_change_control(
975 dc->res_pool->hubbub, false, false);
976
977 if (dc->res_pool->hubbub->funcs->init_crb)
978 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
979
980 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
981 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
982
983 // Get DMCUB capabilities
984 if (dc->ctx->dmub_srv) {
985 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
986 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
987 dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;
988 dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;
989 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
990 dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;
991
992 /* for DCN401 testing only */
993 dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
994 if (dc->caps.dmub_caps.fams_ver == 2) {
995 /* FAMS2 is enabled */
996 dc->debug.fams2_config.bits.enable &= true;
997 } else if (dc->ctx->dmub_srv->dmub->fw_version <
998 DMUB_FW_VERSION(7, 0, 35)) {
999 /* FAMS2 is disabled */
1000 dc->debug.fams2_config.bits.enable = false;
1001 if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) {
1002 /* update bounding box if FAMS2 disabled */
1003 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1004 }
1005 dc->debug.force_disable_subvp = true;
1006 dc->debug.disable_fpo_optimizations = true;
1007 }
1008 }
1009 }
1010
dcn32_update_dsc_on_stream(struct pipe_ctx * pipe_ctx,bool enable)1011 void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
1012 {
1013 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
1014 struct dc *dc = pipe_ctx->stream->ctx->dc;
1015 struct dc_stream_state *stream = pipe_ctx->stream;
1016 struct pipe_ctx *odm_pipe;
1017 int opp_cnt = 1;
1018 struct dccg *dccg = dc->res_pool->dccg;
1019 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN
1020 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a
1021 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is
1022 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings
1023 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger
1024 * this problem. We are implementing a workaround here to keep using dscclk
1025 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e
1026 * 48Mhz) pixel clock to avoid hitting this problem.
1027 */
1028 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&
1029 stream->timing.pix_clk_100hz > 480000;
1030
1031 ASSERT(dsc);
1032 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1033 opp_cnt++;
1034
1035 if (enable) {
1036 struct dsc_config dsc_cfg;
1037 struct dsc_optc_config dsc_optc_cfg = {0};
1038 enum optc_dsc_mode optc_dsc_mode;
1039 struct dcn_dsc_state dsc_state = {0};
1040
1041 if (!dsc) {
1042 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1043 return;
1044 }
1045
1046 if (dsc->funcs->dsc_read_state) {
1047 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1048 if (!dsc_state.dsc_fw_en) {
1049 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1050 return;
1051 }
1052 }
1053
1054 /* Enable DSC hw block */
1055 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow +
1056 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
1057 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
1058 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1059 dsc_cfg.color_depth = stream->timing.display_color_depth;
1060 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1061 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1062 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
1063 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1064
1065 if (should_use_dto_dscclk)
1066 dccg->funcs->set_dto_dscclk(dccg, dsc->inst);
1067 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
1068 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
1069 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1070 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
1071
1072 ASSERT(odm_dsc);
1073 if (should_use_dto_dscclk)
1074 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst);
1075 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
1076 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
1077 }
1078 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
1079 /* Enable DSC in OPTC */
1080 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
1081 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
1082 optc_dsc_mode,
1083 dsc_optc_cfg.bytes_per_pixel,
1084 dsc_optc_cfg.slice_width);
1085 } else {
1086 /* disable DSC in OPTC */
1087 pipe_ctx->stream_res.tg->funcs->set_dsc_config(
1088 pipe_ctx->stream_res.tg,
1089 OPTC_DSC_DISABLED, 0, 0);
1090
1091 /* only disconnect DSC block, DSC is disabled when OPP head pipe is reset */
1092 dsc->funcs->dsc_disconnect(pipe_ctx->stream_res.dsc);
1093 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1094 ASSERT(odm_pipe->stream_res.dsc);
1095 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc);
1096 }
1097 }
1098 }
1099
1100 /*
1101 * Given any pipe_ctx, return the total ODM combine factor, and optionally return
1102 * the OPPids which are used
1103 * */
get_odm_config(struct pipe_ctx * pipe_ctx,unsigned int * opp_instances)1104 static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances)
1105 {
1106 unsigned int opp_count = 1;
1107 struct pipe_ctx *odm_pipe;
1108
1109 /* First get to the top pipe */
1110 for (odm_pipe = pipe_ctx; odm_pipe->prev_odm_pipe; odm_pipe = odm_pipe->prev_odm_pipe)
1111 ;
1112
1113 /* First pipe is always used */
1114 if (opp_instances)
1115 opp_instances[0] = odm_pipe->stream_res.opp->inst;
1116
1117 /* Find and count odm pipes, if any */
1118 for (odm_pipe = odm_pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1119 if (opp_instances)
1120 opp_instances[opp_count] = odm_pipe->stream_res.opp->inst;
1121 opp_count++;
1122 }
1123
1124 return opp_count;
1125 }
1126
dcn32_update_odm(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)1127 void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1128 {
1129 struct pipe_ctx *odm_pipe;
1130 int opp_cnt = 0;
1131 int opp_inst[MAX_PIPES] = {0};
1132 int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
1133 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
1134
1135 opp_cnt = get_odm_config(pipe_ctx, opp_inst);
1136
1137 if (opp_cnt > 1)
1138 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
1139 pipe_ctx->stream_res.tg,
1140 opp_inst, opp_cnt,
1141 odm_slice_width, last_odm_slice_width);
1142 else
1143 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
1144 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1145
1146 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1147 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
1148 odm_pipe->stream_res.opp,
1149 true);
1150 odm_pipe->stream_res.opp->funcs->opp_program_left_edge_extra_pixel(
1151 odm_pipe->stream_res.opp,
1152 pipe_ctx->stream->timing.pixel_encoding,
1153 resource_is_pipe_type(odm_pipe, OTG_MASTER));
1154 }
1155
1156 if (pipe_ctx->stream_res.dsc) {
1157 struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1158
1159 dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
1160
1161 /* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
1162 if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
1163 current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
1164 struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
1165
1166 /* disconnect DSC block from stream */
1167 dsc->funcs->dsc_disconnect(dsc);
1168 }
1169 }
1170
1171 if (!resource_is_pipe_type(pipe_ctx, DPP_PIPE))
1172 /*
1173 * blank pattern is generated by OPP, reprogram blank pattern
1174 * due to OPP count change
1175 */
1176 dc->hwseq->funcs.blank_pixel_data(dc, pipe_ctx, true);
1177 }
1178
dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx * pipe_ctx,unsigned int * k1_div,unsigned int * k2_div)1179 unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div)
1180 {
1181 struct dc_stream_state *stream = pipe_ctx->stream;
1182 unsigned int odm_combine_factor = 0;
1183 bool two_pix_per_container = false;
1184
1185 two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing);
1186 odm_combine_factor = get_odm_config(pipe_ctx, NULL);
1187
1188 if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1189 *k1_div = PIXEL_RATE_DIV_BY_1;
1190 *k2_div = PIXEL_RATE_DIV_BY_1;
1191 } else if (dc_is_hdmi_tmds_signal(stream->signal) || dc_is_dvi_signal(stream->signal)) {
1192 *k1_div = PIXEL_RATE_DIV_BY_1;
1193 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1194 *k2_div = PIXEL_RATE_DIV_BY_2;
1195 else
1196 *k2_div = PIXEL_RATE_DIV_BY_4;
1197 } else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
1198 if (two_pix_per_container) {
1199 *k1_div = PIXEL_RATE_DIV_BY_1;
1200 *k2_div = PIXEL_RATE_DIV_BY_2;
1201 } else {
1202 *k1_div = PIXEL_RATE_DIV_BY_1;
1203 *k2_div = PIXEL_RATE_DIV_BY_4;
1204 if ((odm_combine_factor == 2) || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1205 *k2_div = PIXEL_RATE_DIV_BY_2;
1206 }
1207 }
1208
1209 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA))
1210 ASSERT(false);
1211
1212 return odm_combine_factor;
1213 }
1214
dcn32_calculate_pix_rate_divider(struct dc * dc,struct dc_state * context,const struct dc_stream_state * stream)1215 void dcn32_calculate_pix_rate_divider(
1216 struct dc *dc,
1217 struct dc_state *context,
1218 const struct dc_stream_state *stream)
1219 {
1220 struct dce_hwseq *hws = dc->hwseq;
1221 struct pipe_ctx *pipe_ctx = NULL;
1222 unsigned int k1_div = PIXEL_RATE_DIV_NA;
1223 unsigned int k2_div = PIXEL_RATE_DIV_NA;
1224
1225 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1226
1227 if (pipe_ctx) {
1228
1229 if (hws->funcs.calculate_dccg_k1_k2_values)
1230 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
1231
1232 pipe_ctx->pixel_rate_divider.div_factor1 = k1_div;
1233 pipe_ctx->pixel_rate_divider.div_factor2 = k2_div;
1234 }
1235 }
1236
dcn32_resync_fifo_dccg_dio(struct dce_hwseq * hws,struct dc * dc,struct dc_state * context,unsigned int current_pipe_idx)1237 void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)
1238 {
1239 unsigned int i;
1240 struct pipe_ctx *pipe = NULL;
1241 bool otg_disabled[MAX_PIPES] = {false};
1242 struct dc_state *dc_state = NULL;
1243
1244 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1245 if (i <= current_pipe_idx) {
1246 pipe = &context->res_ctx.pipe_ctx[i];
1247 dc_state = context;
1248 } else {
1249 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1250 dc_state = dc->current_state;
1251 }
1252
1253 if (!resource_is_pipe_type(pipe, OTG_MASTER))
1254 continue;
1255
1256 if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
1257 && dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {
1258 pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
1259 reset_sync_context_for_pipe(dc, context, i);
1260 otg_disabled[i] = true;
1261 }
1262 }
1263
1264 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
1265
1266 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1267 if (i <= current_pipe_idx)
1268 pipe = &context->res_ctx.pipe_ctx[i];
1269 else
1270 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1271
1272 if (otg_disabled[i]) {
1273 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
1274 int opp_cnt = 1;
1275 int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe, true);
1276 int odm_slice_width = resource_get_odm_slice_dst_width(pipe, false);
1277 struct pipe_ctx *odm_pipe;
1278
1279 for (odm_pipe = pipe->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1280 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
1281 opp_cnt++;
1282 }
1283 if (opp_cnt > 1)
1284 pipe->stream_res.tg->funcs->set_odm_combine(
1285 pipe->stream_res.tg,
1286 opp_inst, opp_cnt,
1287 odm_slice_width,
1288 last_odm_slice_width);
1289 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
1290 }
1291 }
1292
1293 dc_trigger_sync(dc, dc->current_state);
1294 }
1295
dcn32_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1296 void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
1297 struct dc_link_settings *link_settings)
1298 {
1299 struct encoder_unblank_param params = {0};
1300 struct dc_stream_state *stream = pipe_ctx->stream;
1301 struct dc_link *link = stream->link;
1302 struct dce_hwseq *hws = link->dc->hwseq;
1303 struct pipe_ctx *odm_pipe;
1304
1305 params.opp_cnt = 1;
1306 params.pix_per_cycle = pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle;
1307
1308 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1309 params.opp_cnt++;
1310
1311 /* only 3 items below are used by unblank */
1312 params.timing = pipe_ctx->stream->timing;
1313
1314 params.link_settings.link_rate = link_settings->link_rate;
1315
1316 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1317 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1318 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank(
1319 pipe_ctx->stream_res.hpo_dp_stream_enc,
1320 pipe_ctx->stream_res.tg->inst);
1321 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1322 if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) ||
1323 params.opp_cnt > 1) {
1324 params.timing.pix_clk_100hz /= 2;
1325 params.pix_per_cycle = 2;
1326 }
1327 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine)
1328 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1329 pipe_ctx->stream_res.stream_enc, params.pix_per_cycle > 1);
1330 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
1331 }
1332
1333 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
1334 hws->funcs.edp_backlight_control(link, true);
1335 }
1336
dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx * pipe_ctx)1337 bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
1338 {
1339 struct dc *dc = pipe_ctx->stream->ctx->dc;
1340
1341 if (!is_h_timing_divisible_by_2(pipe_ctx->stream))
1342 return false;
1343
1344 if (dc_is_dp_signal(pipe_ctx->stream->signal) && !dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) &&
1345 dc->debug.enable_dp_dig_pixel_rate_div_policy)
1346 return true;
1347 return false;
1348 }
1349
apply_symclk_on_tx_off_wa(struct dc_link * link)1350 static void apply_symclk_on_tx_off_wa(struct dc_link *link)
1351 {
1352 /* There are use cases where SYMCLK is referenced by OTG. For instance
1353 * for TMDS signal, OTG relies SYMCLK even if TX video output is off.
1354 * However current link interface will power off PHY when disabling link
1355 * output. This will turn off SYMCLK generated by PHY. The workaround is
1356 * to identify such case where SYMCLK is still in use by OTG when we
1357 * power off PHY. When this is detected, we will temporarily power PHY
1358 * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
1359 * program_pix_clk interface. When OTG is disabled, we will then power
1360 * off PHY by calling disable link output again.
1361 *
1362 * In future dcn generations, we plan to rework transmitter control
1363 * interface so that we could have an option to set SYMCLK ON TX OFF
1364 * state in one step without this workaround
1365 */
1366
1367 struct dc *dc = link->ctx->dc;
1368 struct pipe_ctx *pipe_ctx = NULL;
1369 uint8_t i;
1370
1371 if (link->phy_state.symclk_ref_cnts.otg > 0) {
1372 for (i = 0; i < MAX_PIPES; i++) {
1373 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1374 if (resource_is_pipe_type(pipe_ctx, OPP_HEAD) && pipe_ctx->stream->link == link) {
1375 pipe_ctx->clock_source->funcs->program_pix_clk(
1376 pipe_ctx->clock_source,
1377 &pipe_ctx->stream_res.pix_clk_params,
1378 dc->link_srv->dp_get_encoding_format(
1379 &pipe_ctx->link_config.dp_link_settings),
1380 &pipe_ctx->pll_settings);
1381 link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1382 break;
1383 }
1384 }
1385 }
1386 }
1387
dcn32_disable_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)1388 void dcn32_disable_link_output(struct dc_link *link,
1389 const struct link_resource *link_res,
1390 enum signal_type signal)
1391 {
1392 struct dc *dc = link->ctx->dc;
1393 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1394 struct dmcu *dmcu = dc->res_pool->dmcu;
1395
1396 if (signal == SIGNAL_TYPE_EDP &&
1397 link->dc->hwss.edp_backlight_control &&
1398 !link->skip_implict_edp_power_control)
1399 link->dc->hwss.edp_backlight_control(link, false);
1400 else if (dmcu != NULL && dmcu->funcs->lock_phy)
1401 dmcu->funcs->lock_phy(dmcu);
1402
1403 link_hwss->disable_link_output(link, link_res, signal);
1404 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1405 /*
1406 * Add the logic to extract BOTH power up and power down sequences
1407 * from enable/disable link output and only call edp panel control
1408 * in enable_link_dp and disable_link_dp once.
1409 */
1410 if (dmcu != NULL && dmcu->funcs->unlock_phy)
1411 dmcu->funcs->unlock_phy(dmcu);
1412
1413 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
1414
1415 apply_symclk_on_tx_off_wa(link);
1416 }
1417
1418 /* For SubVP the main pipe can have a viewport position change
1419 * without a full update. In this case we must also update the
1420 * viewport positions for the phantom pipe accordingly.
1421 */
dcn32_update_phantom_vp_position(struct dc * dc,struct dc_state * context,struct pipe_ctx * phantom_pipe)1422 void dcn32_update_phantom_vp_position(struct dc *dc,
1423 struct dc_state *context,
1424 struct pipe_ctx *phantom_pipe)
1425 {
1426 uint32_t i;
1427 struct dc_plane_state *phantom_plane = phantom_pipe->plane_state;
1428
1429 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1430 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1431
1432 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN &&
1433 dc_state_get_paired_subvp_stream(context, pipe->stream) == phantom_pipe->stream) {
1434 if (pipe->plane_state && pipe->plane_state->update_flags.bits.position_change) {
1435
1436 phantom_plane->src_rect.x = pipe->plane_state->src_rect.x;
1437 phantom_plane->src_rect.y = pipe->plane_state->src_rect.y;
1438 phantom_plane->clip_rect.x = pipe->plane_state->clip_rect.x;
1439 phantom_plane->dst_rect.x = pipe->plane_state->dst_rect.x;
1440 phantom_plane->dst_rect.y = pipe->plane_state->dst_rect.y;
1441
1442 phantom_pipe->plane_state->update_flags.bits.position_change = 1;
1443 resource_build_scaling_params(phantom_pipe);
1444 return;
1445 }
1446 }
1447 }
1448 }
1449
1450 /* Treat the phantom pipe as if it needs to be fully enabled.
1451 * If the pipe was previously in use but not phantom, it would
1452 * have been disabled earlier in the sequence so we need to run
1453 * the full enable sequence.
1454 */
dcn32_apply_update_flags_for_phantom(struct pipe_ctx * phantom_pipe)1455 void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe)
1456 {
1457 phantom_pipe->update_flags.raw = 0;
1458 if (resource_is_pipe_type(phantom_pipe, DPP_PIPE)) {
1459 phantom_pipe->update_flags.bits.enable = 1;
1460 phantom_pipe->update_flags.bits.mpcc = 1;
1461 phantom_pipe->update_flags.bits.dppclk = 1;
1462 phantom_pipe->update_flags.bits.hubp_interdependent = 1;
1463 phantom_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1464 phantom_pipe->update_flags.bits.gamut_remap = 1;
1465 phantom_pipe->update_flags.bits.scaler = 1;
1466 phantom_pipe->update_flags.bits.viewport = 1;
1467 phantom_pipe->update_flags.bits.det_size = 1;
1468 if (resource_is_pipe_type(phantom_pipe, OTG_MASTER)) {
1469 phantom_pipe->update_flags.bits.odm = 1;
1470 phantom_pipe->update_flags.bits.global_sync = 1;
1471 }
1472 }
1473 }
1474
dcn32_dsc_pg_status(struct dce_hwseq * hws,unsigned int dsc_inst)1475 bool dcn32_dsc_pg_status(
1476 struct dce_hwseq *hws,
1477 unsigned int dsc_inst)
1478 {
1479 uint32_t pwr_status = 0;
1480
1481 switch (dsc_inst) {
1482 case 0: /* DSC0 */
1483 REG_GET(DOMAIN16_PG_STATUS,
1484 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1485 break;
1486 case 1: /* DSC1 */
1487
1488 REG_GET(DOMAIN17_PG_STATUS,
1489 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1490 break;
1491 case 2: /* DSC2 */
1492 REG_GET(DOMAIN18_PG_STATUS,
1493 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1494 break;
1495 case 3: /* DSC3 */
1496 REG_GET(DOMAIN19_PG_STATUS,
1497 DOMAIN_PGFSM_PWR_STATUS, &pwr_status);
1498 break;
1499 default:
1500 BREAK_TO_DEBUGGER();
1501 break;
1502 }
1503
1504 return pwr_status == 0;
1505 }
1506
dcn32_update_dsc_pg(struct dc * dc,struct dc_state * context,bool safe_to_disable)1507 void dcn32_update_dsc_pg(struct dc *dc,
1508 struct dc_state *context,
1509 bool safe_to_disable)
1510 {
1511 struct dce_hwseq *hws = dc->hwseq;
1512 int i;
1513
1514 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1515 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1516 bool is_dsc_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst);
1517
1518 if (context->res_ctx.is_dsc_acquired[i]) {
1519 if (!is_dsc_ungated) {
1520 hws->funcs.dsc_pg_control(hws, dsc->inst, true);
1521 }
1522 } else if (safe_to_disable) {
1523 if (is_dsc_ungated) {
1524 hws->funcs.dsc_pg_control(hws, dsc->inst, false);
1525 }
1526 }
1527 }
1528 }
1529
dcn32_disable_phantom_streams(struct dc * dc,struct dc_state * context)1530 void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context)
1531 {
1532 struct dce_hwseq *hws = dc->hwseq;
1533 int i;
1534
1535 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1536 struct pipe_ctx *pipe_ctx_old =
1537 &dc->current_state->res_ctx.pipe_ctx[i];
1538 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1539
1540 if (!pipe_ctx_old->stream)
1541 continue;
1542
1543 if (dc_state_get_pipe_subvp_type(dc->current_state, pipe_ctx_old) != SUBVP_PHANTOM)
1544 continue;
1545
1546 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
1547 continue;
1548
1549 if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx) ||
1550 (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)) {
1551 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1552
1553 if (hws->funcs.reset_back_end_for_pipe)
1554 hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1555 if (hws->funcs.enable_stream_gating)
1556 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
1557 if (old_clk)
1558 old_clk->funcs->cs_power_down(old_clk);
1559 }
1560 }
1561 }
1562
dcn32_enable_phantom_streams(struct dc * dc,struct dc_state * context)1563 void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context)
1564 {
1565 unsigned int i;
1566 enum dc_status status = DC_OK;
1567 struct dce_hwseq *hws = dc->hwseq;
1568
1569 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1570 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1571 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1572
1573 /* If an active, non-phantom pipe is being transitioned into a phantom
1574 * pipe, wait for the double buffer update to complete first before we do
1575 * ANY phantom pipe programming.
1576 */
1577 if (pipe->stream && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM &&
1578 old_pipe->stream && dc_state_get_pipe_subvp_type(dc->current_state, old_pipe) != SUBVP_PHANTOM) {
1579 old_pipe->stream_res.tg->funcs->wait_for_state(
1580 old_pipe->stream_res.tg,
1581 CRTC_STATE_VBLANK);
1582 old_pipe->stream_res.tg->funcs->wait_for_state(
1583 old_pipe->stream_res.tg,
1584 CRTC_STATE_VACTIVE);
1585 }
1586 }
1587 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1588 struct pipe_ctx *pipe_ctx_old =
1589 &dc->current_state->res_ctx.pipe_ctx[i];
1590 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1591
1592 if (pipe_ctx->stream == NULL)
1593 continue;
1594
1595 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM)
1596 continue;
1597
1598 if (pipe_ctx->stream == pipe_ctx_old->stream &&
1599 pipe_ctx->stream->link->link_state_valid) {
1600 continue;
1601 }
1602
1603 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
1604 continue;
1605
1606 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
1607 continue;
1608
1609 if (hws->funcs.apply_single_controller_ctx_to_hw)
1610 status = hws->funcs.apply_single_controller_ctx_to_hw(
1611 pipe_ctx,
1612 context,
1613 dc);
1614
1615 ASSERT(status == DC_OK);
1616
1617 #ifdef CONFIG_DRM_AMD_DC_FP
1618 if (hws->funcs.resync_fifo_dccg_dio)
1619 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);
1620 #endif
1621 }
1622 }
1623
1624 /* Blank pixel data during initialization */
dcn32_init_blank(struct dc * dc,struct timing_generator * tg)1625 void dcn32_init_blank(
1626 struct dc *dc,
1627 struct timing_generator *tg)
1628 {
1629 struct dce_hwseq *hws = dc->hwseq;
1630 enum dc_color_space color_space;
1631 struct tg_color black_color = {0};
1632 struct output_pixel_processor *opp = NULL;
1633 struct output_pixel_processor *bottom_opp = NULL;
1634 uint32_t num_opps, opp_id_src0, opp_id_src1;
1635 uint32_t otg_active_width = 0, otg_active_height = 0;
1636 uint32_t i;
1637
1638 /* program opp dpg blank color */
1639 color_space = COLOR_SPACE_SRGB;
1640 color_space_to_black_color(dc, color_space, &black_color);
1641
1642 /* get the OTG active size */
1643 tg->funcs->get_otg_active_size(tg,
1644 &otg_active_width,
1645 &otg_active_height);
1646
1647 /* get the OPTC source */
1648 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1649
1650 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
1651 ASSERT(false);
1652 return;
1653 }
1654
1655 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1656 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1657 opp = dc->res_pool->opps[i];
1658 break;
1659 }
1660 }
1661
1662 if (num_opps == 2) {
1663 otg_active_width = otg_active_width / 2;
1664
1665 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
1666 ASSERT(false);
1667 return;
1668 }
1669 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1670 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
1671 bottom_opp = dc->res_pool->opps[i];
1672 break;
1673 }
1674 }
1675 }
1676
1677 if (opp && opp->funcs->opp_set_disp_pattern_generator)
1678 opp->funcs->opp_set_disp_pattern_generator(
1679 opp,
1680 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1681 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1682 COLOR_DEPTH_UNDEFINED,
1683 &black_color,
1684 otg_active_width,
1685 otg_active_height,
1686 0);
1687
1688 if (num_opps == 2) {
1689 if (bottom_opp && bottom_opp->funcs->opp_set_disp_pattern_generator) {
1690 bottom_opp->funcs->opp_set_disp_pattern_generator(
1691 bottom_opp,
1692 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1693 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1694 COLOR_DEPTH_UNDEFINED,
1695 &black_color,
1696 otg_active_width,
1697 otg_active_height,
1698 0);
1699 hws->funcs.wait_for_blank_complete(bottom_opp);
1700 }
1701 }
1702
1703 if (opp)
1704 hws->funcs.wait_for_blank_complete(opp);
1705 }
1706
1707 /* phantom stream id's can change often, but can be identical between contexts.
1708 * This function checks for the condition the streams are identical to avoid
1709 * redundant pipe transitions.
1710 */
is_subvp_phantom_topology_transition_seamless(const struct dc_state * cur_ctx,const struct dc_state * new_ctx,const struct pipe_ctx * cur_pipe,const struct pipe_ctx * new_pipe)1711 static bool is_subvp_phantom_topology_transition_seamless(
1712 const struct dc_state *cur_ctx,
1713 const struct dc_state *new_ctx,
1714 const struct pipe_ctx *cur_pipe,
1715 const struct pipe_ctx *new_pipe)
1716 {
1717 enum mall_stream_type cur_pipe_type = dc_state_get_pipe_subvp_type(cur_ctx, cur_pipe);
1718 enum mall_stream_type new_pipe_type = dc_state_get_pipe_subvp_type(new_ctx, new_pipe);
1719
1720 const struct dc_stream_state *cur_paired_stream = dc_state_get_paired_subvp_stream(cur_ctx, cur_pipe->stream);
1721 const struct dc_stream_state *new_paired_stream = dc_state_get_paired_subvp_stream(new_ctx, new_pipe->stream);
1722
1723 return cur_pipe_type == SUBVP_PHANTOM &&
1724 cur_pipe_type == new_pipe_type &&
1725 cur_paired_stream && new_paired_stream &&
1726 cur_paired_stream->stream_id == new_paired_stream->stream_id;
1727 }
1728
dcn32_is_pipe_topology_transition_seamless(struct dc * dc,const struct dc_state * cur_ctx,const struct dc_state * new_ctx)1729 bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc,
1730 const struct dc_state *cur_ctx,
1731 const struct dc_state *new_ctx)
1732 {
1733 int i;
1734 const struct pipe_ctx *cur_pipe, *new_pipe;
1735 bool is_seamless = true;
1736
1737 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1738 cur_pipe = &cur_ctx->res_ctx.pipe_ctx[i];
1739 new_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1740
1741 if (resource_is_pipe_type(cur_pipe, FREE_PIPE) ||
1742 resource_is_pipe_type(new_pipe, FREE_PIPE))
1743 /* adding or removing free pipes is always seamless */
1744 continue;
1745 else if (resource_is_pipe_type(cur_pipe, OTG_MASTER)) {
1746 if (resource_is_pipe_type(new_pipe, OTG_MASTER))
1747 if (cur_pipe->stream->stream_id == new_pipe->stream->stream_id ||
1748 is_subvp_phantom_topology_transition_seamless(cur_ctx, new_ctx, cur_pipe, new_pipe))
1749 /* OTG master with the same stream is seamless */
1750 continue;
1751 } else if (resource_is_pipe_type(cur_pipe, OPP_HEAD)) {
1752 if (resource_is_pipe_type(new_pipe, OPP_HEAD)) {
1753 if (cur_pipe->stream_res.tg == new_pipe->stream_res.tg)
1754 /*
1755 * OPP heads sharing the same timing
1756 * generator is seamless
1757 */
1758 continue;
1759 }
1760 } else if (resource_is_pipe_type(cur_pipe, DPP_PIPE)) {
1761 if (resource_is_pipe_type(new_pipe, DPP_PIPE)) {
1762 if (cur_pipe->stream_res.opp == new_pipe->stream_res.opp)
1763 /*
1764 * DPP pipes sharing the same OPP head is
1765 * seamless
1766 */
1767 continue;
1768 }
1769 }
1770
1771 /*
1772 * This pipe's transition doesn't fall under any seamless
1773 * conditions
1774 */
1775 is_seamless = false;
1776 break;
1777 }
1778
1779 return is_seamless;
1780 }
1781
dcn32_prepare_bandwidth(struct dc * dc,struct dc_state * context)1782 void dcn32_prepare_bandwidth(struct dc *dc,
1783 struct dc_state *context)
1784 {
1785 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1786 /* Any transition into an FPO config should disable MCLK switching first to avoid
1787 * driver and FW P-State synchronization issues.
1788 */
1789 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1790 dc->optimized_required = true;
1791 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
1792 }
1793
1794 if (dc->clk_mgr->dc_mode_softmax_enabled)
1795 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
1796 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
1797 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
1798
1799 dcn20_prepare_bandwidth(dc, context);
1800
1801 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
1802 dc_dmub_srv_p_state_delegate(dc, false, context);
1803
1804 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
1805 /* After disabling P-State, restore the original value to ensure we get the correct P-State
1806 * on the next optimize.
1807 */
1808 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
1809 }
1810 }
1811
dcn32_interdependent_update_lock(struct dc * dc,struct dc_state * context,bool lock)1812 void dcn32_interdependent_update_lock(struct dc *dc,
1813 struct dc_state *context, bool lock)
1814 {
1815 unsigned int i;
1816 struct pipe_ctx *pipe;
1817 struct timing_generator *tg;
1818
1819 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1820 pipe = &context->res_ctx.pipe_ctx[i];
1821 tg = pipe->stream_res.tg;
1822
1823 if (!resource_is_pipe_type(pipe, OTG_MASTER) ||
1824 !tg->funcs->is_tg_enabled(tg) ||
1825 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1826 continue;
1827
1828 if (lock)
1829 dc->hwss.pipe_control_lock(dc, pipe, true);
1830 else
1831 dc->hwss.pipe_control_lock(dc, pipe, false);
1832 }
1833 }
1834
dcn32_program_outstanding_updates(struct dc * dc,struct dc_state * context)1835 void dcn32_program_outstanding_updates(struct dc *dc,
1836 struct dc_state *context)
1837 {
1838 struct hubbub *hubbub = dc->res_pool->hubbub;
1839
1840 /* update compbuf if required */
1841 if (hubbub->funcs->program_compbuf_size)
1842 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
1843 }
1844