1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 - 2021 4 * 5 * Richard van Schagen <vschagen@icloud.com> 6 * Christian Marangi <ansuelsmth@gmail.com 7 */ 8 #ifndef REG_EIP93_H 9 #define REG_EIP93_H 10 11 #define EIP93_REG_PE_CTRL_STAT 0x0 12 #define EIP93_PE_CTRL_PE_PAD_CTRL_STAT GENMASK(31, 24) 13 #define EIP93_PE_CTRL_PE_EXT_ERR_CODE GENMASK(23, 20) 14 #define EIP93_PE_CTRL_PE_EXT_ERR_PROCESSING 0x8 15 #define EIP93_PE_CTRL_PE_EXT_ERR_BLOCK_SIZE_ERR 0x7 16 #define EIP93_PE_CTRL_PE_EXT_ERR_INVALID_PK_LENGTH 0x6 17 #define EIP93_PE_CTRL_PE_EXT_ERR_ZERO_LENGTH 0x5 18 #define EIP93_PE_CTRL_PE_EXT_ERR_SPI 0x4 19 #define EIP93_PE_CTRL_PE_EXT_ERR_INVALID_CRYPTO_ALGO 0x3 20 #define EIP93_PE_CTRL_PE_EXT_ERR_INVALID_CRYPTO_OP 0x2 21 #define EIP93_PE_CTRL_PE_EXT_ERR_DESC_OWNER 0x1 22 #define EIP93_PE_CTRL_PE_EXT_ERR_BUS 0x0 23 #define EIP93_PE_CTRL_PE_EXT_ERR BIT(19) 24 #define EIP93_PE_CTRL_PE_SEQNUM_ERR BIT(18) 25 #define EIP93_PE_CTRL_PE_PAD_ERR BIT(17) 26 #define EIP93_PE_CTRL_PE_AUTH_ERR BIT(16) 27 #define EIP93_PE_CTRL_PE_PAD_VALUE GENMASK(15, 8) 28 #define EIP93_PE_CTRL_PE_PRNG_MODE GENMASK(7, 6) 29 #define EIP93_PE_CTRL_PE_HASH_FINAL BIT(4) 30 #define EIP93_PE_CTRL_PE_INIT_ARC4 BIT(3) 31 #define EIP93_PE_CTRL_PE_READY_DES_TRING_OWN GENMASK(1, 0) 32 #define EIP93_PE_CTRL_PE_READY 0x2 33 #define EIP93_PE_CTRL_HOST_READY 0x1 34 #define EIP93_REG_PE_SOURCE_ADDR 0x4 35 #define EIP93_REG_PE_DEST_ADDR 0x8 36 #define EIP93_REG_PE_SA_ADDR 0xc 37 #define EIP93_REG_PE_ADDR 0x10 /* STATE_ADDR */ 38 /* 39 * Special implementation for user ID 40 * user_id in eip93_descriptor is used to identify the 41 * descriptor and is opaque and can be used by the driver 42 * in custom way. 43 * 44 * The usage of this should be to put an address to the crypto 45 * request struct from the kernel but this can't work in 64bit 46 * world. 47 * 48 * Also it's required to put some flags to identify the last 49 * descriptor. 50 * 51 * To handle this, split the u32 in 2 part: 52 * - 31:16 descriptor flags 53 * - 15:0 IDR to connect the crypto request address 54 */ 55 #define EIP93_REG_PE_USER_ID 0x18 56 #define EIP93_PE_USER_ID_DESC_FLAGS GENMASK(31, 16) 57 #define EIP93_PE_USER_ID_CRYPTO_IDR GENMASK(15, 0) 58 #define EIP93_REG_PE_LENGTH 0x1c 59 #define EIP93_PE_LENGTH_BYPASS GENMASK(31, 24) 60 #define EIP93_PE_LENGTH_HOST_PE_READY GENMASK(23, 22) 61 #define EIP93_PE_LENGTH_PE_READY 0x2 62 #define EIP93_PE_LENGTH_HOST_READY 0x1 63 #define EIP93_PE_LENGTH_LENGTH GENMASK(19, 0) 64 65 /* PACKET ENGINE RING configuration registers */ 66 #define EIP93_REG_PE_CDR_BASE 0x80 67 #define EIP93_REG_PE_RDR_BASE 0x84 68 #define EIP93_REG_PE_RING_CONFIG 0x88 69 #define EIP93_PE_EN_EXT_TRIG BIT(31) 70 /* Absent in later revision of eip93 */ 71 /* #define EIP93_PE_RING_OFFSET GENMASK(23, 15) */ 72 #define EIP93_PE_RING_SIZE GENMASK(9, 0) 73 #define EIP93_REG_PE_RING_THRESH 0x8c 74 #define EIPR93_PE_TIMEROUT_EN BIT(31) 75 #define EIPR93_PE_RD_TIMEOUT GENMASK(29, 26) 76 #define EIPR93_PE_RDR_THRESH GENMASK(25, 16) 77 #define EIPR93_PE_CDR_THRESH GENMASK(9, 0) 78 #define EIP93_REG_PE_CD_COUNT 0x90 79 #define EIP93_PE_CD_COUNT GENMASK(10, 0) 80 /* 81 * In the same register, writing a value in GENMASK(7, 0) will 82 * increment the descriptor count and start DMA action. 83 */ 84 #define EIP93_PE_CD_COUNT_INCR GENMASK(7, 0) 85 #define EIP93_REG_PE_RD_COUNT 0x94 86 #define EIP93_PE_RD_COUNT GENMASK(10, 0) 87 /* 88 * In the same register, writing a value in GENMASK(7, 0) will 89 * increment the descriptor count and start DMA action. 90 */ 91 #define EIP93_PE_RD_COUNT_INCR GENMASK(7, 0) 92 #define EIP93_REG_PE_RING_RW_PNTR 0x98 /* RING_PNTR */ 93 94 /* PACKET ENGINE configuration registers */ 95 #define EIP93_REG_PE_CONFIG 0x100 96 #define EIP93_PE_CONFIG_SWAP_TARGET BIT(20) 97 #define EIP93_PE_CONFIG_SWAP_DATA BIT(18) 98 #define EIP93_PE_CONFIG_SWAP_SA BIT(17) 99 #define EIP93_PE_CONFIG_SWAP_CDRD BIT(16) 100 #define EIP93_PE_CONFIG_EN_CDR_UPDATE BIT(10) 101 #define EIP93_PE_CONFIG_PE_MODE GENMASK(9, 8) 102 #define EIP93_PE_TARGET_AUTO_RING_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x3) 103 #define EIP93_PE_TARGET_COMMAND_NO_RDR_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x2) 104 #define EIP93_PE_TARGET_COMMAND_WITH_RDR_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x1) 105 #define EIP93_PE_DIRECT_HOST_MODE FIELD_PREP(EIP93_PE_CONFIG_PE_MODE, 0x0) 106 #define EIP93_PE_CONFIG_RST_RING BIT(2) 107 #define EIP93_PE_CONFIG_RST_PE BIT(0) 108 #define EIP93_REG_PE_STATUS 0x104 109 #define EIP93_REG_PE_BUF_THRESH 0x10c 110 #define EIP93_PE_OUTBUF_THRESH GENMASK(23, 16) 111 #define EIP93_PE_INBUF_THRESH GENMASK(7, 0) 112 #define EIP93_REG_PE_INBUF_COUNT 0x100 113 #define EIP93_REG_PE_OUTBUF_COUNT 0x114 114 #define EIP93_REG_PE_BUF_RW_PNTR 0x118 /* BUF_PNTR */ 115 116 /* PACKET ENGINE endian config */ 117 #define EIP93_REG_PE_ENDIAN_CONFIG 0x1cc 118 #define EIP93_AIROHA_REG_PE_ENDIAN_CONFIG 0x1d0 119 #define EIP93_PE_ENDIAN_TARGET_BYTE_SWAP GENMASK(23, 16) 120 #define EIP93_PE_ENDIAN_MASTER_BYTE_SWAP GENMASK(7, 0) 121 /* 122 * Byte goes 2 and 2 and are referenced by ID 123 * Split GENMASK(7, 0) in 4 part, one for each byte. 124 * Example LITTLE ENDIAN: Example BIG ENDIAN 125 * GENMASK(7, 6) 0x3 GENMASK(7, 6) 0x0 126 * GENMASK(5, 4) 0x2 GENMASK(7, 6) 0x1 127 * GENMASK(3, 2) 0x1 GENMASK(3, 2) 0x2 128 * GENMASK(1, 0) 0x0 GENMASK(1, 0) 0x3 129 */ 130 #define EIP93_PE_ENDIAN_BYTE0 0x0 131 #define EIP93_PE_ENDIAN_BYTE1 0x1 132 #define EIP93_PE_ENDIAN_BYTE2 0x2 133 #define EIP93_PE_ENDIAN_BYTE3 0x3 134 135 /* EIP93 CLOCK control registers */ 136 #define EIP93_REG_PE_CLOCK_CTRL 0x1e8 137 #define EIP93_PE_CLOCK_EN_HASH_CLK BIT(4) 138 #define EIP93_PE_CLOCK_EN_ARC4_CLK BIT(3) 139 #define EIP93_PE_CLOCK_EN_AES_CLK BIT(2) 140 #define EIP93_PE_CLOCK_EN_DES_CLK BIT(1) 141 #define EIP93_PE_CLOCK_EN_PE_CLK BIT(0) 142 143 /* EIP93 Device Option and Revision Register */ 144 #define EIP93_REG_PE_OPTION_1 0x1f4 145 #define EIP93_PE_OPTION_MAC_KEY256 BIT(31) 146 #define EIP93_PE_OPTION_MAC_KEY192 BIT(30) 147 #define EIP93_PE_OPTION_MAC_KEY128 BIT(29) 148 #define EIP93_PE_OPTION_AES_CBC_MAC BIT(28) 149 #define EIP93_PE_OPTION_AES_XCBX BIT(23) 150 #define EIP93_PE_OPTION_SHA_256 BIT(19) 151 #define EIP93_PE_OPTION_SHA_224 BIT(18) 152 #define EIP93_PE_OPTION_SHA_1 BIT(17) 153 #define EIP93_PE_OPTION_MD5 BIT(16) 154 #define EIP93_PE_OPTION_AES_KEY256 BIT(15) 155 #define EIP93_PE_OPTION_AES_KEY192 BIT(14) 156 #define EIP93_PE_OPTION_AES_KEY128 BIT(13) 157 #define EIP93_PE_OPTION_AES BIT(2) 158 #define EIP93_PE_OPTION_ARC4 BIT(1) 159 #define EIP93_PE_OPTION_TDES BIT(0) /* DES and TDES */ 160 #define EIP93_REG_PE_OPTION_0 0x1f8 161 #define EIP93_REG_PE_REVISION 0x1fc 162 #define EIP93_PE_REVISION_MAJ_HW_REV GENMASK(27, 24) 163 #define EIP93_PE_REVISION_MIN_HW_REV GENMASK(23, 20) 164 #define EIP93_PE_REVISION_HW_PATCH GENMASK(19, 16) 165 #define EIP93_PE_REVISION_EIP_NO GENMASK(7, 0) 166 167 /* EIP93 Interrupt Control Register */ 168 #define EIP93_REG_INT_UNMASK_STAT 0x200 169 #define EIP93_REG_INT_MASK_STAT 0x204 170 #define EIP93_REG_INT_CLR 0x204 171 #define EIP93_REG_INT_MASK 0x208 /* INT_EN */ 172 /* Each int reg have the same bitmap */ 173 #define EIP93_INT_INTERFACE_ERR BIT(18) 174 #define EIP93_INT_RPOC_ERR BIT(17) 175 #define EIP93_INT_PE_RING_ERR BIT(16) 176 #define EIP93_INT_HALT BIT(15) 177 #define EIP93_INT_OUTBUF_THRESH BIT(11) 178 #define EIP93_INT_INBUF_THRESH BIT(10) 179 #define EIP93_INT_OPERATION_DONE BIT(9) 180 #define EIP93_INT_RDR_THRESH BIT(1) 181 #define EIP93_INT_CDR_THRESH BIT(0) 182 #define EIP93_INT_ALL (EIP93_INT_INTERFACE_ERR | \ 183 EIP93_INT_RPOC_ERR | \ 184 EIP93_INT_PE_RING_ERR | \ 185 EIP93_INT_HALT | \ 186 EIP93_INT_OUTBUF_THRESH | \ 187 EIP93_INT_INBUF_THRESH | \ 188 EIP93_INT_OPERATION_DONE | \ 189 EIP93_INT_RDR_THRESH | \ 190 EIP93_INT_CDR_THRESH) 191 192 #define EIP93_REG_INT_CFG 0x20c 193 #define EIP93_INT_TYPE_PULSE BIT(0) 194 #define EIP93_REG_MASK_ENABLE 0x210 195 #define EIP93_REG_MASK_DISABLE 0x214 196 197 /* EIP93 SA Record register */ 198 #define EIP93_REG_SA_CMD_0 0x400 199 #define EIP93_SA_CMD_SAVE_HASH BIT(29) 200 #define EIP93_SA_CMD_SAVE_IV BIT(28) 201 #define EIP93_SA_CMD_HASH_SOURCE GENMASK(27, 26) 202 #define EIP93_SA_CMD_HASH_NO_LOAD FIELD_PREP(EIP93_SA_CMD_HASH_SOURCE, 0x3) 203 #define EIP93_SA_CMD_HASH_FROM_STATE FIELD_PREP(EIP93_SA_CMD_HASH_SOURCE, 0x2) 204 #define EIP93_SA_CMD_HASH_FROM_SA FIELD_PREP(EIP93_SA_CMD_HASH_SOURCE, 0x0) 205 #define EIP93_SA_CMD_IV_SOURCE GENMASK(25, 24) 206 #define EIP93_SA_CMD_IV_FROM_PRNG FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x3) 207 #define EIP93_SA_CMD_IV_FROM_STATE FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x2) 208 #define EIP93_SA_CMD_IV_FROM_INPUT FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x1) 209 #define EIP93_SA_CMD_IV_NO_LOAD FIELD_PREP(EIP93_SA_CMD_IV_SOURCE, 0x0) 210 #define EIP93_SA_CMD_DIGEST_LENGTH GENMASK(23, 20) 211 #define EIP93_SA_CMD_DIGEST_10WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0xa) /* SRTP and TLS */ 212 #define EIP93_SA_CMD_DIGEST_8WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x8) /* SHA-256 */ 213 #define EIP93_SA_CMD_DIGEST_7WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x7) /* SHA-224 */ 214 #define EIP93_SA_CMD_DIGEST_6WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x6) 215 #define EIP93_SA_CMD_DIGEST_5WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x5) /* SHA1 */ 216 #define EIP93_SA_CMD_DIGEST_4WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x4) /* MD5 and AES-based */ 217 #define EIP93_SA_CMD_DIGEST_3WORD_IPSEC FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x3) /* IPSEC */ 218 #define EIP93_SA_CMD_DIGEST_2WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x2) 219 #define EIP93_SA_CMD_DIGEST_1WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x1) 220 #define EIP93_SA_CMD_DIGEST_3WORD FIELD_PREP(EIP93_SA_CMD_DIGEST_LENGTH, 0x0) /* 96bit output */ 221 #define EIP93_SA_CMD_HDR_PROC BIT(19) 222 #define EIP93_SA_CMD_EXT_PAD BIT(18) 223 #define EIP93_SA_CMD_SCPAD BIT(17) 224 #define EIP93_SA_CMD_HASH GENMASK(15, 12) 225 #define EIP93_SA_CMD_HASH_NULL FIELD_PREP(EIP93_SA_CMD_HASH, 0xf) 226 #define EIP93_SA_CMD_HASH_SHA256 FIELD_PREP(EIP93_SA_CMD_HASH, 0x3) 227 #define EIP93_SA_CMD_HASH_SHA224 FIELD_PREP(EIP93_SA_CMD_HASH, 0x2) 228 #define EIP93_SA_CMD_HASH_SHA1 FIELD_PREP(EIP93_SA_CMD_HASH, 0x1) 229 #define EIP93_SA_CMD_HASH_MD5 FIELD_PREP(EIP93_SA_CMD_HASH, 0x0) 230 #define EIP93_SA_CMD_CIPHER GENMASK(11, 8) 231 #define EIP93_SA_CMD_CIPHER_NULL FIELD_PREP(EIP93_SA_CMD_CIPHER, 0xf) 232 #define EIP93_SA_CMD_CIPHER_AES FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x3) 233 #define EIP93_SA_CMD_CIPHER_ARC4 FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x2) 234 #define EIP93_SA_CMD_CIPHER_3DES FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x1) 235 #define EIP93_SA_CMD_CIPHER_DES FIELD_PREP(EIP93_SA_CMD_CIPHER, 0x0) 236 #define EIP93_SA_CMD_PAD_TYPE GENMASK(7, 6) 237 #define EIP93_SA_CMD_PAD_CONST_SSL FIELD_PREP(EIP93_SA_CMD_PAD_TYPE, 0x6) 238 #define EIP93_SA_CMD_PAD_TLS_DTLS FIELD_PREP(EIP93_SA_CMD_PAD_TYPE, 0x5) 239 #define EIP93_SA_CMD_PAD_ZERO FIELD_PREP(EIP93_SA_CMD_PAD_TYPE, 0x3) 240 #define EIP93_SA_CMD_PAD_CONST FIELD_PREP(EIP93_SA_CMD_PAD_TYPE, 0x2) 241 #define EIP93_SA_CMD_PAD_PKCS7 FIELD_PREP(EIP93_SA_CMD_PAD_TYPE, 0x1) 242 #define EIP93_SA_CMD_PAD_IPSEC FIELD_PREP(EIP93_SA_CMD_PAD_TYPE, 0x0) 243 #define EIP93_SA_CMD_OPGROUP GENMASK(5, 4) 244 #define EIP93_SA_CMD_OP_EXT FIELD_PREP(EIP93_SA_CMD_OPGROUP, 0x2) 245 #define EIP93_SA_CMD_OP_PROTOCOL FIELD_PREP(EIP93_SA_CMD_OPGROUP, 0x1) 246 #define EIP93_SA_CMD_OP_BASIC FIELD_PREP(EIP93_SA_CMD_OPGROUP, 0x0) 247 #define EIP93_SA_CMD_DIRECTION_IN BIT(3) /* 0: outbount 1: inbound */ 248 #define EIP93_SA_CMD_OPCODE GENMASK(2, 0) 249 #define EIP93_SA_CMD_OPCODE_BASIC_OUT_PRNG 0x7 250 #define EIP93_SA_CMD_OPCODE_BASIC_OUT_HASH 0x3 251 #define EIP93_SA_CMD_OPCODE_BASIC_OUT_ENC_HASH 0x1 252 #define EIP93_SA_CMD_OPCODE_BASIC_OUT_ENC 0x0 253 #define EIP93_SA_CMD_OPCODE_BASIC_IN_HASH 0x3 254 #define EIP93_SA_CMD_OPCODE_BASIC_IN_HASH_DEC 0x1 255 #define EIP93_SA_CMD_OPCODE_BASIC_IN_DEC 0x0 256 #define EIP93_SA_CMD_OPCODE_PROTOCOL_OUT_ESP 0x0 257 #define EIP93_SA_CMD_OPCODE_PROTOCOL_OUT_SSL 0x4 258 #define EIP93_SA_CMD_OPCODE_PROTOCOL_OUT_TLS 0x5 259 #define EIP93_SA_CMD_OPCODE_PROTOCOL_OUT_SRTP 0x7 260 #define EIP93_SA_CMD_OPCODE_PROTOCOL_IN_ESP 0x0 261 #define EIP93_SA_CMD_OPCODE_PROTOCOL_IN_SSL 0x2 262 #define EIP93_SA_CMD_OPCODE_PROTOCOL_IN_TLS 0x3 263 #define EIP93_SA_CMD_OPCODE_PROTOCOL_IN_SRTP 0x7 264 #define EIP93_SA_CMD_OPCODE_EXT_OUT_DTSL 0x1 265 #define EIP93_SA_CMD_OPCODE_EXT_OUT_SSL 0x4 266 #define EIP93_SA_CMD_OPCODE_EXT_OUT_TLSV10 0x5 267 #define EIP93_SA_CMD_OPCODE_EXT_OUT_TLSV11 0x6 268 #define EIP93_SA_CMD_OPCODE_EXT_IN_DTSL 0x1 269 #define EIP93_SA_CMD_OPCODE_EXT_IN_SSL 0x4 270 #define EIP93_SA_CMD_OPCODE_EXT_IN_TLSV10 0x5 271 #define EIP93_SA_CMD_OPCODE_EXT_IN_TLSV11 0x6 272 #define EIP93_REG_SA_CMD_1 0x404 273 #define EIP93_SA_CMD_EN_SEQNUM_CHK BIT(29) 274 /* This mask can be either used for ARC4 or AES */ 275 #define EIP93_SA_CMD_ARC4_KEY_LENGHT GENMASK(28, 24) 276 #define EIP93_SA_CMD_AES_DEC_KEY BIT(28) /* 0: encrypt key 1: decrypt key */ 277 #define EIP93_SA_CMD_AES_KEY_LENGTH GENMASK(26, 24) 278 #define EIP93_SA_CMD_AES_KEY_256BIT FIELD_PREP(EIP93_SA_CMD_AES_KEY_LENGTH, 0x4) 279 #define EIP93_SA_CMD_AES_KEY_192BIT FIELD_PREP(EIP93_SA_CMD_AES_KEY_LENGTH, 0x3) 280 #define EIP93_SA_CMD_AES_KEY_128BIT FIELD_PREP(EIP93_SA_CMD_AES_KEY_LENGTH, 0x2) 281 #define EIP93_SA_CMD_HASH_CRYPT_OFFSET GENMASK(23, 16) 282 #define EIP93_SA_CMD_BYTE_OFFSET BIT(13) /* 0: CRYPT_OFFSET in 32bit word 1: CRYPT_OFFSET in 8bit bytes */ 283 #define EIP93_SA_CMD_HMAC BIT(12) 284 #define EIP93_SA_CMD_SSL_MAC BIT(12) 285 /* This mask can be either used for ARC4 or AES */ 286 #define EIP93_SA_CMD_CHIPER_MODE GENMASK(9, 8) 287 /* AES or DES operations */ 288 #define EIP93_SA_CMD_CHIPER_MODE_ICM FIELD_PREP(EIP93_SA_CMD_CHIPER_MODE, 0x3) 289 #define EIP93_SA_CMD_CHIPER_MODE_CTR FIELD_PREP(EIP93_SA_CMD_CHIPER_MODE, 0x2) 290 #define EIP93_SA_CMD_CHIPER_MODE_CBC FIELD_PREP(EIP93_SA_CMD_CHIPER_MODE, 0x1) 291 #define EIP93_SA_CMD_CHIPER_MODE_ECB FIELD_PREP(EIP93_SA_CMD_CHIPER_MODE, 0x0) 292 /* ARC4 operations */ 293 #define EIP93_SA_CMD_CHIPER_MODE_STATEFULL FIELD_PREP(EIP93_SA_CMD_CHIPER_MODE, 0x1) 294 #define EIP93_SA_CMD_CHIPER_MODE_STATELESS FIELD_PREP(EIP93_SA_CMD_CHIPER_MODE, 0x0) 295 #define EIP93_SA_CMD_COPY_PAD BIT(3) 296 #define EIP93_SA_CMD_COPY_PAYLOAD BIT(2) 297 #define EIP93_SA_CMD_COPY_HEADER BIT(1) 298 #define EIP93_SA_CMD_COPY_DIGEST BIT(0) /* With this enabled, COPY_PAD is required */ 299 300 /* State save register */ 301 #define EIP93_REG_STATE_IV_0 0x500 302 #define EIP93_REG_STATE_IV_1 0x504 303 304 #define EIP93_REG_PE_ARC4STATE 0x700 305 306 struct sa_record { 307 u32 sa_cmd0_word; 308 u32 sa_cmd1_word; 309 u32 sa_key[8]; 310 u8 sa_i_digest[32]; 311 u8 sa_o_digest[32]; 312 u32 sa_spi; 313 u32 sa_seqnum[2]; 314 u32 sa_seqmum_mask[2]; 315 u32 sa_nonce; 316 } __packed; 317 318 struct sa_state { 319 u32 state_iv[4]; 320 u32 state_byte_cnt[2]; 321 u8 state_i_digest[32]; 322 } __packed; 323 324 struct eip93_descriptor { 325 u32 pe_ctrl_stat_word; 326 u32 src_addr; 327 u32 dst_addr; 328 u32 sa_addr; 329 u32 state_addr; 330 u32 arc4_addr; 331 u32 user_id; 332 u32 pe_length_word; 333 } __packed; 334 335 #endif 336