1 /* linux/arch/arm/mach-s3c2412/s3c2412.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/serial_core.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
30
31 #include <mach/hardware.h>
32 #include <asm/proc-fns.h>
33 #include <asm/irq.h>
34
35 #include <mach/idle.h>
36
37 #include <plat/cpu-freq.h>
38
39 #include <mach/regs-clock.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-power.h>
42 #include <mach/regs-gpio.h>
43 #include <mach/regs-gpioj.h>
44 #include <mach/regs-dsc.h>
45 #include <plat/regs-spi.h>
46 #include <mach/regs-s3c2412.h>
47
48 #include <plat/s3c2412.h>
49 #include <plat/cpu.h>
50 #include <plat/devs.h>
51 #include <plat/clock.h>
52 #include <plat/pm.h>
53 #include <plat/pll.h>
54 #include <plat/nand-core.h>
55
56 #ifndef CONFIG_CPU_S3C2412_ONLY
57 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
58
s3c2412_init_gpio2(void)59 static inline void s3c2412_init_gpio2(void)
60 {
61 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
62 }
63 #else
64 #define s3c2412_init_gpio2() do { } while(0)
65 #endif
66
67 /* Initial IO mappings */
68
69 static struct map_desc s3c2412_iodesc[] __initdata = {
70 IODESC_ENT(CLKPWR),
71 IODESC_ENT(TIMER),
72 IODESC_ENT(WATCHDOG),
73 {
74 .virtual = (unsigned long)S3C2412_VA_SSMC,
75 .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
76 .length = SZ_1M,
77 .type = MT_DEVICE,
78 },
79 {
80 .virtual = (unsigned long)S3C2412_VA_EBI,
81 .pfn = __phys_to_pfn(S3C2412_PA_EBI),
82 .length = SZ_1M,
83 .type = MT_DEVICE,
84 },
85 };
86
87 /* uart registration process */
88
s3c2412_init_uarts(struct s3c2410_uartcfg * cfg,int no)89 void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
90 {
91 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
92
93 /* rename devices that are s3c2412/s3c2413 specific */
94 s3c_device_sdi.name = "s3c2412-sdi";
95 s3c_device_lcd.name = "s3c2412-lcd";
96 s3c_nand_setname("s3c2412-nand");
97
98 /* alter IRQ of SDI controller */
99
100 s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
101 s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
102
103 /* spi channel related changes, s3c2412/13 specific */
104 s3c_device_spi0.name = "s3c2412-spi";
105 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
106 s3c_device_spi1.name = "s3c2412-spi";
107 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
108 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
109
110 }
111
112 /* s3c2412_idle
113 *
114 * use the standard idle call by ensuring the idle mode
115 * in power config, then issuing the idle co-processor
116 * instruction
117 */
118
s3c2412_idle(void)119 static void s3c2412_idle(void)
120 {
121 unsigned long tmp;
122
123 /* ensure our idle mode is to go to idle */
124
125 tmp = __raw_readl(S3C2412_PWRCFG);
126 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
127 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
128 __raw_writel(tmp, S3C2412_PWRCFG);
129
130 cpu_do_idle();
131 }
132
s3c2412_restart(char mode,const char * cmd)133 void s3c2412_restart(char mode, const char *cmd)
134 {
135 if (mode == 's')
136 soft_restart(0);
137
138 /* errata "Watch-dog/Software Reset Problem" specifies that
139 * this reset must be done with the SYSCLK sourced from
140 * EXTCLK instead of FOUT to avoid a glitch in the reset
141 * mechanism.
142 *
143 * See the watchdog section of the S3C2412 manual for more
144 * information on this fix.
145 */
146
147 __raw_writel(0x00, S3C2412_CLKSRC);
148 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
149
150 mdelay(1);
151 }
152
153 /* s3c2412_map_io
154 *
155 * register the standard cpu IO areas, and any passed in from the
156 * machine specific initialisation.
157 */
158
s3c2412_map_io(void)159 void __init s3c2412_map_io(void)
160 {
161 /* move base of IO */
162
163 s3c2412_init_gpio2();
164
165 /* set our idle function */
166
167 s3c24xx_idle = s3c2412_idle;
168
169 /* register our io-tables */
170
171 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
172 }
173
s3c2412_setup_clocks(void)174 void __init_or_cpufreq s3c2412_setup_clocks(void)
175 {
176 struct clk *xtal_clk;
177 unsigned long tmp;
178 unsigned long xtal;
179 unsigned long fclk;
180 unsigned long hclk;
181 unsigned long pclk;
182
183 xtal_clk = clk_get(NULL, "xtal");
184 xtal = clk_get_rate(xtal_clk);
185 clk_put(xtal_clk);
186
187 /* now we've got our machine bits initialised, work out what
188 * clocks we've got */
189
190 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
191
192 clk_mpll.rate = fclk;
193
194 tmp = __raw_readl(S3C2410_CLKDIVN);
195
196 /* work out clock scalings */
197
198 hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
199 hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
200 pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
201
202 /* print brieft summary of clocks, etc */
203
204 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
205 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
206
207 s3c24xx_setup_clocks(fclk, hclk, pclk);
208 }
209
s3c2412_init_clocks(int xtal)210 void __init s3c2412_init_clocks(int xtal)
211 {
212 /* initialise the clocks here, to allow other things like the
213 * console to use them
214 */
215
216 s3c24xx_register_baseclocks(xtal);
217 s3c2412_setup_clocks();
218 s3c2412_baseclk_add();
219 }
220
221 /* need to register the subsystem before we actually register the device, and
222 * we also need to ensure that it has been initialised before any of the
223 * drivers even try to use it (even if not on an s3c2412 based system)
224 * as a driver which may support both 2410 and 2440 may try and use it.
225 */
226
227 struct bus_type s3c2412_subsys = {
228 .name = "s3c2412-core",
229 .dev_name = "s3c2412-core",
230 };
231
s3c2412_core_init(void)232 static int __init s3c2412_core_init(void)
233 {
234 return subsys_system_register(&s3c2412_subsys, NULL);
235 }
236
237 core_initcall(s3c2412_core_init);
238
239 static struct device s3c2412_dev = {
240 .bus = &s3c2412_subsys,
241 };
242
s3c2412_init(void)243 int __init s3c2412_init(void)
244 {
245 printk("S3C2412: Initialising architecture\n");
246
247 #ifdef CONFIG_PM
248 register_syscore_ops(&s3c2412_pm_syscore_ops);
249 #endif
250 register_syscore_ops(&s3c24xx_irq_syscore_ops);
251
252 return device_register(&s3c2412_dev);
253 }
254