1 /*
2 * QEMU S/390 CPU
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2011 Alexander Graf
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2012 IBM Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "cpu.h"
26 #include "s390x-internal.h"
27 #include "kvm/kvm_s390x.h"
28 #include "system/kvm.h"
29 #include "qemu/module.h"
30 #include "trace.h"
31 #include "qapi/qapi-types-machine.h"
32 #include "system/hw_accel.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
35 #include "hw/resettable.h"
36 #include "fpu/softfloat-helpers.h"
37 #include "disas/capstone.h"
38 #include "system/tcg.h"
39 #ifndef CONFIG_USER_ONLY
40 #include "system/reset.h"
41 #endif
42 #include "hw/s390x/cpu-topology.h"
43
44 #define CR0_RESET 0xE0UL
45 #define CR14_RESET 0xC2000000UL;
46
47 #ifndef CONFIG_USER_ONLY
is_early_exception_psw(uint64_t mask,uint64_t addr)48 static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
49 {
50 if (mask & PSW_MASK_RESERVED) {
51 return true;
52 }
53
54 switch (mask & (PSW_MASK_32 | PSW_MASK_64)) {
55 case 0:
56 return addr & ~0xffffffULL;
57 case PSW_MASK_32:
58 return addr & ~0x7fffffffULL;
59 case PSW_MASK_32 | PSW_MASK_64:
60 return false;
61 default: /* PSW_MASK_64 */
62 return true;
63 }
64 }
65 #endif
66
s390_cpu_set_psw(CPUS390XState * env,uint64_t mask,uint64_t addr)67 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
68 {
69 #ifndef CONFIG_USER_ONLY
70 uint64_t old_mask = env->psw.mask;
71 #endif
72
73 env->psw.addr = addr;
74 env->psw.mask = mask;
75
76 /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */
77 if (!tcg_enabled()) {
78 return;
79 }
80 env->cc_op = (mask >> 44) & 3;
81
82 #ifndef CONFIG_USER_ONLY
83 if (is_early_exception_psw(mask, addr)) {
84 env->int_pgm_ilen = 0;
85 trigger_pgm_exception(env, PGM_SPECIFICATION);
86 return;
87 }
88
89 if ((old_mask ^ mask) & PSW_MASK_PER) {
90 s390_cpu_recompute_watchpoints(env_cpu(env));
91 }
92
93 if (mask & PSW_MASK_WAIT) {
94 s390_handle_wait(env_archcpu(env));
95 }
96 #endif
97 }
98
s390_cpu_get_psw_mask(CPUS390XState * env)99 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env)
100 {
101 uint64_t r = env->psw.mask;
102
103 if (tcg_enabled()) {
104 uint64_t cc = calc_cc(env, env->cc_op, env->cc_src,
105 env->cc_dst, env->cc_vr);
106
107 assert(cc <= 3);
108 r &= ~PSW_MASK_CC;
109 r |= cc << 44;
110 }
111
112 return r;
113 }
114
s390_cpu_set_pc(CPUState * cs,vaddr value)115 static void s390_cpu_set_pc(CPUState *cs, vaddr value)
116 {
117 S390CPU *cpu = S390_CPU(cs);
118
119 cpu->env.psw.addr = value;
120 }
121
s390_cpu_get_pc(CPUState * cs)122 static vaddr s390_cpu_get_pc(CPUState *cs)
123 {
124 S390CPU *cpu = S390_CPU(cs);
125
126 return cpu->env.psw.addr;
127 }
128
s390_query_cpu_fast(CPUState * cpu,CpuInfoFast * value)129 static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value)
130 {
131 S390CPU *s390_cpu = S390_CPU(cpu);
132
133 value->u.s390x.cpu_state = s390_cpu->env.cpu_state;
134 #if !defined(CONFIG_USER_ONLY)
135 if (s390_has_topology()) {
136 value->u.s390x.has_dedicated = true;
137 value->u.s390x.dedicated = s390_cpu->env.dedicated;
138 value->u.s390x.has_entitlement = true;
139 value->u.s390x.entitlement = s390_cpu->env.entitlement;
140 }
141 #endif
142 }
143
144 /* S390CPUClass Resettable reset_hold phase method */
s390_cpu_reset_hold(Object * obj,ResetType type)145 static void s390_cpu_reset_hold(Object *obj, ResetType type)
146 {
147 S390CPU *cpu = S390_CPU(obj);
148 S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
149 CPUS390XState *env = &cpu->env;
150
151 if (scc->parent_phases.hold) {
152 scc->parent_phases.hold(obj, type);
153 }
154 cpu->env.sigp_order = 0;
155 s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);
156
157 switch (type) {
158 default:
159 /* RESET_TYPE_COLD: power on or "clear" reset */
160 memset(env, 0, offsetof(CPUS390XState, start_initial_reset_fields));
161 /* fall through */
162 case RESET_TYPE_S390_CPU_INITIAL:
163 /* initial reset does not clear everything! */
164 memset(&env->start_initial_reset_fields, 0,
165 offsetof(CPUS390XState, start_normal_reset_fields) -
166 offsetof(CPUS390XState, start_initial_reset_fields));
167
168 /* architectured initial value for Breaking-Event-Address register */
169 env->gbea = 1;
170
171 /* architectured initial values for CR 0 and 14 */
172 env->cregs[0] = CR0_RESET;
173 env->cregs[14] = CR14_RESET;
174
175 #if defined(CONFIG_USER_ONLY)
176 /* user mode should always be allowed to use the full FPU */
177 env->cregs[0] |= CR0_AFP;
178 if (s390_has_feat(S390_FEAT_VECTOR)) {
179 env->cregs[0] |= CR0_VECTOR;
180 }
181 #endif
182
183 /* tininess for underflow is detected before rounding */
184 set_float_detect_tininess(float_tininess_before_rounding,
185 &env->fpu_status);
186 set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
187 set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
188 set_float_infzeronan_rule(float_infzeronan_dnan_always,
189 &env->fpu_status);
190 /* Default NaN value: sign bit clear, frac msb set */
191 set_float_default_nan_pattern(0b01000000, &env->fpu_status);
192 /* fall through */
193 case RESET_TYPE_S390_CPU_NORMAL:
194 env->psw.mask &= ~PSW_MASK_RI;
195 memset(&env->start_normal_reset_fields, 0,
196 offsetof(CPUS390XState, end_reset_fields) -
197 offsetof(CPUS390XState, start_normal_reset_fields));
198
199 env->pfault_token = -1UL;
200 env->bpbc = false;
201 break;
202 }
203
204 /* Reset state inside the kernel that we cannot access yet from QEMU. */
205 if (kvm_enabled()) {
206 switch (type) {
207 default:
208 kvm_s390_reset_vcpu_clear(cpu);
209 break;
210 case RESET_TYPE_S390_CPU_INITIAL:
211 kvm_s390_reset_vcpu_initial(cpu);
212 break;
213 case RESET_TYPE_S390_CPU_NORMAL:
214 kvm_s390_reset_vcpu_normal(cpu);
215 break;
216 }
217 }
218 }
219
s390_cpu_disas_set_info(CPUState * cpu,disassemble_info * info)220 static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
221 {
222 info->mach = bfd_mach_s390_64;
223 info->cap_arch = CS_ARCH_SYSZ;
224 info->endian = BFD_ENDIAN_BIG;
225 info->cap_insn_unit = 2;
226 info->cap_insn_split = 6;
227 }
228
s390_cpu_realizefn(DeviceState * dev,Error ** errp)229 static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
230 {
231 CPUState *cs = CPU(dev);
232 S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
233 Error *err = NULL;
234
235 /* the model has to be realized before qemu_init_vcpu() due to kvm */
236 s390_realize_cpu_model(cs, &err);
237 if (err) {
238 goto out;
239 }
240
241 #if !defined(CONFIG_USER_ONLY)
242 if (!s390_cpu_system_realize(dev, &err)) {
243 goto out;
244 }
245 #endif
246
247 cpu_exec_realizefn(cs, &err);
248 if (err != NULL) {
249 goto out;
250 }
251
252 #if !defined(CONFIG_USER_ONLY)
253 qemu_register_reset(s390_cpu_machine_reset_cb, S390_CPU(dev));
254 #endif
255 s390_cpu_gdb_init(cs);
256 qemu_init_vcpu(cs);
257
258 /*
259 * KVM requires the initial CPU reset ioctl to be executed on the target
260 * CPU thread. CPU hotplug under single-threaded TCG will not work with
261 * run_on_cpu(), as run_on_cpu() will not work properly if called while
262 * the main thread is already running but the CPU hasn't been realized.
263 */
264 if (kvm_enabled()) {
265 run_on_cpu(cs, s390_do_cpu_full_reset, RUN_ON_CPU_NULL);
266 } else {
267 cpu_reset(cs);
268 }
269
270 scc->parent_realize(dev, &err);
271 out:
272 error_propagate(errp, err);
273 }
274
s390_cpu_initfn(Object * obj)275 static void s390_cpu_initfn(Object *obj)
276 {
277 CPUState *cs = CPU(obj);
278
279 cs->exception_index = EXCP_HLT;
280
281 #if !defined(CONFIG_USER_ONLY)
282 s390_cpu_system_init(obj);
283 #endif
284 }
285
s390_gdb_arch_name(CPUState * cs)286 static const gchar *s390_gdb_arch_name(CPUState *cs)
287 {
288 return "s390:64-bit";
289 }
290
291 #ifndef CONFIG_USER_ONLY
292 static const Property s390x_cpu_properties[] = {
293 DEFINE_PROP_UINT32("core-id", S390CPU, env.core_id, 0),
294 DEFINE_PROP_INT32("socket-id", S390CPU, env.socket_id, -1),
295 DEFINE_PROP_INT32("book-id", S390CPU, env.book_id, -1),
296 DEFINE_PROP_INT32("drawer-id", S390CPU, env.drawer_id, -1),
297 DEFINE_PROP_BOOL("dedicated", S390CPU, env.dedicated, false),
298 DEFINE_PROP_CPUS390ENTITLEMENT("entitlement", S390CPU, env.entitlement,
299 S390_CPU_ENTITLEMENT_AUTO),
300 };
301 #endif
302
303 #ifdef CONFIG_TCG
304 #include "accel/tcg/cpu-ops.h"
305 #include "tcg/tcg_s390x.h"
306
s390x_cpu_mmu_index(CPUState * cs,bool ifetch)307 static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch)
308 {
309 return s390x_env_mmu_index(cpu_env(cs), ifetch);
310 }
311
s390x_get_tb_cpu_state(CPUState * cs)312 static TCGTBCPUState s390x_get_tb_cpu_state(CPUState *cs)
313 {
314 CPUS390XState *env = cpu_env(cs);
315 uint32_t flags;
316
317 if (env->psw.addr & 1) {
318 /*
319 * Instructions must be at even addresses.
320 * This needs to be checked before address translation.
321 */
322 env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
323 tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
324 }
325
326 flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
327 if (env->psw.mask & PSW_MASK_PER) {
328 flags |= env->cregs[9] & (FLAG_MASK_PER_BRANCH |
329 FLAG_MASK_PER_IFETCH |
330 FLAG_MASK_PER_IFETCH_NULLIFY);
331 if ((env->cregs[9] & PER_CR9_EVENT_STORE) &&
332 (env->cregs[9] & PER_CR9_EVENT_STORE_REAL)) {
333 flags |= FLAG_MASK_PER_STORE_REAL;
334 }
335 }
336 if (env->cregs[0] & CR0_AFP) {
337 flags |= FLAG_MASK_AFP;
338 }
339 if (env->cregs[0] & CR0_VECTOR) {
340 flags |= FLAG_MASK_VECTOR;
341 }
342
343 return (TCGTBCPUState){
344 .pc = env->psw.addr,
345 .flags = flags,
346 .cs_base = env->ex_value,
347 };
348 }
349
350 #ifndef CONFIG_USER_ONLY
s390_pointer_wrap(CPUState * cs,int mmu_idx,vaddr result,vaddr base)351 static vaddr s390_pointer_wrap(CPUState *cs, int mmu_idx,
352 vaddr result, vaddr base)
353 {
354 return wrap_address(cpu_env(cs), result);
355 }
356 #endif
357
358 static const TCGCPUOps s390_tcg_ops = {
359 .mttcg_supported = true,
360 .precise_smc = true,
361 /*
362 * The z/Architecture has a strong memory model with some
363 * store-after-load re-ordering.
364 */
365 .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD,
366
367 .initialize = s390x_translate_init,
368 .translate_code = s390x_translate_code,
369 .get_tb_cpu_state = s390x_get_tb_cpu_state,
370 .restore_state_to_opc = s390x_restore_state_to_opc,
371 .mmu_index = s390x_cpu_mmu_index,
372
373 #ifdef CONFIG_USER_ONLY
374 .record_sigsegv = s390_cpu_record_sigsegv,
375 .record_sigbus = s390_cpu_record_sigbus,
376 #else
377 .tlb_fill = s390_cpu_tlb_fill,
378 .pointer_wrap = s390_pointer_wrap,
379 .cpu_exec_interrupt = s390_cpu_exec_interrupt,
380 .cpu_exec_halt = s390_cpu_has_work,
381 .cpu_exec_reset = cpu_reset,
382 .do_interrupt = s390_cpu_do_interrupt,
383 .debug_excp_handler = s390x_cpu_debug_excp_handler,
384 .do_unaligned_access = s390x_cpu_do_unaligned_access,
385 #endif /* !CONFIG_USER_ONLY */
386 };
387 #endif /* CONFIG_TCG */
388
s390_cpu_class_init(ObjectClass * oc,const void * data)389 static void s390_cpu_class_init(ObjectClass *oc, const void *data)
390 {
391 S390CPUClass *scc = S390_CPU_CLASS(oc);
392 CPUClass *cc = CPU_CLASS(scc);
393 DeviceClass *dc = DEVICE_CLASS(oc);
394 ResettableClass *rc = RESETTABLE_CLASS(oc);
395
396 device_class_set_parent_realize(dc, s390_cpu_realizefn,
397 &scc->parent_realize);
398 dc->user_creatable = true;
399
400 resettable_class_set_parent_phases(rc, NULL, s390_cpu_reset_hold, NULL,
401 &scc->parent_phases);
402
403 cc->class_by_name = s390_cpu_class_by_name;
404 cc->list_cpus = s390_cpu_list;
405 cc->dump_state = s390_cpu_dump_state;
406 cc->query_cpu_fast = s390_query_cpu_fast;
407 cc->set_pc = s390_cpu_set_pc;
408 cc->get_pc = s390_cpu_get_pc;
409 cc->gdb_read_register = s390_cpu_gdb_read_register;
410 cc->gdb_write_register = s390_cpu_gdb_write_register;
411 #ifndef CONFIG_USER_ONLY
412 device_class_set_props(dc, s390x_cpu_properties);
413 s390_cpu_system_class_init(cc);
414 #endif
415 cc->disas_set_info = s390_cpu_disas_set_info;
416 cc->gdb_core_xml_file = "s390x-core64.xml";
417 cc->gdb_arch_name = s390_gdb_arch_name;
418
419 s390_cpu_model_class_register_props(oc);
420
421 #ifdef CONFIG_TCG
422 cc->tcg_ops = &s390_tcg_ops;
423 #endif /* CONFIG_TCG */
424 }
425
426 static const TypeInfo s390_cpu_type_info = {
427 .name = TYPE_S390_CPU,
428 .parent = TYPE_CPU,
429 .instance_size = sizeof(S390CPU),
430 .instance_align = __alignof__(S390CPU),
431 .instance_init = s390_cpu_initfn,
432
433 #ifndef CONFIG_USER_ONLY
434 .instance_finalize = s390_cpu_finalize,
435 #endif /* !CONFIG_USER_ONLY */
436
437 .abstract = true,
438 .class_size = sizeof(S390CPUClass),
439 .class_init = s390_cpu_class_init,
440 };
441
s390_cpu_register_types(void)442 static void s390_cpu_register_types(void)
443 {
444 type_register_static(&s390_cpu_type_info);
445 }
446
447 type_init(s390_cpu_register_types)
448