1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #ifndef MTK_ETH_H
10 #define MTK_ETH_H
11
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/of_net.h>
15 #include <linux/u64_stats_sync.h>
16 #include <linux/refcount.h>
17 #include <linux/phylink.h>
18 #include <linux/rhashtable.h>
19 #include <linux/dim.h>
20 #include <linux/bitfield.h>
21 #include <net/page_pool/types.h>
22 #include <linux/bpf_trace.h>
23 #include "mtk_ppe.h"
24
25 #define MTK_MAX_DSA_PORTS 7
26 #define MTK_DSA_PORT_MASK GENMASK(2, 0)
27
28 #define MTK_QDMA_NUM_QUEUES 16
29 #define MTK_QDMA_PAGE_SIZE 2048
30 #define MTK_MAX_RX_LENGTH 1536
31 #define MTK_MAX_RX_LENGTH_2K 2048
32 #define MTK_TX_DMA_BUF_LEN 0x3fff
33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff
34 #define MTK_QDMA_RING_SIZE 2048
35 #define MTK_DMA_SIZE(x) (SZ_##x)
36 #define MTK_FQ_DMA_HEAD 32
37 #define MTK_FQ_DMA_LENGTH 2048
38 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
39 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
40 #define MTK_DMA_DUMMY_DESC 0xffffffff
41 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
42 NETIF_MSG_PROBE | \
43 NETIF_MSG_LINK | \
44 NETIF_MSG_TIMER | \
45 NETIF_MSG_IFDOWN | \
46 NETIF_MSG_IFUP | \
47 NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR)
49 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
50 NETIF_F_RXCSUM | \
51 NETIF_F_HW_VLAN_CTAG_TX | \
52 NETIF_F_SG | NETIF_F_TSO | \
53 NETIF_F_TSO6 | \
54 NETIF_F_IPV6_CSUM |\
55 NETIF_F_HW_TC)
56 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
58
59 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM
60 #define MTK_PP_PAD (MTK_PP_HEADROOM + \
61 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
63
64 #define MTK_QRX_OFFSET 0x10
65
66 #define MTK_MAX_RX_RING_NUM 4
67 #define MTK_HW_LRO_DMA_SIZE 8
68
69 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
70 #define MTK_MAX_LRO_IP_CNT 2
71 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
72 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
73 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */
74 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
75 #define MTK_HW_LRO_MAX_AGG_CNT 64
76 #define MTK_HW_LRO_BW_THRE 3000
77 #define MTK_HW_LRO_REPLACE_DELTA 1000
78 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
79
80 /* Frame Engine Global Configuration */
81 #define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
82 #define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16)
83
84 /* Frame Engine Global Reset Register */
85 #define MTK_RST_GL 0x04
86 #define RST_GL_PSE BIT(0)
87
88 /* Frame Engine Interrupt Status Register */
89 #define MTK_INT_STATUS2 0x08
90 #define MTK_FE_INT_ENABLE 0x0c
91 #define MTK_FE_INT_FQ_EMPTY BIT(8)
92 #define MTK_FE_INT_TSO_FAIL BIT(12)
93 #define MTK_FE_INT_TSO_ILLEGAL BIT(13)
94 #define MTK_FE_INT_TSO_ALIGN BIT(14)
95 #define MTK_FE_INT_RFIFO_OV BIT(18)
96 #define MTK_FE_INT_RFIFO_UF BIT(19)
97 #define MTK_GDM1_AF BIT(28)
98 #define MTK_GDM2_AF BIT(29)
99
100 /* PDMA HW LRO Alter Flow Timer Register */
101 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
102
103 /* Frame Engine Interrupt Grouping Register */
104 #define MTK_FE_INT_GRP 0x20
105
106 /* CDMP Ingress Control Register */
107 #define MTK_CDMQ_IG_CTRL 0x1400
108 #define MTK_CDMQ_STAG_EN BIT(0)
109
110 /* CDMQ Exgress Control Register */
111 #define MTK_CDMQ_EG_CTRL 0x1404
112
113 /* CDMP Ingress Control Register */
114 #define MTK_CDMP_IG_CTRL 0x400
115 #define MTK_CDMP_STAG_EN BIT(0)
116
117 /* CDMP Exgress Control Register */
118 #define MTK_CDMP_EG_CTRL 0x404
119
120 /* GDM Exgress Control Register */
121 #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
122 0x540 : 0x500 + (_x * 0x1000); })
123 #define MTK_GDMA_SPECIAL_TAG BIT(24)
124 #define MTK_GDMA_ICS_EN BIT(22)
125 #define MTK_GDMA_TCS_EN BIT(21)
126 #define MTK_GDMA_UCS_EN BIT(20)
127 #define MTK_GDMA_STRP_CRC BIT(16)
128 #define MTK_GDMA_TO_PDMA 0x0
129 #define MTK_GDMA_DROP_ALL 0x7777
130
131 /* GDM Egress Control Register */
132 #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
133 0x544 : 0x504 + (_x * 0x1000); })
134 #define MTK_GDMA_XGDM_SEL BIT(31)
135
136 /* Unicast Filter MAC Address Register - Low */
137 #define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
138 0x548 : 0x508 + (_x * 0x1000); })
139
140 /* Unicast Filter MAC Address Register - High */
141 #define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
142 0x54C : 0x50C + (_x * 0x1000); })
143
144 /* Internal SRAM offset */
145 #define MTK_ETH_SRAM_OFFSET 0x40000
146
147 /* FE global misc reg*/
148 #define MTK_FE_GLO_MISC 0x124
149
150 /* PSE Free Queue Flow Control */
151 #define PSE_FQFC_CFG1 0x100
152 #define PSE_FQFC_CFG2 0x104
153 #define PSE_DROP_CFG 0x108
154 #define PSE_PPE_DROP(x) (0x110 + ((x) * 0x4))
155
156 /* PSE Last FreeQ Page Request Control */
157 #define PSE_DUMY_REQ 0x10C
158 /* PSE_DUMY_REQ is not a typo but actually called like that also in
159 * MediaTek's datasheet
160 */
161 #define PSE_DUMMY_WORK_GDM(x) BIT(16 + (x))
162 #define DUMMY_PAGE_THR 0x1
163
164 /* PSE Input Queue Reservation Register*/
165 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
166
167 /* PSE Output Queue Threshold Register*/
168 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
169
170 /* GDM and CDM Threshold */
171 #define MTK_GDM2_THRES 0x1530
172 #define MTK_CDMW0_THRES 0x164c
173 #define MTK_CDMW1_THRES 0x1650
174 #define MTK_CDME0_THRES 0x1654
175 #define MTK_CDME1_THRES 0x1658
176 #define MTK_CDMM_THRES 0x165c
177
178 /* PDMA HW LRO Control Registers */
179 #define MTK_PDMA_LRO_CTRL_DW0 0x980
180 #define MTK_LRO_EN BIT(0)
181 #define MTK_L3_CKS_UPD_EN BIT(7)
182 #define MTK_L3_CKS_UPD_EN_V2 BIT(19)
183 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
184 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
185 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
186 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
187 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
188
189 #define MTK_PDMA_LRO_CTRL_DW1 0x984
190 #define MTK_PDMA_LRO_CTRL_DW2 0x988
191 #define MTK_PDMA_LRO_CTRL_DW3 0x98c
192 #define MTK_ADMA_MODE BIT(15)
193 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
194
195 #define MTK_RX_DMA_LRO_EN BIT(8)
196 #define MTK_MULTI_EN BIT(10)
197 #define MTK_PDMA_SIZE_8DWORDS (1 << 4)
198
199 /* PDMA Global Configuration Register */
200 #define MTK_PDMA_LRO_SDL 0x3000
201 #define MTK_RX_CFG_SDL_OFFSET 16
202
203 /* PDMA Reset Index Register */
204 #define MTK_PST_DRX_IDX0 BIT(16)
205 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
206
207 /* PDMA Delay Interrupt Register */
208 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
209 #define MTK_PDMA_DELAY_RX_EN BIT(15)
210 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
211 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
212
213 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)
214 #define MTK_PDMA_DELAY_TX_EN BIT(31)
215 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24
216 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16
217
218 #define MTK_PDMA_DELAY_PINT_MASK 0x7f
219 #define MTK_PDMA_DELAY_PTIME_MASK 0xff
220
221 /* PDMA HW LRO Alter Flow Delta Register */
222 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
223
224 /* PDMA HW LRO IP Setting Registers */
225 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
226 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
227 #define MTK_RING_MYIP_VLD BIT(9)
228
229 /* PDMA HW LRO Ring Control Registers */
230 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
231 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
232 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
233 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
234 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
235 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
236 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
237 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
238 #define MTK_RING_AUTO_LERAN_MODE (3 << 6)
239 #define MTK_RING_VLD BIT(8)
240 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
241 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
242 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
243
244 /* QDMA TX Queue Configuration Registers */
245 #define MTK_QTX_OFFSET 0x10
246 #define QDMA_RES_THRES 4
247
248 /* QDMA Tx Queue Scheduler Configuration Registers */
249 #define MTK_QTX_SCH_TX_SEL BIT(31)
250 #define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30)
251
252 #define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30)
253 #define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28)
254 #define MTK_QTX_SCH_MIN_RATE_EN BIT(27)
255 #define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20)
256 #define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16)
257 #define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12)
258 #define MTK_QTX_SCH_MAX_RATE_EN BIT(11)
259 #define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)
260 #define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
261
262 /* QDMA TX Scheduler Rate Control Register */
263 #define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15)
264
265 /* QDMA Global Configuration Register */
266 #define MTK_RX_2B_OFFSET BIT(31)
267 #define MTK_RX_BT_32DWORDS (3 << 11)
268 #define MTK_NDP_CO_PRO BIT(10)
269 #define MTK_TX_WB_DDONE BIT(6)
270 #define MTK_TX_BT_32DWORDS (3 << 4)
271 #define MTK_RX_DMA_BUSY BIT(3)
272 #define MTK_TX_DMA_BUSY BIT(1)
273 #define MTK_RX_DMA_EN BIT(2)
274 #define MTK_TX_DMA_EN BIT(0)
275 #define MTK_DMA_BUSY_TIMEOUT_US 1000000
276
277 /* QDMA V2 Global Configuration Register */
278 #define MTK_CHK_DDONE_EN BIT(28)
279 #define MTK_DMAD_WR_WDONE BIT(26)
280 #define MTK_WCOMP_EN BIT(24)
281 #define MTK_RESV_BUF (0x40 << 16)
282 #define MTK_MUTLI_CNT (0x4 << 12)
283 #define MTK_LEAKY_BUCKET_EN BIT(11)
284
285 /* QDMA Flow Control Register */
286 #define FC_THRES_DROP_MODE BIT(20)
287 #define FC_THRES_DROP_EN (7 << 16)
288 #define FC_THRES_MIN 0x4444
289
290 /* QDMA Interrupt Status Register */
291 #define MTK_RX_DONE_DLY BIT(30)
292 #define MTK_TX_DONE_DLY BIT(28)
293 #define MTK_RX_DONE_INT3 BIT(19)
294 #define MTK_RX_DONE_INT2 BIT(18)
295 #define MTK_RX_DONE_INT1 BIT(17)
296 #define MTK_RX_DONE_INT0 BIT(16)
297 #define MTK_TX_DONE_INT3 BIT(3)
298 #define MTK_TX_DONE_INT2 BIT(2)
299 #define MTK_TX_DONE_INT1 BIT(1)
300 #define MTK_TX_DONE_INT0 BIT(0)
301 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY
302 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY
303
304 #define MTK_RX_DONE_INT_V2 BIT(14)
305
306 #define MTK_CDM_TXFIFO_RDY BIT(7)
307
308 /* QDMA Interrupt grouping registers */
309 #define MTK_RLS_DONE_INT BIT(0)
310
311 /* QDMA TX NUM */
312 #define QID_BITS_V2(x) (((x) & 0x3f) << 16)
313 #define MTK_QDMA_GMAC2_QID 8
314
315 #define MTK_TX_DMA_BUF_SHIFT 8
316
317 /* QDMA V2 descriptor txd6 */
318 #define TX_DMA_INS_VLAN_V2 BIT(16)
319 /* QDMA V2 descriptor txd5 */
320 #define TX_DMA_CHKSUM_V2 (0x7 << 28)
321 #define TX_DMA_TSO_V2 BIT(31)
322
323 #define TX_DMA_SPTAG_V3 BIT(27)
324
325 /* QDMA V2 descriptor txd4 */
326 #define TX_DMA_FPORT_SHIFT_V2 8
327 #define TX_DMA_FPORT_MASK_V2 0xf
328 #define TX_DMA_SWC_V2 BIT(30)
329
330 /* QDMA descriptor txd4 */
331 #define TX_DMA_CHKSUM (0x7 << 29)
332 #define TX_DMA_TSO BIT(28)
333 #define TX_DMA_FPORT_SHIFT 25
334 #define TX_DMA_FPORT_MASK 0x7
335 #define TX_DMA_INS_VLAN BIT(16)
336
337 /* QDMA descriptor txd3 */
338 #define TX_DMA_OWNER_CPU BIT(31)
339 #define TX_DMA_LS0 BIT(30)
340 #define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
341 #define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
342 #define TX_DMA_SWC BIT(14)
343 #define TX_DMA_PQID GENMASK(3, 0)
344 #define TX_DMA_ADDR64_MASK GENMASK(3, 0)
345 #if IS_ENABLED(CONFIG_64BIT)
346 # define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32)
347 # define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32))
348 #else
349 # define TX_DMA_GET_ADDR64(x) (0)
350 # define TX_DMA_PREP_ADDR64(x) (0)
351 #endif
352
353 /* PDMA on MT7628 */
354 #define TX_DMA_DONE BIT(31)
355 #define TX_DMA_LS1 BIT(14)
356 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
357
358 /* QDMA descriptor rxd2 */
359 #define RX_DMA_DONE BIT(31)
360 #define RX_DMA_LSO BIT(30)
361 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
362 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
363 #define RX_DMA_VTAG BIT(15)
364 #define RX_DMA_ADDR64_MASK GENMASK(3, 0)
365 #if IS_ENABLED(CONFIG_64BIT)
366 # define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32)
367 # define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32))
368 #else
369 # define RX_DMA_GET_ADDR64(x) (0)
370 # define RX_DMA_PREP_ADDR64(x) (0)
371 #endif
372
373 /* QDMA descriptor rxd3 */
374 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK)
375 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
376 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
377
378 /* QDMA descriptor rxd4 */
379 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
380 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
381 #define MTK_RXD4_SRC_PORT GENMASK(21, 19)
382 #define MTK_RXD4_ALG GENMASK(31, 22)
383
384 /* QDMA descriptor rxd4 */
385 #define RX_DMA_L4_VALID BIT(24)
386 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
387 #define RX_DMA_SPECIAL_TAG BIT(22)
388
389 /* PDMA descriptor rxd5 */
390 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)
391 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18)
392 #define MTK_RXD5_SRC_PORT GENMASK(29, 26)
393
394 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7)
395 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf)
396
397 /* PDMA V2 descriptor rxd3 */
398 #define RX_DMA_VTAG_V2 BIT(0)
399 #define RX_DMA_L4_VALID_V2 BIT(2)
400
401 /* PHY Polling and SMI Master Control registers */
402 #define MTK_PPSC 0x10000
403 #define PPSC_MDC_CFG GENMASK(29, 24)
404 #define PPSC_MDC_TURBO BIT(20)
405 #define MDC_MAX_FREQ 25000000
406 #define MDC_MAX_DIVIDER 63
407
408 /* PHY Indirect Access Control registers */
409 #define MTK_PHY_IAC 0x10004
410 #define PHY_IAC_ACCESS BIT(31)
411 #define PHY_IAC_REG_MASK GENMASK(29, 25)
412 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x))
413 #define PHY_IAC_ADDR_MASK GENMASK(24, 20)
414 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
415 #define PHY_IAC_CMD_MASK GENMASK(19, 18)
416 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
417 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
418 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
419 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
420 #define PHY_IAC_START_MASK GENMASK(17, 16)
421 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
422 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
423 #define PHY_IAC_DATA_MASK GENMASK(15, 0)
424 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
425 #define PHY_IAC_TIMEOUT HZ
426
427 #define MTK_MAC_MISC 0x1000c
428 #define MTK_MAC_MISC_V3 0x10010
429 #define MTK_MUX_TO_ESW BIT(0)
430 #define MISC_MDC_TURBO BIT(4)
431
432 /* XMAC status registers */
433 #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
434 #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
435 #define MTK_USXGMII_PCS_LINK BIT(8)
436 #define MTK_XGMAC_RX_FC BIT(5)
437 #define MTK_XGMAC_TX_FC BIT(4)
438 #define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
439 #define MTK_XGMAC_LINK_STS BIT(0)
440
441 /* GSW bridge registers */
442 #define MTK_GSW_CFG (0x10080)
443 #define GSWTX_IPG_MASK GENMASK(19, 16)
444 #define GSWTX_IPG_SHIFT 16
445 #define GSWRX_IPG_MASK GENMASK(3, 0)
446 #define GSWRX_IPG_SHIFT 0
447 #define GSW_IPG_11 11
448
449 /* Mac control registers */
450 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
451 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24)
452 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24))
453 #define MAC_MCR_MAX_RX_1518 0x0
454 #define MAC_MCR_MAX_RX_1536 0x1
455 #define MAC_MCR_MAX_RX_1552 0x2
456 #define MAC_MCR_MAX_RX_2048 0x3
457 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
458 #define MAC_MCR_FORCE_MODE BIT(15)
459 #define MAC_MCR_TX_EN BIT(14)
460 #define MAC_MCR_RX_EN BIT(13)
461 #define MAC_MCR_RX_FIFO_CLR_DIS BIT(12)
462 #define MAC_MCR_BACKOFF_EN BIT(9)
463 #define MAC_MCR_BACKPR_EN BIT(8)
464 #define MAC_MCR_EEE1G BIT(7)
465 #define MAC_MCR_EEE100M BIT(6)
466 #define MAC_MCR_FORCE_RX_FC BIT(5)
467 #define MAC_MCR_FORCE_TX_FC BIT(4)
468 #define MAC_MCR_SPEED_1000 BIT(3)
469 #define MAC_MCR_SPEED_100 BIT(2)
470 #define MAC_MCR_FORCE_DPX BIT(1)
471 #define MAC_MCR_FORCE_LINK BIT(0)
472 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
473
474 /* Mac EEE control registers */
475 #define MTK_MAC_EEECR(x) (0x10104 + (x * 0x100))
476 #define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24)
477 #define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16)
478 #define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8)
479 #define MAC_EEE_CKG_TXIDLE BIT(3)
480 #define MAC_EEE_CKG_RXLPI BIT(2)
481 #define MAC_EEE_LPI_MODE BIT(0)
482
483 /* Mac status registers */
484 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
485 #define MAC_MSR_EEE1G BIT(7)
486 #define MAC_MSR_EEE100M BIT(6)
487 #define MAC_MSR_RX_FC BIT(5)
488 #define MAC_MSR_TX_FC BIT(4)
489 #define MAC_MSR_SPEED_1000 BIT(3)
490 #define MAC_MSR_SPEED_100 BIT(2)
491 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
492 #define MAC_MSR_DPX BIT(1)
493 #define MAC_MSR_LINK BIT(0)
494
495 /* TRGMII RXC control register */
496 #define TRGMII_RCK_CTRL 0x10300
497 #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
498 #define DQSI1(x) ((x << 8) & GENMASK(14, 8))
499 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
500 #define RXC_RST BIT(31)
501 #define RXC_DQSISEL BIT(30)
502 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
503 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
504
505 #define NUM_TRGMII_CTRL 5
506
507 /* TRGMII RXC control register */
508 #define TRGMII_TCK_CTRL 0x10340
509 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
510 #define TXC_INV BIT(30)
511 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
512 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
513
514 /* TRGMII TX Drive Strength */
515 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
516 #define TD_DM_DRVP(x) ((x) & 0xf)
517 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
518
519 /* TRGMII Interface mode register */
520 #define INTF_MODE 0x10390
521 #define TRGMII_INTF_DIS BIT(0)
522 #define TRGMII_MODE BIT(1)
523 #define TRGMII_CENTRAL_ALIGNED BIT(2)
524 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
525 #define INTF_MODE_RGMII_10_100 0
526
527 /* GPIO port control registers for GMAC 2*/
528 #define GPIO_OD33_CTRL8 0x4c0
529 #define GPIO_BIAS_CTRL 0xed0
530 #define GPIO_DRV_SEL10 0xf00
531
532 /* ethernet subsystem chip id register */
533 #define ETHSYS_CHIPID0_3 0x0
534 #define ETHSYS_CHIPID4_7 0x4
535 #define MT7623_ETH 7623
536 #define MT7622_ETH 7622
537 #define MT7621_ETH 7621
538
539 /* ethernet system control register */
540 #define ETHSYS_SYSCFG 0x10
541 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
542
543 /* ethernet subsystem config register */
544 #define ETHSYS_SYSCFG0 0x14
545 #define SYSCFG0_GE_MASK 0x3
546 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
547 #define SYSCFG0_SGMII_MASK GENMASK(9, 7)
548 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
549 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
550 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
551 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
552
553
554 /* ethernet subsystem clock register */
555 #define ETHSYS_CLKCFG0 0x2c
556 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
557 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
558 #define ETHSYS_TRGMII_MT7621_APLL BIT(6)
559 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
560
561 /* ethernet reset control register */
562 #define ETHSYS_RSTCTRL 0x34
563 #define RSTCTRL_FE BIT(6)
564 #define RSTCTRL_WDMA0 BIT(24)
565 #define RSTCTRL_WDMA1 BIT(25)
566 #define RSTCTRL_WDMA2 BIT(26)
567 #define RSTCTRL_PPE0 BIT(31)
568 #define RSTCTRL_PPE0_V2 BIT(30)
569 #define RSTCTRL_PPE1 BIT(31)
570 #define RSTCTRL_PPE0_V3 BIT(29)
571 #define RSTCTRL_PPE1_V3 BIT(30)
572 #define RSTCTRL_PPE2 BIT(31)
573 #define RSTCTRL_ETH BIT(23)
574
575 /* ethernet reset check idle register */
576 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
577
578 /* ethernet dma channel agent map */
579 #define ETHSYS_DMA_AG_MAP 0x408
580 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
581 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
582 #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
583
584 /* Infrasys subsystem config registers */
585 #define INFRA_MISC2 0x70c
586 #define CO_QPHY_SEL BIT(0)
587 #define GEPHY_MAC_SEL BIT(1)
588
589 /* Top misc registers */
590 #define USB_PHY_SWITCH_REG 0x218
591 #define QPHY_SEL_MASK GENMASK(1, 0)
592 #define SGMII_QPHY_SEL 0x2
593
594 /* MT7628/88 specific stuff */
595 #define MT7628_PDMA_OFFSET 0x0800
596 #define MT7628_SDM_OFFSET 0x0c00
597
598 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
599 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
600 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
601 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
602 #define MT7628_PST_DTX_IDX0 BIT(0)
603
604 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
605 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
606
607 /* Counter / stat register */
608 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
609 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
610 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
611 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
612 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
613
614 #define MTK_FE_CDM1_FSM 0x220
615 #define MTK_FE_CDM2_FSM 0x224
616 #define MTK_FE_CDM3_FSM 0x238
617 #define MTK_FE_CDM4_FSM 0x298
618 #define MTK_FE_CDM5_FSM 0x318
619 #define MTK_FE_CDM6_FSM 0x328
620 #define MTK_FE_GDM1_FSM 0x228
621 #define MTK_FE_GDM2_FSM 0x22C
622
623 #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
624
625 struct mtk_rx_dma {
626 unsigned int rxd1;
627 unsigned int rxd2;
628 unsigned int rxd3;
629 unsigned int rxd4;
630 } __packed __aligned(4);
631
632 struct mtk_rx_dma_v2 {
633 unsigned int rxd1;
634 unsigned int rxd2;
635 unsigned int rxd3;
636 unsigned int rxd4;
637 unsigned int rxd5;
638 unsigned int rxd6;
639 unsigned int rxd7;
640 unsigned int rxd8;
641 } __packed __aligned(4);
642
643 struct mtk_tx_dma {
644 unsigned int txd1;
645 unsigned int txd2;
646 unsigned int txd3;
647 unsigned int txd4;
648 } __packed __aligned(4);
649
650 struct mtk_tx_dma_v2 {
651 unsigned int txd1;
652 unsigned int txd2;
653 unsigned int txd3;
654 unsigned int txd4;
655 unsigned int txd5;
656 unsigned int txd6;
657 unsigned int txd7;
658 unsigned int txd8;
659 } __packed __aligned(4);
660
661 struct mtk_eth;
662 struct mtk_mac;
663
664 struct mtk_xdp_stats {
665 u64 rx_xdp_redirect;
666 u64 rx_xdp_pass;
667 u64 rx_xdp_drop;
668 u64 rx_xdp_tx;
669 u64 rx_xdp_tx_errors;
670 u64 tx_xdp_xmit;
671 u64 tx_xdp_xmit_errors;
672 };
673
674 /* struct mtk_hw_stats - the structure that holds the traffic statistics.
675 * @stats_lock: make sure that stats operations are atomic
676 * @reg_offset: the status register offset of the SoC
677 * @syncp: the refcount
678 *
679 * All of the supported SoCs have hardware counters for traffic statistics.
680 * Whenever the status IRQ triggers we can read the latest stats from these
681 * counters and store them in this struct.
682 */
683 struct mtk_hw_stats {
684 u64 tx_bytes;
685 u64 tx_packets;
686 u64 tx_skip;
687 u64 tx_collisions;
688 u64 rx_bytes;
689 u64 rx_packets;
690 u64 rx_overflow;
691 u64 rx_fcs_errors;
692 u64 rx_short_errors;
693 u64 rx_long_errors;
694 u64 rx_checksum_errors;
695 u64 rx_flow_control_packets;
696
697 struct mtk_xdp_stats xdp_stats;
698
699 spinlock_t stats_lock;
700 u32 reg_offset;
701 struct u64_stats_sync syncp;
702 };
703
704 enum mtk_tx_flags {
705 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
706 * track how memory was allocated so that it can be freed properly.
707 */
708 MTK_TX_FLAGS_SINGLE0 = 0x01,
709 MTK_TX_FLAGS_PAGE0 = 0x02,
710 };
711
712 /* This enum allows us to identify how the clock is defined on the array of the
713 * clock in the order
714 */
715 enum mtk_clks_map {
716 MTK_CLK_ETHIF,
717 MTK_CLK_SGMIITOP,
718 MTK_CLK_ESW,
719 MTK_CLK_GP0,
720 MTK_CLK_GP1,
721 MTK_CLK_GP2,
722 MTK_CLK_GP3,
723 MTK_CLK_XGP1,
724 MTK_CLK_XGP2,
725 MTK_CLK_XGP3,
726 MTK_CLK_CRYPTO,
727 MTK_CLK_FE,
728 MTK_CLK_TRGPLL,
729 MTK_CLK_SGMII_TX_250M,
730 MTK_CLK_SGMII_RX_250M,
731 MTK_CLK_SGMII_CDR_REF,
732 MTK_CLK_SGMII_CDR_FB,
733 MTK_CLK_SGMII2_TX_250M,
734 MTK_CLK_SGMII2_RX_250M,
735 MTK_CLK_SGMII2_CDR_REF,
736 MTK_CLK_SGMII2_CDR_FB,
737 MTK_CLK_SGMII_CK,
738 MTK_CLK_ETH2PLL,
739 MTK_CLK_WOCPU0,
740 MTK_CLK_WOCPU1,
741 MTK_CLK_NETSYS0,
742 MTK_CLK_NETSYS1,
743 MTK_CLK_ETHWARP_WOCPU2,
744 MTK_CLK_ETHWARP_WOCPU1,
745 MTK_CLK_ETHWARP_WOCPU0,
746 MTK_CLK_TOP_SGM_0_SEL,
747 MTK_CLK_TOP_SGM_1_SEL,
748 MTK_CLK_TOP_ETH_GMII_SEL,
749 MTK_CLK_TOP_ETH_REFCK_50M_SEL,
750 MTK_CLK_TOP_ETH_SYS_200M_SEL,
751 MTK_CLK_TOP_ETH_SYS_SEL,
752 MTK_CLK_TOP_ETH_XGMII_SEL,
753 MTK_CLK_TOP_ETH_MII_SEL,
754 MTK_CLK_TOP_NETSYS_SEL,
755 MTK_CLK_TOP_NETSYS_500M_SEL,
756 MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
757 MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
758 MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
759 MTK_CLK_TOP_NETSYS_WARP_SEL,
760 MTK_CLK_MAX
761 };
762
763 #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
764 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
765 BIT_ULL(MTK_CLK_TRGPLL))
766 #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
767 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
768 BIT_ULL(MTK_CLK_GP2) | \
769 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
770 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
771 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
772 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
773 BIT_ULL(MTK_CLK_SGMII_CK) | \
774 BIT_ULL(MTK_CLK_ETH2PLL))
775 #define MT7621_CLKS_BITMAP (0)
776 #define MT7628_CLKS_BITMAP (0)
777 #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
778 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
779 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
780 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
781 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
782 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
783 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
784 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
785 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
786 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
787 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
788 BIT_ULL(MTK_CLK_SGMII_CK) | \
789 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
790 #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
791 BIT_ULL(MTK_CLK_GP1) | \
792 BIT_ULL(MTK_CLK_WOCPU0) | \
793 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
794 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
795 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
796 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
797 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
798 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
799 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
800 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
801 BIT_ULL(MTK_CLK_SGMII_CK))
802 #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
803 BIT_ULL(MTK_CLK_GP1) | \
804 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
805 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
806 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
807 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
808 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
809 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
810 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
811 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
812 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
813 #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
814 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
815 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
816 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
817 BIT_ULL(MTK_CLK_CRYPTO) | \
818 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
819 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
820 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
821 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
822 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
823 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
824 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
825 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
826 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
827 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
828 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
829 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
830 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
831 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
832 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
833
834 enum mtk_dev_state {
835 MTK_HW_INIT,
836 MTK_RESETTING
837 };
838
839 /* PSE Port Definition */
840 enum mtk_pse_port {
841 PSE_ADMA_PORT = 0,
842 PSE_GDM1_PORT,
843 PSE_GDM2_PORT,
844 PSE_PPE0_PORT,
845 PSE_PPE1_PORT,
846 PSE_QDMA_TX_PORT,
847 PSE_QDMA_RX_PORT,
848 PSE_DROP_PORT,
849 PSE_WDMA0_PORT,
850 PSE_WDMA1_PORT,
851 PSE_TDMA_PORT,
852 PSE_NONE_PORT,
853 PSE_PPE2_PORT,
854 PSE_WDMA2_PORT,
855 PSE_EIP197_PORT,
856 PSE_GDM3_PORT,
857 PSE_PORT_MAX
858 };
859
860 /* GMAC Identifier */
861 enum mtk_gmac_id {
862 MTK_GMAC1_ID = 0,
863 MTK_GMAC2_ID,
864 MTK_GMAC3_ID,
865 MTK_GMAC_ID_MAX
866 };
867
868 enum mtk_tx_buf_type {
869 MTK_TYPE_SKB,
870 MTK_TYPE_XDP_TX,
871 MTK_TYPE_XDP_NDO,
872 };
873
874 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
875 * by the TX descriptor s
876 * @skb: The SKB pointer of the packet being sent
877 * @dma_addr0: The base addr of the first segment
878 * @dma_len0: The length of the first segment
879 * @dma_addr1: The base addr of the second segment
880 * @dma_len1: The length of the second segment
881 */
882 struct mtk_tx_buf {
883 enum mtk_tx_buf_type type;
884 void *data;
885
886 u16 mac_id;
887 u16 flags;
888 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
889 DEFINE_DMA_UNMAP_LEN(dma_len0);
890 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
891 DEFINE_DMA_UNMAP_LEN(dma_len1);
892 };
893
894 /* struct mtk_tx_ring - This struct holds info describing a TX ring
895 * @dma: The descriptor ring
896 * @buf: The memory pointed at by the ring
897 * @phys: The physical addr of tx_buf
898 * @next_free: Pointer to the next free descriptor
899 * @last_free: Pointer to the last free descriptor
900 * @last_free_ptr: Hardware pointer value of the last free descriptor
901 * @thresh: The threshold of minimum amount of free descriptors
902 * @free_count: QDMA uses a linked list. Track how many free descriptors
903 * are present
904 */
905 struct mtk_tx_ring {
906 void *dma;
907 struct mtk_tx_buf *buf;
908 dma_addr_t phys;
909 struct mtk_tx_dma *next_free;
910 struct mtk_tx_dma *last_free;
911 u32 last_free_ptr;
912 u16 thresh;
913 atomic_t free_count;
914 int dma_size;
915 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
916 dma_addr_t phys_pdma;
917 int cpu_idx;
918 };
919
920 /* PDMA rx ring mode */
921 enum mtk_rx_flags {
922 MTK_RX_FLAGS_NORMAL = 0,
923 MTK_RX_FLAGS_HWLRO,
924 MTK_RX_FLAGS_QDMA,
925 };
926
927 /* struct mtk_rx_ring - This struct holds info describing a RX ring
928 * @dma: The descriptor ring
929 * @data: The memory pointed at by the ring
930 * @phys: The physical addr of rx_buf
931 * @frag_size: How big can each fragment be
932 * @buf_size: The size of each packet buffer
933 * @calc_idx: The current head of ring
934 */
935 struct mtk_rx_ring {
936 void *dma;
937 u8 **data;
938 dma_addr_t phys;
939 u16 frag_size;
940 u16 buf_size;
941 u16 dma_size;
942 bool calc_idx_update;
943 u16 calc_idx;
944 u32 crx_idx_reg;
945 /* page_pool */
946 struct page_pool *page_pool;
947 struct xdp_rxq_info xdp_q;
948 };
949
950 enum mkt_eth_capabilities {
951 MTK_RGMII_BIT = 0,
952 MTK_TRGMII_BIT,
953 MTK_SGMII_BIT,
954 MTK_ESW_BIT,
955 MTK_GEPHY_BIT,
956 MTK_MUX_BIT,
957 MTK_INFRA_BIT,
958 MTK_SHARED_SGMII_BIT,
959 MTK_HWLRO_BIT,
960 MTK_SHARED_INT_BIT,
961 MTK_TRGMII_MT7621_CLK_BIT,
962 MTK_QDMA_BIT,
963 MTK_SOC_MT7628_BIT,
964 MTK_RSTCTRL_PPE1_BIT,
965 MTK_RSTCTRL_PPE2_BIT,
966 MTK_U3_COPHY_V2_BIT,
967 MTK_SRAM_BIT,
968 MTK_36BIT_DMA_BIT,
969
970 /* MUX BITS*/
971 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
972 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
973 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
974 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
975 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
976
977 /* PATH BITS */
978 MTK_ETH_PATH_GMAC1_RGMII_BIT,
979 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
980 MTK_ETH_PATH_GMAC1_SGMII_BIT,
981 MTK_ETH_PATH_GMAC2_RGMII_BIT,
982 MTK_ETH_PATH_GMAC2_SGMII_BIT,
983 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
984 MTK_ETH_PATH_GDM1_ESW_BIT,
985 };
986
987 /* Supported hardware group on SoCs */
988 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
989 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
990 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
991 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
992 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
993 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
994 #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT)
995 #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT)
996 #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT)
997 #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT)
998 #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
999 #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT)
1000 #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT)
1001 #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
1002 #define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
1003 #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
1004 #define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
1005 #define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
1006
1007 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
1008 BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
1009 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
1010 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
1011 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
1012 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
1013 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1014 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
1015 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
1016 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
1017
1018 /* Supported path present on SoCs */
1019 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
1020 #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
1021 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
1022 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
1023 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
1024 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
1025 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
1026
1027 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
1028 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
1029 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
1030 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
1031 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
1032 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1033 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
1034
1035 /* MUXes present on SoCs */
1036 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1037 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
1038
1039 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
1040 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
1041 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
1042
1043 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1044 #define MTK_MUX_U3_GMAC2_TO_QPHY \
1045 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
1046
1047 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
1048 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1049 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
1050 MTK_SHARED_SGMII)
1051
1052 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
1053 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
1054 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
1055
1056 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
1057
1058 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
1059 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
1060 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
1061
1062 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
1063 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
1064 MTK_MUX_GDM1_TO_GMAC1_ESW | \
1065 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
1066
1067 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
1068 MTK_QDMA)
1069
1070 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
1071
1072 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1073 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
1074 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
1075 MTK_MUX_U3_GMAC2_TO_QPHY | \
1076 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
1077
1078 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1079 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1080 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1081 MTK_RSTCTRL_PPE1 | MTK_SRAM)
1082
1083 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
1084 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1085 MTK_RSTCTRL_PPE1 | MTK_SRAM)
1086
1087 #define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
1088 MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
1089
1090 struct mtk_tx_dma_desc_info {
1091 dma_addr_t addr;
1092 u32 size;
1093 u16 vlan_tci;
1094 u16 qid;
1095 u8 gso:1;
1096 u8 csum:1;
1097 u8 vlan:1;
1098 u8 first:1;
1099 u8 last:1;
1100 };
1101
1102 struct mtk_reg_map {
1103 u32 tx_irq_mask;
1104 u32 tx_irq_status;
1105 struct {
1106 u32 rx_ptr; /* rx base pointer */
1107 u32 rx_cnt_cfg; /* rx max count configuration */
1108 u32 pcrx_ptr; /* rx cpu pointer */
1109 u32 glo_cfg; /* global configuration */
1110 u32 rst_idx; /* reset index */
1111 u32 delay_irq; /* delay interrupt */
1112 u32 irq_status; /* interrupt status */
1113 u32 irq_mask; /* interrupt mask */
1114 u32 adma_rx_dbg0;
1115 u32 int_grp;
1116 } pdma;
1117 struct {
1118 u32 qtx_cfg; /* tx queue configuration */
1119 u32 qtx_sch; /* tx queue scheduler configuration */
1120 u32 rx_ptr; /* rx base pointer */
1121 u32 rx_cnt_cfg; /* rx max count configuration */
1122 u32 qcrx_ptr; /* rx cpu pointer */
1123 u32 glo_cfg; /* global configuration */
1124 u32 rst_idx; /* reset index */
1125 u32 delay_irq; /* delay interrupt */
1126 u32 fc_th; /* flow control */
1127 u32 int_grp;
1128 u32 hred; /* interrupt mask */
1129 u32 ctx_ptr; /* tx acquire cpu pointer */
1130 u32 dtx_ptr; /* tx acquire dma pointer */
1131 u32 crx_ptr; /* tx release cpu pointer */
1132 u32 drx_ptr; /* tx release dma pointer */
1133 u32 fq_head; /* fq head pointer */
1134 u32 fq_tail; /* fq tail pointer */
1135 u32 fq_count; /* fq free page count */
1136 u32 fq_blen; /* fq free page buffer length */
1137 u32 tx_sch_rate; /* tx scheduler rate control registers */
1138 } qdma;
1139 u32 gdm1_cnt;
1140 u32 gdma_to_ppe[3];
1141 u32 ppe_base;
1142 u32 wdma_base[3];
1143 u32 pse_iq_sta;
1144 u32 pse_oq_sta;
1145 };
1146
1147 /* struct mtk_eth_data - This is the structure holding all differences
1148 * among various plaforms
1149 * @reg_map Soc register map.
1150 * @ana_rgc3: The offset for register ANA_RGC3 related to
1151 * sgmiisys syscon
1152 * @caps Flags shown the extra capability for the SoC
1153 * @hw_features Flags shown HW features
1154 * @required_clks Flags shown the bitmap for required clocks on
1155 * the target SoC
1156 * @required_pctl A bool value to show whether the SoC requires
1157 * the extra setup for those pins used by GMAC.
1158 * @hash_offset Flow table hash offset.
1159 * @version SoC version.
1160 * @foe_entry_size Foe table entry size.
1161 * @has_accounting Bool indicating support for accounting of
1162 * offloaded flows.
1163 * @desc_size Tx/Rx DMA descriptor size.
1164 * @irq_done_mask Rx irq done register mask.
1165 * @dma_l4_valid Rx DMA valid register mask.
1166 * @dma_max_len Max DMA tx/rx buffer length.
1167 * @dma_len_offset Tx/Rx DMA length field offset.
1168 */
1169 struct mtk_soc_data {
1170 const struct mtk_reg_map *reg_map;
1171 u32 ana_rgc3;
1172 u64 caps;
1173 u64 required_clks;
1174 bool required_pctl;
1175 u8 offload_version;
1176 u8 hash_offset;
1177 u8 version;
1178 u8 ppe_num;
1179 u16 foe_entry_size;
1180 netdev_features_t hw_features;
1181 bool has_accounting;
1182 bool disable_pll_modes;
1183 struct {
1184 u32 desc_size;
1185 u32 dma_max_len;
1186 u32 dma_len_offset;
1187 u32 dma_size;
1188 u32 fq_dma_size;
1189 } tx;
1190 struct {
1191 u32 desc_size;
1192 u32 irq_done_mask;
1193 u32 dma_l4_valid;
1194 u32 dma_max_len;
1195 u32 dma_len_offset;
1196 u32 dma_size;
1197 } rx;
1198 };
1199
1200 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
1201
1202 /* currently no SoC has more than 3 macs */
1203 #define MTK_MAX_DEVS 3
1204
1205 /* struct mtk_eth - This is the main datasructure for holding the state
1206 * of the driver
1207 * @dev: The device pointer
1208 * @dev: The device pointer used for dma mapping/alloc
1209 * @base: The mapped register i/o base
1210 * @page_lock: Make sure that register operations are atomic
1211 * @tx_irq__lock: Make sure that IRQ register operations are atomic
1212 * @rx_irq__lock: Make sure that IRQ register operations are atomic
1213 * @dim_lock: Make sure that Net DIM operations are atomic
1214 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1215 * dummy for NAPI to work
1216 * @netdev: The netdev instances
1217 * @mac: Each netdev is linked to a physical MAC
1218 * @irq: The IRQ that we are using
1219 * @msg_enable: Ethtool msg level
1220 * @ethsys: The register map pointing at the range used to setup
1221 * MII modes
1222 * @infra: The register map pointing at the range used to setup
1223 * SGMII and GePHY path
1224 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
1225 * @pctl: The register map pointing at the range used to setup
1226 * GMAC port drive/slew values
1227 * @dma_refcnt: track how many netdevs are using the DMA engine
1228 * @tx_ring: Pointer to the memory holding info about the TX ring
1229 * @rx_ring: Pointer to the memory holding info about the RX ring
1230 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
1231 * @tx_napi: The TX NAPI struct
1232 * @rx_napi: The RX NAPI struct
1233 * @rx_events: Net DIM RX event counter
1234 * @rx_packets: Net DIM RX packet counter
1235 * @rx_bytes: Net DIM RX byte counter
1236 * @rx_dim: Net DIM RX context
1237 * @tx_events: Net DIM TX event counter
1238 * @tx_packets: Net DIM TX packet counter
1239 * @tx_bytes: Net DIM TX byte counter
1240 * @tx_dim: Net DIM TX context
1241 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
1242 * @phy_scratch_ring: physical address of scratch_ring
1243 * @scratch_head: The scratch memory that scratch_ring points to.
1244 * @clks: clock array for all clocks required
1245 * @mii_bus: If there is a bus we need to create an instance for it
1246 * @pending_work: The workqueue used to reset the dma ring
1247 * @state: Initialization and runtime state of the device
1248 * @soc: Holding specific data among vaious SoCs
1249 */
1250
1251 struct mtk_eth {
1252 struct device *dev;
1253 struct device *dma_dev;
1254 void __iomem *base;
1255 void *sram_base;
1256 spinlock_t page_lock;
1257 spinlock_t tx_irq_lock;
1258 spinlock_t rx_irq_lock;
1259 struct net_device *dummy_dev;
1260 struct net_device *netdev[MTK_MAX_DEVS];
1261 struct mtk_mac *mac[MTK_MAX_DEVS];
1262 int irq[3];
1263 u32 msg_enable;
1264 unsigned long sysclk;
1265 struct regmap *ethsys;
1266 struct regmap *infra;
1267 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
1268 struct regmap *pctl;
1269 bool hwlro;
1270 refcount_t dma_refcnt;
1271 struct mtk_tx_ring tx_ring;
1272 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
1273 struct mtk_rx_ring rx_ring_qdma;
1274 struct napi_struct tx_napi;
1275 struct napi_struct rx_napi;
1276 void *scratch_ring;
1277 dma_addr_t phy_scratch_ring;
1278 void *scratch_head[MTK_FQ_DMA_HEAD];
1279 struct clk *clks[MTK_CLK_MAX];
1280
1281 struct mii_bus *mii_bus;
1282 unsigned int mdc_divider;
1283 struct work_struct pending_work;
1284 unsigned long state;
1285
1286 const struct mtk_soc_data *soc;
1287
1288 spinlock_t dim_lock;
1289
1290 u32 rx_events;
1291 u32 rx_packets;
1292 u32 rx_bytes;
1293 struct dim rx_dim;
1294
1295 u32 tx_events;
1296 u32 tx_packets;
1297 u32 tx_bytes;
1298 struct dim tx_dim;
1299
1300 int ip_align;
1301
1302 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS];
1303
1304 struct mtk_ppe *ppe[3];
1305 struct rhashtable flow_table;
1306
1307 struct bpf_prog __rcu *prog;
1308
1309 struct {
1310 struct delayed_work monitor_work;
1311 u32 wdidx;
1312 u8 wdma_hang_count;
1313 u8 qdma_hang_count;
1314 u8 adma_hang_count;
1315 } reset;
1316 };
1317
1318 /* struct mtk_mac - the structure that holds the info about the MACs of the
1319 * SoC
1320 * @id: The number of the MAC
1321 * @interface: Interface mode kept for detecting change in hw settings
1322 * @of_node: Our devicetree node
1323 * @hw: Backpointer to our main datastruture
1324 * @hw_stats: Packet statistics counter
1325 */
1326 struct mtk_mac {
1327 int id;
1328 phy_interface_t interface;
1329 u8 ppe_idx;
1330 int speed;
1331 struct device_node *of_node;
1332 struct phylink *phylink;
1333 struct phylink_config phylink_config;
1334 struct mtk_eth *hw;
1335 struct mtk_hw_stats *hw_stats;
1336 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1337 int hwlro_ip_cnt;
1338 unsigned int syscfg0;
1339 struct notifier_block device_notifier;
1340 };
1341
1342 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
1343 extern const struct of_device_id of_mtk_match[];
1344
mtk_is_netsys_v1(struct mtk_eth * eth)1345 static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
1346 {
1347 return eth->soc->version == 1;
1348 }
1349
mtk_is_netsys_v2_or_greater(struct mtk_eth * eth)1350 static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
1351 {
1352 return eth->soc->version > 1;
1353 }
1354
mtk_is_netsys_v3_or_greater(struct mtk_eth * eth)1355 static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth)
1356 {
1357 return eth->soc->version > 2;
1358 }
1359
1360 static inline struct mtk_foe_entry *
mtk_foe_get_entry(struct mtk_ppe * ppe,u16 hash)1361 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
1362 {
1363 const struct mtk_soc_data *soc = ppe->eth->soc;
1364
1365 return ppe->foe_table + hash * soc->foe_entry_size;
1366 }
1367
mtk_get_ib1_ts_mask(struct mtk_eth * eth)1368 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
1369 {
1370 if (mtk_is_netsys_v2_or_greater(eth))
1371 return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
1372
1373 return MTK_FOE_IB1_BIND_TIMESTAMP;
1374 }
1375
mtk_get_ib1_ppoe_mask(struct mtk_eth * eth)1376 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
1377 {
1378 if (mtk_is_netsys_v2_or_greater(eth))
1379 return MTK_FOE_IB1_BIND_PPPOE_V2;
1380
1381 return MTK_FOE_IB1_BIND_PPPOE;
1382 }
1383
mtk_get_ib1_vlan_tag_mask(struct mtk_eth * eth)1384 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
1385 {
1386 if (mtk_is_netsys_v2_or_greater(eth))
1387 return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
1388
1389 return MTK_FOE_IB1_BIND_VLAN_TAG;
1390 }
1391
mtk_get_ib1_vlan_layer_mask(struct mtk_eth * eth)1392 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
1393 {
1394 if (mtk_is_netsys_v2_or_greater(eth))
1395 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
1396
1397 return MTK_FOE_IB1_BIND_VLAN_LAYER;
1398 }
1399
mtk_prep_ib1_vlan_layer(struct mtk_eth * eth,u32 val)1400 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
1401 {
1402 if (mtk_is_netsys_v2_or_greater(eth))
1403 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
1404
1405 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
1406 }
1407
mtk_get_ib1_vlan_layer(struct mtk_eth * eth,u32 val)1408 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
1409 {
1410 if (mtk_is_netsys_v2_or_greater(eth))
1411 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
1412
1413 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
1414 }
1415
mtk_get_ib1_pkt_type_mask(struct mtk_eth * eth)1416 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
1417 {
1418 if (mtk_is_netsys_v2_or_greater(eth))
1419 return MTK_FOE_IB1_PACKET_TYPE_V2;
1420
1421 return MTK_FOE_IB1_PACKET_TYPE;
1422 }
1423
mtk_get_ib1_pkt_type(struct mtk_eth * eth,u32 val)1424 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
1425 {
1426 if (mtk_is_netsys_v2_or_greater(eth))
1427 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
1428
1429 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
1430 }
1431
mtk_get_ib2_multicast_mask(struct mtk_eth * eth)1432 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
1433 {
1434 if (mtk_is_netsys_v2_or_greater(eth))
1435 return MTK_FOE_IB2_MULTICAST_V2;
1436
1437 return MTK_FOE_IB2_MULTICAST;
1438 }
1439
1440 /* read the hardware status register */
1441 void mtk_stats_update_mac(struct mtk_mac *mac);
1442
1443 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1444 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1445 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
1446
1447 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1448 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1449 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
1450
1451 int mtk_eth_offload_init(struct mtk_eth *eth, u8 id);
1452 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
1453 void *type_data);
1454 int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls,
1455 int ppe_index);
1456 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
1457 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
1458
1459
1460 #endif /* MTK_ETH_H */
1461