1 /*
2 * QEMU RX CPU
3 *
4 * Copyright (c) 2019 Yoshinori Sato
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "migration/vmstate.h"
24 #include "exec/cputlb.h"
25 #include "exec/page-protection.h"
26 #include "exec/translation-block.h"
27 #include "exec/target_page.h"
28 #include "hw/loader.h"
29 #include "fpu/softfloat.h"
30 #include "tcg/debug-assert.h"
31 #include "accel/tcg/cpu-ops.h"
32
rx_cpu_set_pc(CPUState * cs,vaddr value)33 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
34 {
35 RXCPU *cpu = RX_CPU(cs);
36
37 cpu->env.pc = value;
38 }
39
rx_cpu_get_pc(CPUState * cs)40 static vaddr rx_cpu_get_pc(CPUState *cs)
41 {
42 RXCPU *cpu = RX_CPU(cs);
43
44 return cpu->env.pc;
45 }
46
rx_get_tb_cpu_state(CPUState * cs)47 static TCGTBCPUState rx_get_tb_cpu_state(CPUState *cs)
48 {
49 CPURXState *env = cpu_env(cs);
50 uint32_t flags = 0;
51
52 flags = FIELD_DP32(flags, PSW, PM, env->psw_pm);
53 flags = FIELD_DP32(flags, PSW, U, env->psw_u);
54
55 return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
56 }
57
rx_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)58 static void rx_cpu_synchronize_from_tb(CPUState *cs,
59 const TranslationBlock *tb)
60 {
61 RXCPU *cpu = RX_CPU(cs);
62
63 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
64 cpu->env.pc = tb->pc;
65 }
66
rx_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)67 static void rx_restore_state_to_opc(CPUState *cs,
68 const TranslationBlock *tb,
69 const uint64_t *data)
70 {
71 RXCPU *cpu = RX_CPU(cs);
72
73 cpu->env.pc = data[0];
74 }
75
rx_cpu_has_work(CPUState * cs)76 static bool rx_cpu_has_work(CPUState *cs)
77 {
78 return cs->interrupt_request &
79 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
80 }
81
rx_cpu_mmu_index(CPUState * cs,bool ifunc)82 static int rx_cpu_mmu_index(CPUState *cs, bool ifunc)
83 {
84 return 0;
85 }
86
rx_cpu_reset_hold(Object * obj,ResetType type)87 static void rx_cpu_reset_hold(Object *obj, ResetType type)
88 {
89 CPUState *cs = CPU(obj);
90 RXCPUClass *rcc = RX_CPU_GET_CLASS(obj);
91 CPURXState *env = cpu_env(cs);
92 uint32_t *resetvec;
93
94 if (rcc->parent_phases.hold) {
95 rcc->parent_phases.hold(obj, type);
96 }
97
98 memset(env, 0, offsetof(CPURXState, end_reset_fields));
99
100 resetvec = rom_ptr(0xfffffffc, 4);
101 if (resetvec) {
102 /* In the case of kernel, it is ignored because it is not set. */
103 env->pc = ldl_p(resetvec);
104 }
105 rx_cpu_unpack_psw(env, 0, 1);
106 env->regs[0] = env->isp = env->usp = 0;
107 env->fpsw = 0;
108 set_flush_to_zero(1, &env->fp_status);
109 set_flush_inputs_to_zero(1, &env->fp_status);
110 /*
111 * TODO: this is not the correct NaN propagation rule for this
112 * architecture. The "RX Family User's Manual: Software" table 1.6
113 * defines the propagation rules as "prefer SNaN over QNaN;
114 * then prefer dest over source", which is float_2nan_prop_s_ab.
115 */
116 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
117 /* Default NaN value: sign bit clear, set frac msb */
118 set_float_default_nan_pattern(0b01000000, &env->fp_status);
119 /*
120 * TODO: "RX Family RXv1 Instruction Set Architecture" is not 100% clear
121 * on whether flush-to-zero should happen before or after rounding, but
122 * section 1.3.2 says that it happens when underflow is detected, and
123 * implies that underflow is detected after rounding. So this may not
124 * be the correct setting.
125 */
126 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
127 }
128
rx_cpu_class_by_name(const char * cpu_model)129 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
130 {
131 ObjectClass *oc;
132 char *typename;
133
134 oc = object_class_by_name(cpu_model);
135 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) {
136 return oc;
137 }
138 typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
139 oc = object_class_by_name(typename);
140 g_free(typename);
141
142 return oc;
143 }
144
rx_cpu_realize(DeviceState * dev,Error ** errp)145 static void rx_cpu_realize(DeviceState *dev, Error **errp)
146 {
147 CPUState *cs = CPU(dev);
148 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
149 Error *local_err = NULL;
150
151 cpu_exec_realizefn(cs, &local_err);
152 if (local_err != NULL) {
153 error_propagate(errp, local_err);
154 return;
155 }
156
157 qemu_init_vcpu(cs);
158 cpu_reset(cs);
159
160 rcc->parent_realize(dev, errp);
161 }
162
rx_cpu_set_irq(void * opaque,int no,int request)163 static void rx_cpu_set_irq(void *opaque, int no, int request)
164 {
165 RXCPU *cpu = opaque;
166 CPUState *cs = CPU(cpu);
167 int irq = request & 0xff;
168
169 static const int mask[] = {
170 [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
171 [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
172 };
173 if (irq) {
174 cpu->env.req_irq = irq;
175 cpu->env.req_ipl = (request >> 8) & 0x0f;
176 cpu_interrupt(cs, mask[no]);
177 } else {
178 cpu_reset_interrupt(cs, mask[no]);
179 }
180 }
181
rx_cpu_disas_set_info(CPUState * cpu,disassemble_info * info)182 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
183 {
184 info->endian = BFD_ENDIAN_LITTLE;
185 info->mach = bfd_mach_rx;
186 info->print_insn = print_insn_rx;
187 }
188
rx_cpu_tlb_fill(CPUState * cs,vaddr addr,int size,MMUAccessType access_type,int mmu_idx,bool probe,uintptr_t retaddr)189 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
190 MMUAccessType access_type, int mmu_idx,
191 bool probe, uintptr_t retaddr)
192 {
193 uint32_t address, physical, prot;
194
195 /* Linear mapping */
196 address = physical = addr & TARGET_PAGE_MASK;
197 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
198 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
199 return true;
200 }
201
rx_cpu_init(Object * obj)202 static void rx_cpu_init(Object *obj)
203 {
204 RXCPU *cpu = RX_CPU(obj);
205
206 qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
207 }
208
209 #include "hw/core/sysemu-cpu-ops.h"
210
211 static const struct SysemuCPUOps rx_sysemu_ops = {
212 .has_work = rx_cpu_has_work,
213 .get_phys_page_debug = rx_cpu_get_phys_page_debug,
214 };
215
216 static const TCGCPUOps rx_tcg_ops = {
217 /* MTTCG not yet supported: require strict ordering */
218 .guest_default_memory_order = TCG_MO_ALL,
219 .mttcg_supported = false,
220
221 .initialize = rx_translate_init,
222 .translate_code = rx_translate_code,
223 .get_tb_cpu_state = rx_get_tb_cpu_state,
224 .synchronize_from_tb = rx_cpu_synchronize_from_tb,
225 .restore_state_to_opc = rx_restore_state_to_opc,
226 .mmu_index = rx_cpu_mmu_index,
227 .tlb_fill = rx_cpu_tlb_fill,
228 .pointer_wrap = cpu_pointer_wrap_uint32,
229
230 .cpu_exec_interrupt = rx_cpu_exec_interrupt,
231 .cpu_exec_halt = rx_cpu_has_work,
232 .cpu_exec_reset = cpu_reset,
233 .do_interrupt = rx_cpu_do_interrupt,
234 };
235
rx_cpu_class_init(ObjectClass * klass,const void * data)236 static void rx_cpu_class_init(ObjectClass *klass, const void *data)
237 {
238 DeviceClass *dc = DEVICE_CLASS(klass);
239 CPUClass *cc = CPU_CLASS(klass);
240 RXCPUClass *rcc = RX_CPU_CLASS(klass);
241 ResettableClass *rc = RESETTABLE_CLASS(klass);
242
243 device_class_set_parent_realize(dc, rx_cpu_realize,
244 &rcc->parent_realize);
245 resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
246 &rcc->parent_phases);
247
248 cc->class_by_name = rx_cpu_class_by_name;
249 cc->dump_state = rx_cpu_dump_state;
250 cc->set_pc = rx_cpu_set_pc;
251 cc->get_pc = rx_cpu_get_pc;
252
253 cc->sysemu_ops = &rx_sysemu_ops;
254 cc->gdb_read_register = rx_cpu_gdb_read_register;
255 cc->gdb_write_register = rx_cpu_gdb_write_register;
256 cc->disas_set_info = rx_cpu_disas_set_info;
257
258 cc->gdb_core_xml_file = "rx-core.xml";
259 cc->tcg_ops = &rx_tcg_ops;
260 }
261
262 static const TypeInfo rx_cpu_info = {
263 .name = TYPE_RX_CPU,
264 .parent = TYPE_CPU,
265 .instance_size = sizeof(RXCPU),
266 .instance_align = __alignof(RXCPU),
267 .instance_init = rx_cpu_init,
268 .abstract = true,
269 .class_size = sizeof(RXCPUClass),
270 .class_init = rx_cpu_class_init,
271 };
272
273 static const TypeInfo rx62n_rx_cpu_info = {
274 .name = TYPE_RX62N_CPU,
275 .parent = TYPE_RX_CPU,
276 };
277
rx_cpu_register_types(void)278 static void rx_cpu_register_types(void)
279 {
280 type_register_static(&rx_cpu_info);
281 type_register_static(&rx62n_rx_cpu_info);
282 }
283
284 type_init(rx_cpu_register_types)
285