1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/irq.h>
12 #include <linux/pci.h>
13 #include <linux/sysfs.h>
14
15 #include "cgx.h"
16 #include "rvu.h"
17 #include "rvu_reg.h"
18 #include "ptp.h"
19 #include "mcs.h"
20
21 #include "rvu_trace.h"
22 #include "rvu_npc_hash.h"
23
24 #define DRV_NAME "rvu_af"
25 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
26
27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
28 struct rvu_block *block, int lf);
29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
30 struct rvu_block *block, int lf);
31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
32
33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
34 int type, int num,
35 void (mbox_handler)(struct work_struct *),
36 void (mbox_up_handler)(struct work_struct *));
37 enum {
38 TYPE_AFVF,
39 TYPE_AFPF,
40 };
41
42 /* Supported devices */
43 static const struct pci_device_id rvu_id_table[] = {
44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
45 { 0, } /* end of table */
46 };
47
48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
49 MODULE_DESCRIPTION(DRV_STRING);
50 MODULE_LICENSE("GPL v2");
51 MODULE_DEVICE_TABLE(pci, rvu_id_table);
52
53 static char *mkex_profile; /* MKEX profile name */
54 module_param(mkex_profile, charp, 0000);
55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
56
57 static char *kpu_profile; /* KPU profile name */
58 module_param(kpu_profile, charp, 0000);
59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string");
60
rvu_setup_hw_capabilities(struct rvu * rvu)61 static void rvu_setup_hw_capabilities(struct rvu *rvu)
62 {
63 struct rvu_hwinfo *hw = rvu->hw;
64
65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
66 hw->cap.nix_fixed_txschq_mapping = false;
67 hw->cap.nix_shaping = true;
68 hw->cap.nix_tx_link_bp = true;
69 hw->cap.nix_rx_multicast = true;
70 hw->cap.nix_shaper_toggle_wait = false;
71 hw->cap.npc_hash_extract = false;
72 hw->cap.npc_exact_match_enabled = false;
73 hw->rvu = rvu;
74
75 if (is_rvu_pre_96xx_C0(rvu)) {
76 hw->cap.nix_fixed_txschq_mapping = true;
77 hw->cap.nix_txsch_per_cgx_lmac = 4;
78 hw->cap.nix_txsch_per_lbk_lmac = 132;
79 hw->cap.nix_txsch_per_sdp_lmac = 76;
80 hw->cap.nix_shaping = false;
81 hw->cap.nix_tx_link_bp = false;
82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))
83 hw->cap.nix_rx_multicast = false;
84 }
85 if (!is_rvu_pre_96xx_C0(rvu))
86 hw->cap.nix_shaper_toggle_wait = true;
87
88 if (!is_rvu_otx2(rvu))
89 hw->cap.per_pf_mbox_regs = true;
90
91 if (is_rvu_npc_hash_extract_en(rvu))
92 hw->cap.npc_hash_extract = true;
93 }
94
95 /* Poll a RVU block's register 'offset', for a 'zero'
96 * or 'nonzero' at bits specified by 'mask'
97 */
rvu_poll_reg(struct rvu * rvu,u64 block,u64 offset,u64 mask,bool zero)98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
99 {
100 unsigned long timeout = jiffies + usecs_to_jiffies(20000);
101 bool twice = false;
102 void __iomem *reg;
103 u64 reg_val;
104
105 reg = rvu->afreg_base + ((block << 28) | offset);
106 again:
107 reg_val = readq(reg);
108 if (zero && !(reg_val & mask))
109 return 0;
110 if (!zero && (reg_val & mask))
111 return 0;
112 if (time_before(jiffies, timeout)) {
113 usleep_range(1, 5);
114 goto again;
115 }
116 /* In scenarios where CPU is scheduled out before checking
117 * 'time_before' (above) and gets scheduled in such that
118 * jiffies are beyond timeout value, then check again if HW is
119 * done with the operation in the meantime.
120 */
121 if (!twice) {
122 twice = true;
123 goto again;
124 }
125 return -EBUSY;
126 }
127
rvu_alloc_rsrc(struct rsrc_bmap * rsrc)128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
129 {
130 int id;
131
132 if (!rsrc->bmap)
133 return -EINVAL;
134
135 id = find_first_zero_bit(rsrc->bmap, rsrc->max);
136 if (id >= rsrc->max)
137 return -ENOSPC;
138
139 __set_bit(id, rsrc->bmap);
140
141 return id;
142 }
143
rvu_alloc_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc)144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
145 {
146 int start;
147
148 if (!rsrc->bmap)
149 return -EINVAL;
150
151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
152 if (start >= rsrc->max)
153 return -ENOSPC;
154
155 bitmap_set(rsrc->bmap, start, nrsrc);
156 return start;
157 }
158
rvu_free_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc,int start)159 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
160 {
161 if (!rsrc->bmap)
162 return;
163 if (start >= rsrc->max)
164 return;
165
166 bitmap_clear(rsrc->bmap, start, nrsrc);
167 }
168
rvu_rsrc_check_contig(struct rsrc_bmap * rsrc,int nrsrc)169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
170 {
171 int start;
172
173 if (!rsrc->bmap)
174 return false;
175
176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
177 if (start >= rsrc->max)
178 return false;
179
180 return true;
181 }
182
rvu_free_rsrc(struct rsrc_bmap * rsrc,int id)183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
184 {
185 if (!rsrc->bmap)
186 return;
187
188 __clear_bit(id, rsrc->bmap);
189 }
190
rvu_rsrc_free_count(struct rsrc_bmap * rsrc)191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
192 {
193 int used;
194
195 if (!rsrc->bmap)
196 return 0;
197
198 used = bitmap_weight(rsrc->bmap, rsrc->max);
199 return (rsrc->max - used);
200 }
201
is_rsrc_free(struct rsrc_bmap * rsrc,int id)202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id)
203 {
204 if (!rsrc->bmap)
205 return false;
206
207 return !test_bit(id, rsrc->bmap);
208 }
209
rvu_alloc_bitmap(struct rsrc_bmap * rsrc)210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
211 {
212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
213 sizeof(long), GFP_KERNEL);
214 if (!rsrc->bmap)
215 return -ENOMEM;
216 return 0;
217 }
218
rvu_free_bitmap(struct rsrc_bmap * rsrc)219 void rvu_free_bitmap(struct rsrc_bmap *rsrc)
220 {
221 kfree(rsrc->bmap);
222 }
223
224 /* Get block LF's HW index from a PF_FUNC's block slot number */
rvu_get_lf(struct rvu * rvu,struct rvu_block * block,u16 pcifunc,u16 slot)225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
226 {
227 u16 match = 0;
228 int lf;
229
230 mutex_lock(&rvu->rsrc_lock);
231 for (lf = 0; lf < block->lf.max; lf++) {
232 if (block->fn_map[lf] == pcifunc) {
233 if (slot == match) {
234 mutex_unlock(&rvu->rsrc_lock);
235 return lf;
236 }
237 match++;
238 }
239 }
240 mutex_unlock(&rvu->rsrc_lock);
241 return -ENODEV;
242 }
243
244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
245 * Some silicon variants of OcteonTX2 supports
246 * multiple blocks of same type.
247 *
248 * @pcifunc has to be zero when no LF is yet attached.
249 *
250 * For a pcifunc if LFs are attached from multiple blocks of same type, then
251 * return blkaddr of first encountered block.
252 */
rvu_get_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc)253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
254 {
255 int devnum, blkaddr = -ENODEV;
256 u64 cfg, reg;
257 bool is_pf;
258
259 switch (blktype) {
260 case BLKTYPE_NPC:
261 blkaddr = BLKADDR_NPC;
262 goto exit;
263 case BLKTYPE_NPA:
264 blkaddr = BLKADDR_NPA;
265 goto exit;
266 case BLKTYPE_NIX:
267 /* For now assume NIX0 */
268 if (!pcifunc) {
269 blkaddr = BLKADDR_NIX0;
270 goto exit;
271 }
272 break;
273 case BLKTYPE_SSO:
274 blkaddr = BLKADDR_SSO;
275 goto exit;
276 case BLKTYPE_SSOW:
277 blkaddr = BLKADDR_SSOW;
278 goto exit;
279 case BLKTYPE_TIM:
280 blkaddr = BLKADDR_TIM;
281 goto exit;
282 case BLKTYPE_CPT:
283 /* For now assume CPT0 */
284 if (!pcifunc) {
285 blkaddr = BLKADDR_CPT0;
286 goto exit;
287 }
288 break;
289 }
290
291 /* Check if this is a RVU PF or VF */
292 if (pcifunc & RVU_PFVF_FUNC_MASK) {
293 is_pf = false;
294 devnum = rvu_get_hwvf(rvu, pcifunc);
295 } else {
296 is_pf = true;
297 devnum = rvu_get_pf(pcifunc);
298 }
299
300 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or
301 * 'BLKADDR_NIX1'.
302 */
303 if (blktype == BLKTYPE_NIX) {
304 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) :
305 RVU_PRIV_HWVFX_NIXX_CFG(0);
306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
307 if (cfg) {
308 blkaddr = BLKADDR_NIX0;
309 goto exit;
310 }
311
312 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) :
313 RVU_PRIV_HWVFX_NIXX_CFG(1);
314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
315 if (cfg)
316 blkaddr = BLKADDR_NIX1;
317 }
318
319 if (blktype == BLKTYPE_CPT) {
320 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) :
321 RVU_PRIV_HWVFX_CPTX_CFG(0);
322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
323 if (cfg) {
324 blkaddr = BLKADDR_CPT0;
325 goto exit;
326 }
327
328 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) :
329 RVU_PRIV_HWVFX_CPTX_CFG(1);
330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
331 if (cfg)
332 blkaddr = BLKADDR_CPT1;
333 }
334
335 exit:
336 if (is_block_implemented(rvu->hw, blkaddr))
337 return blkaddr;
338 return -ENODEV;
339 }
340
rvu_update_rsrc_map(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,u16 pcifunc,u16 lf,bool attach)341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
342 struct rvu_block *block, u16 pcifunc,
343 u16 lf, bool attach)
344 {
345 int devnum, num_lfs = 0;
346 bool is_pf;
347 u64 reg;
348
349 if (lf >= block->lf.max) {
350 dev_err(&rvu->pdev->dev,
351 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
352 __func__, lf, block->name, block->lf.max);
353 return;
354 }
355
356 /* Check if this is for a RVU PF or VF */
357 if (pcifunc & RVU_PFVF_FUNC_MASK) {
358 is_pf = false;
359 devnum = rvu_get_hwvf(rvu, pcifunc);
360 } else {
361 is_pf = true;
362 devnum = rvu_get_pf(pcifunc);
363 }
364
365 block->fn_map[lf] = attach ? pcifunc : 0;
366
367 switch (block->addr) {
368 case BLKADDR_NPA:
369 pfvf->npalf = attach ? true : false;
370 num_lfs = pfvf->npalf;
371 break;
372 case BLKADDR_NIX0:
373 case BLKADDR_NIX1:
374 pfvf->nixlf = attach ? true : false;
375 num_lfs = pfvf->nixlf;
376 break;
377 case BLKADDR_SSO:
378 attach ? pfvf->sso++ : pfvf->sso--;
379 num_lfs = pfvf->sso;
380 break;
381 case BLKADDR_SSOW:
382 attach ? pfvf->ssow++ : pfvf->ssow--;
383 num_lfs = pfvf->ssow;
384 break;
385 case BLKADDR_TIM:
386 attach ? pfvf->timlfs++ : pfvf->timlfs--;
387 num_lfs = pfvf->timlfs;
388 break;
389 case BLKADDR_CPT0:
390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
391 num_lfs = pfvf->cptlfs;
392 break;
393 case BLKADDR_CPT1:
394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--;
395 num_lfs = pfvf->cpt1_lfs;
396 break;
397 }
398
399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
400 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
401 }
402
rvu_get_pf(u16 pcifunc)403 inline int rvu_get_pf(u16 pcifunc)
404 {
405 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
406 }
407
rvu_get_pf_numvfs(struct rvu * rvu,int pf,int * numvfs,int * hwvf)408 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
409 {
410 u64 cfg;
411
412 /* Get numVFs attached to this PF and first HWVF */
413 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
414 if (numvfs)
415 *numvfs = (cfg >> 12) & 0xFF;
416 if (hwvf)
417 *hwvf = cfg & 0xFFF;
418 }
419
rvu_get_hwvf(struct rvu * rvu,int pcifunc)420 int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
421 {
422 int pf, func;
423 u64 cfg;
424
425 pf = rvu_get_pf(pcifunc);
426 func = pcifunc & RVU_PFVF_FUNC_MASK;
427
428 /* Get first HWVF attached to this PF */
429 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
430
431 return ((cfg & 0xFFF) + func - 1);
432 }
433
rvu_get_pfvf(struct rvu * rvu,int pcifunc)434 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
435 {
436 /* Check if it is a PF or VF */
437 if (pcifunc & RVU_PFVF_FUNC_MASK)
438 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
439 else
440 return &rvu->pf[rvu_get_pf(pcifunc)];
441 }
442
is_pf_func_valid(struct rvu * rvu,u16 pcifunc)443 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
444 {
445 int pf, vf, nvfs;
446 u64 cfg;
447
448 pf = rvu_get_pf(pcifunc);
449 if (pf >= rvu->hw->total_pfs)
450 return false;
451
452 if (!(pcifunc & RVU_PFVF_FUNC_MASK))
453 return true;
454
455 /* Check if VF is within number of VFs attached to this PF */
456 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
457 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
458 nvfs = (cfg >> 12) & 0xFF;
459 if (vf >= nvfs)
460 return false;
461
462 return true;
463 }
464
is_block_implemented(struct rvu_hwinfo * hw,int blkaddr)465 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
466 {
467 struct rvu_block *block;
468
469 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
470 return false;
471
472 block = &hw->block[blkaddr];
473 return block->implemented;
474 }
475
rvu_check_block_implemented(struct rvu * rvu)476 static void rvu_check_block_implemented(struct rvu *rvu)
477 {
478 struct rvu_hwinfo *hw = rvu->hw;
479 struct rvu_block *block;
480 int blkid;
481 u64 cfg;
482
483 /* For each block check if 'implemented' bit is set */
484 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
485 block = &hw->block[blkid];
486 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
487 if (cfg & BIT_ULL(11))
488 block->implemented = true;
489 }
490 }
491
rvu_setup_rvum_blk_revid(struct rvu * rvu)492 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
493 {
494 rvu_write64(rvu, BLKADDR_RVUM,
495 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
496 RVU_BLK_RVUM_REVID);
497 }
498
rvu_clear_rvum_blk_revid(struct rvu * rvu)499 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
500 {
501 rvu_write64(rvu, BLKADDR_RVUM,
502 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
503 }
504
rvu_lf_reset(struct rvu * rvu,struct rvu_block * block,int lf)505 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
506 {
507 int err;
508
509 if (!block->implemented)
510 return 0;
511
512 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
513 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
514 true);
515 return err;
516 }
517
rvu_block_reset(struct rvu * rvu,int blkaddr,u64 rst_reg)518 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
519 {
520 struct rvu_block *block = &rvu->hw->block[blkaddr];
521 int err;
522
523 if (!block->implemented)
524 return;
525
526 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
527 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
528 if (err) {
529 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr);
530 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY)
531 ;
532 }
533 }
534
rvu_reset_all_blocks(struct rvu * rvu)535 static void rvu_reset_all_blocks(struct rvu *rvu)
536 {
537 /* Do a HW reset of all RVU blocks */
538 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
539 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
540 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST);
541 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
542 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
543 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
544 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
545 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST);
546 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
547 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
548 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST);
549 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST);
550 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
551 }
552
rvu_scan_block(struct rvu * rvu,struct rvu_block * block)553 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
554 {
555 struct rvu_pfvf *pfvf;
556 u64 cfg;
557 int lf;
558
559 for (lf = 0; lf < block->lf.max; lf++) {
560 cfg = rvu_read64(rvu, block->addr,
561 block->lfcfg_reg | (lf << block->lfshift));
562 if (!(cfg & BIT_ULL(63)))
563 continue;
564
565 /* Set this resource as being used */
566 __set_bit(lf, block->lf.bmap);
567
568 /* Get, to whom this LF is attached */
569 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
570 rvu_update_rsrc_map(rvu, pfvf, block,
571 (cfg >> 8) & 0xFFFF, lf, true);
572
573 /* Set start MSIX vector for this LF within this PF/VF */
574 rvu_set_msix_offset(rvu, pfvf, block, lf);
575 }
576 }
577
rvu_check_min_msix_vec(struct rvu * rvu,int nvecs,int pf,int vf)578 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
579 {
580 int min_vecs;
581
582 if (!vf)
583 goto check_pf;
584
585 if (!nvecs) {
586 dev_warn(rvu->dev,
587 "PF%d:VF%d is configured with zero msix vectors, %d\n",
588 pf, vf - 1, nvecs);
589 }
590 return;
591
592 check_pf:
593 if (pf == 0)
594 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
595 else
596 min_vecs = RVU_PF_INT_VEC_CNT;
597
598 if (!(nvecs < min_vecs))
599 return;
600 dev_warn(rvu->dev,
601 "PF%d is configured with too few vectors, %d, min is %d\n",
602 pf, nvecs, min_vecs);
603 }
604
rvu_setup_msix_resources(struct rvu * rvu)605 static int rvu_setup_msix_resources(struct rvu *rvu)
606 {
607 struct rvu_hwinfo *hw = rvu->hw;
608 int pf, vf, numvfs, hwvf, err;
609 int nvecs, offset, max_msix;
610 struct rvu_pfvf *pfvf;
611 u64 cfg, phy_addr;
612 dma_addr_t iova;
613
614 for (pf = 0; pf < hw->total_pfs; pf++) {
615 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
616 /* If PF is not enabled, nothing to do */
617 if (!((cfg >> 20) & 0x01))
618 continue;
619
620 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
621
622 pfvf = &rvu->pf[pf];
623 /* Get num of MSIX vectors attached to this PF */
624 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
625 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
626 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
627
628 /* Alloc msix bitmap for this PF */
629 err = rvu_alloc_bitmap(&pfvf->msix);
630 if (err)
631 return err;
632
633 /* Allocate memory for MSIX vector to RVU block LF mapping */
634 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
635 sizeof(u16), GFP_KERNEL);
636 if (!pfvf->msix_lfmap)
637 return -ENOMEM;
638
639 /* For PF0 (AF) firmware will set msix vector offsets for
640 * AF, block AF and PF0_INT vectors, so jump to VFs.
641 */
642 if (!pf)
643 goto setup_vfmsix;
644
645 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
646 * These are allocated on driver init and never freed,
647 * so no need to set 'msix_lfmap' for these.
648 */
649 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
650 nvecs = (cfg >> 12) & 0xFF;
651 cfg &= ~0x7FFULL;
652 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
653 rvu_write64(rvu, BLKADDR_RVUM,
654 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
655 setup_vfmsix:
656 /* Alloc msix bitmap for VFs */
657 for (vf = 0; vf < numvfs; vf++) {
658 pfvf = &rvu->hwvf[hwvf + vf];
659 /* Get num of MSIX vectors attached to this VF */
660 cfg = rvu_read64(rvu, BLKADDR_RVUM,
661 RVU_PRIV_PFX_MSIX_CFG(pf));
662 pfvf->msix.max = (cfg & 0xFFF) + 1;
663 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
664
665 /* Alloc msix bitmap for this VF */
666 err = rvu_alloc_bitmap(&pfvf->msix);
667 if (err)
668 return err;
669
670 pfvf->msix_lfmap =
671 devm_kcalloc(rvu->dev, pfvf->msix.max,
672 sizeof(u16), GFP_KERNEL);
673 if (!pfvf->msix_lfmap)
674 return -ENOMEM;
675
676 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
677 * These are allocated on driver init and never freed,
678 * so no need to set 'msix_lfmap' for these.
679 */
680 cfg = rvu_read64(rvu, BLKADDR_RVUM,
681 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
682 nvecs = (cfg >> 12) & 0xFF;
683 cfg &= ~0x7FFULL;
684 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
685 rvu_write64(rvu, BLKADDR_RVUM,
686 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
687 cfg | offset);
688 }
689 }
690
691 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
692 * create an IOMMU mapping for the physical address configured by
693 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
694 */
695 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
696 max_msix = cfg & 0xFFFFF;
697 if (rvu->fwdata && rvu->fwdata->msixtr_base)
698 phy_addr = rvu->fwdata->msixtr_base;
699 else
700 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
701
702 iova = dma_map_resource(rvu->dev, phy_addr,
703 max_msix * PCI_MSIX_ENTRY_SIZE,
704 DMA_BIDIRECTIONAL, 0);
705
706 if (dma_mapping_error(rvu->dev, iova))
707 return -ENOMEM;
708
709 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
710 rvu->msix_base_iova = iova;
711 rvu->msixtr_base_phy = phy_addr;
712
713 return 0;
714 }
715
rvu_reset_msix(struct rvu * rvu)716 static void rvu_reset_msix(struct rvu *rvu)
717 {
718 /* Restore msixtr base register */
719 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
720 rvu->msixtr_base_phy);
721 }
722
rvu_free_hw_resources(struct rvu * rvu)723 static void rvu_free_hw_resources(struct rvu *rvu)
724 {
725 struct rvu_hwinfo *hw = rvu->hw;
726 struct rvu_block *block;
727 struct rvu_pfvf *pfvf;
728 int id, max_msix;
729 u64 cfg;
730
731 rvu_npa_freemem(rvu);
732 rvu_npc_freemem(rvu);
733 rvu_nix_freemem(rvu);
734
735 /* Free block LF bitmaps */
736 for (id = 0; id < BLK_COUNT; id++) {
737 block = &hw->block[id];
738 kfree(block->lf.bmap);
739 }
740
741 /* Free MSIX bitmaps */
742 for (id = 0; id < hw->total_pfs; id++) {
743 pfvf = &rvu->pf[id];
744 kfree(pfvf->msix.bmap);
745 }
746
747 for (id = 0; id < hw->total_vfs; id++) {
748 pfvf = &rvu->hwvf[id];
749 kfree(pfvf->msix.bmap);
750 }
751
752 /* Unmap MSIX vector base IOVA mapping */
753 if (!rvu->msix_base_iova)
754 return;
755 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
756 max_msix = cfg & 0xFFFFF;
757 dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
758 max_msix * PCI_MSIX_ENTRY_SIZE,
759 DMA_BIDIRECTIONAL, 0);
760
761 rvu_reset_msix(rvu);
762 mutex_destroy(&rvu->rsrc_lock);
763 }
764
rvu_setup_pfvf_macaddress(struct rvu * rvu)765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
766 {
767 struct rvu_hwinfo *hw = rvu->hw;
768 int pf, vf, numvfs, hwvf;
769 struct rvu_pfvf *pfvf;
770 u64 *mac;
771
772 for (pf = 0; pf < hw->total_pfs; pf++) {
773 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */
774 if (!pf)
775 goto lbkvf;
776
777 if (!is_pf_cgxmapped(rvu, pf))
778 continue;
779 /* Assign MAC address to PF */
780 pfvf = &rvu->pf[pf];
781 if (rvu->fwdata && pf < PF_MACNUM_MAX) {
782 mac = &rvu->fwdata->pf_macs[pf];
783 if (*mac)
784 u64_to_ether_addr(*mac, pfvf->mac_addr);
785 else
786 eth_random_addr(pfvf->mac_addr);
787 } else {
788 eth_random_addr(pfvf->mac_addr);
789 }
790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
791
792 lbkvf:
793 /* Assign MAC address to VFs*/
794 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
795 for (vf = 0; vf < numvfs; vf++, hwvf++) {
796 pfvf = &rvu->hwvf[hwvf];
797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
798 mac = &rvu->fwdata->vf_macs[hwvf];
799 if (*mac)
800 u64_to_ether_addr(*mac, pfvf->mac_addr);
801 else
802 eth_random_addr(pfvf->mac_addr);
803 } else {
804 eth_random_addr(pfvf->mac_addr);
805 }
806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
807 }
808 }
809 }
810
rvu_fwdata_init(struct rvu * rvu)811 static int rvu_fwdata_init(struct rvu *rvu)
812 {
813 u64 fwdbase;
814 int err;
815
816 /* Get firmware data base address */
817 err = cgx_get_fwdata_base(&fwdbase);
818 if (err)
819 goto fail;
820 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
821 if (!rvu->fwdata)
822 goto fail;
823 if (!is_rvu_fwdata_valid(rvu)) {
824 dev_err(rvu->dev,
825 "Mismatch in 'fwdata' struct btw kernel and firmware\n");
826 iounmap(rvu->fwdata);
827 rvu->fwdata = NULL;
828 return -EINVAL;
829 }
830 return 0;
831 fail:
832 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
833 return -EIO;
834 }
835
rvu_fwdata_exit(struct rvu * rvu)836 static void rvu_fwdata_exit(struct rvu *rvu)
837 {
838 if (rvu->fwdata)
839 iounmap(rvu->fwdata);
840 }
841
rvu_setup_nix_hw_resource(struct rvu * rvu,int blkaddr)842 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr)
843 {
844 struct rvu_hwinfo *hw = rvu->hw;
845 struct rvu_block *block;
846 int blkid;
847 u64 cfg;
848
849 /* Init NIX LF's bitmap */
850 block = &hw->block[blkaddr];
851 if (!block->implemented)
852 return 0;
853 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
854 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
855 block->lf.max = cfg & 0xFFF;
856 block->addr = blkaddr;
857 block->type = BLKTYPE_NIX;
858 block->lfshift = 8;
859 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
860 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid);
861 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid);
862 block->lfcfg_reg = NIX_PRIV_LFX_CFG;
863 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
864 block->lfreset_reg = NIX_AF_LF_RST;
865 block->rvu = rvu;
866 sprintf(block->name, "NIX%d", blkid);
867 rvu->nix_blkaddr[blkid] = blkaddr;
868 return rvu_alloc_bitmap(&block->lf);
869 }
870
rvu_setup_cpt_hw_resource(struct rvu * rvu,int blkaddr)871 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr)
872 {
873 struct rvu_hwinfo *hw = rvu->hw;
874 struct rvu_block *block;
875 int blkid;
876 u64 cfg;
877
878 /* Init CPT LF's bitmap */
879 block = &hw->block[blkaddr];
880 if (!block->implemented)
881 return 0;
882 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
883 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
884 block->lf.max = cfg & 0xFF;
885 block->addr = blkaddr;
886 block->type = BLKTYPE_CPT;
887 block->multislot = true;
888 block->lfshift = 3;
889 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
890 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid);
891 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid);
892 block->lfcfg_reg = CPT_PRIV_LFX_CFG;
893 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
894 block->lfreset_reg = CPT_AF_LF_RST;
895 block->rvu = rvu;
896 sprintf(block->name, "CPT%d", blkid);
897 return rvu_alloc_bitmap(&block->lf);
898 }
899
rvu_get_lbk_bufsize(struct rvu * rvu)900 static void rvu_get_lbk_bufsize(struct rvu *rvu)
901 {
902 struct pci_dev *pdev = NULL;
903 void __iomem *base;
904 u64 lbk_const;
905
906 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
907 PCI_DEVID_OCTEONTX2_LBK, pdev);
908 if (!pdev)
909 return;
910
911 base = pci_ioremap_bar(pdev, 0);
912 if (!base)
913 goto err_put;
914
915 lbk_const = readq(base + LBK_CONST);
916
917 /* cache fifo size */
918 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const);
919
920 iounmap(base);
921 err_put:
922 pci_dev_put(pdev);
923 }
924
rvu_setup_hw_resources(struct rvu * rvu)925 static int rvu_setup_hw_resources(struct rvu *rvu)
926 {
927 struct rvu_hwinfo *hw = rvu->hw;
928 struct rvu_block *block;
929 int blkid, err;
930 u64 cfg;
931
932 /* Get HW supported max RVU PF & VF count */
933 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
934 hw->total_pfs = (cfg >> 32) & 0xFF;
935 hw->total_vfs = (cfg >> 20) & 0xFFF;
936 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
937
938 if (!is_rvu_otx2(rvu))
939 rvu_apr_block_cn10k_init(rvu);
940
941 /* Init NPA LF's bitmap */
942 block = &hw->block[BLKADDR_NPA];
943 if (!block->implemented)
944 goto nix;
945 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
946 block->lf.max = (cfg >> 16) & 0xFFF;
947 block->addr = BLKADDR_NPA;
948 block->type = BLKTYPE_NPA;
949 block->lfshift = 8;
950 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
951 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
952 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
953 block->lfcfg_reg = NPA_PRIV_LFX_CFG;
954 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
955 block->lfreset_reg = NPA_AF_LF_RST;
956 block->rvu = rvu;
957 sprintf(block->name, "NPA");
958 err = rvu_alloc_bitmap(&block->lf);
959 if (err) {
960 dev_err(rvu->dev,
961 "%s: Failed to allocate NPA LF bitmap\n", __func__);
962 return err;
963 }
964
965 nix:
966 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0);
967 if (err) {
968 dev_err(rvu->dev,
969 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__);
970 return err;
971 }
972
973 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1);
974 if (err) {
975 dev_err(rvu->dev,
976 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__);
977 return err;
978 }
979
980 /* Init SSO group's bitmap */
981 block = &hw->block[BLKADDR_SSO];
982 if (!block->implemented)
983 goto ssow;
984 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
985 block->lf.max = cfg & 0xFFFF;
986 block->addr = BLKADDR_SSO;
987 block->type = BLKTYPE_SSO;
988 block->multislot = true;
989 block->lfshift = 3;
990 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
991 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
992 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
993 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
994 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
995 block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
996 block->rvu = rvu;
997 sprintf(block->name, "SSO GROUP");
998 err = rvu_alloc_bitmap(&block->lf);
999 if (err) {
1000 dev_err(rvu->dev,
1001 "%s: Failed to allocate SSO LF bitmap\n", __func__);
1002 return err;
1003 }
1004
1005 ssow:
1006 /* Init SSO workslot's bitmap */
1007 block = &hw->block[BLKADDR_SSOW];
1008 if (!block->implemented)
1009 goto tim;
1010 block->lf.max = (cfg >> 56) & 0xFF;
1011 block->addr = BLKADDR_SSOW;
1012 block->type = BLKTYPE_SSOW;
1013 block->multislot = true;
1014 block->lfshift = 3;
1015 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
1016 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
1017 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
1018 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
1019 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
1020 block->lfreset_reg = SSOW_AF_LF_HWS_RST;
1021 block->rvu = rvu;
1022 sprintf(block->name, "SSOWS");
1023 err = rvu_alloc_bitmap(&block->lf);
1024 if (err) {
1025 dev_err(rvu->dev,
1026 "%s: Failed to allocate SSOW LF bitmap\n", __func__);
1027 return err;
1028 }
1029
1030 tim:
1031 /* Init TIM LF's bitmap */
1032 block = &hw->block[BLKADDR_TIM];
1033 if (!block->implemented)
1034 goto cpt;
1035 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
1036 block->lf.max = cfg & 0xFFFF;
1037 block->addr = BLKADDR_TIM;
1038 block->type = BLKTYPE_TIM;
1039 block->multislot = true;
1040 block->lfshift = 3;
1041 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
1042 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
1043 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
1044 block->lfcfg_reg = TIM_PRIV_LFX_CFG;
1045 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
1046 block->lfreset_reg = TIM_AF_LF_RST;
1047 block->rvu = rvu;
1048 sprintf(block->name, "TIM");
1049 err = rvu_alloc_bitmap(&block->lf);
1050 if (err) {
1051 dev_err(rvu->dev,
1052 "%s: Failed to allocate TIM LF bitmap\n", __func__);
1053 return err;
1054 }
1055
1056 cpt:
1057 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0);
1058 if (err) {
1059 dev_err(rvu->dev,
1060 "%s: Failed to allocate CPT0 LF bitmap\n", __func__);
1061 return err;
1062 }
1063 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1);
1064 if (err) {
1065 dev_err(rvu->dev,
1066 "%s: Failed to allocate CPT1 LF bitmap\n", __func__);
1067 return err;
1068 }
1069
1070 /* Allocate memory for PFVF data */
1071 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
1072 sizeof(struct rvu_pfvf), GFP_KERNEL);
1073 if (!rvu->pf) {
1074 dev_err(rvu->dev,
1075 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__);
1076 return -ENOMEM;
1077 }
1078
1079 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
1080 sizeof(struct rvu_pfvf), GFP_KERNEL);
1081 if (!rvu->hwvf) {
1082 dev_err(rvu->dev,
1083 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__);
1084 return -ENOMEM;
1085 }
1086
1087 mutex_init(&rvu->rsrc_lock);
1088
1089 rvu_fwdata_init(rvu);
1090
1091 err = rvu_setup_msix_resources(rvu);
1092 if (err) {
1093 dev_err(rvu->dev,
1094 "%s: Failed to setup MSIX resources\n", __func__);
1095 return err;
1096 }
1097
1098 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1099 block = &hw->block[blkid];
1100 if (!block->lf.bmap)
1101 continue;
1102
1103 /* Allocate memory for block LF/slot to pcifunc mapping info */
1104 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
1105 sizeof(u16), GFP_KERNEL);
1106 if (!block->fn_map) {
1107 err = -ENOMEM;
1108 goto msix_err;
1109 }
1110
1111 /* Scan all blocks to check if low level firmware has
1112 * already provisioned any of the resources to a PF/VF.
1113 */
1114 rvu_scan_block(rvu, block);
1115 }
1116
1117 err = rvu_set_channels_base(rvu);
1118 if (err)
1119 goto msix_err;
1120
1121 err = rvu_npc_init(rvu);
1122 if (err) {
1123 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__);
1124 goto npc_err;
1125 }
1126
1127 err = rvu_cgx_init(rvu);
1128 if (err) {
1129 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__);
1130 goto cgx_err;
1131 }
1132
1133 err = rvu_npc_exact_init(rvu);
1134 if (err) {
1135 dev_err(rvu->dev, "failed to initialize exact match table\n");
1136 return err;
1137 }
1138
1139 /* Assign MACs for CGX mapped functions */
1140 rvu_setup_pfvf_macaddress(rvu);
1141
1142 err = rvu_npa_init(rvu);
1143 if (err) {
1144 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__);
1145 goto npa_err;
1146 }
1147
1148 rvu_get_lbk_bufsize(rvu);
1149
1150 err = rvu_nix_init(rvu);
1151 if (err) {
1152 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__);
1153 goto nix_err;
1154 }
1155
1156 err = rvu_sdp_init(rvu);
1157 if (err) {
1158 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);
1159 goto nix_err;
1160 }
1161
1162 rvu_program_channels(rvu);
1163
1164 err = rvu_mcs_init(rvu);
1165 if (err) {
1166 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__);
1167 goto nix_err;
1168 }
1169
1170 err = rvu_cpt_init(rvu);
1171 if (err) {
1172 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__);
1173 goto mcs_err;
1174 }
1175
1176 return 0;
1177
1178 mcs_err:
1179 rvu_mcs_exit(rvu);
1180 nix_err:
1181 rvu_nix_freemem(rvu);
1182 npa_err:
1183 rvu_npa_freemem(rvu);
1184 cgx_err:
1185 rvu_cgx_exit(rvu);
1186 npc_err:
1187 rvu_npc_freemem(rvu);
1188 rvu_fwdata_exit(rvu);
1189 msix_err:
1190 rvu_reset_msix(rvu);
1191 return err;
1192 }
1193
1194 /* NPA and NIX admin queue APIs */
rvu_aq_free(struct rvu * rvu,struct admin_queue * aq)1195 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
1196 {
1197 if (!aq)
1198 return;
1199
1200 qmem_free(rvu->dev, aq->inst);
1201 qmem_free(rvu->dev, aq->res);
1202 devm_kfree(rvu->dev, aq);
1203 }
1204
rvu_aq_alloc(struct rvu * rvu,struct admin_queue ** ad_queue,int qsize,int inst_size,int res_size)1205 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
1206 int qsize, int inst_size, int res_size)
1207 {
1208 struct admin_queue *aq;
1209 int err;
1210
1211 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
1212 if (!*ad_queue)
1213 return -ENOMEM;
1214 aq = *ad_queue;
1215
1216 /* Alloc memory for instructions i.e AQ */
1217 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
1218 if (err) {
1219 devm_kfree(rvu->dev, aq);
1220 return err;
1221 }
1222
1223 /* Alloc memory for results */
1224 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1225 if (err) {
1226 rvu_aq_free(rvu, aq);
1227 return err;
1228 }
1229
1230 spin_lock_init(&aq->lock);
1231 return 0;
1232 }
1233
rvu_mbox_handler_ready(struct rvu * rvu,struct msg_req * req,struct ready_msg_rsp * rsp)1234 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1235 struct ready_msg_rsp *rsp)
1236 {
1237 if (rvu->fwdata) {
1238 rsp->rclk_freq = rvu->fwdata->rclk;
1239 rsp->sclk_freq = rvu->fwdata->sclk;
1240 }
1241 return 0;
1242 }
1243
1244 /* Get current count of a RVU block's LF/slots
1245 * provisioned to a given RVU func.
1246 */
rvu_get_rsrc_mapcount(struct rvu_pfvf * pfvf,int blkaddr)1247 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr)
1248 {
1249 switch (blkaddr) {
1250 case BLKADDR_NPA:
1251 return pfvf->npalf ? 1 : 0;
1252 case BLKADDR_NIX0:
1253 case BLKADDR_NIX1:
1254 return pfvf->nixlf ? 1 : 0;
1255 case BLKADDR_SSO:
1256 return pfvf->sso;
1257 case BLKADDR_SSOW:
1258 return pfvf->ssow;
1259 case BLKADDR_TIM:
1260 return pfvf->timlfs;
1261 case BLKADDR_CPT0:
1262 return pfvf->cptlfs;
1263 case BLKADDR_CPT1:
1264 return pfvf->cpt1_lfs;
1265 }
1266 return 0;
1267 }
1268
1269 /* Return true if LFs of block type are attached to pcifunc */
is_blktype_attached(struct rvu_pfvf * pfvf,int blktype)1270 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype)
1271 {
1272 switch (blktype) {
1273 case BLKTYPE_NPA:
1274 return pfvf->npalf ? 1 : 0;
1275 case BLKTYPE_NIX:
1276 return pfvf->nixlf ? 1 : 0;
1277 case BLKTYPE_SSO:
1278 return !!pfvf->sso;
1279 case BLKTYPE_SSOW:
1280 return !!pfvf->ssow;
1281 case BLKTYPE_TIM:
1282 return !!pfvf->timlfs;
1283 case BLKTYPE_CPT:
1284 return pfvf->cptlfs || pfvf->cpt1_lfs;
1285 }
1286
1287 return false;
1288 }
1289
is_pffunc_map_valid(struct rvu * rvu,u16 pcifunc,int blktype)1290 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1291 {
1292 struct rvu_pfvf *pfvf;
1293
1294 if (!is_pf_func_valid(rvu, pcifunc))
1295 return false;
1296
1297 pfvf = rvu_get_pfvf(rvu, pcifunc);
1298
1299 /* Check if this PFFUNC has a LF of type blktype attached */
1300 if (!is_blktype_attached(pfvf, blktype))
1301 return false;
1302
1303 return true;
1304 }
1305
rvu_lookup_rsrc(struct rvu * rvu,struct rvu_block * block,int pcifunc,int slot)1306 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1307 int pcifunc, int slot)
1308 {
1309 u64 val;
1310
1311 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1312 rvu_write64(rvu, block->addr, block->lookup_reg, val);
1313 /* Wait for the lookup to finish */
1314 /* TODO: put some timeout here */
1315 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1316 ;
1317
1318 val = rvu_read64(rvu, block->addr, block->lookup_reg);
1319
1320 /* Check LF valid bit */
1321 if (!(val & (1ULL << 12)))
1322 return -1;
1323
1324 return (val & 0xFFF);
1325 }
1326
rvu_get_blkaddr_from_slot(struct rvu * rvu,int blktype,u16 pcifunc,u16 global_slot,u16 * slot_in_block)1327 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
1328 u16 global_slot, u16 *slot_in_block)
1329 {
1330 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1331 int numlfs, total_lfs = 0, nr_blocks = 0;
1332 int i, num_blkaddr[BLK_COUNT] = { 0 };
1333 struct rvu_block *block;
1334 int blkaddr;
1335 u16 start_slot;
1336
1337 if (!is_blktype_attached(pfvf, blktype))
1338 return -ENODEV;
1339
1340 /* Get all the block addresses from which LFs are attached to
1341 * the given pcifunc in num_blkaddr[].
1342 */
1343 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) {
1344 block = &rvu->hw->block[blkaddr];
1345 if (block->type != blktype)
1346 continue;
1347 if (!is_block_implemented(rvu->hw, blkaddr))
1348 continue;
1349
1350 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr);
1351 if (numlfs) {
1352 total_lfs += numlfs;
1353 num_blkaddr[nr_blocks] = blkaddr;
1354 nr_blocks++;
1355 }
1356 }
1357
1358 if (global_slot >= total_lfs)
1359 return -ENODEV;
1360
1361 /* Based on the given global slot number retrieve the
1362 * correct block address out of all attached block
1363 * addresses and slot number in that block.
1364 */
1365 total_lfs = 0;
1366 blkaddr = -ENODEV;
1367 for (i = 0; i < nr_blocks; i++) {
1368 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]);
1369 total_lfs += numlfs;
1370 if (global_slot < total_lfs) {
1371 blkaddr = num_blkaddr[i];
1372 start_slot = total_lfs - numlfs;
1373 *slot_in_block = global_slot - start_slot;
1374 break;
1375 }
1376 }
1377
1378 return blkaddr;
1379 }
1380
rvu_detach_block(struct rvu * rvu,int pcifunc,int blktype)1381 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1382 {
1383 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1384 struct rvu_hwinfo *hw = rvu->hw;
1385 struct rvu_block *block;
1386 int slot, lf, num_lfs;
1387 int blkaddr;
1388
1389 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1390 if (blkaddr < 0)
1391 return;
1392
1393 if (blktype == BLKTYPE_NIX)
1394 rvu_nix_reset_mac(pfvf, pcifunc);
1395
1396 block = &hw->block[blkaddr];
1397
1398 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1399 if (!num_lfs)
1400 return;
1401
1402 for (slot = 0; slot < num_lfs; slot++) {
1403 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1404 if (lf < 0) /* This should never happen */
1405 continue;
1406
1407 /* Disable the LF */
1408 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1409 (lf << block->lfshift), 0x00ULL);
1410
1411 /* Update SW maintained mapping info as well */
1412 rvu_update_rsrc_map(rvu, pfvf, block,
1413 pcifunc, lf, false);
1414
1415 /* Free the resource */
1416 rvu_free_rsrc(&block->lf, lf);
1417
1418 /* Clear MSIX vector offset for this LF */
1419 rvu_clear_msix_offset(rvu, pfvf, block, lf);
1420 }
1421 }
1422
rvu_detach_rsrcs(struct rvu * rvu,struct rsrc_detach * detach,u16 pcifunc)1423 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1424 u16 pcifunc)
1425 {
1426 struct rvu_hwinfo *hw = rvu->hw;
1427 bool detach_all = true;
1428 struct rvu_block *block;
1429 int blkid;
1430
1431 mutex_lock(&rvu->rsrc_lock);
1432
1433 /* Check for partial resource detach */
1434 if (detach && detach->partial)
1435 detach_all = false;
1436
1437 /* Check for RVU block's LFs attached to this func,
1438 * if so, detach them.
1439 */
1440 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1441 block = &hw->block[blkid];
1442 if (!block->lf.bmap)
1443 continue;
1444 if (!detach_all && detach) {
1445 if (blkid == BLKADDR_NPA && !detach->npalf)
1446 continue;
1447 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1448 continue;
1449 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf)
1450 continue;
1451 else if ((blkid == BLKADDR_SSO) && !detach->sso)
1452 continue;
1453 else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1454 continue;
1455 else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1456 continue;
1457 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1458 continue;
1459 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs)
1460 continue;
1461 }
1462 rvu_detach_block(rvu, pcifunc, block->type);
1463 }
1464
1465 mutex_unlock(&rvu->rsrc_lock);
1466 return 0;
1467 }
1468
rvu_mbox_handler_detach_resources(struct rvu * rvu,struct rsrc_detach * detach,struct msg_rsp * rsp)1469 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1470 struct rsrc_detach *detach,
1471 struct msg_rsp *rsp)
1472 {
1473 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1474 }
1475
rvu_get_nix_blkaddr(struct rvu * rvu,u16 pcifunc)1476 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
1477 {
1478 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1479 int blkaddr = BLKADDR_NIX0, vf;
1480 struct rvu_pfvf *pf;
1481
1482 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1483
1484 /* All CGX mapped PFs are set with assigned NIX block during init */
1485 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
1486 blkaddr = pf->nix_blkaddr;
1487 } else if (is_afvf(pcifunc)) {
1488 vf = pcifunc - 1;
1489 /* Assign NIX based on VF number. All even numbered VFs get
1490 * NIX0 and odd numbered gets NIX1
1491 */
1492 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0;
1493 /* NIX1 is not present on all silicons */
1494 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1495 blkaddr = BLKADDR_NIX0;
1496 }
1497
1498 /* if SDP1 then the blkaddr is NIX1 */
1499 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)
1500 blkaddr = BLKADDR_NIX1;
1501
1502 switch (blkaddr) {
1503 case BLKADDR_NIX1:
1504 pfvf->nix_blkaddr = BLKADDR_NIX1;
1505 pfvf->nix_rx_intf = NIX_INTFX_RX(1);
1506 pfvf->nix_tx_intf = NIX_INTFX_TX(1);
1507 break;
1508 case BLKADDR_NIX0:
1509 default:
1510 pfvf->nix_blkaddr = BLKADDR_NIX0;
1511 pfvf->nix_rx_intf = NIX_INTFX_RX(0);
1512 pfvf->nix_tx_intf = NIX_INTFX_TX(0);
1513 break;
1514 }
1515
1516 return pfvf->nix_blkaddr;
1517 }
1518
rvu_get_attach_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc,struct rsrc_attach * attach)1519 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype,
1520 u16 pcifunc, struct rsrc_attach *attach)
1521 {
1522 int blkaddr;
1523
1524 switch (blktype) {
1525 case BLKTYPE_NIX:
1526 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc);
1527 break;
1528 case BLKTYPE_CPT:
1529 if (attach->hdr.ver < RVU_MULTI_BLK_VER)
1530 return rvu_get_blkaddr(rvu, blktype, 0);
1531 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr :
1532 BLKADDR_CPT0;
1533 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
1534 return -ENODEV;
1535 break;
1536 default:
1537 return rvu_get_blkaddr(rvu, blktype, 0);
1538 }
1539
1540 if (is_block_implemented(rvu->hw, blkaddr))
1541 return blkaddr;
1542
1543 return -ENODEV;
1544 }
1545
rvu_attach_block(struct rvu * rvu,int pcifunc,int blktype,int num_lfs,struct rsrc_attach * attach)1546 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype,
1547 int num_lfs, struct rsrc_attach *attach)
1548 {
1549 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1550 struct rvu_hwinfo *hw = rvu->hw;
1551 struct rvu_block *block;
1552 int slot, lf;
1553 int blkaddr;
1554 u64 cfg;
1555
1556 if (!num_lfs)
1557 return;
1558
1559 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach);
1560 if (blkaddr < 0)
1561 return;
1562
1563 block = &hw->block[blkaddr];
1564 if (!block->lf.bmap)
1565 return;
1566
1567 for (slot = 0; slot < num_lfs; slot++) {
1568 /* Allocate the resource */
1569 lf = rvu_alloc_rsrc(&block->lf);
1570 if (lf < 0)
1571 return;
1572
1573 cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1574 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1575 (lf << block->lfshift), cfg);
1576 rvu_update_rsrc_map(rvu, pfvf, block,
1577 pcifunc, lf, true);
1578
1579 /* Set start MSIX vector for this LF within this PF/VF */
1580 rvu_set_msix_offset(rvu, pfvf, block, lf);
1581 }
1582 }
1583
rvu_check_rsrc_availability(struct rvu * rvu,struct rsrc_attach * req,u16 pcifunc)1584 static int rvu_check_rsrc_availability(struct rvu *rvu,
1585 struct rsrc_attach *req, u16 pcifunc)
1586 {
1587 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1588 int free_lfs, mappedlfs, blkaddr;
1589 struct rvu_hwinfo *hw = rvu->hw;
1590 struct rvu_block *block;
1591
1592 /* Only one NPA LF can be attached */
1593 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) {
1594 block = &hw->block[BLKADDR_NPA];
1595 free_lfs = rvu_rsrc_free_count(&block->lf);
1596 if (!free_lfs)
1597 goto fail;
1598 } else if (req->npalf) {
1599 dev_err(&rvu->pdev->dev,
1600 "Func 0x%x: Invalid req, already has NPA\n",
1601 pcifunc);
1602 return -EINVAL;
1603 }
1604
1605 /* Only one NIX LF can be attached */
1606 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) {
1607 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX,
1608 pcifunc, req);
1609 if (blkaddr < 0)
1610 return blkaddr;
1611 block = &hw->block[blkaddr];
1612 free_lfs = rvu_rsrc_free_count(&block->lf);
1613 if (!free_lfs)
1614 goto fail;
1615 } else if (req->nixlf) {
1616 dev_err(&rvu->pdev->dev,
1617 "Func 0x%x: Invalid req, already has NIX\n",
1618 pcifunc);
1619 return -EINVAL;
1620 }
1621
1622 if (req->sso) {
1623 block = &hw->block[BLKADDR_SSO];
1624 /* Is request within limits ? */
1625 if (req->sso > block->lf.max) {
1626 dev_err(&rvu->pdev->dev,
1627 "Func 0x%x: Invalid SSO req, %d > max %d\n",
1628 pcifunc, req->sso, block->lf.max);
1629 return -EINVAL;
1630 }
1631 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1632 free_lfs = rvu_rsrc_free_count(&block->lf);
1633 /* Check if additional resources are available */
1634 if (req->sso > mappedlfs &&
1635 ((req->sso - mappedlfs) > free_lfs))
1636 goto fail;
1637 }
1638
1639 if (req->ssow) {
1640 block = &hw->block[BLKADDR_SSOW];
1641 if (req->ssow > block->lf.max) {
1642 dev_err(&rvu->pdev->dev,
1643 "Func 0x%x: Invalid SSOW req, %d > max %d\n",
1644 pcifunc, req->sso, block->lf.max);
1645 return -EINVAL;
1646 }
1647 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1648 free_lfs = rvu_rsrc_free_count(&block->lf);
1649 if (req->ssow > mappedlfs &&
1650 ((req->ssow - mappedlfs) > free_lfs))
1651 goto fail;
1652 }
1653
1654 if (req->timlfs) {
1655 block = &hw->block[BLKADDR_TIM];
1656 if (req->timlfs > block->lf.max) {
1657 dev_err(&rvu->pdev->dev,
1658 "Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1659 pcifunc, req->timlfs, block->lf.max);
1660 return -EINVAL;
1661 }
1662 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1663 free_lfs = rvu_rsrc_free_count(&block->lf);
1664 if (req->timlfs > mappedlfs &&
1665 ((req->timlfs - mappedlfs) > free_lfs))
1666 goto fail;
1667 }
1668
1669 if (req->cptlfs) {
1670 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT,
1671 pcifunc, req);
1672 if (blkaddr < 0)
1673 return blkaddr;
1674 block = &hw->block[blkaddr];
1675 if (req->cptlfs > block->lf.max) {
1676 dev_err(&rvu->pdev->dev,
1677 "Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1678 pcifunc, req->cptlfs, block->lf.max);
1679 return -EINVAL;
1680 }
1681 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1682 free_lfs = rvu_rsrc_free_count(&block->lf);
1683 if (req->cptlfs > mappedlfs &&
1684 ((req->cptlfs - mappedlfs) > free_lfs))
1685 goto fail;
1686 }
1687
1688 return 0;
1689
1690 fail:
1691 dev_info(rvu->dev, "Request for %s failed\n", block->name);
1692 return -ENOSPC;
1693 }
1694
rvu_attach_from_same_block(struct rvu * rvu,int blktype,struct rsrc_attach * attach)1695 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype,
1696 struct rsrc_attach *attach)
1697 {
1698 int blkaddr, num_lfs;
1699
1700 blkaddr = rvu_get_attach_blkaddr(rvu, blktype,
1701 attach->hdr.pcifunc, attach);
1702 if (blkaddr < 0)
1703 return false;
1704
1705 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc),
1706 blkaddr);
1707 /* Requester already has LFs from given block ? */
1708 return !!num_lfs;
1709 }
1710
rvu_mbox_handler_attach_resources(struct rvu * rvu,struct rsrc_attach * attach,struct msg_rsp * rsp)1711 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1712 struct rsrc_attach *attach,
1713 struct msg_rsp *rsp)
1714 {
1715 u16 pcifunc = attach->hdr.pcifunc;
1716 int err;
1717
1718 /* If first request, detach all existing attached resources */
1719 if (!attach->modify)
1720 rvu_detach_rsrcs(rvu, NULL, pcifunc);
1721
1722 mutex_lock(&rvu->rsrc_lock);
1723
1724 /* Check if the request can be accommodated */
1725 err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1726 if (err)
1727 goto exit;
1728
1729 /* Now attach the requested resources */
1730 if (attach->npalf)
1731 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach);
1732
1733 if (attach->nixlf)
1734 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach);
1735
1736 if (attach->sso) {
1737 /* RVU func doesn't know which exact LF or slot is attached
1738 * to it, it always sees as slot 0,1,2. So for a 'modify'
1739 * request, simply detach all existing attached LFs/slots
1740 * and attach a fresh.
1741 */
1742 if (attach->modify)
1743 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1744 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO,
1745 attach->sso, attach);
1746 }
1747
1748 if (attach->ssow) {
1749 if (attach->modify)
1750 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1751 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW,
1752 attach->ssow, attach);
1753 }
1754
1755 if (attach->timlfs) {
1756 if (attach->modify)
1757 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1758 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM,
1759 attach->timlfs, attach);
1760 }
1761
1762 if (attach->cptlfs) {
1763 if (attach->modify &&
1764 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach))
1765 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1766 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT,
1767 attach->cptlfs, attach);
1768 }
1769
1770 exit:
1771 mutex_unlock(&rvu->rsrc_lock);
1772 return err;
1773 }
1774
rvu_get_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,int blkaddr,int lf)1775 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1776 int blkaddr, int lf)
1777 {
1778 u16 vec;
1779
1780 if (lf < 0)
1781 return MSIX_VECTOR_INVALID;
1782
1783 for (vec = 0; vec < pfvf->msix.max; vec++) {
1784 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1785 return vec;
1786 }
1787 return MSIX_VECTOR_INVALID;
1788 }
1789
rvu_set_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1790 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1791 struct rvu_block *block, int lf)
1792 {
1793 u16 nvecs, vec, offset;
1794 u64 cfg;
1795
1796 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1797 (lf << block->lfshift));
1798 nvecs = (cfg >> 12) & 0xFF;
1799
1800 /* Check and alloc MSIX vectors, must be contiguous */
1801 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1802 return;
1803
1804 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1805
1806 /* Config MSIX offset in LF */
1807 rvu_write64(rvu, block->addr, block->msixcfg_reg |
1808 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1809
1810 /* Update the bitmap as well */
1811 for (vec = 0; vec < nvecs; vec++)
1812 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1813 }
1814
rvu_clear_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1815 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1816 struct rvu_block *block, int lf)
1817 {
1818 u16 nvecs, vec, offset;
1819 u64 cfg;
1820
1821 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1822 (lf << block->lfshift));
1823 nvecs = (cfg >> 12) & 0xFF;
1824
1825 /* Clear MSIX offset in LF */
1826 rvu_write64(rvu, block->addr, block->msixcfg_reg |
1827 (lf << block->lfshift), cfg & ~0x7FFULL);
1828
1829 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1830
1831 /* Update the mapping */
1832 for (vec = 0; vec < nvecs; vec++)
1833 pfvf->msix_lfmap[offset + vec] = 0;
1834
1835 /* Free the same in MSIX bitmap */
1836 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1837 }
1838
rvu_mbox_handler_msix_offset(struct rvu * rvu,struct msg_req * req,struct msix_offset_rsp * rsp)1839 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1840 struct msix_offset_rsp *rsp)
1841 {
1842 struct rvu_hwinfo *hw = rvu->hw;
1843 u16 pcifunc = req->hdr.pcifunc;
1844 struct rvu_pfvf *pfvf;
1845 int lf, slot, blkaddr;
1846
1847 pfvf = rvu_get_pfvf(rvu, pcifunc);
1848 if (!pfvf->msix.bmap)
1849 return 0;
1850
1851 /* Set MSIX offsets for each block's LFs attached to this PF/VF */
1852 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1853 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1854
1855 /* Get BLKADDR from which LFs are attached to pcifunc */
1856 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1857 if (blkaddr < 0) {
1858 rsp->nix_msixoff = MSIX_VECTOR_INVALID;
1859 } else {
1860 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
1861 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf);
1862 }
1863
1864 rsp->sso = pfvf->sso;
1865 for (slot = 0; slot < rsp->sso; slot++) {
1866 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1867 rsp->sso_msixoff[slot] =
1868 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1869 }
1870
1871 rsp->ssow = pfvf->ssow;
1872 for (slot = 0; slot < rsp->ssow; slot++) {
1873 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1874 rsp->ssow_msixoff[slot] =
1875 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1876 }
1877
1878 rsp->timlfs = pfvf->timlfs;
1879 for (slot = 0; slot < rsp->timlfs; slot++) {
1880 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1881 rsp->timlf_msixoff[slot] =
1882 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1883 }
1884
1885 rsp->cptlfs = pfvf->cptlfs;
1886 for (slot = 0; slot < rsp->cptlfs; slot++) {
1887 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1888 rsp->cptlf_msixoff[slot] =
1889 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1890 }
1891
1892 rsp->cpt1_lfs = pfvf->cpt1_lfs;
1893 for (slot = 0; slot < rsp->cpt1_lfs; slot++) {
1894 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot);
1895 rsp->cpt1_lf_msixoff[slot] =
1896 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf);
1897 }
1898
1899 return 0;
1900 }
1901
rvu_mbox_handler_free_rsrc_cnt(struct rvu * rvu,struct msg_req * req,struct free_rsrcs_rsp * rsp)1902 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,
1903 struct free_rsrcs_rsp *rsp)
1904 {
1905 struct rvu_hwinfo *hw = rvu->hw;
1906 struct rvu_block *block;
1907 struct nix_txsch *txsch;
1908 struct nix_hw *nix_hw;
1909
1910 mutex_lock(&rvu->rsrc_lock);
1911
1912 block = &hw->block[BLKADDR_NPA];
1913 rsp->npa = rvu_rsrc_free_count(&block->lf);
1914
1915 block = &hw->block[BLKADDR_NIX0];
1916 rsp->nix = rvu_rsrc_free_count(&block->lf);
1917
1918 block = &hw->block[BLKADDR_NIX1];
1919 rsp->nix1 = rvu_rsrc_free_count(&block->lf);
1920
1921 block = &hw->block[BLKADDR_SSO];
1922 rsp->sso = rvu_rsrc_free_count(&block->lf);
1923
1924 block = &hw->block[BLKADDR_SSOW];
1925 rsp->ssow = rvu_rsrc_free_count(&block->lf);
1926
1927 block = &hw->block[BLKADDR_TIM];
1928 rsp->tim = rvu_rsrc_free_count(&block->lf);
1929
1930 block = &hw->block[BLKADDR_CPT0];
1931 rsp->cpt = rvu_rsrc_free_count(&block->lf);
1932
1933 block = &hw->block[BLKADDR_CPT1];
1934 rsp->cpt1 = rvu_rsrc_free_count(&block->lf);
1935
1936 if (rvu->hw->cap.nix_fixed_txschq_mapping) {
1937 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1;
1938 rsp->schq[NIX_TXSCH_LVL_TL4] = 1;
1939 rsp->schq[NIX_TXSCH_LVL_TL3] = 1;
1940 rsp->schq[NIX_TXSCH_LVL_TL2] = 1;
1941 /* NIX1 */
1942 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1943 goto out;
1944 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1;
1945 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1;
1946 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1;
1947 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1;
1948 } else {
1949 nix_hw = get_nix_hw(hw, BLKADDR_NIX0);
1950 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1951 rsp->schq[NIX_TXSCH_LVL_SMQ] =
1952 rvu_rsrc_free_count(&txsch->schq);
1953
1954 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1955 rsp->schq[NIX_TXSCH_LVL_TL4] =
1956 rvu_rsrc_free_count(&txsch->schq);
1957
1958 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1959 rsp->schq[NIX_TXSCH_LVL_TL3] =
1960 rvu_rsrc_free_count(&txsch->schq);
1961
1962 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1963 rsp->schq[NIX_TXSCH_LVL_TL2] =
1964 rvu_rsrc_free_count(&txsch->schq);
1965
1966 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1967 goto out;
1968
1969 nix_hw = get_nix_hw(hw, BLKADDR_NIX1);
1970 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1971 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] =
1972 rvu_rsrc_free_count(&txsch->schq);
1973
1974 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1975 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] =
1976 rvu_rsrc_free_count(&txsch->schq);
1977
1978 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1979 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] =
1980 rvu_rsrc_free_count(&txsch->schq);
1981
1982 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1983 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] =
1984 rvu_rsrc_free_count(&txsch->schq);
1985 }
1986
1987 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1;
1988 out:
1989 rsp->schq[NIX_TXSCH_LVL_TL1] = 1;
1990 mutex_unlock(&rvu->rsrc_lock);
1991
1992 return 0;
1993 }
1994
rvu_mbox_handler_vf_flr(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1995 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
1996 struct msg_rsp *rsp)
1997 {
1998 u16 pcifunc = req->hdr.pcifunc;
1999 u16 vf, numvfs;
2000 u64 cfg;
2001
2002 vf = pcifunc & RVU_PFVF_FUNC_MASK;
2003 cfg = rvu_read64(rvu, BLKADDR_RVUM,
2004 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc)));
2005 numvfs = (cfg >> 12) & 0xFF;
2006
2007 if (vf && vf <= numvfs)
2008 __rvu_flr_handler(rvu, pcifunc);
2009 else
2010 return RVU_INVALID_VF_ID;
2011
2012 return 0;
2013 }
2014
rvu_mbox_handler_get_hw_cap(struct rvu * rvu,struct msg_req * req,struct get_hw_cap_rsp * rsp)2015 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
2016 struct get_hw_cap_rsp *rsp)
2017 {
2018 struct rvu_hwinfo *hw = rvu->hw;
2019
2020 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
2021 rsp->nix_shaping = hw->cap.nix_shaping;
2022 rsp->npc_hash_extract = hw->cap.npc_hash_extract;
2023
2024 return 0;
2025 }
2026
rvu_mbox_handler_set_vf_perm(struct rvu * rvu,struct set_vf_perm * req,struct msg_rsp * rsp)2027 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
2028 struct msg_rsp *rsp)
2029 {
2030 struct rvu_hwinfo *hw = rvu->hw;
2031 u16 pcifunc = req->hdr.pcifunc;
2032 struct rvu_pfvf *pfvf;
2033 int blkaddr, nixlf;
2034 u16 target;
2035
2036 /* Only PF can add VF permissions */
2037 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc))
2038 return -EOPNOTSUPP;
2039
2040 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
2041 pfvf = rvu_get_pfvf(rvu, target);
2042
2043 if (req->flags & RESET_VF_PERM) {
2044 pfvf->flags &= RVU_CLEAR_VF_PERM;
2045 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^
2046 (req->flags & VF_TRUSTED)) {
2047 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags);
2048 /* disable multicast and promisc entries */
2049 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) {
2050 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target);
2051 if (blkaddr < 0)
2052 return 0;
2053 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
2054 target, 0);
2055 if (nixlf < 0)
2056 return 0;
2057 npc_enadis_default_mce_entry(rvu, target, nixlf,
2058 NIXLF_ALLMULTI_ENTRY,
2059 false);
2060 npc_enadis_default_mce_entry(rvu, target, nixlf,
2061 NIXLF_PROMISC_ENTRY,
2062 false);
2063 }
2064 }
2065
2066 return 0;
2067 }
2068
rvu_process_mbox_msg(struct otx2_mbox * mbox,int devid,struct mbox_msghdr * req)2069 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
2070 struct mbox_msghdr *req)
2071 {
2072 struct rvu *rvu = pci_get_drvdata(mbox->pdev);
2073
2074 /* Check if valid, if not reply with a invalid msg */
2075 if (req->sig != OTX2_MBOX_REQ_SIG)
2076 goto bad_message;
2077
2078 switch (req->id) {
2079 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
2080 case _id: { \
2081 struct _rsp_type *rsp; \
2082 int err; \
2083 \
2084 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
2085 mbox, devid, \
2086 sizeof(struct _rsp_type)); \
2087 /* some handlers should complete even if reply */ \
2088 /* could not be allocated */ \
2089 if (!rsp && \
2090 _id != MBOX_MSG_DETACH_RESOURCES && \
2091 _id != MBOX_MSG_NIX_TXSCH_FREE && \
2092 _id != MBOX_MSG_VF_FLR) \
2093 return -ENOMEM; \
2094 if (rsp) { \
2095 rsp->hdr.id = _id; \
2096 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
2097 rsp->hdr.pcifunc = req->pcifunc; \
2098 rsp->hdr.rc = 0; \
2099 } \
2100 \
2101 err = rvu_mbox_handler_ ## _fn_name(rvu, \
2102 (struct _req_type *)req, \
2103 rsp); \
2104 if (rsp && err) \
2105 rsp->hdr.rc = err; \
2106 \
2107 trace_otx2_msg_process(mbox->pdev, _id, err); \
2108 return rsp ? err : -ENOMEM; \
2109 }
2110 MBOX_MESSAGES
2111 #undef M
2112
2113 bad_message:
2114 default:
2115 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
2116 return -ENODEV;
2117 }
2118 }
2119
__rvu_mbox_handler(struct rvu_work * mwork,int type)2120 static void __rvu_mbox_handler(struct rvu_work *mwork, int type)
2121 {
2122 struct rvu *rvu = mwork->rvu;
2123 int offset, err, id, devid;
2124 struct otx2_mbox_dev *mdev;
2125 struct mbox_hdr *req_hdr;
2126 struct mbox_msghdr *msg;
2127 struct mbox_wq_info *mw;
2128 struct otx2_mbox *mbox;
2129
2130 switch (type) {
2131 case TYPE_AFPF:
2132 mw = &rvu->afpf_wq_info;
2133 break;
2134 case TYPE_AFVF:
2135 mw = &rvu->afvf_wq_info;
2136 break;
2137 default:
2138 return;
2139 }
2140
2141 devid = mwork - mw->mbox_wrk;
2142 mbox = &mw->mbox;
2143 mdev = &mbox->dev[devid];
2144
2145 /* Process received mbox messages */
2146 req_hdr = mdev->mbase + mbox->rx_start;
2147 if (mw->mbox_wrk[devid].num_msgs == 0)
2148 return;
2149
2150 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
2151
2152 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
2153 msg = mdev->mbase + offset;
2154
2155 /* Set which PF/VF sent this message based on mbox IRQ */
2156 switch (type) {
2157 case TYPE_AFPF:
2158 msg->pcifunc &=
2159 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
2160 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);
2161 break;
2162 case TYPE_AFVF:
2163 msg->pcifunc &=
2164 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
2165 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
2166 break;
2167 }
2168
2169 err = rvu_process_mbox_msg(mbox, devid, msg);
2170 if (!err) {
2171 offset = mbox->rx_start + msg->next_msgoff;
2172 continue;
2173 }
2174
2175 if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
2176 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
2177 err, otx2_mbox_id2name(msg->id),
2178 msg->id, rvu_get_pf(msg->pcifunc),
2179 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
2180 else
2181 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
2182 err, otx2_mbox_id2name(msg->id),
2183 msg->id, devid);
2184 }
2185 mw->mbox_wrk[devid].num_msgs = 0;
2186
2187 /* Send mbox responses to VF/PF */
2188 otx2_mbox_msg_send(mbox, devid);
2189 }
2190
rvu_afpf_mbox_handler(struct work_struct * work)2191 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
2192 {
2193 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2194
2195 __rvu_mbox_handler(mwork, TYPE_AFPF);
2196 }
2197
rvu_afvf_mbox_handler(struct work_struct * work)2198 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
2199 {
2200 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2201
2202 __rvu_mbox_handler(mwork, TYPE_AFVF);
2203 }
2204
__rvu_mbox_up_handler(struct rvu_work * mwork,int type)2205 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
2206 {
2207 struct rvu *rvu = mwork->rvu;
2208 struct otx2_mbox_dev *mdev;
2209 struct mbox_hdr *rsp_hdr;
2210 struct mbox_msghdr *msg;
2211 struct mbox_wq_info *mw;
2212 struct otx2_mbox *mbox;
2213 int offset, id, devid;
2214
2215 switch (type) {
2216 case TYPE_AFPF:
2217 mw = &rvu->afpf_wq_info;
2218 break;
2219 case TYPE_AFVF:
2220 mw = &rvu->afvf_wq_info;
2221 break;
2222 default:
2223 return;
2224 }
2225
2226 devid = mwork - mw->mbox_wrk_up;
2227 mbox = &mw->mbox_up;
2228 mdev = &mbox->dev[devid];
2229
2230 rsp_hdr = mdev->mbase + mbox->rx_start;
2231 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
2232 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
2233 return;
2234 }
2235
2236 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
2237
2238 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
2239 msg = mdev->mbase + offset;
2240
2241 if (msg->id >= MBOX_MSG_MAX) {
2242 dev_err(rvu->dev,
2243 "Mbox msg with unknown ID 0x%x\n", msg->id);
2244 goto end;
2245 }
2246
2247 if (msg->sig != OTX2_MBOX_RSP_SIG) {
2248 dev_err(rvu->dev,
2249 "Mbox msg with wrong signature %x, ID 0x%x\n",
2250 msg->sig, msg->id);
2251 goto end;
2252 }
2253
2254 switch (msg->id) {
2255 case MBOX_MSG_CGX_LINK_EVENT:
2256 break;
2257 default:
2258 if (msg->rc)
2259 dev_err(rvu->dev,
2260 "Mbox msg response has err %d, ID 0x%x\n",
2261 msg->rc, msg->id);
2262 break;
2263 }
2264 end:
2265 offset = mbox->rx_start + msg->next_msgoff;
2266 mdev->msgs_acked++;
2267 }
2268 mw->mbox_wrk_up[devid].up_num_msgs = 0;
2269
2270 otx2_mbox_reset(mbox, devid);
2271 }
2272
rvu_afpf_mbox_up_handler(struct work_struct * work)2273 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
2274 {
2275 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2276
2277 __rvu_mbox_up_handler(mwork, TYPE_AFPF);
2278 }
2279
rvu_afvf_mbox_up_handler(struct work_struct * work)2280 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
2281 {
2282 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2283
2284 __rvu_mbox_up_handler(mwork, TYPE_AFVF);
2285 }
2286
rvu_get_mbox_regions(struct rvu * rvu,void ** mbox_addr,int num,int type,unsigned long * pf_bmap)2287 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
2288 int num, int type, unsigned long *pf_bmap)
2289 {
2290 struct rvu_hwinfo *hw = rvu->hw;
2291 int region;
2292 u64 bar4;
2293
2294 /* For cn10k platform VF mailbox regions of a PF follows after the
2295 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from
2296 * RVU_PF_VF_BAR4_ADDR register.
2297 */
2298 if (type == TYPE_AFVF) {
2299 for (region = 0; region < num; region++) {
2300 if (!test_bit(region, pf_bmap))
2301 continue;
2302
2303 if (hw->cap.per_pf_mbox_regs) {
2304 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2305 RVU_AF_PFX_BAR4_ADDR(0)) +
2306 MBOX_SIZE;
2307 bar4 += region * MBOX_SIZE;
2308 } else {
2309 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
2310 bar4 += region * MBOX_SIZE;
2311 }
2312 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2313 if (!mbox_addr[region])
2314 goto error;
2315 }
2316 return 0;
2317 }
2318
2319 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per
2320 * PF registers. Whereas for Octeontx2 it is read from
2321 * RVU_AF_PF_BAR4_ADDR register.
2322 */
2323 for (region = 0; region < num; region++) {
2324 if (!test_bit(region, pf_bmap))
2325 continue;
2326
2327 if (hw->cap.per_pf_mbox_regs) {
2328 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2329 RVU_AF_PFX_BAR4_ADDR(region));
2330 } else {
2331 bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2332 RVU_AF_PF_BAR4_ADDR);
2333 bar4 += region * MBOX_SIZE;
2334 }
2335 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2336 if (!mbox_addr[region])
2337 goto error;
2338 }
2339 return 0;
2340
2341 error:
2342 while (region--)
2343 iounmap((void __iomem *)mbox_addr[region]);
2344 return -ENOMEM;
2345 }
2346
rvu_mbox_init(struct rvu * rvu,struct mbox_wq_info * mw,int type,int num,void (mbox_handler)(struct work_struct *),void (mbox_up_handler)(struct work_struct *))2347 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2348 int type, int num,
2349 void (mbox_handler)(struct work_struct *),
2350 void (mbox_up_handler)(struct work_struct *))
2351 {
2352 int err = -EINVAL, i, dir, dir_up;
2353 void __iomem *reg_base;
2354 struct rvu_work *mwork;
2355 unsigned long *pf_bmap;
2356 void **mbox_regions;
2357 const char *name;
2358 u64 cfg;
2359
2360 pf_bmap = bitmap_zalloc(num, GFP_KERNEL);
2361 if (!pf_bmap)
2362 return -ENOMEM;
2363
2364 /* RVU VFs */
2365 if (type == TYPE_AFVF)
2366 bitmap_set(pf_bmap, 0, num);
2367
2368 if (type == TYPE_AFPF) {
2369 /* Mark enabled PFs in bitmap */
2370 for (i = 0; i < num; i++) {
2371 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i));
2372 if (cfg & BIT_ULL(20))
2373 set_bit(i, pf_bmap);
2374 }
2375 }
2376
2377 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL);
2378 if (!mbox_regions) {
2379 err = -ENOMEM;
2380 goto free_bitmap;
2381 }
2382
2383 switch (type) {
2384 case TYPE_AFPF:
2385 name = "rvu_afpf_mailbox";
2386 dir = MBOX_DIR_AFPF;
2387 dir_up = MBOX_DIR_AFPF_UP;
2388 reg_base = rvu->afreg_base;
2389 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap);
2390 if (err)
2391 goto free_regions;
2392 break;
2393 case TYPE_AFVF:
2394 name = "rvu_afvf_mailbox";
2395 dir = MBOX_DIR_PFVF;
2396 dir_up = MBOX_DIR_PFVF_UP;
2397 reg_base = rvu->pfreg_base;
2398 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap);
2399 if (err)
2400 goto free_regions;
2401 break;
2402 default:
2403 goto free_regions;
2404 }
2405
2406 mw->mbox_wq = alloc_workqueue(name,
2407 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2408 num);
2409 if (!mw->mbox_wq) {
2410 err = -ENOMEM;
2411 goto unmap_regions;
2412 }
2413
2414 mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
2415 sizeof(struct rvu_work), GFP_KERNEL);
2416 if (!mw->mbox_wrk) {
2417 err = -ENOMEM;
2418 goto exit;
2419 }
2420
2421 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
2422 sizeof(struct rvu_work), GFP_KERNEL);
2423 if (!mw->mbox_wrk_up) {
2424 err = -ENOMEM;
2425 goto exit;
2426 }
2427
2428 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev,
2429 reg_base, dir, num, pf_bmap);
2430 if (err)
2431 goto exit;
2432
2433 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev,
2434 reg_base, dir_up, num, pf_bmap);
2435 if (err)
2436 goto exit;
2437
2438 for (i = 0; i < num; i++) {
2439 if (!test_bit(i, pf_bmap))
2440 continue;
2441
2442 mwork = &mw->mbox_wrk[i];
2443 mwork->rvu = rvu;
2444 INIT_WORK(&mwork->work, mbox_handler);
2445
2446 mwork = &mw->mbox_wrk_up[i];
2447 mwork->rvu = rvu;
2448 INIT_WORK(&mwork->work, mbox_up_handler);
2449 }
2450 goto free_regions;
2451
2452 exit:
2453 destroy_workqueue(mw->mbox_wq);
2454 unmap_regions:
2455 while (num--)
2456 iounmap((void __iomem *)mbox_regions[num]);
2457 free_regions:
2458 kfree(mbox_regions);
2459 free_bitmap:
2460 bitmap_free(pf_bmap);
2461 return err;
2462 }
2463
rvu_mbox_destroy(struct mbox_wq_info * mw)2464 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
2465 {
2466 struct otx2_mbox *mbox = &mw->mbox;
2467 struct otx2_mbox_dev *mdev;
2468 int devid;
2469
2470 if (mw->mbox_wq) {
2471 destroy_workqueue(mw->mbox_wq);
2472 mw->mbox_wq = NULL;
2473 }
2474
2475 for (devid = 0; devid < mbox->ndevs; devid++) {
2476 mdev = &mbox->dev[devid];
2477 if (mdev->hwbase)
2478 iounmap((void __iomem *)mdev->hwbase);
2479 }
2480
2481 otx2_mbox_destroy(&mw->mbox);
2482 otx2_mbox_destroy(&mw->mbox_up);
2483 }
2484
rvu_queue_work(struct mbox_wq_info * mw,int first,int mdevs,u64 intr)2485 static void rvu_queue_work(struct mbox_wq_info *mw, int first,
2486 int mdevs, u64 intr)
2487 {
2488 struct otx2_mbox_dev *mdev;
2489 struct otx2_mbox *mbox;
2490 struct mbox_hdr *hdr;
2491 int i;
2492
2493 for (i = first; i < mdevs; i++) {
2494 /* start from 0 */
2495 if (!(intr & BIT_ULL(i - first)))
2496 continue;
2497
2498 mbox = &mw->mbox;
2499 mdev = &mbox->dev[i];
2500 hdr = mdev->mbase + mbox->rx_start;
2501
2502 /*The hdr->num_msgs is set to zero immediately in the interrupt
2503 * handler to ensure that it holds a correct value next time
2504 * when the interrupt handler is called.
2505 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
2506 * pf>mbox.up_num_msgs holds the data for use in
2507 * pfaf_mbox_up_handler.
2508 */
2509
2510 if (hdr->num_msgs) {
2511 mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
2512 hdr->num_msgs = 0;
2513 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
2514 }
2515 mbox = &mw->mbox_up;
2516 mdev = &mbox->dev[i];
2517 hdr = mdev->mbase + mbox->rx_start;
2518 if (hdr->num_msgs) {
2519 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
2520 hdr->num_msgs = 0;
2521 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
2522 }
2523 }
2524 }
2525
rvu_mbox_intr_handler(int irq,void * rvu_irq)2526 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
2527 {
2528 struct rvu *rvu = (struct rvu *)rvu_irq;
2529 int vfs = rvu->vfs;
2530 u64 intr;
2531
2532 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
2533 /* Clear interrupts */
2534 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
2535 if (intr)
2536 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
2537
2538 /* Sync with mbox memory region */
2539 rmb();
2540
2541 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
2542
2543 /* Handle VF interrupts */
2544 if (vfs > 64) {
2545 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
2546 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
2547
2548 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
2549 vfs -= 64;
2550 }
2551
2552 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
2553 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
2554 if (intr)
2555 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
2556
2557 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
2558
2559 return IRQ_HANDLED;
2560 }
2561
rvu_enable_mbox_intr(struct rvu * rvu)2562 static void rvu_enable_mbox_intr(struct rvu *rvu)
2563 {
2564 struct rvu_hwinfo *hw = rvu->hw;
2565
2566 /* Clear spurious irqs, if any */
2567 rvu_write64(rvu, BLKADDR_RVUM,
2568 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
2569
2570 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
2571 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
2572 INTR_MASK(hw->total_pfs) & ~1ULL);
2573 }
2574
rvu_blklf_teardown(struct rvu * rvu,u16 pcifunc,u8 blkaddr)2575 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
2576 {
2577 struct rvu_block *block;
2578 int slot, lf, num_lfs;
2579 int err;
2580
2581 block = &rvu->hw->block[blkaddr];
2582 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
2583 block->addr);
2584 if (!num_lfs)
2585 return;
2586 for (slot = 0; slot < num_lfs; slot++) {
2587 lf = rvu_get_lf(rvu, block, pcifunc, slot);
2588 if (lf < 0)
2589 continue;
2590
2591 /* Cleanup LF and reset it */
2592 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1)
2593 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
2594 else if (block->addr == BLKADDR_NPA)
2595 rvu_npa_lf_teardown(rvu, pcifunc, lf);
2596 else if ((block->addr == BLKADDR_CPT0) ||
2597 (block->addr == BLKADDR_CPT1))
2598 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf,
2599 slot);
2600
2601 err = rvu_lf_reset(rvu, block, lf);
2602 if (err) {
2603 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
2604 block->addr, lf);
2605 }
2606 }
2607 }
2608
__rvu_flr_handler(struct rvu * rvu,u16 pcifunc)2609 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
2610 {
2611 if (rvu_npc_exact_has_match_table(rvu))
2612 rvu_npc_exact_reset(rvu, pcifunc);
2613
2614 mutex_lock(&rvu->flr_lock);
2615 /* Reset order should reflect inter-block dependencies:
2616 * 1. Reset any packet/work sources (NIX, CPT, TIM)
2617 * 2. Flush and reset SSO/SSOW
2618 * 3. Cleanup pools (NPA)
2619 */
2620
2621 /* Free multicast/mirror node associated with the 'pcifunc' */
2622 rvu_nix_mcast_flr_free_entries(rvu, pcifunc);
2623
2624 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
2625 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);
2626 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
2627 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1);
2628 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
2629 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2630 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2631 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2632 rvu_reset_lmt_map_tbl(rvu, pcifunc);
2633 rvu_detach_rsrcs(rvu, NULL, pcifunc);
2634 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM
2635 * entries, check and free the MCAM entries explicitly to avoid leak.
2636 * Since LF is detached use LF number as -1.
2637 */
2638 rvu_npc_free_mcam_entries(rvu, pcifunc, -1);
2639 rvu_mac_reset(rvu, pcifunc);
2640
2641 if (rvu->mcs_blk_cnt)
2642 rvu_mcs_flr_handler(rvu, pcifunc);
2643
2644 mutex_unlock(&rvu->flr_lock);
2645 }
2646
rvu_afvf_flr_handler(struct rvu * rvu,int vf)2647 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
2648 {
2649 int reg = 0;
2650
2651 /* pcifunc = 0(PF0) | (vf + 1) */
2652 __rvu_flr_handler(rvu, vf + 1);
2653
2654 if (vf >= 64) {
2655 reg = 1;
2656 vf = vf - 64;
2657 }
2658
2659 /* Signal FLR finish and enable IRQ */
2660 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
2661 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
2662 }
2663
rvu_flr_handler(struct work_struct * work)2664 static void rvu_flr_handler(struct work_struct *work)
2665 {
2666 struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
2667 struct rvu *rvu = flrwork->rvu;
2668 u16 pcifunc, numvfs, vf;
2669 u64 cfg;
2670 int pf;
2671
2672 pf = flrwork - rvu->flr_wrk;
2673 if (pf >= rvu->hw->total_pfs) {
2674 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2675 return;
2676 }
2677
2678 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2679 numvfs = (cfg >> 12) & 0xFF;
2680 pcifunc = pf << RVU_PFVF_PF_SHIFT;
2681
2682 for (vf = 0; vf < numvfs; vf++)
2683 __rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2684
2685 __rvu_flr_handler(rvu, pcifunc);
2686
2687 /* Signal FLR finish */
2688 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2689
2690 /* Enable interrupt */
2691 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf));
2692 }
2693
rvu_afvf_queue_flr_work(struct rvu * rvu,int start_vf,int numvfs)2694 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2695 {
2696 int dev, vf, reg = 0;
2697 u64 intr;
2698
2699 if (start_vf >= 64)
2700 reg = 1;
2701
2702 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2703 if (!intr)
2704 return;
2705
2706 for (vf = 0; vf < numvfs; vf++) {
2707 if (!(intr & BIT_ULL(vf)))
2708 continue;
2709 /* Clear and disable the interrupt */
2710 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2711 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2712
2713 dev = vf + start_vf + rvu->hw->total_pfs;
2714 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2715 }
2716 }
2717
rvu_flr_intr_handler(int irq,void * rvu_irq)2718 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2719 {
2720 struct rvu *rvu = (struct rvu *)rvu_irq;
2721 u64 intr;
2722 u8 pf;
2723
2724 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2725 if (!intr)
2726 goto afvf_flr;
2727
2728 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2729 if (intr & (1ULL << pf)) {
2730 /* clear interrupt */
2731 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2732 BIT_ULL(pf));
2733 /* Disable the interrupt */
2734 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2735 BIT_ULL(pf));
2736 /* PF is already dead do only AF related operations */
2737 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2738 }
2739 }
2740
2741 afvf_flr:
2742 rvu_afvf_queue_flr_work(rvu, 0, 64);
2743 if (rvu->vfs > 64)
2744 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2745
2746 return IRQ_HANDLED;
2747 }
2748
rvu_me_handle_vfset(struct rvu * rvu,int idx,u64 intr)2749 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2750 {
2751 int vf;
2752
2753 /* Nothing to be done here other than clearing the
2754 * TRPEND bit.
2755 */
2756 for (vf = 0; vf < 64; vf++) {
2757 if (intr & (1ULL << vf)) {
2758 /* clear the trpend due to ME(master enable) */
2759 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2760 /* clear interrupt */
2761 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2762 }
2763 }
2764 }
2765
2766 /* Handles ME interrupts from VFs of AF */
rvu_me_vf_intr_handler(int irq,void * rvu_irq)2767 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2768 {
2769 struct rvu *rvu = (struct rvu *)rvu_irq;
2770 int vfset;
2771 u64 intr;
2772
2773 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2774
2775 for (vfset = 0; vfset <= 1; vfset++) {
2776 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2777 if (intr)
2778 rvu_me_handle_vfset(rvu, vfset, intr);
2779 }
2780
2781 return IRQ_HANDLED;
2782 }
2783
2784 /* Handles ME interrupts from PFs */
rvu_me_pf_intr_handler(int irq,void * rvu_irq)2785 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2786 {
2787 struct rvu *rvu = (struct rvu *)rvu_irq;
2788 u64 intr;
2789 u8 pf;
2790
2791 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2792
2793 /* Nothing to be done here other than clearing the
2794 * TRPEND bit.
2795 */
2796 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2797 if (intr & (1ULL << pf)) {
2798 /* clear the trpend due to ME(master enable) */
2799 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2800 BIT_ULL(pf));
2801 /* clear interrupt */
2802 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2803 BIT_ULL(pf));
2804 }
2805 }
2806
2807 return IRQ_HANDLED;
2808 }
2809
rvu_unregister_interrupts(struct rvu * rvu)2810 static void rvu_unregister_interrupts(struct rvu *rvu)
2811 {
2812 int irq;
2813
2814 rvu_cpt_unregister_interrupts(rvu);
2815
2816 /* Disable the Mbox interrupt */
2817 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2818 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2819
2820 /* Disable the PF FLR interrupt */
2821 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2822 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2823
2824 /* Disable the PF ME interrupt */
2825 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2826 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2827
2828 for (irq = 0; irq < rvu->num_vec; irq++) {
2829 if (rvu->irq_allocated[irq]) {
2830 free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2831 rvu->irq_allocated[irq] = false;
2832 }
2833 }
2834
2835 pci_free_irq_vectors(rvu->pdev);
2836 rvu->num_vec = 0;
2837 }
2838
rvu_afvf_msix_vectors_num_ok(struct rvu * rvu)2839 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2840 {
2841 struct rvu_pfvf *pfvf = &rvu->pf[0];
2842 int offset;
2843
2844 pfvf = &rvu->pf[0];
2845 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2846
2847 /* Make sure there are enough MSIX vectors configured so that
2848 * VF interrupts can be handled. Offset equal to zero means
2849 * that PF vectors are not configured and overlapping AF vectors.
2850 */
2851 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
2852 offset;
2853 }
2854
rvu_register_interrupts(struct rvu * rvu)2855 static int rvu_register_interrupts(struct rvu *rvu)
2856 {
2857 int ret, offset, pf_vec_start;
2858
2859 rvu->num_vec = pci_msix_vec_count(rvu->pdev);
2860
2861 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
2862 NAME_SIZE, GFP_KERNEL);
2863 if (!rvu->irq_name)
2864 return -ENOMEM;
2865
2866 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
2867 sizeof(bool), GFP_KERNEL);
2868 if (!rvu->irq_allocated)
2869 return -ENOMEM;
2870
2871 /* Enable MSI-X */
2872 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
2873 rvu->num_vec, PCI_IRQ_MSIX);
2874 if (ret < 0) {
2875 dev_err(rvu->dev,
2876 "RVUAF: Request for %d msix vectors failed, ret %d\n",
2877 rvu->num_vec, ret);
2878 return ret;
2879 }
2880
2881 /* Register mailbox interrupt handler */
2882 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
2883 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
2884 rvu_mbox_intr_handler, 0,
2885 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
2886 if (ret) {
2887 dev_err(rvu->dev,
2888 "RVUAF: IRQ registration failed for mbox irq\n");
2889 goto fail;
2890 }
2891
2892 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
2893
2894 /* Enable mailbox interrupts from all PFs */
2895 rvu_enable_mbox_intr(rvu);
2896
2897 /* Register FLR interrupt handler */
2898 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2899 "RVUAF FLR");
2900 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
2901 rvu_flr_intr_handler, 0,
2902 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2903 rvu);
2904 if (ret) {
2905 dev_err(rvu->dev,
2906 "RVUAF: IRQ registration failed for FLR\n");
2907 goto fail;
2908 }
2909 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
2910
2911 /* Enable FLR interrupt for all PFs*/
2912 rvu_write64(rvu, BLKADDR_RVUM,
2913 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
2914
2915 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
2916 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2917
2918 /* Register ME interrupt handler */
2919 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2920 "RVUAF ME");
2921 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
2922 rvu_me_pf_intr_handler, 0,
2923 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2924 rvu);
2925 if (ret) {
2926 dev_err(rvu->dev,
2927 "RVUAF: IRQ registration failed for ME\n");
2928 }
2929 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
2930
2931 /* Clear TRPEND bit for all PF */
2932 rvu_write64(rvu, BLKADDR_RVUM,
2933 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
2934 /* Enable ME interrupt for all PFs*/
2935 rvu_write64(rvu, BLKADDR_RVUM,
2936 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
2937
2938 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
2939 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2940
2941 if (!rvu_afvf_msix_vectors_num_ok(rvu))
2942 return 0;
2943
2944 /* Get PF MSIX vectors offset. */
2945 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
2946 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2947
2948 /* Register MBOX0 interrupt. */
2949 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
2950 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
2951 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2952 rvu_mbox_intr_handler, 0,
2953 &rvu->irq_name[offset * NAME_SIZE],
2954 rvu);
2955 if (ret)
2956 dev_err(rvu->dev,
2957 "RVUAF: IRQ registration failed for Mbox0\n");
2958
2959 rvu->irq_allocated[offset] = true;
2960
2961 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
2962 * simply increment current offset by 1.
2963 */
2964 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
2965 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
2966 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2967 rvu_mbox_intr_handler, 0,
2968 &rvu->irq_name[offset * NAME_SIZE],
2969 rvu);
2970 if (ret)
2971 dev_err(rvu->dev,
2972 "RVUAF: IRQ registration failed for Mbox1\n");
2973
2974 rvu->irq_allocated[offset] = true;
2975
2976 /* Register FLR interrupt handler for AF's VFs */
2977 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
2978 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
2979 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2980 rvu_flr_intr_handler, 0,
2981 &rvu->irq_name[offset * NAME_SIZE], rvu);
2982 if (ret) {
2983 dev_err(rvu->dev,
2984 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
2985 goto fail;
2986 }
2987 rvu->irq_allocated[offset] = true;
2988
2989 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
2990 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
2991 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2992 rvu_flr_intr_handler, 0,
2993 &rvu->irq_name[offset * NAME_SIZE], rvu);
2994 if (ret) {
2995 dev_err(rvu->dev,
2996 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
2997 goto fail;
2998 }
2999 rvu->irq_allocated[offset] = true;
3000
3001 /* Register ME interrupt handler for AF's VFs */
3002 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
3003 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
3004 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3005 rvu_me_vf_intr_handler, 0,
3006 &rvu->irq_name[offset * NAME_SIZE], rvu);
3007 if (ret) {
3008 dev_err(rvu->dev,
3009 "RVUAF: IRQ registration failed for RVUAFVF ME0\n");
3010 goto fail;
3011 }
3012 rvu->irq_allocated[offset] = true;
3013
3014 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
3015 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
3016 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
3017 rvu_me_vf_intr_handler, 0,
3018 &rvu->irq_name[offset * NAME_SIZE], rvu);
3019 if (ret) {
3020 dev_err(rvu->dev,
3021 "RVUAF: IRQ registration failed for RVUAFVF ME1\n");
3022 goto fail;
3023 }
3024 rvu->irq_allocated[offset] = true;
3025
3026 ret = rvu_cpt_register_interrupts(rvu);
3027 if (ret)
3028 goto fail;
3029
3030 return 0;
3031
3032 fail:
3033 rvu_unregister_interrupts(rvu);
3034 return ret;
3035 }
3036
rvu_flr_wq_destroy(struct rvu * rvu)3037 static void rvu_flr_wq_destroy(struct rvu *rvu)
3038 {
3039 if (rvu->flr_wq) {
3040 destroy_workqueue(rvu->flr_wq);
3041 rvu->flr_wq = NULL;
3042 }
3043 }
3044
rvu_flr_init(struct rvu * rvu)3045 static int rvu_flr_init(struct rvu *rvu)
3046 {
3047 int dev, num_devs;
3048 u64 cfg;
3049 int pf;
3050
3051 /* Enable FLR for all PFs*/
3052 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
3053 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
3054 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
3055 cfg | BIT_ULL(22));
3056 }
3057
3058 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr",
3059 WQ_HIGHPRI | WQ_MEM_RECLAIM);
3060 if (!rvu->flr_wq)
3061 return -ENOMEM;
3062
3063 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
3064 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
3065 sizeof(struct rvu_work), GFP_KERNEL);
3066 if (!rvu->flr_wrk) {
3067 destroy_workqueue(rvu->flr_wq);
3068 return -ENOMEM;
3069 }
3070
3071 for (dev = 0; dev < num_devs; dev++) {
3072 rvu->flr_wrk[dev].rvu = rvu;
3073 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
3074 }
3075
3076 mutex_init(&rvu->flr_lock);
3077
3078 return 0;
3079 }
3080
rvu_disable_afvf_intr(struct rvu * rvu)3081 static void rvu_disable_afvf_intr(struct rvu *rvu)
3082 {
3083 int vfs = rvu->vfs;
3084
3085 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
3086 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
3087 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
3088 if (vfs <= 64)
3089 return;
3090
3091 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
3092 INTR_MASK(vfs - 64));
3093 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3094 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
3095 }
3096
rvu_enable_afvf_intr(struct rvu * rvu)3097 static void rvu_enable_afvf_intr(struct rvu *rvu)
3098 {
3099 int vfs = rvu->vfs;
3100
3101 /* Clear any pending interrupts and enable AF VF interrupts for
3102 * the first 64 VFs.
3103 */
3104 /* Mbox */
3105 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
3106 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
3107
3108 /* FLR */
3109 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
3110 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
3111 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
3112
3113 /* Same for remaining VFs, if any. */
3114 if (vfs <= 64)
3115 return;
3116
3117 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
3118 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
3119 INTR_MASK(vfs - 64));
3120
3121 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
3122 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3123 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3124 }
3125
rvu_get_num_lbk_chans(void)3126 int rvu_get_num_lbk_chans(void)
3127 {
3128 struct pci_dev *pdev;
3129 void __iomem *base;
3130 int ret = -EIO;
3131
3132 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
3133 NULL);
3134 if (!pdev)
3135 goto err;
3136
3137 base = pci_ioremap_bar(pdev, 0);
3138 if (!base)
3139 goto err_put;
3140
3141 /* Read number of available LBK channels from LBK(0)_CONST register. */
3142 ret = (readq(base + 0x10) >> 32) & 0xffff;
3143 iounmap(base);
3144 err_put:
3145 pci_dev_put(pdev);
3146 err:
3147 return ret;
3148 }
3149
rvu_enable_sriov(struct rvu * rvu)3150 static int rvu_enable_sriov(struct rvu *rvu)
3151 {
3152 struct pci_dev *pdev = rvu->pdev;
3153 int err, chans, vfs;
3154
3155 if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
3156 dev_warn(&pdev->dev,
3157 "Skipping SRIOV enablement since not enough IRQs are available\n");
3158 return 0;
3159 }
3160
3161 chans = rvu_get_num_lbk_chans();
3162 if (chans < 0)
3163 return chans;
3164
3165 vfs = pci_sriov_get_totalvfs(pdev);
3166
3167 /* Limit VFs in case we have more VFs than LBK channels available. */
3168 if (vfs > chans)
3169 vfs = chans;
3170
3171 if (!vfs)
3172 return 0;
3173
3174 /* LBK channel number 63 is used for switching packets between
3175 * CGX mapped VFs. Hence limit LBK pairs till 62 only.
3176 */
3177 if (vfs > 62)
3178 vfs = 62;
3179
3180 /* Save VFs number for reference in VF interrupts handlers.
3181 * Since interrupts might start arriving during SRIOV enablement
3182 * ordinary API cannot be used to get number of enabled VFs.
3183 */
3184 rvu->vfs = vfs;
3185
3186 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
3187 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
3188 if (err)
3189 return err;
3190
3191 rvu_enable_afvf_intr(rvu);
3192 /* Make sure IRQs are enabled before SRIOV. */
3193 mb();
3194
3195 err = pci_enable_sriov(pdev, vfs);
3196 if (err) {
3197 rvu_disable_afvf_intr(rvu);
3198 rvu_mbox_destroy(&rvu->afvf_wq_info);
3199 return err;
3200 }
3201
3202 return 0;
3203 }
3204
rvu_disable_sriov(struct rvu * rvu)3205 static void rvu_disable_sriov(struct rvu *rvu)
3206 {
3207 rvu_disable_afvf_intr(rvu);
3208 rvu_mbox_destroy(&rvu->afvf_wq_info);
3209 pci_disable_sriov(rvu->pdev);
3210 }
3211
rvu_update_module_params(struct rvu * rvu)3212 static void rvu_update_module_params(struct rvu *rvu)
3213 {
3214 const char *default_pfl_name = "default";
3215
3216 strscpy(rvu->mkex_pfl_name,
3217 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
3218 strscpy(rvu->kpu_pfl_name,
3219 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN);
3220 }
3221
rvu_probe(struct pci_dev * pdev,const struct pci_device_id * id)3222 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3223 {
3224 struct device *dev = &pdev->dev;
3225 struct rvu *rvu;
3226 int err;
3227
3228 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
3229 if (!rvu)
3230 return -ENOMEM;
3231
3232 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
3233 if (!rvu->hw) {
3234 devm_kfree(dev, rvu);
3235 return -ENOMEM;
3236 }
3237
3238 pci_set_drvdata(pdev, rvu);
3239 rvu->pdev = pdev;
3240 rvu->dev = &pdev->dev;
3241
3242 err = pci_enable_device(pdev);
3243 if (err) {
3244 dev_err(dev, "Failed to enable PCI device\n");
3245 goto err_freemem;
3246 }
3247
3248 err = pci_request_regions(pdev, DRV_NAME);
3249 if (err) {
3250 dev_err(dev, "PCI request regions failed 0x%x\n", err);
3251 goto err_disable_device;
3252 }
3253
3254 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
3255 if (err) {
3256 dev_err(dev, "DMA mask config failed, abort\n");
3257 goto err_release_regions;
3258 }
3259
3260 pci_set_master(pdev);
3261
3262 rvu->ptp = ptp_get();
3263 if (IS_ERR(rvu->ptp)) {
3264 err = PTR_ERR(rvu->ptp);
3265 if (err)
3266 goto err_release_regions;
3267 rvu->ptp = NULL;
3268 }
3269
3270 /* Map Admin function CSRs */
3271 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
3272 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
3273 if (!rvu->afreg_base || !rvu->pfreg_base) {
3274 dev_err(dev, "Unable to map admin function CSRs, aborting\n");
3275 err = -ENOMEM;
3276 goto err_put_ptp;
3277 }
3278
3279 /* Store module params in rvu structure */
3280 rvu_update_module_params(rvu);
3281
3282 /* Check which blocks the HW supports */
3283 rvu_check_block_implemented(rvu);
3284
3285 rvu_reset_all_blocks(rvu);
3286
3287 rvu_setup_hw_capabilities(rvu);
3288
3289 err = rvu_setup_hw_resources(rvu);
3290 if (err)
3291 goto err_put_ptp;
3292
3293 /* Init mailbox btw AF and PFs */
3294 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
3295 rvu->hw->total_pfs, rvu_afpf_mbox_handler,
3296 rvu_afpf_mbox_up_handler);
3297 if (err) {
3298 dev_err(dev, "%s: Failed to initialize mbox\n", __func__);
3299 goto err_hwsetup;
3300 }
3301
3302 err = rvu_flr_init(rvu);
3303 if (err) {
3304 dev_err(dev, "%s: Failed to initialize flr\n", __func__);
3305 goto err_mbox;
3306 }
3307
3308 err = rvu_register_interrupts(rvu);
3309 if (err) {
3310 dev_err(dev, "%s: Failed to register interrupts\n", __func__);
3311 goto err_flr;
3312 }
3313
3314 err = rvu_register_dl(rvu);
3315 if (err) {
3316 dev_err(dev, "%s: Failed to register devlink\n", __func__);
3317 goto err_irq;
3318 }
3319
3320 rvu_setup_rvum_blk_revid(rvu);
3321
3322 /* Enable AF's VFs (if any) */
3323 err = rvu_enable_sriov(rvu);
3324 if (err) {
3325 dev_err(dev, "%s: Failed to enable sriov\n", __func__);
3326 goto err_dl;
3327 }
3328
3329 /* Initialize debugfs */
3330 rvu_dbg_init(rvu);
3331
3332 mutex_init(&rvu->rswitch.switch_lock);
3333
3334 if (rvu->fwdata)
3335 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate,
3336 rvu->fwdata->ptp_ext_tstamp);
3337
3338 return 0;
3339 err_dl:
3340 rvu_unregister_dl(rvu);
3341 err_irq:
3342 rvu_unregister_interrupts(rvu);
3343 err_flr:
3344 rvu_flr_wq_destroy(rvu);
3345 err_mbox:
3346 rvu_mbox_destroy(&rvu->afpf_wq_info);
3347 err_hwsetup:
3348 rvu_cgx_exit(rvu);
3349 rvu_fwdata_exit(rvu);
3350 rvu_mcs_exit(rvu);
3351 rvu_reset_all_blocks(rvu);
3352 rvu_free_hw_resources(rvu);
3353 rvu_clear_rvum_blk_revid(rvu);
3354 err_put_ptp:
3355 ptp_put(rvu->ptp);
3356 err_release_regions:
3357 pci_release_regions(pdev);
3358 err_disable_device:
3359 pci_disable_device(pdev);
3360 err_freemem:
3361 pci_set_drvdata(pdev, NULL);
3362 devm_kfree(&pdev->dev, rvu->hw);
3363 devm_kfree(dev, rvu);
3364 return err;
3365 }
3366
rvu_remove(struct pci_dev * pdev)3367 static void rvu_remove(struct pci_dev *pdev)
3368 {
3369 struct rvu *rvu = pci_get_drvdata(pdev);
3370
3371 rvu_dbg_exit(rvu);
3372 rvu_unregister_dl(rvu);
3373 rvu_unregister_interrupts(rvu);
3374 rvu_flr_wq_destroy(rvu);
3375 rvu_cgx_exit(rvu);
3376 rvu_fwdata_exit(rvu);
3377 rvu_mcs_exit(rvu);
3378 rvu_mbox_destroy(&rvu->afpf_wq_info);
3379 rvu_disable_sriov(rvu);
3380 rvu_reset_all_blocks(rvu);
3381 rvu_free_hw_resources(rvu);
3382 rvu_clear_rvum_blk_revid(rvu);
3383 ptp_put(rvu->ptp);
3384 pci_release_regions(pdev);
3385 pci_disable_device(pdev);
3386 pci_set_drvdata(pdev, NULL);
3387
3388 devm_kfree(&pdev->dev, rvu->hw);
3389 devm_kfree(&pdev->dev, rvu);
3390 }
3391
3392 static struct pci_driver rvu_driver = {
3393 .name = DRV_NAME,
3394 .id_table = rvu_id_table,
3395 .probe = rvu_probe,
3396 .remove = rvu_remove,
3397 };
3398
rvu_init_module(void)3399 static int __init rvu_init_module(void)
3400 {
3401 int err;
3402
3403 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3404
3405 err = pci_register_driver(&cgx_driver);
3406 if (err < 0)
3407 return err;
3408
3409 err = pci_register_driver(&ptp_driver);
3410 if (err < 0)
3411 goto ptp_err;
3412
3413 err = pci_register_driver(&mcs_driver);
3414 if (err < 0)
3415 goto mcs_err;
3416
3417 err = pci_register_driver(&rvu_driver);
3418 if (err < 0)
3419 goto rvu_err;
3420
3421 return 0;
3422 rvu_err:
3423 pci_unregister_driver(&mcs_driver);
3424 mcs_err:
3425 pci_unregister_driver(&ptp_driver);
3426 ptp_err:
3427 pci_unregister_driver(&cgx_driver);
3428
3429 return err;
3430 }
3431
rvu_cleanup_module(void)3432 static void __exit rvu_cleanup_module(void)
3433 {
3434 pci_unregister_driver(&rvu_driver);
3435 pci_unregister_driver(&mcs_driver);
3436 pci_unregister_driver(&ptp_driver);
3437 pci_unregister_driver(&cgx_driver);
3438 }
3439
3440 module_init(rvu_init_module);
3441 module_exit(rvu_cleanup_module);
3442