1 /*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28 #include "reg_helper.h"
29 #include <linux/delay.h>
30
31 #define MAX_INSTANCE 5
32 #define MAX_SEGMENT 5
33
34 struct IP_BASE_INSTANCE {
35 unsigned int segment[MAX_SEGMENT];
36 };
37
38 struct IP_BASE {
39 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
40 };
41
42
43 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } } } };
48
49 #define mmMP1_SMN_C2PMSG_91 0x29B
50 #define mmMP1_SMN_C2PMSG_83 0x293
51 #define mmMP1_SMN_C2PMSG_67 0x283
52 #define mmMP1_SMN_C2PMSG_91_BASE_IDX 0
53 #define mmMP1_SMN_C2PMSG_83_BASE_IDX 0
54 #define mmMP1_SMN_C2PMSG_67_BASE_IDX 0
55
56 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xffffffffL
57 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xffffffffL
58 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xffffffffL
59 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x00000000
60 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x00000000
61 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x00000000
62
63 #define REG(reg_name) \
64 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
65
66 #define FN(reg_name, field) \
67 FD(reg_name##__##field)
68
69 #define VBIOSSMC_MSG_SetDispclkFreq 0x4
70 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5
71
72 #define VBIOSSMC_Status_BUSY 0x0
73 #define VBIOSSMC_Result_OK 0x1
74 #define VBIOSSMC_Result_Failed 0xFF
75 #define VBIOSSMC_Result_UnknownCmd 0xFE
76 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
77 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC
78
79 /*
80 * Function to be used instead of REG_WAIT macro because the wait ends when
81 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
82 * won't work with REG_WAIT.
83 */
rv1_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)84 static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
85 {
86 uint32_t res_val = VBIOSSMC_Status_BUSY;
87
88 do {
89 res_val = REG_READ(MP1_SMN_C2PMSG_91);
90 if (res_val != VBIOSSMC_Status_BUSY)
91 break;
92
93 if (delay_us >= 1000)
94 msleep(delay_us/1000);
95 else if (delay_us > 0)
96 udelay(delay_us);
97 } while (max_retries--);
98
99 return res_val;
100 }
101
rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,unsigned int msg_id,unsigned int param)102 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
103 {
104 uint32_t result;
105
106 /* First clear response register */
107 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
108
109 /* Set the parameter register for the SMU message, unit is Mhz */
110 REG_WRITE(MP1_SMN_C2PMSG_83, param);
111
112 /* Trigger the message transaction by writing the message ID */
113 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
114
115 result = rv1_smu_wait_for_response(clk_mgr, 10, 1000);
116
117 ASSERT(result == VBIOSSMC_Result_OK);
118
119 /* Actual dispclk set is returned in the parameter register */
120 return REG_READ(MP1_SMN_C2PMSG_83);
121 }
122
rv1_vbios_smu_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_dispclk_khz)123 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
124 {
125 int actual_dispclk_set_mhz = -1;
126 struct dc *dc = clk_mgr->base.ctx->dc;
127 struct dmcu *dmcu = dc->res_pool->dmcu;
128
129 /* Unit of SMU msg parameter is Mhz */
130 actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
131 clk_mgr,
132 VBIOSSMC_MSG_SetDispclkFreq,
133 requested_dispclk_khz / 1000);
134
135 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
136 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
137 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
138 dmcu->funcs->set_psr_wait_loop(dmcu,
139 actual_dispclk_set_mhz / 7);
140 }
141 }
142
143 return actual_dispclk_set_mhz * 1000;
144 }
145
rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal * clk_mgr)146 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
147 {
148 int actual_dprefclk_set_mhz = -1;
149
150 actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
151 clk_mgr,
152 VBIOSSMC_MSG_SetDprefclkFreq,
153 clk_mgr->base.dprefclk_khz / 1000);
154
155 /* TODO: add code for programing DP DTO, currently this is down by command table */
156
157 return actual_dprefclk_set_mhz * 1000;
158 }
159