1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 * Copyright(c) 2020-2022 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CHAN_H__
6 #define __RTW89_CHAN_H__
7
8 #include "core.h"
9
10 /* The dwell time in TU before doing rtw89_chanctx_work(). */
11 #define RTW89_CHANCTX_TIME_MCC_PREPARE 100
12 #define RTW89_CHANCTX_TIME_MCC 100
13
14 /* various MCC setting time in TU */
15 #define RTW89_MCC_LONG_TRIGGER_TIME 300
16 #define RTW89_MCC_SHORT_TRIGGER_TIME 100
17 #define RTW89_MCC_EARLY_TX_BCN_TIME 10
18 #define RTW89_MCC_EARLY_RX_BCN_TIME 5
19 #define RTW89_MCC_MIN_RX_BCN_TIME 10
20 #define RTW89_MCC_DFLT_BCN_OFST_TIME 40
21
22 #define RTW89_MCC_MIN_GO_DURATION \
23 (RTW89_MCC_EARLY_TX_BCN_TIME + RTW89_MCC_MIN_RX_BCN_TIME)
24
25 #define RTW89_MCC_MIN_STA_DURATION \
26 (RTW89_MCC_EARLY_RX_BCN_TIME + RTW89_MCC_MIN_RX_BCN_TIME)
27
28 #define RTW89_MCC_DFLT_GROUP 0
29 #define RTW89_MCC_NEXT_GROUP(cur) (((cur) + 1) % 4)
30
31 #define RTW89_MCC_DFLT_TX_NULL_EARLY 3
32 #define RTW89_MCC_DFLT_COURTESY_SLOT 3
33
34 #define NUM_OF_RTW89_MCC_ROLES 2
35
36 enum rtw89_chanctx_pause_reasons {
37 RTW89_CHANCTX_PAUSE_REASON_HW_SCAN,
38 RTW89_CHANCTX_PAUSE_REASON_ROC,
39 };
40
rtw89_get_entity_state(struct rtw89_dev * rtwdev)41 static inline bool rtw89_get_entity_state(struct rtw89_dev *rtwdev)
42 {
43 struct rtw89_hal *hal = &rtwdev->hal;
44
45 return READ_ONCE(hal->entity_active);
46 }
47
rtw89_set_entity_state(struct rtw89_dev * rtwdev,bool active)48 static inline void rtw89_set_entity_state(struct rtw89_dev *rtwdev, bool active)
49 {
50 struct rtw89_hal *hal = &rtwdev->hal;
51
52 WRITE_ONCE(hal->entity_active, active);
53 }
54
55 static inline
rtw89_get_entity_mode(struct rtw89_dev * rtwdev)56 enum rtw89_entity_mode rtw89_get_entity_mode(struct rtw89_dev *rtwdev)
57 {
58 struct rtw89_hal *hal = &rtwdev->hal;
59
60 return READ_ONCE(hal->entity_mode);
61 }
62
rtw89_set_entity_mode(struct rtw89_dev * rtwdev,enum rtw89_entity_mode mode)63 static inline void rtw89_set_entity_mode(struct rtw89_dev *rtwdev,
64 enum rtw89_entity_mode mode)
65 {
66 struct rtw89_hal *hal = &rtwdev->hal;
67
68 WRITE_ONCE(hal->entity_mode, mode);
69 }
70
71 void rtw89_chan_create(struct rtw89_chan *chan, u8 center_chan, u8 primary_chan,
72 enum rtw89_band band, enum rtw89_bandwidth bandwidth);
73 bool rtw89_assign_entity_chan(struct rtw89_dev *rtwdev,
74 enum rtw89_sub_entity_idx idx,
75 const struct rtw89_chan *new);
76 void rtw89_config_entity_chandef(struct rtw89_dev *rtwdev,
77 enum rtw89_sub_entity_idx idx,
78 const struct cfg80211_chan_def *chandef);
79 void rtw89_config_roc_chandef(struct rtw89_dev *rtwdev,
80 enum rtw89_sub_entity_idx idx,
81 const struct cfg80211_chan_def *chandef);
82 void rtw89_entity_init(struct rtw89_dev *rtwdev);
83 enum rtw89_entity_mode rtw89_entity_recalc(struct rtw89_dev *rtwdev);
84 void rtw89_chanctx_work(struct work_struct *work);
85 void rtw89_queue_chanctx_work(struct rtw89_dev *rtwdev);
86 void rtw89_queue_chanctx_change(struct rtw89_dev *rtwdev,
87 enum rtw89_chanctx_changes change);
88 void rtw89_chanctx_track(struct rtw89_dev *rtwdev);
89 void rtw89_chanctx_pause(struct rtw89_dev *rtwdev,
90 enum rtw89_chanctx_pause_reasons rsn);
91 void rtw89_chanctx_proceed(struct rtw89_dev *rtwdev);
92 int rtw89_chanctx_ops_add(struct rtw89_dev *rtwdev,
93 struct ieee80211_chanctx_conf *ctx);
94 void rtw89_chanctx_ops_remove(struct rtw89_dev *rtwdev,
95 struct ieee80211_chanctx_conf *ctx);
96 void rtw89_chanctx_ops_change(struct rtw89_dev *rtwdev,
97 struct ieee80211_chanctx_conf *ctx,
98 u32 changed);
99 int rtw89_chanctx_ops_assign_vif(struct rtw89_dev *rtwdev,
100 struct rtw89_vif *rtwvif,
101 struct ieee80211_chanctx_conf *ctx);
102 void rtw89_chanctx_ops_unassign_vif(struct rtw89_dev *rtwdev,
103 struct rtw89_vif *rtwvif,
104 struct ieee80211_chanctx_conf *ctx);
105
106 #endif
107