1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "debug.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "reg.h"
10
11 static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = {
12 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE,
13 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE,
14 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE,
15 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE,
16 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE,
17 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE,
18 [RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE,
19 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE,
20 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE,
21 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE,
22 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE,
23 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE,
24 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE,
25 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE,
26 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE,
27 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE,
28 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE,
29 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE,
30 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE,
31 [RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE,
32 [RTW89_MAC_MEM_MLD_TBL] = MLD_TBL_BASE_ADDR_BE,
33 };
34
35 static const struct rtw89_port_reg rtw89_port_base_be = {
36 .port_cfg = R_BE_PORT_CFG_P0,
37 .tbtt_prohib = R_BE_TBTT_PROHIB_P0,
38 .bcn_area = R_BE_BCN_AREA_P0,
39 .bcn_early = R_BE_BCNERLYINT_CFG_P0,
40 .tbtt_early = R_BE_TBTTERLYINT_CFG_P0,
41 .tbtt_agg = R_BE_TBTT_AGG_P0,
42 .bcn_space = R_BE_BCN_SPACE_CFG_P0,
43 .bcn_forcetx = R_BE_BCN_FORCETX_P0,
44 .bcn_err_cnt = R_BE_BCN_ERR_CNT_P0,
45 .bcn_err_flag = R_BE_BCN_ERR_FLAG_P0,
46 .dtim_ctrl = R_BE_DTIM_CTRL_P0,
47 .tbtt_shift = R_BE_TBTT_SHIFT_P0,
48 .bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0,
49 .tsftr_l = R_BE_TSFTR_LOW_P0,
50 .tsftr_h = R_BE_TSFTR_HIGH_P0,
51 .md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL,
52 .bss_color = R_BE_PTCL_BSS_COLOR_0,
53 .mbssid = R_BE_MBSSID_CTRL,
54 .mbssid_drop = R_BE_MBSSID_DROP_0,
55 .tsf_sync = R_BE_PORT_0_TSF_SYNC,
56 .ptcl_dbg = R_BE_PTCL_DBG,
57 .ptcl_dbg_info = R_BE_PTCL_DBG_INFO,
58 .bcn_drop_all = R_BE_BCN_DROP_ALL0,
59 .bcn_psr_rpt = R_BE_BCN_PSR_RPT_P0,
60 .hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG,
61 R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2,
62 R_BE_PORT_HGQ_WINDOW_CFG + 3},
63 };
64
65 static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_be = {
66 .position_en = {R_BE_GID_POSITION_EN0, R_BE_GID_POSITION_EN1},
67 .position = {R_BE_GID_POSITION0, R_BE_GID_POSITION1,
68 R_BE_GID_POSITION2, R_BE_GID_POSITION3},
69 };
70
rtw89_mac_check_mac_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)71 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx,
72 enum rtw89_mac_hwmod_sel sel)
73 {
74 if (sel == RTW89_DMAC_SEL &&
75 test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags))
76 return 0;
77 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_0 &&
78 test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags))
79 return 0;
80 if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_1 &&
81 test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags))
82 return 0;
83
84 return -EFAULT;
85 }
86
is_qta_poh(struct rtw89_dev * rtwdev)87 static bool is_qta_poh(struct rtw89_dev *rtwdev)
88 {
89 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
90 }
91
hfc_get_mix_info_be(struct rtw89_dev * rtwdev)92 static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev)
93 {
94 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
95 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
96 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
97 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
98 const struct rtw89_chip_info *chip = rtwdev->chip;
99 u32 val;
100
101 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1);
102 info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK);
103 info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK);
104
105 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO3);
106 info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK);
107 info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK);
108 info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2),
109 B_BE_PUB_AVAL_PG_MASK);
110 info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1),
111 B_BE_WP_AVAL_PG_MASK);
112
113 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
114 param->en = !!(val & B_BE_HCI_FC_EN);
115 param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN);
116 param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK);
117 prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK);
118 prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK);
119 prec_cfg->wp_ch07_full_cond =
120 u32_get_bits(val, B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
121 prec_cfg->wp_ch811_full_cond =
122 u32_get_bits(val, B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
123
124 val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL);
125 prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);
126 if (chip->chip_id == RTL8922D)
127 prec_cfg->ch011_full_page = u32_get_bits(val, B_BE_FULL_WD_PG_MASK);
128 prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);
129
130 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2);
131 pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);
132
133 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1);
134 if (chip->chip_id == RTL8922D) {
135 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_V1_MASK);
136 prec_cfg->wp_ch07_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH07_MASK);
137 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_V1_MASK);
138 prec_cfg->wp_ch811_full_page = u32_get_bits(val, B_BE_FULL_PAGE_WP_CH811_MASK);
139 } else {
140 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
141 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
142 }
143
144 val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2);
145 pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);
146
147 val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL1);
148 pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK);
149 pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK);
150 }
151
hfc_h2c_cfg_be(struct rtw89_dev * rtwdev)152 static void hfc_h2c_cfg_be(struct rtw89_dev *rtwdev)
153 {
154 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
155 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
156 u32 val;
157
158 val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
159 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
160 }
161
hfc_mix_cfg_be(struct rtw89_dev * rtwdev)162 static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev)
163 {
164 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
165 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
166 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
167 const struct rtw89_chip_info *chip = rtwdev->chip;
168 u32 val;
169
170 val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |
171 u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
172 if (chip->chip_id == RTL8922D)
173 val = u32_replace_bits(val, prec_cfg->ch011_full_page, B_BE_FULL_WD_PG_MASK);
174 rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
175
176 val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);
177 rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val);
178
179 if (chip->chip_id == RTL8922D)
180 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_V1_MASK) |
181 u32_encode_bits(prec_cfg->wp_ch07_full_page, B_BE_FULL_PAGE_WP_CH07_MASK) |
182 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_V1_MASK) |
183 u32_encode_bits(prec_cfg->wp_ch811_full_page, B_BE_FULL_PAGE_WP_CH811_MASK);
184 else
185 val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
186 u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
187 rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val);
188
189 val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL),
190 param->mode, B_BE_HCI_FC_MODE_MASK);
191 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
192 B_BE_HCI_FC_WD_FULL_COND_MASK);
193 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
194 B_BE_HCI_FC_CH12_FULL_COND_MASK);
195 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
196 B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
197 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
198 B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
199 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
200 }
201
hfc_func_en_be(struct rtw89_dev * rtwdev,bool en,bool h2c_en)202 static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
203 {
204 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
205 u32 val;
206
207 val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
208 param->en = en;
209 param->h2c_en = h2c_en;
210 val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN);
211 val = h2c_en ? (val | B_BE_HCI_FC_CH12_EN) :
212 (val & ~B_BE_HCI_FC_CH12_EN);
213 rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
214 }
215
dle_func_en_be(struct rtw89_dev * rtwdev,bool enable)216 static void dle_func_en_be(struct rtw89_dev *rtwdev, bool enable)
217 {
218 if (enable)
219 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
220 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
221 else
222 rtw89_write32_clr(rtwdev, R_BE_DMAC_FUNC_EN,
223 B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
224 }
225
dle_clk_en_be(struct rtw89_dev * rtwdev,bool enable)226 static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable)
227 {
228 if (rtwdev->chip->chip_id != RTL8922A)
229 return;
230
231 if (enable)
232 rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN,
233 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
234 else
235 rtw89_write32_clr(rtwdev, R_BE_DMAC_CLK_EN,
236 B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
237 }
238
dle_mix_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg)239 static int dle_mix_cfg_be(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
240 {
241 const struct rtw89_dle_size *wde_size_cfg, *ple_size_cfg;
242 u32 bound;
243 u32 val;
244
245 wde_size_cfg = cfg->wde_size;
246 ple_size_cfg = cfg->ple_size;
247
248 val = rtw89_read32(rtwdev, R_BE_WDE_PKTBUF_CFG);
249
250 switch (wde_size_cfg->pge_size) {
251 default:
252 case RTW89_WDE_PG_64:
253 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
254 B_BE_WDE_PAGE_SEL_MASK);
255 break;
256 case RTW89_WDE_PG_128:
257 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
258 B_BE_WDE_PAGE_SEL_MASK);
259 break;
260 case RTW89_WDE_PG_256:
261 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
262 return -EINVAL;
263 }
264
265 bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT;
266 val = u32_replace_bits(val, bound, B_BE_WDE_START_BOUND_MASK);
267 val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num,
268 B_BE_WDE_FREE_PAGE_NUM_MASK);
269 rtw89_write32(rtwdev, R_BE_WDE_PKTBUF_CFG, val);
270
271 val = rtw89_read32(rtwdev, R_BE_PLE_PKTBUF_CFG);
272
273 switch (ple_size_cfg->pge_size) {
274 default:
275 case RTW89_PLE_PG_64:
276 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
277 return -EINVAL;
278 case RTW89_PLE_PG_128:
279 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
280 B_BE_PLE_PAGE_SEL_MASK);
281 break;
282 case RTW89_PLE_PG_256:
283 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
284 B_BE_PLE_PAGE_SEL_MASK);
285 break;
286 }
287
288 bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT;
289 val = u32_replace_bits(val, bound, B_BE_PLE_START_BOUND_MASK);
290 val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num,
291 B_BE_PLE_FREE_PAGE_NUM_MASK);
292 rtw89_write32(rtwdev, R_BE_PLE_PKTBUF_CFG, val);
293
294 return 0;
295 }
296
chk_dle_rdy_be(struct rtw89_dev * rtwdev,bool wde_or_ple)297 static int chk_dle_rdy_be(struct rtw89_dev *rtwdev, bool wde_or_ple)
298 {
299 u32 reg, mask;
300 u32 ini;
301
302 if (wde_or_ple) {
303 reg = R_AX_WDE_INI_STATUS;
304 mask = WDE_MGN_INI_RDY;
305 } else {
306 reg = R_AX_PLE_INI_STATUS;
307 mask = PLE_MGN_INI_RDY;
308 }
309
310 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1,
311 2000, false, rtwdev, reg);
312 }
313
314 #define INVALID_QT_WCPU U16_MAX
315 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \
316 do { \
317 val = u32_encode_bits(_min_x, B_BE_ ## _module ## _Q ## _idx ## _MIN_SIZE_MASK) | \
318 u32_encode_bits(_max_x, B_BE_ ## _module ## _Q ## _idx ## _MAX_SIZE_MASK); \
319 rtw89_write32(rtwdev, \
320 R_BE_ ## _module ## _QTA ## _idx ## _CFG, \
321 val); \
322 } while (0)
323 #define SET_QUOTA(_x, _module, _idx) \
324 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
325
wde_quota_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_wde_quota * min_cfg,const struct rtw89_wde_quota * max_cfg,u16 ext_wde_min_qt_wcpu)326 static void wde_quota_cfg_be(struct rtw89_dev *rtwdev,
327 const struct rtw89_wde_quota *min_cfg,
328 const struct rtw89_wde_quota *max_cfg,
329 u16 ext_wde_min_qt_wcpu)
330 {
331 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
332 ext_wde_min_qt_wcpu : min_cfg->wcpu;
333 u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu);
334 u32 val;
335
336 SET_QUOTA(hif, WDE, 0);
337 SET_QUOTA_VAL(min_qt_wcpu, max_qt_wcpu, WDE, 1);
338 SET_QUOTA_VAL(0, 0, WDE, 2);
339 SET_QUOTA(pkt_in, WDE, 3);
340 SET_QUOTA(cpu_io, WDE, 4);
341 }
342
ple_quota_cfg_be(struct rtw89_dev * rtwdev,const struct rtw89_ple_quota * min_cfg,const struct rtw89_ple_quota * max_cfg)343 static void ple_quota_cfg_be(struct rtw89_dev *rtwdev,
344 const struct rtw89_ple_quota *min_cfg,
345 const struct rtw89_ple_quota *max_cfg)
346 {
347 u32 val;
348
349 SET_QUOTA(cma0_tx, PLE, 0);
350 SET_QUOTA(cma1_tx, PLE, 1);
351 SET_QUOTA(c2h, PLE, 2);
352 SET_QUOTA(h2c, PLE, 3);
353 SET_QUOTA(wcpu, PLE, 4);
354 SET_QUOTA(mpdu_proc, PLE, 5);
355 SET_QUOTA(cma0_dma, PLE, 6);
356 SET_QUOTA(cma1_dma, PLE, 7);
357 SET_QUOTA(bb_rpt, PLE, 8);
358 SET_QUOTA(wd_rel, PLE, 9);
359 SET_QUOTA(cpu_io, PLE, 10);
360 SET_QUOTA(tx_rpt, PLE, 11);
361 SET_QUOTA(h2d, PLE, 12);
362
363 if (rtwdev->chip->chip_id == RTL8922A)
364 return;
365
366 SET_QUOTA(snrpt, PLE, 13);
367 }
368
rtw89_mac_hci_func_en_be(struct rtw89_dev * rtwdev)369 static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev)
370 {
371 rtw89_write32_set(rtwdev, R_BE_HCI_FUNC_EN, B_BE_HCI_TXDMA_EN |
372 B_BE_HCI_RXDMA_EN);
373 }
374
rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev * rtwdev)375 static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
376 {
377 const struct rtw89_chip_info *chip = rtwdev->chip;
378 u32 mask;
379 u32 val;
380
381 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
382
383 switch (rtwdev->hci.type) {
384 case RTW89_HCI_TYPE_PCIE:
385 val = u32_replace_bits(val, S_BE_DMA_MOD_PCIE_NO_DATA_CPU,
386 B_BE_DMA_MODE_MASK);
387 break;
388 case RTW89_HCI_TYPE_USB:
389 val = u32_replace_bits(val, S_BE_DMA_MOD_USB, B_BE_DMA_MODE_MASK);
390 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
391 break;
392 case RTW89_HCI_TYPE_SDIO:
393 val = u32_replace_bits(val, S_BE_DMA_MOD_SDIO, B_BE_DMA_MODE_MASK);
394 val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
395 break;
396 default:
397 return;
398 }
399
400 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
401
402 if (chip->chip_id == RTL8922A)
403 mask = B_BE_TX_STOP1_MASK;
404 else
405 mask = B_BE_TX_STOP1_MASK_V1;
406
407 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, mask);
408
409 rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
410 }
411
412 static
rtw89_mac_write_xtal_si_be(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)413 int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
414 {
415 u32 val32;
416 int ret;
417
418 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
419 u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) |
420 u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) |
421 u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) |
422 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
423 B_BE_WL_XTAL_SI_CMD_POLL;
424 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
425
426 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
427 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
428 if (ret) {
429 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
430 offset, val, mask);
431 return ret;
432 }
433
434 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
435 (u32_get_bits(val32, B_BE_WL_XTAL_SI_ADDR_MASK) != offset ||
436 u32_get_bits(val32, B_BE_WL_XTAL_SI_DATA_MASK) != val))
437 rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n",
438 offset, val, val32);
439
440 return 0;
441 }
442
443 static
rtw89_mac_read_xtal_si_be(struct rtw89_dev * rtwdev,u8 offset,u8 * val)444 int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
445 {
446 u32 val32;
447 int ret;
448
449 val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
450 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) |
451 u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) |
452 u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) |
453 u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
454 B_BE_WL_XTAL_SI_CMD_POLL;
455 rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
456
457 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
458 50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
459 if (ret) {
460 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
461 return ret;
462 }
463
464 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) &&
465 u32_get_bits(val32, B_BE_WL_XTAL_SI_ADDR_MASK) != offset)
466 rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n",
467 offset, val32);
468
469 *val = u32_get_bits(val32, B_BE_WL_XTAL_SI_DATA_MASK);
470
471 return 0;
472 }
473
rtw89_mac_reset_pwr_state_be(struct rtw89_dev * rtwdev)474 static int rtw89_mac_reset_pwr_state_be(struct rtw89_dev *rtwdev)
475 {
476 u32 val32;
477 int ret;
478
479 val32 = rtw89_read32(rtwdev, R_BE_SYSON_FSM_MON);
480 val32 &= WLAN_FSM_MASK;
481 val32 |= WLAN_FSM_SET;
482 rtw89_write32(rtwdev, R_BE_SYSON_FSM_MON, val32);
483
484 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == WLAN_FSM_IDLE,
485 1000, 2000000, false,
486 rtwdev, R_BE_SYSON_FSM_MON, WLAN_FSM_STATE_MASK);
487 if (ret) {
488 rtw89_err(rtwdev, "[ERR]Polling WLAN PMC timeout= %X\n", val32);
489 return ret;
490 }
491
492 val32 = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
493 if (val32 == MAC_AX_MAC_OFF) {
494 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
495
496 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
497 1000, 2000000, false,
498 rtwdev, R_BE_HCI_OPT_CTRL,
499 B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
500 if (ret) {
501 rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
502 return ret;
503 }
504
505 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
506
507 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
508 1000, 2000000, false,
509 rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
510 if (ret) {
511 rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
512 return ret;
513 }
514
515 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
516 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
517 } else if (val32 == MAC_AX_MAC_ON) {
518 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
519
520 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
521 1000, 2000000, false,
522 rtwdev, R_BE_HCI_OPT_CTRL,
523 B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
524 if (ret) {
525 rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
526 return ret;
527 }
528
529 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
530
531 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
532 1000, 2000000, false,
533 rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
534 if (ret) {
535 rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
536 return ret;
537 }
538
539 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
540 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
541
542 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
543 1000, 2000000, false,
544 rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
545 if (ret) {
546 rtw89_err(rtwdev, "[ERR]Polling MAC state timeout= %X\n", val32);
547 return ret;
548 }
549
550 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
551 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
552 } else if (val32 == MAC_AX_MAC_LPS) {
553 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
554
555 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
556 1000, 2000000, false,
557 rtwdev, R_BE_HCI_OPT_CTRL,
558 B_BE_HAXIDMA_IO_ST | B_BE_HAXIDMA_BACKUP_RESTORE_ST);
559 if (ret) {
560 rtw89_err(rtwdev, "[ERR]Polling HAXI IO timeout= %X\n", val32);
561 return ret;
562 }
563
564 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
565
566 ret = read_poll_timeout(rtw89_read32_mask, val32, !val32,
567 1000, 2000000, false,
568 rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_ST);
569 if (ret) {
570 rtw89_err(rtwdev, "[ERR]Polling WLAN IO timeout= %X\n", val32);
571 return ret;
572 }
573
574 rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_FORCE_LEAVE_LPS);
575
576 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_ON,
577 1000, 2000000, false,
578 rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
579 if (ret) {
580 rtw89_err(rtwdev, "[ERR]Polling MAC STS timeout= %X\n", val32);
581 return ret;
582 }
583
584 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
585 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
586
587 ret = read_poll_timeout(rtw89_read32_mask, val32, val32 == MAC_AX_MAC_OFF,
588 1000, 2000000, false,
589 rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
590 if (ret) {
591 rtw89_err(rtwdev, "[ERR]Polling MAC state timeout= %X\n", val32);
592 return ret;
593 }
594
595 rtw89_write32_clr(rtwdev, R_BE_WLLPS_CTRL, B_BE_FORCE_LEAVE_LPS);
596 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
597 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
598 }
599
600 return 0;
601 }
602
rtw89_mac_disable_cpu_be(struct rtw89_dev * rtwdev)603 static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev)
604 {
605 u32 val32;
606
607 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
608
609 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
610 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
611 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
612
613 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
614 val32 &= B_BE_RUN_ENV_MASK;
615 rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32);
616
617 if (rtwdev->chip->chip_id == RTL8922A)
618 rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN);
619
620 rtw89_write32(rtwdev, R_BE_UDM0, 0);
621 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
622 rtw89_write32(rtwdev, R_BE_UDM2, 0);
623 }
624
set_cpu_en(struct rtw89_dev * rtwdev,bool include_bb)625 static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb)
626 {
627 u32 set = B_BE_WLANCPU_FWDL_EN;
628
629 if (include_bb)
630 set |= B_BE_BBMCU0_FWDL_EN;
631
632 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set);
633 }
634
wcpu_on(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw)635 static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
636 {
637 const struct rtw89_chip_info *chip = rtwdev->chip;
638 u32 val32;
639 int ret;
640
641 val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H);
642 if (val32) {
643 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
644 rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32);
645 }
646 val32 = rtw89_read32(rtwdev, R_BE_UDM1);
647 if (val32) {
648 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
649 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32);
650 }
651 val32 = rtw89_read32(rtwdev, R_BE_UDM2);
652 if (val32) {
653 rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
654 rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32);
655 }
656
657 rtw89_write32(rtwdev, R_BE_UDM1, 0);
658 rtw89_write32(rtwdev, R_BE_UDM2, 0);
659 rtw89_write32(rtwdev, R_BE_BOOT_DBG, 0x0);
660 rtw89_write32(rtwdev, R_BE_HALT_H2C, 0);
661 rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
662 rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0);
663 rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0);
664
665 val32 = rtw89_read32(rtwdev, R_BE_HISR0);
666 rtw89_write32(rtwdev, R_BE_HISR0, B_BE_HALT_C2H_INT);
667 rtw89_debug(rtwdev, RTW89_DBG_SER, "HISR0=0x%x\n", val32);
668
669 rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN);
670 rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5,
671 B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN);
672 rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL,
673 B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET);
674 rtw89_write32(rtwdev, R_BE_SECURE_BOOT_MALLOC_INFO, 0);
675 rtw89_write32_clr(rtwdev, R_BE_GPIO_MUXCFG, B_BE_BOOT_MODE);
676
677 if (chip->chip_id != RTL8922A)
678 rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, B_BE_HOST_EXIST);
679
680 rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason);
681 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
682 rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
683 rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
684
685 if (!dlfw) {
686 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
687 if (ret)
688 return ret;
689 }
690
691 return 0;
692 }
693
rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw,bool include_bb)694 static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev,
695 u8 boot_reason, bool dlfw,
696 bool include_bb)
697 {
698 set_cpu_en(rtwdev, include_bb);
699
700 return wcpu_on(rtwdev, boot_reason, dlfw);
701 }
702
703 static const u8 fwdl_status_map[] = {
704 [0] = RTW89_FWDL_INITIAL_STATE,
705 [1] = RTW89_FWDL_FWDL_ONGOING,
706 [4] = RTW89_FWDL_CHECKSUM_FAIL,
707 [5] = RTW89_FWDL_SECURITY_FAIL,
708 [6] = RTW89_FWDL_SECURITY_FAIL,
709 [7] = RTW89_FWDL_CV_NOT_MATCH,
710 [8] = RTW89_FWDL_RSVD0,
711 [2] = RTW89_FWDL_WCPU_FWDL_RDY,
712 [3] = RTW89_FWDL_WCPU_FW_INIT_RDY,
713 [9] = RTW89_FWDL_RSVD0,
714 };
715
fwdl_get_status_be(struct rtw89_dev * rtwdev,enum rtw89_fwdl_check_type type)716 static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
717 {
718 bool check_pass = false;
719 u32 val32;
720 u8 st;
721
722 val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
723
724 switch (type) {
725 case RTW89_FWDL_CHECK_WCPU_FWDL_DONE:
726 check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN);
727 break;
728 case RTW89_FWDL_CHECK_DCPU_FWDL_DONE:
729 check_pass = !(val32 & B_BE_DATACPU_FWDL_EN);
730 break;
731 case RTW89_FWDL_CHECK_BB0_FWDL_DONE:
732 check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN);
733 break;
734 case RTW89_FWDL_CHECK_BB1_FWDL_DONE:
735 check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN);
736 break;
737 default:
738 break;
739 }
740
741 if (check_pass)
742 return RTW89_FWDL_WCPU_FW_INIT_RDY;
743
744 st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK);
745 if (st < ARRAY_SIZE(fwdl_status_map))
746 return fwdl_status_map[st];
747
748 return st;
749 }
750
rtw89_fwdl_check_path_ready_be(struct rtw89_dev * rtwdev,bool h2c_or_fwdl)751 static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev,
752 bool h2c_or_fwdl)
753 {
754 u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY;
755 u32 val;
756
757 return read_poll_timeout_atomic(rtw89_read32, val, val & check,
758 1, 1000000, false,
759 rtwdev, R_BE_WCPU_FW_CTRL);
760 }
761
dmac_func_en_be(struct rtw89_dev * rtwdev)762 static int dmac_func_en_be(struct rtw89_dev *rtwdev)
763 {
764 const struct rtw89_chip_info *chip = rtwdev->chip;
765
766 if (chip->chip_id == RTL8922A)
767 return 0;
768
769 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
770 B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN |
771 B_BE_MPDU_PROC_EN | B_BE_WD_RLS_EN |
772 B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
773 B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN |
774 B_BE_PKT_BUF_EN | B_BE_DMAC_TBL_EN |
775 B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
776 B_BE_DISPATCHER_EN | B_BE_BBRPT_EN |
777 B_BE_MAC_SEC_EN | B_BE_H_AXIDMA_EN |
778 B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
779 B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN);
780
781 return 0;
782 }
783
cmac_share_func_en_be(struct rtw89_dev * rtwdev)784 static int cmac_share_func_en_be(struct rtw89_dev *rtwdev)
785 {
786 const struct rtw89_chip_info *chip = rtwdev->chip;
787
788 if (chip->chip_id == RTL8922A)
789 return 0;
790
791 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
792 B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN |
793 B_BE_ADDRSRCH_EN | B_BE_BTCOEX_EN);
794
795 return 0;
796 }
797
cmac_pwr_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)798 static int cmac_pwr_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
799 {
800 if (mac_idx > RTW89_MAC_1)
801 return -EINVAL;
802
803 if (mac_idx == RTW89_MAC_0) {
804 if (en == test_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags))
805 return 0;
806
807 if (en) {
808 rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1,
809 B_BE_R_SYM_WLCMAC0_ALL_EN);
810 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
811 B_BE_R_SYM_ISO_CMAC02PP);
812 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
813 B_BE_CMAC0_FEN);
814
815 set_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
816 } else {
817 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
818 B_BE_CMAC0_FEN);
819 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
820 B_BE_R_SYM_ISO_CMAC02PP);
821 rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1,
822 B_BE_R_SYM_WLCMAC0_ALL_EN);
823
824 clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags);
825 }
826 } else {
827 if (en == test_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags))
828 return 0;
829
830 if (en) {
831 rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1,
832 B_BE_R_SYM_WLCMAC1_ALL_EN);
833 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
834 B_BE_R_SYM_ISO_CMAC12PP);
835 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
836 B_BE_CMAC1_FEN);
837
838 set_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
839 } else {
840 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
841 B_BE_CMAC1_FEN);
842 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
843 B_BE_R_SYM_ISO_CMAC12PP);
844 rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1,
845 B_BE_R_SYM_WLCMAC1_ALL_EN);
846
847 clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags);
848 }
849 }
850
851 return 0;
852 }
853
cmac_func_en_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)854 static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
855 {
856 enum rtw89_flags pwr_flag, func_flag;
857 u32 reg;
858
859 if (mac_idx > RTW89_MAC_1)
860 return -EINVAL;
861
862 if (mac_idx == RTW89_MAC_0) {
863 pwr_flag = RTW89_FLAG_CMAC0_PWR;
864 func_flag = RTW89_FLAG_CMAC0_FUNC;
865 } else {
866 pwr_flag = RTW89_FLAG_CMAC1_PWR;
867 func_flag = RTW89_FLAG_CMAC1_FUNC;
868 }
869
870 if (!test_bit(pwr_flag, rtwdev->flags)) {
871 rtw89_warn(rtwdev, "CMAC %u power cut did not release\n", mac_idx);
872 return 0;
873 }
874
875 if (en) {
876 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
877 rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET);
878
879 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
880 rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
881
882 set_bit(func_flag, rtwdev->flags);
883 } else {
884 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
885 rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
886
887 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
888 rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET);
889
890 clear_bit(func_flag, rtwdev->flags);
891 }
892
893 return 0;
894 }
895
chip_func_en_be(struct rtw89_dev * rtwdev)896 static int chip_func_en_be(struct rtw89_dev *rtwdev)
897 {
898 return 0;
899 }
900
sys_init_be(struct rtw89_dev * rtwdev)901 static int sys_init_be(struct rtw89_dev *rtwdev)
902 {
903 int ret;
904
905 ret = dmac_func_en_be(rtwdev);
906 if (ret)
907 return ret;
908
909 ret = cmac_share_func_en_be(rtwdev);
910 if (ret)
911 return ret;
912
913 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_0, true);
914 if (ret)
915 return ret;
916
917 ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
918 if (ret)
919 return ret;
920
921 ret = chip_func_en_be(rtwdev);
922 if (ret)
923 return ret;
924
925 return ret;
926 }
927
mac_func_en_be(struct rtw89_dev * rtwdev)928 static int mac_func_en_be(struct rtw89_dev *rtwdev)
929 {
930 u32 val;
931 int ret;
932
933 ret = dmac_func_en_be(rtwdev);
934 if (ret)
935 return ret;
936
937 ret = cmac_share_func_en_be(rtwdev);
938 if (ret)
939 return ret;
940
941 val = rtw89_read32(rtwdev, R_BE_FEN_RST_ENABLE);
942 if (val & B_BE_CMAC0_FEN) {
943 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_0, true);
944 if (ret)
945 return ret;
946
947 ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
948 if (ret)
949 return ret;
950 }
951
952 if (val & B_BE_CMAC1_FEN) {
953 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, true);
954 if (ret)
955 return ret;
956
957 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
958 if (ret)
959 return ret;
960 }
961
962 return 0;
963 }
964
sta_sch_init_be(struct rtw89_dev * rtwdev)965 static int sta_sch_init_be(struct rtw89_dev *rtwdev)
966 {
967 u32 p_val;
968 int ret;
969
970 if (rtwdev->chip->chip_id == RTL8922D) {
971 rtw89_write32_set(rtwdev, R_BE_SS_LITE_TXL_MACID, B_BE_RPT_OTHER_BAND_EN);
972 return 0;
973 }
974
975 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
976 if (ret)
977 return ret;
978
979 rtw89_write8_set(rtwdev, R_BE_SS_CTRL, B_BE_SS_EN);
980
981 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_BE_SS_INIT_DONE,
982 1, TRXCFG_WAIT_CNT, false, rtwdev, R_BE_SS_CTRL);
983 if (ret) {
984 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
985 return ret;
986 }
987
988 rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_WARM_INIT);
989 rtw89_write32_clr(rtwdev, R_BE_SS_CTRL, B_BE_BAND_TRIG_EN | B_BE_BAND1_TRIG_EN);
990
991 return 0;
992 }
993
mpdu_proc_init_be(struct rtw89_dev * rtwdev)994 static int mpdu_proc_init_be(struct rtw89_dev *rtwdev)
995 {
996 u32 val32;
997 int ret;
998
999 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1000 if (ret)
1001 return ret;
1002
1003 rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS);
1004 rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL |
1005 B_BE_CA_CHK_ADDRCAM_EN);
1006
1007 val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING);
1008 val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN);
1009 val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK;
1010 rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32);
1011
1012 rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV |
1013 B_BE_HC_ADDR_HIT_EN);
1014
1015 val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0);
1016 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK);
1017 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK);
1018 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK);
1019 val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK);
1020 rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32);
1021
1022 return 0;
1023 }
1024
sec_eng_init_be(struct rtw89_dev * rtwdev)1025 static int sec_eng_init_be(struct rtw89_dev *rtwdev)
1026 {
1027 u32 val32;
1028 int ret;
1029
1030 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1031 if (ret)
1032 return ret;
1033
1034 val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL);
1035 val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP |
1036 B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC |
1037 B_BE_MC_DEC | B_BE_BC_DEC |
1038 B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC |
1039 B_BE_SEC_PRE_ENQUE_TX;
1040 rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32);
1041
1042 rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC);
1043
1044 return 0;
1045 }
1046
txpktctrl_init_be(struct rtw89_dev * rtwdev)1047 static int txpktctrl_init_be(struct rtw89_dev *rtwdev)
1048 {
1049 struct rtw89_mac_info *mac = &rtwdev->mac;
1050 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
1051 const struct rtw89_dle_input *dle_input;
1052 u32 mpdu_info_b1_ofst;
1053 u32 val32;
1054 int ret;
1055
1056 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, DLE_RSVD_QT_MPDU_INFO, &qt_cfg);
1057 if (ret) {
1058 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n",
1059 DLE_RSVD_QT_MPDU_INFO, ret);
1060 return ret;
1061 }
1062
1063 dle_input = mac->dle_info.dle_input;
1064 if (dle_input)
1065 mpdu_info_b1_ofst = DIV_ROUND_UP(dle_input->mpdu_info_tbl_b0,
1066 BIT(MPDU_INFO_TBL_FACTOR));
1067 else
1068 mpdu_info_b1_ofst = MPDU_INFO_B1_OFST;
1069
1070 val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG);
1071 val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK);
1072 val32 = u32_replace_bits(val32, mpdu_info_b1_ofst, B_BE_MPDUINFO_B1_BADDR_MASK);
1073 val32 |= B_BE_MPDUINFO_FEN;
1074 rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32);
1075
1076 return 0;
1077 }
1078
mlo_init_be(struct rtw89_dev * rtwdev)1079 static int mlo_init_be(struct rtw89_dev *rtwdev)
1080 {
1081 const struct rtw89_chip_info *chip = rtwdev->chip;
1082 u32 val32;
1083 u32 reg;
1084 int ret;
1085
1086 val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
1087
1088 val32 |= B_BE_MLO_TABLE_REINIT;
1089 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
1090 val32 &= ~B_BE_MLO_TABLE_REINIT;
1091 rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
1092
1093 ret = read_poll_timeout_atomic(rtw89_read32, val32,
1094 val32 & B_BE_MLO_TABLE_INIT_DONE,
1095 1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL);
1096 if (ret)
1097 rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__);
1098
1099 if (chip->chip_id == RTL8922A)
1100 reg = R_BE_SS_CTRL;
1101 else
1102 reg = R_BE_SS_CTRL_V1;
1103
1104 rtw89_write32_set(rtwdev, reg, B_BE_MLO_HW_CHGLINK_EN);
1105 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN);
1106
1107 return ret;
1108 }
1109
dmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1110 static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1111 {
1112 int ret;
1113
1114 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
1115 if (ret) {
1116 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
1117 return ret;
1118 }
1119
1120 ret = rtw89_mac_preload_init(rtwdev, mac_idx, rtwdev->mac.qta_mode);
1121 if (ret) {
1122 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
1123 return ret;
1124 }
1125
1126 ret = rtw89_mac_hfc_init(rtwdev, true, true, true);
1127 if (ret) {
1128 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
1129 return ret;
1130 }
1131
1132 ret = sta_sch_init_be(rtwdev);
1133 if (ret) {
1134 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
1135 return ret;
1136 }
1137
1138 ret = mpdu_proc_init_be(rtwdev);
1139 if (ret) {
1140 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
1141 return ret;
1142 }
1143
1144 ret = sec_eng_init_be(rtwdev);
1145 if (ret) {
1146 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
1147 return ret;
1148 }
1149
1150 ret = txpktctrl_init_be(rtwdev);
1151 if (ret) {
1152 rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret);
1153 return ret;
1154 }
1155
1156 ret = mlo_init_be(rtwdev);
1157 if (ret) {
1158 rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret);
1159 return ret;
1160 }
1161
1162 return ret;
1163 }
1164
scheduler_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1165 static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1166 {
1167 const struct rtw89_chip_info *chip = rtwdev->chip;
1168 u32 val32;
1169 u32 reg;
1170 int ret;
1171
1172 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1173 if (ret)
1174 return ret;
1175
1176 if (chip->chip_id == RTL8922D) {
1177 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EXT_CTRL, mac_idx);
1178 rtw89_write32_set(rtwdev, reg, B_BE_CWCNT_PLUS_MODE);
1179 }
1180
1181 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx);
1182 val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 |
1183 B_BE_HE_CTN_CHK_CCA_BITMAP | B_BE_HE_CTN_CHK_EDCCA_BITMAP |
1184 B_BE_HE_CTN_CHK_NO_GNT_WL | B_BE_HE_CTN_CHK_BASIC_NAV |
1185 B_BE_HE_CTN_CHK_INTRA_NAV | B_BE_HE_CTN_CHK_TX_NAV;
1186 rtw89_write32(rtwdev, reg, val32);
1187
1188 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx);
1189 val32 = B_BE_HE_SIFS_CHK_EDCCA_P20 | B_BE_HE_SIFS_CHK_EDCCA_BITMAP |
1190 B_BE_HE_SIFS_CHK_NO_GNT_WL;
1191 rtw89_write32(rtwdev, reg, val32);
1192
1193 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx);
1194 val32 = B_BE_TB_CHK_EDCCA_BITMAP | B_BE_TB_CHK_NO_GNT_WL | B_BE_TB_CHK_BASIC_NAV;
1195 rtw89_write32(rtwdev, reg, val32);
1196
1197 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx);
1198 rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN);
1199
1200 if (is_qta_poh(rtwdev)) {
1201 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx);
1202 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK,
1203 SCH_PREBKF_24US);
1204
1205 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx);
1206 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK,
1207 SCH_PREBKF_24US);
1208 }
1209
1210 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx);
1211 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32);
1212 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US);
1213
1214 if (chip->chip_id == RTL8922D) {
1215 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SCH_EDCA_RST_CFG, mac_idx);
1216 rtw89_write32_set(rtwdev, reg, B_BE_TX_NAV_RST_EDCA_EN);
1217 }
1218
1219 return 0;
1220 }
1221
addr_cam_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1222 static int addr_cam_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1223 {
1224 u32 val32;
1225 u16 val16;
1226 u32 reg;
1227 int ret;
1228
1229 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1230 if (ret)
1231 return ret;
1232
1233 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
1234 val32 = rtw89_read32(rtwdev, reg);
1235 val32 = u32_replace_bits(val32, ADDR_CAM_SERCH_RANGE, B_BE_ADDR_CAM_RANGE_MASK);
1236 val32 |= B_BE_ADDR_CAM_EN;
1237 if (mac_idx == RTW89_MAC_0)
1238 val32 |= B_BE_ADDR_CAM_CLR;
1239 rtw89_write32(rtwdev, reg, val32);
1240
1241 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
1242 ret = read_poll_timeout_atomic(rtw89_read16, val16, !(val16 & B_BE_ADDR_CAM_CLR),
1243 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
1244 if (ret)
1245 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
1246
1247 return ret;
1248 }
1249
rtw89_mac_typ_fltr_opt_be(struct rtw89_dev * rtwdev,enum rtw89_machdr_frame_type type,enum rtw89_mac_fwd_target fwd_target,u8 mac_idx)1250 static int rtw89_mac_typ_fltr_opt_be(struct rtw89_dev *rtwdev,
1251 enum rtw89_machdr_frame_type type,
1252 enum rtw89_mac_fwd_target fwd_target,
1253 u8 mac_idx)
1254 {
1255 u32 reg;
1256 u32 val;
1257
1258 switch (fwd_target) {
1259 case RTW89_FWD_DONT_CARE:
1260 val = RX_FLTR_FRAME_DROP_BE;
1261 break;
1262 case RTW89_FWD_TO_HOST:
1263 case RTW89_FWD_TO_WLAN_CPU:
1264 val = RX_FLTR_FRAME_ACCEPT_BE;
1265 break;
1266 default:
1267 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
1268 return -EINVAL;
1269 }
1270
1271 switch (type) {
1272 case RTW89_MGNT:
1273 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx);
1274 break;
1275 case RTW89_CTRL:
1276 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx);
1277 break;
1278 case RTW89_DATA:
1279 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx);
1280 break;
1281 default:
1282 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
1283 return -EINVAL;
1284 }
1285 rtw89_write32(rtwdev, reg, val);
1286
1287 return 0;
1288 }
1289
rx_fltr_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1290 static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1291 {
1292 u32 reg;
1293 u32 val;
1294
1295 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx);
1296 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx);
1297 rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx);
1298
1299 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
1300 val = B_BE_A_BC_CAM_MATCH | B_BE_A_UC_CAM_MATCH | B_BE_A_MC |
1301 B_BE_A_BC | B_BE_A_A1_MATCH | B_BE_SNIFFER_MODE |
1302 u32_encode_bits(15, B_BE_UID_FILTER_MASK);
1303 rtw89_write32(rtwdev, reg, val);
1304 u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK);
1305
1306 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1307 val = B_BE_HE_SIGB_CRC_CHK | B_BE_VHT_MU_SIGB_CRC_CHK |
1308 B_BE_VHT_SU_SIGB_CRC_CHK | B_BE_SIGA_CRC_CHK |
1309 B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK;
1310 rtw89_write16(rtwdev, reg, val);
1311
1312 return 0;
1313 }
1314
cca_ctrl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1315 static int cca_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1316 {
1317 return 0;
1318 }
1319
nav_ctrl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1320 static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1321 {
1322 u32 val32;
1323 u32 reg;
1324
1325 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx);
1326
1327 val32 = rtw89_read32(rtwdev, reg);
1328 val32 &= ~B_BE_WMAC_PLCP_UP_NAV_EN;
1329 val32 |= B_BE_WMAC_TF_UP_NAV_EN | B_BE_WMAC_NAV_UPPER_EN;
1330 val32 = u32_replace_bits(val32, NAV_25MS, B_BE_WMAC_NAV_UPPER_MASK);
1331
1332 rtw89_write32(rtwdev, reg, val32);
1333
1334 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SPECIAL_TX_SETTING, mac_idx);
1335 rtw89_write32_clr(rtwdev, reg, B_BE_BMC_NAV_PROTECT);
1336
1337 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
1338 rtw89_write32_set(rtwdev, reg, B_BE_WMAC_MBA_DUR_FORCE);
1339
1340 return 0;
1341 }
1342
spatial_reuse_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1343 static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1344 {
1345 u32 reg;
1346 int ret;
1347
1348 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1349 if (ret)
1350 return ret;
1351
1352 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx);
1353 rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN);
1354
1355 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx);
1356 rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN);
1357
1358 return 0;
1359 }
1360
tmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1361 static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1362 {
1363 const struct rtw89_chip_info *chip = rtwdev->chip;
1364 struct rtw89_hal *hal = &rtwdev->hal;
1365 u32 reg;
1366
1367 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_PPDU_CTRL, mac_idx);
1368 rtw89_write32_clr(rtwdev, reg, B_BE_QOSNULL_UPD_MUEDCA_EN);
1369
1370 if (chip->chip_id == RTL8922A) {
1371 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx);
1372 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12);
1373 rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe);
1374 }
1375
1376 if (chip->chip_id == RTL8922D && hal->cid != RTL8922D_CID7090) {
1377 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_COMMON_PHYINTF_CTRL_0, mac_idx);
1378 rtw89_write32_clr(rtwdev, reg, CLEAR_DTOP_DIS);
1379 }
1380
1381 return 0;
1382 }
1383
trxptcl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1384 static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1385 {
1386 const struct rtw89_chip_info *chip = rtwdev->chip;
1387 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
1388 struct rtw89_hal *hal = &rtwdev->hal;
1389 u32 val32;
1390 u32 reg;
1391 int ret;
1392
1393 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1394 if (ret)
1395 return ret;
1396
1397 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx);
1398 val32 = rtw89_read32(rtwdev, reg);
1399 val32 = u32_replace_bits(val32, S_BE_MACLBK_PLCP_DLY_DEF,
1400 B_BE_MACLBK_PLCP_DLY_MASK);
1401 val32 &= ~B_BE_MACLBK_EN;
1402 rtw89_write32(rtwdev, reg, val32);
1403
1404 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
1405 rtw89_write32_set(rtwdev, reg, B_BE_PHYINTF_EN);
1406
1407 if (chip->chip_id == RTL8922D) {
1408 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_2, mac_idx);
1409 rtw89_write32_set(rtwdev, reg, B_BE_PLCP_PHASE_B_CRC_CHK_EN |
1410 B_BE_PLCP_PHASE_A_CRC_CHK_EN);
1411 }
1412
1413 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx);
1414 val32 = rtw89_read32(rtwdev, reg);
1415 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_CCK,
1416 B_BE_WMAC_SPEC_SIFS_CCK_MASK);
1417 val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_OFDM_1115E,
1418 B_BE_WMAC_SPEC_SIFS_OFDM_MASK);
1419 rtw89_write32(rtwdev, reg, val32);
1420
1421 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY, mac_idx);
1422 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA);
1423
1424 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE, mac_idx);
1425 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_HE_CHK_EDCCA);
1426
1427 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC, mac_idx);
1428 rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA);
1429
1430 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXTRIG_TEST_USER_2, mac_idx);
1431 rtw89_write32_set(rtwdev, reg, B_BE_RXTRIG_FCSCHK_EN);
1432
1433 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_1, mac_idx);
1434 val32 = rtw89_read32(rtwdev, reg);
1435 val32 &= B_BE_FTM_RRSR_RATE_EN_MASK | B_BE_WMAC_RESP_DOPPLEB_BE_EN |
1436 B_BE_WMAC_RESP_DCM_EN | B_BE_WMAC_RESP_REF_RATE_MASK;
1437 rtw89_write32(rtwdev, reg, val32);
1438 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
1439
1440 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx);
1441 val32 = rtw89_read32(rtwdev, reg);
1442 val32 &= B_BE_RRSR_RATE_EN_MASK | B_BE_RRSR_CCK_MASK | B_BE_RSC_MASK;
1443 rtw89_write32(rtwdev, reg, val32);
1444
1445 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR0, mac_idx);
1446 val32 = rtw89_read32(rtwdev, reg);
1447 val32 &= B_BE_RRSR_OFDM_MASK | B_BE_RRSR_HT_MASK | B_BE_RRSR_VHT_MASK |
1448 B_BE_RRSR_HE_MASK;
1449 rtw89_write32(rtwdev, reg, val32);
1450
1451 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) {
1452 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx);
1453 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1);
1454 }
1455
1456 return 0;
1457 }
1458
rst_bacam_be(struct rtw89_dev * rtwdev)1459 static int rst_bacam_be(struct rtw89_dev *rtwdev)
1460 {
1461 u32 val;
1462 int ret;
1463
1464 rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK,
1465 S_BE_BACAM_RST_ALL);
1466
1467 ret = read_poll_timeout_atomic(rtw89_read32_mask, val, val == S_BE_BACAM_RST_DONE,
1468 1, 1000, false,
1469 rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK);
1470 if (ret)
1471 rtw89_err(rtwdev, "[ERR]bacam rst timeout\n");
1472
1473 return ret;
1474 }
1475
1476 #define PLD_RLS_MAX_PG 127
1477 #define RX_MAX_LEN_UNIT 512
1478 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
1479
rmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1480 static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1481 {
1482 const struct rtw89_chip_info *chip = rtwdev->chip;
1483 u32 rx_min_qta, rx_max_len, rx_max_pg;
1484 u16 val16;
1485 u32 reg;
1486 int ret;
1487
1488 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1489 if (ret)
1490 return ret;
1491
1492 if (mac_idx == RTW89_MAC_0) {
1493 ret = rst_bacam_be(rtwdev);
1494 if (ret)
1495 return ret;
1496 }
1497
1498 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx);
1499 val16 = rtw89_read16(rtwdev, reg);
1500 val16 = u16_replace_bits(val16, TRXCFG_RMAC_DATA_TO, B_BE_RX_DLK_DATA_TIME_MASK);
1501 val16 = u16_replace_bits(val16, TRXCFG_RMAC_CCA_TO, B_BE_RX_DLK_CCA_TIME_MASK);
1502 val16 |= B_BE_RX_DLK_RST_EN;
1503 rtw89_write16(rtwdev, reg, val16);
1504
1505 if (mac_idx == RTW89_MAC_0)
1506 rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta;
1507 else
1508 rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta;
1509 rx_max_pg = min_t(u32, rx_min_qta, PLD_RLS_MAX_PG);
1510 rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size;
1511 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN);
1512 rx_max_len /= RX_MAX_LEN_UNIT;
1513
1514 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
1515 rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len);
1516
1517 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1518 rtw89_write8_clr(rtwdev, reg, B_BE_VHT_SU_SIGB_CRC_CHK);
1519
1520 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx);
1521 rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN);
1522
1523 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx);
1524 rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC);
1525
1526 if (chip->chip_id == RTL8922D) {
1527 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSR_UPD_CTRL, mac_idx);
1528 rtw89_write32_set(rtwdev, reg, B_BE_QSIZE_RULE);
1529
1530 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXGCK_CTRL, mac_idx);
1531 rtw89_write16_mask(rtwdev, reg, B_BE_RXGCK_GCK_RATE_LIMIT_MASK, RX_GCK_LEGACY);
1532
1533 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
1534 rtw89_write32_set(rtwdev, reg, B_BE_DIS_CHK_MIN_LEN);
1535 }
1536
1537 return 0;
1538 }
1539
resp_pktctl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1540 static int resp_pktctl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1541 {
1542 struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
1543 enum rtw89_mac_dle_rsvd_qt_type type;
1544 u32 reg;
1545 int ret;
1546
1547 if (mac_idx == RTW89_MAC_1)
1548 type = DLE_RSVD_QT_B1_CSI;
1549 else
1550 type = DLE_RSVD_QT_B0_CSI;
1551
1552 ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, type, &qt_cfg);
1553 if (ret) {
1554 rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", type, ret);
1555 return ret;
1556 }
1557
1558 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx);
1559 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid);
1560 rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num + 1);
1561
1562 return 0;
1563 }
1564
cmac_com_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1565 static int cmac_com_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1566 {
1567 u32 val32;
1568 int ret;
1569
1570 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1571 if (ret)
1572 return ret;
1573
1574 if (mac_idx == RTW89_MAC_0) {
1575 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE);
1576 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_8, B_BE_TXSB_20M_MASK);
1577 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_4, B_BE_TXSB_40M_MASK);
1578 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_2, B_BE_TXSB_80M_MASK);
1579 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_1, B_BE_TXSB_160M_MASK);
1580 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE, val32);
1581 } else {
1582 val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1);
1583 val32 = u32_replace_bits(val32, S_BE_TXSB_20M_2, B_BE_TXSB_20M_MASK);
1584 val32 = u32_replace_bits(val32, S_BE_TXSB_40M_1, B_BE_TXSB_40M_MASK);
1585 val32 = u32_replace_bits(val32, S_BE_TXSB_80M_0, B_BE_TXSB_80M_MASK);
1586 val32 = u32_replace_bits(val32, S_BE_TXSB_160M_0, B_BE_TXSB_160M_MASK);
1587 rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1, val32);
1588 }
1589
1590 return 0;
1591 }
1592
ptcl_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1593 static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1594 {
1595 const struct rtw89_chip_info *chip = rtwdev->chip;
1596 u32 val32;
1597 u8 val8;
1598 u32 reg;
1599 int ret;
1600
1601 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1602 if (ret)
1603 return ret;
1604
1605 if (is_qta_poh(rtwdev)) {
1606 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx);
1607 val32 = rtw89_read32(rtwdev, reg);
1608 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_1K,
1609 B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK);
1610 if (chip->chip_id == RTL8922A)
1611 val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B,
1612 B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
1613 val32 |= B_BE_HW_CTS2SELF_EN;
1614 rtw89_write32(rtwdev, reg, val32);
1615
1616 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_FSM_MON, mac_idx);
1617 val32 = rtw89_read32(rtwdev, reg);
1618 val32 = u32_replace_bits(val32, S_AX_PTCL_TO_2MS,
1619 B_BE_PTCL_TX_ARB_TO_THR_MASK);
1620 val32 &= ~B_BE_PTCL_TX_ARB_TO_MODE;
1621 rtw89_write32(rtwdev, reg, val32);
1622 }
1623
1624 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_COMMON_SETTING_0, mac_idx);
1625 val8 = rtw89_read8(rtwdev, reg);
1626 val8 |= B_BE_CMAC_TX_MODE_0 | B_BE_CMAC_TX_MODE_1;
1627 val8 &= ~(B_BE_PTCL_TRIGGER_SS_EN_0 |
1628 B_BE_PTCL_TRIGGER_SS_EN_1 |
1629 B_BE_PTCL_TRIGGER_SS_EN_UL);
1630 rtw89_write8(rtwdev, reg, val8);
1631
1632 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1633 if (chip->chip_id == RTL8922A)
1634 val32 = AMPDU_MAX_TIME;
1635 else
1636 val32 = AMPDU_MAX_TIME_V1;
1637 rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, val32);
1638
1639 if (chip->chip_id == RTL8922D) {
1640 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AGG_BK_0, mac_idx);
1641 rtw89_write32_clr(rtwdev, reg, B_BE_WDBK_CFG | B_BE_EN_RTY_BK |
1642 B_BE_EN_RTY_BK_COD);
1643
1644 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx);
1645 rtw89_write32_mask(rtwdev, reg, B_BE_MAX_AGG_NUM_MASK,
1646 MAX_TX_AMPDU_NUM_V1 - 1);
1647 }
1648
1649 if (rtw89_mac_chk_preload_allow(rtwdev)) {
1650 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AGG_BK_0, mac_idx);
1651 rtw89_write32_set(rtwdev, reg, B_BE_PRELD_MGQ0_EN |
1652 B_BE_PRELD_HIQ_P4_EN |
1653 B_BE_PRELD_HIQ_P3_EN |
1654 B_BE_PRELD_HIQ_P2_EN |
1655 B_BE_PRELD_HIQ_P1_EN |
1656 B_BE_PRELD_HIQ_P0MB15_EN |
1657 B_BE_PRELD_HIQ_P0MB14_EN |
1658 B_BE_PRELD_HIQ_P0MB13_EN |
1659 B_BE_PRELD_HIQ_P0MB12_EN |
1660 B_BE_PRELD_HIQ_P0MB11_EN |
1661 B_BE_PRELD_HIQ_P0MB10_EN |
1662 B_BE_PRELD_HIQ_P0MB9_EN |
1663 B_BE_PRELD_HIQ_P0MB8_EN |
1664 B_BE_PRELD_HIQ_P0MB7_EN |
1665 B_BE_PRELD_HIQ_P0MB6_EN |
1666 B_BE_PRELD_HIQ_P0MB5_EN |
1667 B_BE_PRELD_HIQ_P0MB4_EN |
1668 B_BE_PRELD_HIQ_P0MB3_EN |
1669 B_BE_PRELD_HIQ_P0MB2_EN |
1670 B_BE_PRELD_HIQ_P0MB1_EN |
1671 B_BE_PRELD_HIQ_P0_EN);
1672 }
1673
1674 return 0;
1675 }
1676
cmac_dma_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1677 static int cmac_dma_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1678 {
1679 u32 val32;
1680 u32 reg;
1681 int ret;
1682
1683 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1684 if (ret)
1685 return ret;
1686
1687 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_CTRL_1, mac_idx);
1688
1689 val32 = rtw89_read32(rtwdev, reg);
1690 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID,
1691 B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK);
1692 val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID,
1693 B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK);
1694 rtw89_write32(rtwdev, reg, val32);
1695
1696 return 0;
1697 }
1698
cmac_init_be(struct rtw89_dev * rtwdev,u8 mac_idx)1699 static int cmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1700 {
1701 int ret;
1702
1703 ret = scheduler_init_be(rtwdev, mac_idx);
1704 if (ret) {
1705 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
1706 return ret;
1707 }
1708
1709 ret = addr_cam_init_be(rtwdev, mac_idx);
1710 if (ret) {
1711 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
1712 ret);
1713 return ret;
1714 }
1715
1716 ret = rx_fltr_init_be(rtwdev, mac_idx);
1717 if (ret) {
1718 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
1719 ret);
1720 return ret;
1721 }
1722
1723 ret = cca_ctrl_init_be(rtwdev, mac_idx);
1724 if (ret) {
1725 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
1726 ret);
1727 return ret;
1728 }
1729
1730 ret = nav_ctrl_init_be(rtwdev, mac_idx);
1731 if (ret) {
1732 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
1733 ret);
1734 return ret;
1735 }
1736
1737 ret = spatial_reuse_init_be(rtwdev, mac_idx);
1738 if (ret) {
1739 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
1740 mac_idx, ret);
1741 return ret;
1742 }
1743
1744 ret = tmac_init_be(rtwdev, mac_idx);
1745 if (ret) {
1746 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
1747 return ret;
1748 }
1749
1750 ret = trxptcl_init_be(rtwdev, mac_idx);
1751 if (ret) {
1752 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
1753 return ret;
1754 }
1755
1756 ret = rmac_init_be(rtwdev, mac_idx);
1757 if (ret) {
1758 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
1759 return ret;
1760 }
1761
1762 ret = resp_pktctl_init_be(rtwdev, mac_idx);
1763 if (ret) {
1764 rtw89_err(rtwdev, "[ERR]CMAC%d resp pktctl init %d\n", mac_idx, ret);
1765 return ret;
1766 }
1767
1768 ret = cmac_com_init_be(rtwdev, mac_idx);
1769 if (ret) {
1770 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
1771 return ret;
1772 }
1773
1774 ret = ptcl_init_be(rtwdev, mac_idx);
1775 if (ret) {
1776 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
1777 return ret;
1778 }
1779
1780 ret = cmac_dma_init_be(rtwdev, mac_idx);
1781 if (ret) {
1782 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
1783 return ret;
1784 }
1785
1786 return ret;
1787 }
1788
tx_idle_poll_band_be(struct rtw89_dev * rtwdev,u8 mac_idx)1789 static int tx_idle_poll_band_be(struct rtw89_dev *rtwdev, u8 mac_idx)
1790 {
1791 u32 reg;
1792 u8 val8;
1793 int ret;
1794
1795 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1796 if (ret)
1797 return ret;
1798
1799 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_TX_CTN_SEL, mac_idx);
1800
1801 ret = read_poll_timeout_atomic(rtw89_read8, val8, !(val8 & B_BE_PTCL_BUSY),
1802 30, 66000, false, rtwdev, reg);
1803
1804 return ret;
1805 }
1806
dle_buf_req_be(struct rtw89_dev * rtwdev,u16 buf_len,bool wd,u16 * pkt_id)1807 static int dle_buf_req_be(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
1808 {
1809 u32 val, reg;
1810 int ret;
1811
1812 reg = wd ? R_BE_WD_BUF_REQ : R_BE_PL_BUF_REQ;
1813 val = buf_len;
1814 val |= B_BE_WD_BUF_REQ_EXEC;
1815 rtw89_write32(rtwdev, reg, val);
1816
1817 reg = wd ? R_BE_WD_BUF_STATUS : R_BE_PL_BUF_STATUS;
1818
1819 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_BUF_STAT_DONE,
1820 1, 2000, false, rtwdev, reg);
1821 if (ret)
1822 return ret;
1823
1824 *pkt_id = u32_get_bits(val, B_BE_WD_BUF_STAT_PKTID_MASK);
1825 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID)
1826 return -ENOENT;
1827
1828 return 0;
1829 }
1830
set_cpuio_be(struct rtw89_dev * rtwdev,struct rtw89_cpuio_ctrl * ctrl_para,bool wd)1831 static int set_cpuio_be(struct rtw89_dev *rtwdev,
1832 struct rtw89_cpuio_ctrl *ctrl_para, bool wd)
1833 {
1834 u32 val_op0, val_op1, val_op2, val_op3;
1835 u32 val, cmd_type, reg;
1836 int ret;
1837
1838 cmd_type = ctrl_para->cmd_type;
1839
1840 reg = wd ? R_BE_WD_CPUQ_OP_3 : R_BE_PL_CPUQ_OP_3;
1841 val_op3 = u32_replace_bits(0, ctrl_para->start_pktid,
1842 B_BE_WD_CPUQ_OP_STRT_PKTID_MASK);
1843 val_op3 = u32_replace_bits(val_op3, ctrl_para->end_pktid,
1844 B_BE_WD_CPUQ_OP_END_PKTID_MASK);
1845 rtw89_write32(rtwdev, reg, val_op3);
1846
1847 reg = wd ? R_BE_WD_CPUQ_OP_1 : R_BE_PL_CPUQ_OP_1;
1848 val_op1 = u32_replace_bits(0, ctrl_para->src_pid,
1849 B_BE_WD_CPUQ_OP_SRC_PID_MASK);
1850 val_op1 = u32_replace_bits(val_op1, ctrl_para->src_qid,
1851 B_BE_WD_CPUQ_OP_SRC_QID_MASK);
1852 val_op1 = u32_replace_bits(val_op1, ctrl_para->macid,
1853 B_BE_WD_CPUQ_OP_SRC_MACID_MASK);
1854 rtw89_write32(rtwdev, reg, val_op1);
1855
1856 reg = wd ? R_BE_WD_CPUQ_OP_2 : R_BE_PL_CPUQ_OP_2;
1857 val_op2 = u32_replace_bits(0, ctrl_para->dst_pid,
1858 B_BE_WD_CPUQ_OP_DST_PID_MASK);
1859 val_op2 = u32_replace_bits(val_op2, ctrl_para->dst_qid,
1860 B_BE_WD_CPUQ_OP_DST_QID_MASK);
1861 val_op2 = u32_replace_bits(val_op2, ctrl_para->macid,
1862 B_BE_WD_CPUQ_OP_DST_MACID_MASK);
1863 rtw89_write32(rtwdev, reg, val_op2);
1864
1865 reg = wd ? R_BE_WD_CPUQ_OP_0 : R_BE_PL_CPUQ_OP_0;
1866 val_op0 = u32_replace_bits(0, cmd_type,
1867 B_BE_WD_CPUQ_OP_CMD_TYPE_MASK);
1868 val_op0 = u32_replace_bits(val_op0, ctrl_para->pkt_num,
1869 B_BE_WD_CPUQ_OP_PKTNUM_MASK);
1870 val_op0 |= B_BE_WD_CPUQ_OP_EXEC;
1871 rtw89_write32(rtwdev, reg, val_op0);
1872
1873 reg = wd ? R_BE_WD_CPUQ_OP_STATUS : R_BE_PL_CPUQ_OP_STATUS;
1874
1875 ret = read_poll_timeout(rtw89_read32, val, val & B_BE_WD_CPUQ_OP_STAT_DONE,
1876 1, 2000, false, rtwdev, reg);
1877 if (ret) {
1878 rtw89_err(rtwdev, "[ERR]set cpuio wd timeout\n");
1879 rtw89_err(rtwdev, "[ERR]op_0=0x%X, op_1=0x%X, op_2=0x%X\n",
1880 val_op0, val_op1, val_op2);
1881 return ret;
1882 }
1883
1884 if (cmd_type == CPUIO_OP_CMD_GET_NEXT_PID ||
1885 cmd_type == CPUIO_OP_CMD_GET_1ST_PID)
1886 ctrl_para->pktid = u32_get_bits(val, B_BE_WD_CPUQ_OP_PKTID_MASK);
1887
1888 return 0;
1889 }
1890
dle_upd_qta_aval_page_be(struct rtw89_dev * rtwdev,enum rtw89_mac_dle_ctrl_type type,enum rtw89_mac_dle_ple_quota_id quota_id)1891 static int dle_upd_qta_aval_page_be(struct rtw89_dev *rtwdev,
1892 enum rtw89_mac_dle_ctrl_type type,
1893 enum rtw89_mac_dle_ple_quota_id quota_id)
1894 {
1895 u32 val;
1896
1897 if (type == DLE_CTRL_TYPE_WDE) {
1898 rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL,
1899 B_BE_WDE_AVAL_UPD_QTAID_MASK, quota_id);
1900 rtw89_write32_set(rtwdev, R_BE_WDE_BUFMGN_CTL, B_BE_WDE_AVAL_UPD_REQ);
1901
1902 return read_poll_timeout(rtw89_read32, val,
1903 !(val & B_BE_WDE_AVAL_UPD_REQ),
1904 1, 2000, false, rtwdev, R_BE_WDE_BUFMGN_CTL);
1905 } else if (type == DLE_CTRL_TYPE_PLE) {
1906 rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL,
1907 B_BE_PLE_AVAL_UPD_QTAID_MASK, quota_id);
1908 rtw89_write32_set(rtwdev, R_BE_PLE_BUFMGN_CTL, B_BE_PLE_AVAL_UPD_REQ);
1909
1910 return read_poll_timeout(rtw89_read32, val,
1911 !(val & B_BE_PLE_AVAL_UPD_REQ),
1912 1, 2000, false, rtwdev, R_BE_PLE_BUFMGN_CTL);
1913 }
1914
1915 rtw89_warn(rtwdev, "%s wrong type %d\n", __func__, type);
1916 return -EINVAL;
1917 }
1918
dle_quota_change_be(struct rtw89_dev * rtwdev,bool band1_en)1919 static int dle_quota_change_be(struct rtw89_dev *rtwdev, bool band1_en)
1920 {
1921 int ret;
1922
1923 if (band1_en) {
1924 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1925 PLE_QTAID_B0_TXPL);
1926 if (ret) {
1927 rtw89_err(rtwdev, "update PLE B0 TX avail page fail %d\n", ret);
1928 return ret;
1929 }
1930
1931 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1932 PLE_QTAID_CMAC0_RX);
1933 if (ret) {
1934 rtw89_err(rtwdev, "update PLE CMAC0 RX avail page fail %d\n", ret);
1935 return ret;
1936 }
1937 } else {
1938 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1939 PLE_QTAID_B1_TXPL);
1940 if (ret) {
1941 rtw89_err(rtwdev, "update PLE B1 TX avail page fail %d\n", ret);
1942 return ret;
1943 }
1944
1945 ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
1946 PLE_QTAID_CMAC1_RX);
1947 if (ret) {
1948 rtw89_err(rtwdev, "update PLE CMAC1 RX avail page fail %d\n", ret);
1949 return ret;
1950 }
1951 }
1952
1953 return 0;
1954 }
1955
preload_init_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_qta_mode mode)1956 static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
1957 enum rtw89_qta_mode mode)
1958 {
1959 const struct rtw89_chip_info *chip = rtwdev->chip;
1960 u32 max_preld_size, min_rsvd_size;
1961 u8 preld_acq, preld_miscq;
1962 u32 val32;
1963 u32 reg;
1964
1965 if (!(chip->chip_id == RTL8922A || rtw89_mac_chk_preload_allow(rtwdev)))
1966 return 0;
1967
1968 max_preld_size = mac_idx == RTW89_MAC_0 ?
1969 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM;
1970 if (chip->chip_id == RTL8922D)
1971 max_preld_size = PRELD_B01_ENT_NUM_8922D;
1972 max_preld_size *= PRELD_AMSDU_SIZE;
1973 min_rsvd_size = PRELD_NEXT_MIN_SIZE;
1974
1975 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 :
1976 R_BE_TXPKTCTL_B1_PRELD_CFG1;
1977 val32 = rtw89_read32(rtwdev, reg);
1978 val32 = u32_replace_bits(val32, PRELD_NEXT_WND, B_BE_B0_PRELD_NXT_TXENDWIN_MASK);
1979 val32 = u32_replace_bits(val32, min_rsvd_size, B_BE_B0_PRELD_NXT_RSVMINSZ_MASK);
1980 rtw89_write32(rtwdev, reg, val32);
1981
1982 reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 :
1983 R_BE_TXPKTCTL_B1_PRELD_CFG0;
1984 if (chip->chip_id == RTL8922D) {
1985 preld_acq = PRELD_ACQ_ENT_NUM_8922D;
1986 preld_miscq = PRELD_MISCQ_ENT_NUM_8922D;
1987 } else {
1988 preld_acq = mac_idx == RTW89_MAC_0 ? PRELD_B0_ACQ_ENT_NUM_8922A :
1989 PRELD_B1_ACQ_ENT_NUM_8922A;
1990 preld_miscq = PRELD_MISCQ_ENT_NUM_8922A;
1991 }
1992
1993 val32 = rtw89_read32(rtwdev, reg);
1994 val32 = u32_replace_bits(val32, preld_acq, B_BE_B0_PRELD_CAM_G0ENTNUM_MASK);
1995 val32 = u32_replace_bits(val32, preld_miscq, B_BE_B0_PRELD_CAM_G1ENTNUM_MASK);
1996 val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK);
1997 val32 |= B_BE_B0_PRELD_FEN;
1998 rtw89_write32(rtwdev, reg, val32);
1999
2000 return 0;
2001 }
2002
clr_aon_intr_be(struct rtw89_dev * rtwdev)2003 static void clr_aon_intr_be(struct rtw89_dev *rtwdev)
2004 {
2005 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
2006 return;
2007
2008 rtw89_write32_clr(rtwdev, R_BE_FWS0IMR, B_BE_FS_GPIOA_INT_EN);
2009 rtw89_write32_set(rtwdev, R_BE_FWS0ISR, B_BE_FS_GPIOA_INT);
2010 }
2011
dbcc_bb_ctrl_be(struct rtw89_dev * rtwdev,bool bb1_en)2012 static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en)
2013 {
2014 u32 set = B_BE_FEN_BB1PLAT_RSTB | B_BE_FEN_BB1_IP_RSTN;
2015
2016 if (bb1_en)
2017 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, set);
2018 else
2019 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, set);
2020
2021 return 0;
2022 }
2023
enable_imr_be(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)2024 static int enable_imr_be(struct rtw89_dev *rtwdev, u8 mac_idx,
2025 enum rtw89_mac_hwmod_sel sel)
2026 {
2027 const struct rtw89_chip_info *chip = rtwdev->chip;
2028 const struct rtw89_imr_table *table;
2029 const struct rtw89_reg_imr *reg;
2030 u32 addr;
2031 u32 val;
2032 int i;
2033
2034 if (sel == RTW89_DMAC_SEL)
2035 table = chip->imr_dmac_table;
2036 else if (sel == RTW89_CMAC_SEL)
2037 table = chip->imr_cmac_table;
2038 else
2039 return -EINVAL;
2040
2041 if (chip->chip_id == RTL8922D)
2042 rtw89_write32_mask(rtwdev, R_BE_NO_RX_ERR_CFG,
2043 B_BE_NO_RX_ERR_TO_MASK, 0);
2044
2045 for (i = 0; i < table->n_regs; i++) {
2046 reg = &table->regs[i];
2047 addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx);
2048
2049 val = rtw89_read32(rtwdev, addr);
2050 val &= ~reg->clr;
2051 val |= reg->set;
2052 rtw89_write32(rtwdev, addr, val);
2053 }
2054
2055 return 0;
2056 }
2057
err_imr_ctrl_be(struct rtw89_dev * rtwdev,bool en)2058 static void err_imr_ctrl_be(struct rtw89_dev *rtwdev, bool en)
2059 {
2060 u32 v32_dmac = en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS;
2061 u32 v32_cmac0 = en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS;
2062 u32 v32_cmac1 = en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS;
2063
2064 v32_dmac &= ~B_BE_DMAC_NOTX_ERR_INT_EN;
2065
2066 rtw89_write32(rtwdev, R_BE_DMAC_ERR_IMR, v32_dmac);
2067 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR, v32_cmac0);
2068
2069 if (rtwdev->dbcc_en)
2070 rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR_C1, v32_cmac1);
2071 }
2072
band1_enable_be(struct rtw89_dev * rtwdev)2073 static int band1_enable_be(struct rtw89_dev *rtwdev)
2074 {
2075 int ret;
2076
2077 ret = tx_idle_poll_band_be(rtwdev, RTW89_MAC_0);
2078 if (ret) {
2079 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
2080 return ret;
2081 }
2082
2083 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
2084 if (ret) {
2085 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
2086 return ret;
2087 }
2088
2089 ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode);
2090 if (ret) {
2091 rtw89_err(rtwdev, "[ERR]preload init B1 %d\n", ret);
2092 return ret;
2093 }
2094
2095 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, true);
2096 if (ret) {
2097 rtw89_err(rtwdev, "[ERR]CMAC%d pwr en %d\n", RTW89_MAC_1, ret);
2098 return ret;
2099 }
2100
2101 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true);
2102 if (ret) {
2103 rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret);
2104 return ret;
2105 }
2106
2107 ret = cmac_init_be(rtwdev, RTW89_MAC_1);
2108 if (ret) {
2109 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", RTW89_MAC_1, ret);
2110 return ret;
2111 }
2112
2113 ret = dbcc_bb_ctrl_be(rtwdev, true);
2114 if (ret) {
2115 rtw89_err(rtwdev, "[ERR]enable bb 1 %d\n", ret);
2116 return ret;
2117 }
2118
2119 ret = enable_imr_be(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
2120 if (ret) {
2121 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
2122 return ret;
2123 }
2124
2125 return 0;
2126 }
2127
band1_disable_be(struct rtw89_dev * rtwdev)2128 static int band1_disable_be(struct rtw89_dev *rtwdev)
2129 {
2130 int ret;
2131
2132 ret = dbcc_bb_ctrl_be(rtwdev, false);
2133 if (ret) {
2134 rtw89_err(rtwdev, "[ERR]disable bb 1 %d\n", ret);
2135 return ret;
2136 }
2137
2138 ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, false);
2139 if (ret) {
2140 rtw89_err(rtwdev, "[ERR]CMAC%d func dis %d\n", RTW89_MAC_1, ret);
2141 return ret;
2142 }
2143
2144 ret = cmac_pwr_en_be(rtwdev, RTW89_MAC_1, false);
2145 if (ret) {
2146 rtw89_err(rtwdev, "[ERR]CMAC%d pwr dis %d\n", RTW89_MAC_1, ret);
2147 return ret;
2148 }
2149
2150 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false);
2151 if (ret) {
2152 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
2153 return ret;
2154 }
2155
2156 return 0;
2157 }
2158
dbcc_enable_be(struct rtw89_dev * rtwdev,bool enable)2159 static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable)
2160 {
2161 int ret;
2162
2163 if (enable) {
2164 ret = band1_enable_be(rtwdev);
2165 if (ret) {
2166 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
2167 return ret;
2168 }
2169
2170 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {
2171 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, true);
2172 if (ret) {
2173 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n",
2174 __func__, ret);
2175 return ret;
2176 }
2177 }
2178 } else {
2179 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) {
2180 ret = rtw89_fw_h2c_notify_dbcc(rtwdev, false);
2181 if (ret) {
2182 rtw89_err(rtwdev, "%s:[ERR] notify dbcc1 fail %d\n",
2183 __func__, ret);
2184 return ret;
2185 }
2186 }
2187
2188 ret = band1_disable_be(rtwdev);
2189 if (ret) {
2190 rtw89_err(rtwdev, "[ERR] band1_disable %d\n", ret);
2191 return ret;
2192 }
2193 }
2194
2195 return 0;
2196 }
2197
set_host_rpr_be(struct rtw89_dev * rtwdev)2198 static int set_host_rpr_be(struct rtw89_dev *rtwdev)
2199 {
2200 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2201 u32 val32;
2202 u32 mode;
2203 u32 fltr;
2204 u32 qid;
2205 bool poh;
2206
2207 poh = is_qta_poh(rtwdev);
2208
2209 if (poh) {
2210 mode = RTW89_RPR_MODE_POH;
2211 qid = WDRLS_DEST_QID_POH;
2212 } else {
2213 mode = RTW89_RPR_MODE_STF;
2214 fltr = 0;
2215 qid = WDRLS_DEST_QID_STF;
2216 }
2217
2218 if (chip_id == RTL8922A) {
2219 fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT |
2220 S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID;
2221 } else {
2222 fltr = S_BE_WDRLS_FLTR_TXOK_V1 | S_BE_WDRLS_FLTR_RTYLMT_V1 |
2223 S_BE_WDRLS_FLTR_LIFTIM_V1 | S_BE_WDRLS_FLTR_MACID_V1;
2224 }
2225
2226 rtw89_write32_mask(rtwdev, R_BE_WDRLS_CFG, B_BE_WDRLS_MODE_MASK, mode);
2227 rtw89_write32_mask(rtwdev, R_BE_RLSRPT0_CFG0, B_BE_RLSRPT0_QID_MASK, qid);
2228
2229 val32 = rtw89_read32(rtwdev, R_BE_RLSRPT0_CFG1);
2230 if (chip_id == RTL8922A)
2231 val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK);
2232 else
2233 val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_V1_MASK);
2234 val32 = u32_replace_bits(val32, 30, B_BE_RLSRPT0_AGGNUM_MASK);
2235 val32 = u32_replace_bits(val32, 255, B_BE_RLSRPT0_TO_MASK);
2236 rtw89_write32(rtwdev, R_BE_RLSRPT0_CFG1, val32);
2237
2238 return 0;
2239 }
2240
trx_init_be(struct rtw89_dev * rtwdev)2241 static int trx_init_be(struct rtw89_dev *rtwdev)
2242 {
2243 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2244 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
2245 int ret;
2246
2247 ret = dmac_init_be(rtwdev, 0);
2248 if (ret) {
2249 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
2250 return ret;
2251 }
2252
2253 ret = cmac_init_be(rtwdev, 0);
2254 if (ret) {
2255 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
2256 return ret;
2257 }
2258
2259 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) {
2260 ret = dbcc_enable_be(rtwdev, true);
2261 if (ret) {
2262 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
2263 return ret;
2264 }
2265 }
2266
2267 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2268 if (ret) {
2269 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
2270 return ret;
2271 }
2272
2273 ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
2274 if (ret) {
2275 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
2276 return ret;
2277 }
2278
2279 err_imr_ctrl_be(rtwdev, true);
2280
2281 ret = set_host_rpr_be(rtwdev);
2282 if (ret) {
2283 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
2284 return ret;
2285 }
2286
2287 if (chip_id == RTL8922A)
2288 rtw89_write32_clr(rtwdev, R_BE_RSP_CHK_SIG,
2289 B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN);
2290
2291 return 0;
2292 }
2293
rtw89_mac_cfg_gnt_v2(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)2294 int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev,
2295 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
2296 {
2297 u32 val = 0;
2298
2299 if (gnt_cfg->band[0].gnt_bt)
2300 val |= B_BE_GNT_BT_BB0_VAL | B_BE_GNT_BT_RX_BB0_VAL |
2301 B_BE_GNT_BT_TX_BB0_VAL;
2302
2303 if (gnt_cfg->band[0].gnt_bt_sw_en)
2304 val |= B_BE_GNT_BT_BB0_SWCTRL | B_BE_GNT_BT_RX_BB0_SWCTRL |
2305 B_BE_GNT_BT_TX_BB0_SWCTRL;
2306
2307 if (gnt_cfg->band[0].gnt_wl)
2308 val |= B_BE_GNT_WL_BB0_VAL | B_BE_GNT_WL_RX_VAL |
2309 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL;
2310
2311 if (gnt_cfg->band[0].gnt_wl_sw_en)
2312 val |= B_BE_GNT_WL_BB0_SWCTRL | B_BE_GNT_WL_RX_SWCTRL |
2313 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL;
2314
2315 if (gnt_cfg->band[1].gnt_bt)
2316 val |= B_BE_GNT_BT_BB1_VAL | B_BE_GNT_BT_RX_BB1_VAL |
2317 B_BE_GNT_BT_TX_BB1_VAL;
2318
2319 if (gnt_cfg->band[1].gnt_bt_sw_en)
2320 val |= B_BE_GNT_BT_BB1_SWCTRL | B_BE_GNT_BT_RX_BB1_SWCTRL |
2321 B_BE_GNT_BT_TX_BB1_SWCTRL;
2322
2323 if (gnt_cfg->band[1].gnt_wl)
2324 val |= B_BE_GNT_WL_BB1_VAL | B_BE_GNT_WL_RX_VAL |
2325 B_BE_GNT_WL_TX_VAL | B_BE_GNT_WL_BB_PWR_VAL;
2326
2327 if (gnt_cfg->band[1].gnt_wl_sw_en)
2328 val |= B_BE_GNT_WL_BB1_SWCTRL | B_BE_GNT_WL_RX_SWCTRL |
2329 B_BE_GNT_WL_TX_SWCTRL | B_BE_GNT_WL_BB_PWR_SWCTRL;
2330
2331 if (gnt_cfg->bt[0].wlan_act_en)
2332 val |= B_BE_WL_ACT_SWCTRL;
2333 if (gnt_cfg->bt[0].wlan_act)
2334 val |= B_BE_WL_ACT_VAL;
2335 if (gnt_cfg->bt[1].wlan_act_en)
2336 val |= B_BE_WL_ACT2_SWCTRL;
2337 if (gnt_cfg->bt[1].wlan_act)
2338 val |= B_BE_WL_ACT2_VAL;
2339
2340 rtw89_write32(rtwdev, R_BE_GNT_SW_CTRL, val);
2341
2342 return 0;
2343 }
2344 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v2);
2345
rtw89_mac_cfg_gnt_v3(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)2346 int rtw89_mac_cfg_gnt_v3(struct rtw89_dev *rtwdev,
2347 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
2348 {
2349 u32 val = 0;
2350
2351 if (gnt_cfg->band[0].gnt_bt)
2352 val |= B_BE_PTA_GNT_BT0_BB_VAL | B_BE_PTA_GNT_BT0_RX_BB0_VAL |
2353 B_BE_PTA_GNT_BT0_TX_BB0_VAL;
2354
2355 if (gnt_cfg->band[0].gnt_bt_sw_en)
2356 val |= B_BE_PTA_GNT_BT0_BB_SWCTRL | B_BE_PTA_GNT_BT0_RX_BB0_SWCTRL |
2357 B_BE_PTA_GNT_BT0_TX_BB0_SWCTRL;
2358
2359 if (gnt_cfg->band[0].gnt_wl)
2360 val |= B_BE_PTA_GNT_WL_BB0_VAL;
2361
2362 if (gnt_cfg->band[0].gnt_wl_sw_en)
2363 val |= B_BE_PTA_GNT_WL_BB0_SWCTRL;
2364
2365 if (gnt_cfg->band[1].gnt_bt)
2366 val |= B_BE_PTA_GNT_BT0_BB_VAL | B_BE_PTA_GNT_BT0_RX_BB1_VAL |
2367 B_BE_PTA_GNT_BT0_TX_BB1_VAL;
2368
2369 if (gnt_cfg->band[1].gnt_bt_sw_en)
2370 val |= B_BE_PTA_GNT_BT0_BB_SWCTRL | B_BE_PTA_GNT_BT0_RX_BB1_SWCTRL |
2371 B_BE_PTA_GNT_BT0_TX_BB1_SWCTRL;
2372
2373 if (gnt_cfg->band[1].gnt_wl)
2374 val |= B_BE_PTA_GNT_WL_BB1_VAL;
2375
2376 if (gnt_cfg->band[1].gnt_wl_sw_en)
2377 val |= B_BE_PTA_GNT_WL_BB1_SWCTRL;
2378
2379 if (gnt_cfg->bt[0].wlan_act_en)
2380 val |= B_BE_PTA_WL_ACT0_SWCTRL | B_BE_PTA_WL_ACT_RX_BT0_SWCTRL |
2381 B_BE_PTA_WL_ACT_TX_BT0_SWCTRL;
2382 if (gnt_cfg->bt[0].wlan_act)
2383 val |= B_BE_PTA_WL_ACT0_VAL | B_BE_PTA_WL_ACT_RX_BT0_VAL |
2384 B_BE_PTA_WL_ACT_TX_BT0_VAL;
2385 if (gnt_cfg->bt[1].wlan_act_en)
2386 val |= B_BE_PTA_WL_ACT1_SWCTRL | B_BE_PTA_WL_ACT_RX_BT1_SWCTRL |
2387 B_BE_PTA_WL_ACT_TX_BT1_SWCTRL;
2388 if (gnt_cfg->bt[1].wlan_act)
2389 val |= B_BE_PTA_WL_ACT1_VAL | B_BE_PTA_WL_ACT_RX_BT1_VAL |
2390 B_BE_PTA_WL_ACT_TX_BT1_VAL;
2391
2392 rtw89_write32(rtwdev, R_BE_PTA_GNT_SW_CTRL, val);
2393
2394 return 0;
2395 }
2396 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v3);
2397
rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev * rtwdev,bool wl)2398 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl)
2399 {
2400 struct rtw89_btc *btc = &rtwdev->btc;
2401 struct rtw89_btc_dm *dm = &btc->dm;
2402 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
2403 struct rtw89_mac_ax_wl_act *gbt = dm->gnt.bt;
2404 const struct rtw89_chip_info *chip = rtwdev->chip;
2405 int i;
2406
2407 if (wl)
2408 return 0;
2409
2410 for (i = 0; i < RTW89_PHY_NUM; i++) {
2411 g[i].gnt_bt_sw_en = 1;
2412 g[i].gnt_bt = 1;
2413 g[i].gnt_wl_sw_en = 1;
2414 g[i].gnt_wl = 0;
2415 gbt[i].wlan_act = 1;
2416 gbt[i].wlan_act_en = 0;
2417 }
2418
2419 if (chip->chip_id == RTL8922A)
2420 return rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt);
2421 else
2422 return rtw89_mac_cfg_gnt_v3(rtwdev, &dm->gnt);
2423
2424 }
2425 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v2);
2426
2427 static
rtw89_mac_cfg_plt_be(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)2428 int rtw89_mac_cfg_plt_be(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
2429 {
2430 u32 reg;
2431 u16 val;
2432 int ret;
2433
2434 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
2435 if (ret)
2436 return ret;
2437
2438 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, plt->band);
2439 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_TX_PLT_GNT_LTE_RX : 0) |
2440 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_TX_PLT_GNT_BT_TX : 0) |
2441 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_TX_PLT_GNT_BT_RX : 0) |
2442 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_TX_PLT_GNT_WL : 0) |
2443 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_BE_RX_PLT_GNT_LTE_RX : 0) |
2444 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_BE_RX_PLT_GNT_BT_TX : 0) |
2445 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_BE_RX_PLT_GNT_BT_RX : 0) |
2446 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_BE_RX_PLT_GNT_WL : 0) |
2447 B_BE_PLT_EN;
2448 rtw89_write16(rtwdev, reg, val);
2449
2450 return 0;
2451 }
2452
rtw89_mac_get_plt_cnt_be(struct rtw89_dev * rtwdev,u8 band)2453 static u16 rtw89_mac_get_plt_cnt_be(struct rtw89_dev *rtwdev, u8 band)
2454 {
2455 u32 reg;
2456 u16 cnt;
2457
2458 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BT_PLT, band);
2459 cnt = rtw89_read32_mask(rtwdev, reg, B_BE_BT_PLT_PKT_CNT_MASK);
2460 rtw89_write16_set(rtwdev, reg, B_BE_BT_PLT_RST);
2461
2462 return cnt;
2463 }
2464
rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en,u32 tx_en_mask)2465 static int rtw89_set_hw_sch_tx_en_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
2466 u32 tx_en, u32 tx_en_mask)
2467 {
2468 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx);
2469 u32 val;
2470 int ret;
2471
2472 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2473 if (ret)
2474 return ret;
2475
2476 val = rtw89_read32(rtwdev, reg);
2477 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2478 rtw89_write32(rtwdev, reg, val);
2479
2480 return 0;
2481 }
2482
rtw89_mac_stop_sch_tx_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)2483 int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx,
2484 u32 *tx_en, enum rtw89_sch_tx_sel sel)
2485 {
2486 int ret;
2487
2488 *tx_en = rtw89_read32(rtwdev,
2489 rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_DRV_TXEN, mac_idx));
2490
2491 switch (sel) {
2492 case RTW89_SCH_TX_SEL_ALL:
2493 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0,
2494 B_BE_CTN_TXEN_ALL_MASK);
2495 if (ret)
2496 return ret;
2497 break;
2498 case RTW89_SCH_TX_SEL_HIQ:
2499 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx,
2500 0, B_BE_CTN_TXEN_HGQ);
2501 if (ret)
2502 return ret;
2503 break;
2504 case RTW89_SCH_TX_SEL_MG0:
2505 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx,
2506 0, B_BE_CTN_TXEN_MGQ);
2507 if (ret)
2508 return ret;
2509 break;
2510 case RTW89_SCH_TX_SEL_MACID:
2511 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, 0,
2512 B_BE_CTN_TXEN_ALL_MASK);
2513 if (ret)
2514 return ret;
2515 break;
2516 default:
2517 return 0;
2518 }
2519
2520 return 0;
2521 }
2522 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v2);
2523
rtw89_mac_resume_sch_tx_v2(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)2524 int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2525 {
2526 int ret;
2527
2528 ret = rtw89_set_hw_sch_tx_en_v2(rtwdev, mac_idx, tx_en,
2529 B_BE_CTN_TXEN_ALL_MASK);
2530 if (ret)
2531 return ret;
2532
2533 return 0;
2534 }
2535 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v2);
2536
rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)2537 void rtw89_mac_cfg_phy_rpt_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
2538 {
2539 u32 reg, val;
2540
2541 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx);
2542 val = enable ? MAC_AX_PHY_RPT_SIZE_8 : MAC_AX_PHY_RPT_SIZE_0;
2543 rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val);
2544 rtw89_write32_mask(rtwdev, reg, B_BE_HDR_CNV_SZ_MASK, MAC_AX_HDR_CNV_SIZE_0);
2545
2546 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DRV_INFO_OPTION, mac_idx);
2547 rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable);
2548 }
2549 EXPORT_SYMBOL(rtw89_mac_cfg_phy_rpt_be);
2550
2551 static
rtw89_mac_set_edcca_mode_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool normal)2552 void rtw89_mac_set_edcca_mode_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool normal)
2553 {
2554 u16 resp_ack, resp_rts, resp_rts_punc, resp_normal, resp_normal_punc;
2555
2556 if (rtwdev->chip->chip_id == RTL8922A)
2557 return;
2558
2559 resp_ack = RESP_ACK_CFG_BE;
2560 resp_rts = RESP_RTS_CFG_BE;
2561 resp_rts_punc = RESP_RTS_PUNC_CFG_BE;
2562 resp_normal = RESP_NORMAL_CFG_BE;
2563 resp_normal_punc = RESP_NORMAL_PUNC_CFG_BE;
2564
2565 if (normal) {
2566 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
2567 resp_ack, mac_idx);
2568 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
2569 resp_ack, mac_idx);
2570 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
2571 resp_ack, mac_idx);
2572 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
2573 resp_rts, mac_idx);
2574 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
2575 resp_rts_punc, mac_idx);
2576 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
2577 resp_normal, mac_idx);
2578 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
2579 resp_normal_punc, mac_idx);
2580 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
2581 resp_normal, mac_idx);
2582 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
2583 resp_normal_punc, mac_idx);
2584 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
2585 resp_normal_punc, mac_idx);
2586 } else {
2587 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY,
2588 resp_normal, mac_idx);
2589 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE,
2590 resp_normal_punc, mac_idx);
2591 rtw89_write16_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC,
2592 resp_normal_punc, mac_idx);
2593 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY,
2594 resp_rts, mac_idx);
2595 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_RTS_RESP_LEGACY_PUNC,
2596 resp_rts_punc, mac_idx);
2597 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY,
2598 resp_normal, mac_idx);
2599 rtw89_write16_idx(rtwdev, R_BE_WMAC_RX_MURTS_RESP_LEGACY_PUNC,
2600 resp_normal_punc, mac_idx);
2601 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_LEGACY,
2602 resp_normal, mac_idx);
2603 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_HE,
2604 resp_normal_punc, mac_idx);
2605 rtw89_write16_idx(rtwdev, R_BE_WMAC_OTHERS_RESP_EHT_LEG_PUNC,
2606 resp_normal_punc, mac_idx);
2607 }
2608 }
2609
2610 static
rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)2611 int rtw89_mac_cfg_ppdu_status_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
2612 {
2613 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PPDU_STAT, mac_idx);
2614 int ret;
2615
2616 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2617 if (ret)
2618 return ret;
2619
2620 if (!enable) {
2621 rtw89_write32_clr(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN);
2622 return 0;
2623 }
2624
2625 rtw89_write32_mask(rtwdev, R_BE_HW_PPDU_STATUS, B_BE_FWD_PPDU_STAT_MASK, 3);
2626 rtw89_write32(rtwdev, reg, B_BE_PPDU_STAT_RPT_EN |
2627 B_BE_APP_RX_CNT_RPT | B_BE_APP_PLCP_HDR_RPT |
2628 B_BE_PPDU_STAT_RPT_CRC32 | B_BE_PPDU_STAT_RPT_DMA);
2629
2630 return 0;
2631 }
2632
rtw89_mac_get_txpwr_cr_be(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr)2633 static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev,
2634 enum rtw89_phy_idx phy_idx,
2635 u32 reg_base, u32 *cr)
2636 {
2637 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
2638 int ret;
2639
2640 ret = rtw89_mac_check_mac_en(rtwdev, (enum rtw89_mac_idx)phy_idx,
2641 RTW89_CMAC_SEL);
2642 if (ret) {
2643 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2644 return false;
2645
2646 rtw89_err(rtwdev, "[TXPWR] check mac enable failed\n");
2647 return false;
2648 }
2649
2650 if (reg_base < R_BE_PWR_MODULE || reg_base > R_BE_CMAC_FUNC_EN_C1) {
2651 rtw89_err(rtwdev, "[TXPWR] reg_base=0x%x exceed txpwr cr\n",
2652 reg_base);
2653 return false;
2654 }
2655
2656 *cr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
2657
2658 if (*cr >= CMAC1_START_ADDR_BE && *cr <= CMAC1_END_ADDR_BE) {
2659 if (mode == RTW89_QTA_SCC) {
2660 rtw89_err(rtwdev,
2661 "[TXPWR] addr=0x%x but hw not enable\n",
2662 *cr);
2663 return false;
2664 }
2665 }
2666
2667 return true;
2668 }
2669
rtw89_mac_init_bfee_be(struct rtw89_dev * rtwdev,u8 mac_idx)2670 static int rtw89_mac_init_bfee_be(struct rtw89_dev *rtwdev, u8 mac_idx)
2671 {
2672 u32 reg;
2673 u32 val;
2674 int ret;
2675
2676 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2677 if (ret)
2678 return ret;
2679
2680 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
2681
2682 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2683 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL |
2684 B_BE_BFMEE_USE_NSTS |
2685 B_BE_BFMEE_CSI_GID_SEL |
2686 B_BE_BFMEE_CSI_FORCE_RETE_EN);
2687 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_CSI_RSC_MASK, CSI_RX_BW_CFG);
2688
2689 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CSIRPT_OPTION, mac_idx);
2690 rtw89_write32_set(rtwdev, reg, B_BE_CSIPRT_VHTSU_AID_EN |
2691 B_BE_CSIPRT_HESU_AID_EN |
2692 B_BE_CSIPRT_EHTSU_AID_EN);
2693
2694 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx);
2695 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP_BE);
2696
2697 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
2698 rtw89_write32_mask(rtwdev, reg, B_BE_BFMEE_BE_CSI_RRSC_BITMAP_MASK,
2699 CSI_RRSC_BITMAP_CFG);
2700
2701 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RATE, mac_idx);
2702 val = u32_encode_bits(CSI_INIT_RATE_HT, B_BE_BFMEE_HT_CSI_RATE_MASK) |
2703 u32_encode_bits(CSI_INIT_RATE_VHT, B_BE_BFMEE_VHT_CSI_RATE_MASK) |
2704 u32_encode_bits(CSI_INIT_RATE_HE, B_BE_BFMEE_HE_CSI_RATE_MASK) |
2705 u32_encode_bits(CSI_INIT_RATE_EHT, B_BE_BFMEE_EHT_CSI_RATE_MASK);
2706
2707 rtw89_write32(rtwdev, reg, val);
2708
2709 return 0;
2710 }
2711
rtw89_mac_set_csi_para_reg_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2712 static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev,
2713 struct rtw89_vif_link *rtwvif_link,
2714 struct rtw89_sta_link *rtwsta_link)
2715 {
2716 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;
2717 struct ieee80211_link_sta *link_sta;
2718 u8 mac_idx = rtwvif_link->mac_idx;
2719 u8 port_sel = rtwvif_link->port;
2720 u8 sound_dim = 3, t;
2721 u8 *phy_cap;
2722 u32 reg;
2723 u16 val;
2724 int ret;
2725
2726 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2727 if (ret)
2728 return ret;
2729
2730 rcu_read_lock();
2731
2732 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2733 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
2734
2735 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
2736 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) {
2737 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD);
2738 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ);
2739 t = u8_get_bits(phy_cap[5],
2740 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK);
2741 sound_dim = min(sound_dim, t);
2742 }
2743
2744 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
2745 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
2746 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
2747 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
2748 t = u32_get_bits(link_sta->vht_cap.cap,
2749 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK);
2750 sound_dim = min(sound_dim, t);
2751 }
2752
2753 nc = min(nc, sound_dim);
2754 nr = min(nr, sound_dim);
2755
2756 rcu_read_unlock();
2757
2758 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2759 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL);
2760
2761 val = u16_encode_bits(nc, B_BE_BFMEE_CSIINFO0_NC_MASK) |
2762 u16_encode_bits(nr, B_BE_BFMEE_CSIINFO0_NR_MASK) |
2763 u16_encode_bits(ng, B_BE_BFMEE_CSIINFO0_NG_MASK) |
2764 u16_encode_bits(cb, B_BE_BFMEE_CSIINFO0_CB_MASK) |
2765 u16_encode_bits(cs, B_BE_BFMEE_CSIINFO0_CS_MASK) |
2766 u16_encode_bits(ldpc_en, B_BE_BFMEE_CSIINFO0_LDPC_EN) |
2767 u16_encode_bits(stbc_en, B_BE_BFMEE_CSIINFO0_STBC_EN);
2768
2769 if (port_sel == 0)
2770 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0,
2771 mac_idx);
2772 else
2773 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_1,
2774 mac_idx);
2775
2776 rtw89_write16(rtwdev, reg, val);
2777
2778 return 0;
2779 }
2780
rtw89_mac_csi_rrsc_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2781 static int rtw89_mac_csi_rrsc_be(struct rtw89_dev *rtwdev,
2782 struct rtw89_vif_link *rtwvif_link,
2783 struct rtw89_sta_link *rtwsta_link)
2784 {
2785 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M);
2786 struct ieee80211_link_sta *link_sta;
2787 u8 mac_idx = rtwvif_link->mac_idx;
2788 int ret;
2789 u32 reg;
2790
2791 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2792 if (ret)
2793 return ret;
2794
2795 rcu_read_lock();
2796
2797 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2798
2799 if (link_sta->he_cap.has_he) {
2800 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) |
2801 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) |
2802 BIT(RTW89_MAC_BF_RRSC_HE_MSC5));
2803 }
2804 if (link_sta->vht_cap.vht_supported) {
2805 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) |
2806 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) |
2807 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5));
2808 }
2809 if (link_sta->ht_cap.ht_supported) {
2810 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) |
2811 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |
2812 BIT(RTW89_MAC_BF_RRSC_HT_MSC5));
2813 }
2814
2815 rcu_read_unlock();
2816
2817 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
2818 rtw89_write32_set(rtwdev, reg, B_BE_BFMEE_BFPARAM_SEL);
2819 rtw89_write32_clr(rtwdev, reg, B_BE_BFMEE_CSI_FORCE_RETE_EN);
2820
2821 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_CSI_RRSC, mac_idx);
2822 rtw89_write32(rtwdev, reg, rrsc);
2823
2824 return 0;
2825 }
2826
rtw89_mac_bf_assoc_be(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)2827 static void rtw89_mac_bf_assoc_be(struct rtw89_dev *rtwdev,
2828 struct rtw89_vif_link *rtwvif_link,
2829 struct rtw89_sta_link *rtwsta_link)
2830 {
2831 struct ieee80211_link_sta *link_sta;
2832 bool has_beamformer_cap;
2833
2834 rcu_read_lock();
2835
2836 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
2837 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta);
2838
2839 rcu_read_unlock();
2840
2841 if (has_beamformer_cap) {
2842 rtw89_debug(rtwdev, RTW89_DBG_BF,
2843 "initialize bfee for new association\n");
2844 rtw89_mac_init_bfee_be(rtwdev, rtwvif_link->mac_idx);
2845 rtw89_mac_set_csi_para_reg_be(rtwdev, rtwvif_link, rtwsta_link);
2846 rtw89_mac_csi_rrsc_be(rtwdev, rtwvif_link, rtwsta_link);
2847 }
2848 }
2849
dump_err_status_dispatcher_be(struct rtw89_dev * rtwdev)2850 static void dump_err_status_dispatcher_be(struct rtw89_dev *rtwdev)
2851 {
2852 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x ",
2853 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR));
2854 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n",
2855 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1));
2856 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x ",
2857 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR));
2858 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n",
2859 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2));
2860 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x ",
2861 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR));
2862 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n",
2863 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0));
2864 }
2865
rtw89_mac_dump_qta_lost_be(struct rtw89_dev * rtwdev)2866 static void rtw89_mac_dump_qta_lost_be(struct rtw89_dev *rtwdev)
2867 {
2868 struct rtw89_mac_dle_dfi_qempty qempty;
2869 struct rtw89_mac_dle_dfi_quota quota;
2870 struct rtw89_mac_dle_dfi_ctrl ctrl;
2871 u32 val, not_empty, i;
2872 int ret;
2873
2874 qempty.dle_type = DLE_CTRL_TYPE_PLE;
2875 qempty.grpsel = 0;
2876 qempty.qempty = ~(u32)0;
2877 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
2878 if (ret)
2879 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2880 else
2881 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
2882
2883 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
2884 if (!(not_empty & BIT(0)))
2885 continue;
2886 ctrl.type = DLE_CTRL_TYPE_PLE;
2887 ctrl.target = DLE_DFI_TYPE_QLNKTBL;
2888 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
2889 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK);
2890 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
2891 if (ret)
2892 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2893 else
2894 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i,
2895 u32_get_bits(ctrl.out_data,
2896 QLNKTBL_DATA_SEL1_PKT_CNT_MASK));
2897 }
2898
2899 quota.dle_type = DLE_CTRL_TYPE_PLE;
2900 quota.qtaid = 6;
2901 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
2902 if (ret)
2903 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2904 else
2905 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
2906 quota.rsv_pgnum, quota.use_pgnum);
2907
2908 val = rtw89_read32(rtwdev, R_BE_PLE_QTA6_CFG);
2909 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n",
2910 u32_get_bits(val, B_BE_PLE_Q6_MIN_SIZE_MASK));
2911 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n",
2912 u32_get_bits(val, B_BE_PLE_Q6_MAX_SIZE_MASK));
2913 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT);
2914 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n",
2915 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK));
2916 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG=0x%08x\n",
2917 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG));
2918 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0=0x%08x\n",
2919 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0));
2920
2921 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
2922 quota.dle_type = DLE_CTRL_TYPE_PLE;
2923 quota.qtaid = 7;
2924 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
2925 if (ret)
2926 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
2927 else
2928 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n",
2929 quota.rsv_pgnum, quota.use_pgnum);
2930
2931 val = rtw89_read32(rtwdev, R_BE_PLE_QTA7_CFG);
2932 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n",
2933 u32_get_bits(val, B_BE_PLE_Q7_MIN_SIZE_MASK));
2934 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n",
2935 u32_get_bits(val, B_BE_PLE_Q7_MAX_SIZE_MASK));
2936 val = rtw89_read32(rtwdev, R_BE_RX_FLTR_OPT_C1);
2937 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_BE_RX_MPDU_MAX_LEN=0x%x\n",
2938 u32_get_bits(val, B_BE_RX_MPDU_MAX_LEN_MASK));
2939 rtw89_info(rtwdev, "R_BE_RSP_CHK_SIG_C1=0x%08x\n",
2940 rtw89_read32(rtwdev, R_BE_RSP_CHK_SIG_C1));
2941 rtw89_info(rtwdev, "R_BE_TRXPTCL_RESP_0_C1=0x%08x\n",
2942 rtw89_read32(rtwdev, R_BE_TRXPTCL_RESP_0_C1));
2943 }
2944
2945 rtw89_info(rtwdev, "R_BE_DLE_EMPTY0=0x%08x\n",
2946 rtw89_read32(rtwdev, R_BE_DLE_EMPTY0));
2947 rtw89_info(rtwdev, "R_BE_DLE_EMPTY1=0x%08x\n",
2948 rtw89_read32(rtwdev, R_BE_DLE_EMPTY1));
2949
2950 dump_err_status_dispatcher_be(rtwdev);
2951 }
2952
rtw89_wow_config_mac_be(struct rtw89_dev * rtwdev,bool enable_wow)2953 static int rtw89_wow_config_mac_be(struct rtw89_dev *rtwdev, bool enable_wow)
2954 {
2955 if (enable_wow) {
2956 rtw89_write32_set(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
2957 rtw89_write32_clr(rtwdev, R_BE_RX_FLTR_OPT, B_BE_SNIFFER_MODE);
2958 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
2959 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
2960 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
2961 rtw89_write32(rtwdev, R_BE_FWD_ACTN0, 0);
2962 rtw89_write32(rtwdev, R_BE_FWD_ACTN1, 0);
2963 rtw89_write32(rtwdev, R_BE_FWD_ACTN2, 0);
2964 rtw89_write32(rtwdev, R_BE_FWD_TF0, 0);
2965 rtw89_write32(rtwdev, R_BE_FWD_TF1, 0);
2966 rtw89_write32(rtwdev, R_BE_FWD_ERR, 0);
2967 rtw89_write32(rtwdev, R_BE_HW_PPDU_STATUS, 0);
2968 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
2969 } else {
2970 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
2971 rtw89_write32_clr(rtwdev, R_BE_RX_STOP, B_BE_HOST_RX_STOP);
2972 rtw89_write32_set(rtwdev, R_BE_RX_FLTR_OPT, R_BE_RX_FLTR_OPT);
2973 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
2974 }
2975
2976 return 0;
2977 }
2978
rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev * rtwdev,u8 band)2979 static void rtw89_mac_dump_cmac_err_status_be(struct rtw89_dev *rtwdev,
2980 u8 band)
2981 {
2982 u32 offset = 0;
2983 u32 cmac_err;
2984 int ret;
2985
2986 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
2987 if (ret) {
2988 rtw89_info(rtwdev, "[CMAC] : CMAC%d not enabled\n", band);
2989 return;
2990 }
2991
2992 if (band)
2993 offset = RTW89_MAC_BE_BAND_REG_OFFSET;
2994
2995 cmac_err = rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset);
2996 rtw89_info(rtwdev, "R_BE_CMAC_ERR_ISR [%d]=0x%08x\n", band,
2997 rtw89_read32(rtwdev, R_BE_CMAC_ERR_ISR + offset));
2998 rtw89_info(rtwdev, "R_BE_CMAC_FUNC_EN [%d]=0x%08x\n", band,
2999 rtw89_read32(rtwdev, R_BE_CMAC_FUNC_EN + offset));
3000 rtw89_info(rtwdev, "R_BE_CK_EN [%d]=0x%08x\n", band,
3001 rtw89_read32(rtwdev, R_BE_CK_EN + offset));
3002
3003 if (cmac_err & B_BE_SCHEDULE_TOP_ERR_IND) {
3004 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
3005 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_IMR + offset));
3006 rtw89_info(rtwdev, "R_BE_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
3007 rtw89_read32(rtwdev, R_BE_SCHEDULE_ERR_ISR + offset));
3008 }
3009
3010 if (cmac_err & B_BE_PTCL_TOP_ERR_IND) {
3011 rtw89_info(rtwdev, "R_BE_PTCL_IMR0 [%d]=0x%08x\n", band,
3012 rtw89_read32(rtwdev, R_BE_PTCL_IMR0 + offset));
3013 rtw89_info(rtwdev, "R_BE_PTCL_ISR0 [%d]=0x%08x\n", band,
3014 rtw89_read32(rtwdev, R_BE_PTCL_ISR0 + offset));
3015 rtw89_info(rtwdev, "R_BE_PTCL_IMR1 [%d]=0x%08x\n", band,
3016 rtw89_read32(rtwdev, R_BE_PTCL_IMR1 + offset));
3017 rtw89_info(rtwdev, "R_BE_PTCL_ISR1 [%d]=0x%08x\n", band,
3018 rtw89_read32(rtwdev, R_BE_PTCL_ISR1 + offset));
3019 }
3020
3021 if (cmac_err & B_BE_DMA_TOP_ERR_IND) {
3022 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR [%d]=0x%08x\n", band,
3023 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR + offset));
3024 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG [%d]=0x%08x\n", band,
3025 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG + offset));
3026 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG_IMR [%d]=0x%08x\n", band,
3027 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG_IMR + offset));
3028 rtw89_info(rtwdev, "R_BE_TX_ERROR_FLAG [%d]=0x%08x\n", band,
3029 rtw89_read32(rtwdev, R_BE_TX_ERROR_FLAG + offset));
3030 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_IMR_1 [%d]=0x%08x\n", band,
3031 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_IMR_1 + offset));
3032 rtw89_info(rtwdev, "R_BE_RX_ERROR_FLAG_1 [%d]=0x%08x\n", band,
3033 rtw89_read32(rtwdev, R_BE_RX_ERROR_FLAG_1 + offset));
3034 }
3035
3036 if (cmac_err & B_BE_PHYINTF_ERR_IND) {
3037 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
3038 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_IMR_V1 + offset));
3039 rtw89_info(rtwdev, "R_BE_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
3040 rtw89_read32(rtwdev, R_BE_PHYINFO_ERR_ISR + offset));
3041 }
3042
3043 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
3044 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_FLAG [%d]=0x%08x\n", band,
3045 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_FLAG + offset));
3046 rtw89_info(rtwdev, "R_BE_TXPWR_ERR_IMR [%d]=0x%08x\n", band,
3047 rtw89_read32(rtwdev, R_BE_TXPWR_ERR_IMR + offset));
3048 }
3049
3050 if (cmac_err & (B_BE_WMAC_RX_ERR_IND | B_BE_WMAC_TX_ERR_IND |
3051 B_BE_WMAC_RX_IDLETO_IDCT | B_BE_PTCL_TX_IDLETO_IDCT)) {
3052 rtw89_info(rtwdev, "R_BE_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
3053 rtw89_read32(rtwdev, R_BE_DBGSEL_TRXPTCL + offset));
3054 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
3055 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA_MASK + offset));
3056 rtw89_info(rtwdev, "R_BE_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
3057 rtw89_read32(rtwdev, R_BE_TRXPTCL_ERROR_INDICA + offset));
3058 rtw89_info(rtwdev, "R_BE_RX_ERR_IMR [%d]=0x%08x\n", band,
3059 rtw89_read32(rtwdev, R_BE_RX_ERR_IMR + offset));
3060 rtw89_info(rtwdev, "R_BE_RX_ERR_ISR [%d]=0x%08x\n", band,
3061 rtw89_read32(rtwdev, R_BE_RX_ERR_ISR + offset));
3062 }
3063
3064 rtw89_info(rtwdev, "R_BE_CMAC_ERR_IMR [%d]=0x%08x\n", band,
3065 rtw89_read32(rtwdev, R_BE_CMAC_ERR_IMR + offset));
3066 }
3067
rtw89_mac_dump_err_status_be(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)3068 static void rtw89_mac_dump_err_status_be(struct rtw89_dev *rtwdev,
3069 enum mac_ax_err_info err)
3070 {
3071 if (err != MAC_AX_ERR_L1_ERR_DMAC &&
3072 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
3073 err != MAC_AX_ERR_L0_ERR_CMAC0 &&
3074 err != MAC_AX_ERR_L0_ERR_CMAC1 &&
3075 err != MAC_AX_ERR_RXI300)
3076 return;
3077
3078 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
3079 rtw89_info(rtwdev, "R_BE_SER_DBG_INFO=0x%08x\n",
3080 rtw89_read32(rtwdev, R_BE_SER_DBG_INFO));
3081 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT=0x%08x\n",
3082 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT));
3083 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1=0x%08x\n",
3084 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1));
3085 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT2=0x%08x\n",
3086 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT2));
3087 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT3=0x%08x\n",
3088 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT3));
3089 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
3090 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT_C1=0x%08x\n",
3091 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT_C1));
3092 rtw89_info(rtwdev, "R_BE_SER_L0_DBG_CNT1_C1=0x%08x\n",
3093 rtw89_read32(rtwdev, R_BE_SER_L0_DBG_CNT1_C1));
3094 }
3095 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_0=0x%08x\n",
3096 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_0));
3097 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_1=0x%08x\n",
3098 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_1));
3099 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_2=0x%08x\n",
3100 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_2));
3101 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_3=0x%08x\n",
3102 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_3));
3103 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_4=0x%08x\n",
3104 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_4));
3105 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_5=0x%08x\n",
3106 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_5));
3107 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_6=0x%08x\n",
3108 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_6));
3109 rtw89_info(rtwdev, "R_BE_SER_L1_DBG_CNT_7=0x%08x\n",
3110 rtw89_read32(rtwdev, R_BE_SER_L1_DBG_CNT_7));
3111
3112 rtw89_mac_dump_dmac_err_status(rtwdev);
3113 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_0);
3114 rtw89_mac_dump_cmac_err_status_be(rtwdev, RTW89_MAC_1);
3115
3116 rtwdev->hci.ops->dump_err_status(rtwdev);
3117
3118 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
3119 rtw89_mac_dump_l0_to_l1(rtwdev, err);
3120
3121 rtw89_info(rtwdev, "<---\n");
3122 }
3123
mac_is_txq_empty_be(struct rtw89_dev * rtwdev)3124 static bool mac_is_txq_empty_be(struct rtw89_dev *rtwdev)
3125 {
3126 struct rtw89_mac_dle_dfi_qempty qempty;
3127 u32 val32, msk32;
3128 u32 grpnum;
3129 int ret;
3130 int i;
3131
3132 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
3133 qempty.dle_type = DLE_CTRL_TYPE_WDE;
3134
3135 for (i = 0; i < grpnum; i++) {
3136 qempty.grpsel = i;
3137 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
3138 if (ret) {
3139 rtw89_warn(rtwdev,
3140 "%s: failed to dle dfi acq empty: %d\n",
3141 __func__, ret);
3142 return false;
3143 }
3144
3145 /* Each acq group contains 32 queues (8 macid * 4 acq),
3146 * but here, we can simply check if all bits are set.
3147 */
3148 if (qempty.qempty != MASKDWORD)
3149 return false;
3150 }
3151
3152 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
3153 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
3154 if (ret) {
3155 rtw89_warn(rtwdev, "%s: failed to dle dfi mgq empty: %d\n",
3156 __func__, ret);
3157 return false;
3158 }
3159
3160 msk32 = B_CMAC0_MGQ_NORMAL_BE | B_CMAC1_MGQ_NORMAL_BE;
3161 if ((qempty.qempty & msk32) != msk32)
3162 return false;
3163
3164 msk32 = B_BE_WDE_EMPTY_QUE_OTHERS;
3165 val32 = rtw89_read32(rtwdev, R_BE_DLE_EMPTY0);
3166 return (val32 & msk32) == msk32;
3167 }
3168
3169 const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
3170 .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET,
3171 .filter_model_addr = R_BE_FILTER_MODEL_ADDR,
3172 .indir_access_addr = R_BE_INDIR_ACCESS_ENTRY,
3173 .mem_base_addrs = rtw89_mac_mem_base_addrs_be,
3174 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_BE,
3175 .rx_fltr = R_BE_RX_FLTR_OPT,
3176 .port_base = &rtw89_port_base_be,
3177 .agg_len_ht = R_BE_AGG_LEN_HT_0,
3178 .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL,
3179 .mu_gid = &rtw89_mac_mu_gid_addr_be,
3180
3181 .muedca_ctrl = {
3182 .addr = R_BE_MUEDCA_EN,
3183 .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0,
3184 },
3185 .bfee_ctrl = {
3186 .addr = R_BE_BFMEE_RESP_OPTION,
3187 .mask = B_BE_BFMEE_HT_NDPA_EN | B_BE_BFMEE_VHT_NDPA_EN |
3188 B_BE_BFMEE_HE_NDPA_EN | B_BE_BFMEE_EHT_NDPA_EN,
3189 },
3190 .narrow_bw_ru_dis = {
3191 .addr = R_BE_RXTRIG_TEST_USER_2,
3192 .mask = B_BE_RXTRIG_RU26_DIS,
3193 },
3194 .wow_ctrl = {.addr = R_BE_WOW_CTRL, .mask = B_BE_WOW_WOWEN,},
3195 .agg_limit = {.addr = R_BE_AMPDU_AGG_LIMIT, .mask = B_BE_AMPDU_MAX_TIME_MASK,},
3196 .txcnt_limit = {.addr = R_BE_TXCNT, .mask = B_BE_L_TXCNT_LMT_MASK,},
3197
3198 .check_mac_en = rtw89_mac_check_mac_en_be,
3199 .sys_init = sys_init_be,
3200 .trx_init = trx_init_be,
3201 .preload_init = preload_init_be,
3202 .clr_aon_intr = clr_aon_intr_be,
3203 .err_imr_ctrl = err_imr_ctrl_be,
3204 .mac_func_en = mac_func_en_be,
3205 .hci_func_en = rtw89_mac_hci_func_en_be,
3206 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be,
3207 .dle_func_en = dle_func_en_be,
3208 .dle_clk_en = dle_clk_en_be,
3209 .bf_assoc = rtw89_mac_bf_assoc_be,
3210
3211 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_be,
3212 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_be,
3213 .cfg_phy_rpt = rtw89_mac_cfg_phy_rpt_be,
3214 .set_edcca_mode = rtw89_mac_set_edcca_mode_be,
3215
3216 .dle_mix_cfg = dle_mix_cfg_be,
3217 .chk_dle_rdy = chk_dle_rdy_be,
3218 .dle_buf_req = dle_buf_req_be,
3219 .hfc_func_en = hfc_func_en_be,
3220 .hfc_h2c_cfg = hfc_h2c_cfg_be,
3221 .hfc_mix_cfg = hfc_mix_cfg_be,
3222 .hfc_get_mix_info = hfc_get_mix_info_be,
3223 .wde_quota_cfg = wde_quota_cfg_be,
3224 .ple_quota_cfg = ple_quota_cfg_be,
3225 .set_cpuio = set_cpuio_be,
3226 .dle_quota_change = dle_quota_change_be,
3227
3228 .reset_pwr_state = rtw89_mac_reset_pwr_state_be,
3229 .disable_cpu = rtw89_mac_disable_cpu_be,
3230 .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
3231 .fwdl_get_status = fwdl_get_status_be,
3232 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_be,
3233 .fwdl_secure_idmem_share_mode = NULL,
3234 .parse_efuse_map = rtw89_parse_efuse_map_be,
3235 .parse_phycap_map = rtw89_parse_phycap_map_be,
3236 .cnv_efuse_state = rtw89_cnv_efuse_state_be,
3237 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_be,
3238 .efuse_read_ecv = rtw89_efuse_read_ecv_be,
3239
3240 .cfg_plt = rtw89_mac_cfg_plt_be,
3241 .get_plt_cnt = rtw89_mac_get_plt_cnt_be,
3242
3243 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_be,
3244
3245 .write_xtal_si = rtw89_mac_write_xtal_si_be,
3246 .read_xtal_si = rtw89_mac_read_xtal_si_be,
3247
3248 .dump_qta_lost = rtw89_mac_dump_qta_lost_be,
3249 .dump_err_status = rtw89_mac_dump_err_status_be,
3250
3251 .is_txq_empty = mac_is_txq_empty_be,
3252
3253 .prep_chan_list = rtw89_hw_scan_prep_chan_list_be,
3254 .free_chan_list = rtw89_hw_scan_free_chan_list_be,
3255 .add_chan_list = rtw89_hw_scan_add_chan_list_be,
3256 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_be,
3257 .scan_offload = rtw89_fw_h2c_scan_offload_be,
3258
3259 .wow_config_mac = rtw89_wow_config_mac_be,
3260 };
3261 EXPORT_SYMBOL(rtw89_mac_gen_be);
3262