1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/module.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "fw.h"
9 #include "tx.h"
10 #include "rx.h"
11 #include "phy.h"
12 #include "rtw8822c.h"
13 #include "rtw8822c_table.h"
14 #include "mac.h"
15 #include "reg.h"
16 #include "debug.h"
17 #include "util.h"
18 #include "bf.h"
19 #include "efuse.h"
20
21 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
22 u8 rx_path, bool is_tx2_path);
23
rtw8822ce_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822c_efuse * map)24 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
25 struct rtw8822c_efuse *map)
26 {
27 ether_addr_copy(efuse->addr, map->e.mac_addr);
28 }
29
rtw8822c_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)30 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
31 {
32 struct rtw_efuse *efuse = &rtwdev->efuse;
33 struct rtw8822c_efuse *map;
34 int i;
35
36 map = (struct rtw8822c_efuse *)log_map;
37
38 efuse->rfe_option = map->rfe_option;
39 efuse->rf_board_option = map->rf_board_option;
40 efuse->crystal_cap = map->xtal_k;
41 efuse->channel_plan = map->channel_plan;
42 efuse->country_code[0] = map->country_code[0];
43 efuse->country_code[1] = map->country_code[1];
44 efuse->bt_setting = map->rf_bt_setting;
45 efuse->regd = map->rf_board_option & 0x7;
46 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
47 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
48 efuse->thermal_meter_k =
49 (map->path_a_thermal + map->path_b_thermal) >> 1;
50 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
51
52 for (i = 0; i < 4; i++)
53 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
54
55 switch (rtw_hci_type(rtwdev)) {
56 case RTW_HCI_TYPE_PCIE:
57 rtw8822ce_efuse_parsing(efuse, map);
58 break;
59 default:
60 /* unsupported now */
61 return -ENOTSUPP;
62 }
63
64 return 0;
65 }
66
rtw8822c_header_file_init(struct rtw_dev * rtwdev,bool pre)67 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
68 {
69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
70 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
72 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
73
74 if (pre)
75 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
76 else
77 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
78 }
79
rtw8822c_dac_backup_reg(struct rtw_dev * rtwdev,struct rtw_backup_info * backup,struct rtw_backup_info * backup_rf)80 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
81 struct rtw_backup_info *backup,
82 struct rtw_backup_info *backup_rf)
83 {
84 u32 path, i;
85 u32 val;
86 u32 reg;
87 u32 rf_addr[DACK_RF_8822C] = {0x8f};
88 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
89 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
90 0x1a00, 0x1a14, 0x1d58, 0x1c38,
91 0x1e24, 0x1e28, 0x1860, 0x4160};
92
93 for (i = 0; i < DACK_REG_8822C; i++) {
94 backup[i].len = 4;
95 backup[i].reg = addrs[i];
96 backup[i].val = rtw_read32(rtwdev, addrs[i]);
97 }
98
99 for (path = 0; path < DACK_PATH_8822C; path++) {
100 for (i = 0; i < DACK_RF_8822C; i++) {
101 reg = rf_addr[i];
102 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
103 backup_rf[path * i + i].reg = reg;
104 backup_rf[path * i + i].val = val;
105 }
106 }
107 }
108
rtw8822c_dac_restore_reg(struct rtw_dev * rtwdev,struct rtw_backup_info * backup,struct rtw_backup_info * backup_rf)109 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
110 struct rtw_backup_info *backup,
111 struct rtw_backup_info *backup_rf)
112 {
113 u32 path, i;
114 u32 val;
115 u32 reg;
116
117 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
118
119 for (path = 0; path < DACK_PATH_8822C; path++) {
120 for (i = 0; i < DACK_RF_8822C; i++) {
121 val = backup_rf[path * i + i].val;
122 reg = backup_rf[path * i + i].reg;
123 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
124 }
125 }
126 }
127
rtw8822c_rf_minmax_cmp(struct rtw_dev * rtwdev,u32 value,u32 * min,u32 * max)128 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
129 u32 *min, u32 *max)
130 {
131 if (value >= 0x200) {
132 if (*min >= 0x200) {
133 if (*min > value)
134 *min = value;
135 } else {
136 *min = value;
137 }
138 if (*max >= 0x200) {
139 if (*max < value)
140 *max = value;
141 }
142 } else {
143 if (*min < 0x200) {
144 if (*min > value)
145 *min = value;
146 }
147
148 if (*max >= 0x200) {
149 *max = value;
150 } else {
151 if (*max < value)
152 *max = value;
153 }
154 }
155 }
156
__rtw8822c_dac_iq_sort(struct rtw_dev * rtwdev,u32 * v1,u32 * v2)157 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
158 {
159 if (*v1 >= 0x200 && *v2 >= 0x200) {
160 if (*v1 > *v2)
161 swap(*v1, *v2);
162 } else if (*v1 < 0x200 && *v2 < 0x200) {
163 if (*v1 > *v2)
164 swap(*v1, *v2);
165 } else if (*v1 < 0x200 && *v2 >= 0x200) {
166 swap(*v1, *v2);
167 }
168 }
169
rtw8822c_dac_iq_sort(struct rtw_dev * rtwdev,u32 * iv,u32 * qv)170 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
171 {
172 u32 i, j;
173
174 for (i = 0; i < DACK_SN_8822C - 1; i++) {
175 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
176 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
177 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
178 }
179 }
180 }
181
rtw8822c_dac_iq_offset(struct rtw_dev * rtwdev,u32 * vec,u32 * val)182 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
183 {
184 u32 p, m, t, i;
185
186 m = 0;
187 p = 0;
188 for (i = 10; i < DACK_SN_8822C - 10; i++) {
189 if (vec[i] > 0x200)
190 m = (0x400 - vec[i]) + m;
191 else
192 p = vec[i] + p;
193 }
194
195 if (p > m) {
196 t = p - m;
197 t = t / (DACK_SN_8822C - 20);
198 } else {
199 t = m - p;
200 t = t / (DACK_SN_8822C - 20);
201 if (t != 0x0)
202 t = 0x400 - t;
203 }
204
205 *val = t;
206 }
207
rtw8822c_get_path_write_addr(u8 path)208 static u32 rtw8822c_get_path_write_addr(u8 path)
209 {
210 u32 base_addr;
211
212 switch (path) {
213 case RF_PATH_A:
214 base_addr = 0x1800;
215 break;
216 case RF_PATH_B:
217 base_addr = 0x4100;
218 break;
219 default:
220 WARN_ON(1);
221 return -1;
222 }
223
224 return base_addr;
225 }
226
rtw8822c_get_path_read_addr(u8 path)227 static u32 rtw8822c_get_path_read_addr(u8 path)
228 {
229 u32 base_addr;
230
231 switch (path) {
232 case RF_PATH_A:
233 base_addr = 0x2800;
234 break;
235 case RF_PATH_B:
236 base_addr = 0x4500;
237 break;
238 default:
239 WARN_ON(1);
240 return -1;
241 }
242
243 return base_addr;
244 }
245
rtw8822c_dac_iq_check(struct rtw_dev * rtwdev,u32 value)246 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
247 {
248 bool ret = true;
249
250 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
251 (value < 0x200 && value > 0x64)) {
252 ret = false;
253 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
254 }
255
256 return ret;
257 }
258
rtw8822c_dac_cal_iq_sample(struct rtw_dev * rtwdev,u32 * iv,u32 * qv)259 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
260 {
261 u32 temp;
262 int i = 0, cnt = 0;
263
264 while (i < DACK_SN_8822C && cnt < 10000) {
265 cnt++;
266 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
267 iv[i] = (temp & 0x3ff000) >> 12;
268 qv[i] = temp & 0x3ff;
269
270 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
271 rtw8822c_dac_iq_check(rtwdev, qv[i]))
272 i++;
273 }
274 }
275
rtw8822c_dac_cal_iq_search(struct rtw_dev * rtwdev,u32 * iv,u32 * qv,u32 * i_value,u32 * q_value)276 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
277 u32 *iv, u32 *qv,
278 u32 *i_value, u32 *q_value)
279 {
280 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
281 u32 i_delta, q_delta;
282 u32 temp;
283 int i, cnt = 0;
284
285 do {
286 i_min = iv[0];
287 i_max = iv[0];
288 q_min = qv[0];
289 q_max = qv[0];
290 for (i = 0; i < DACK_SN_8822C; i++) {
291 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
292 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
293 }
294
295 if (i_max < 0x200 && i_min < 0x200)
296 i_delta = i_max - i_min;
297 else if (i_max >= 0x200 && i_min >= 0x200)
298 i_delta = i_max - i_min;
299 else
300 i_delta = i_max + (0x400 - i_min);
301
302 if (q_max < 0x200 && q_min < 0x200)
303 q_delta = q_max - q_min;
304 else if (q_max >= 0x200 && q_min >= 0x200)
305 q_delta = q_max - q_min;
306 else
307 q_delta = q_max + (0x400 - q_min);
308
309 rtw_dbg(rtwdev, RTW_DBG_RFK,
310 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
311 i_min, i_max, i_delta);
312 rtw_dbg(rtwdev, RTW_DBG_RFK,
313 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
314 q_min, q_max, q_delta);
315
316 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
317
318 if (i_delta > 5 || q_delta > 5) {
319 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
320 iv[0] = (temp & 0x3ff000) >> 12;
321 qv[0] = temp & 0x3ff;
322 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
323 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
324 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
325 } else {
326 break;
327 }
328 } while (cnt++ < 100);
329
330 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
331 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
332 }
333
rtw8822c_dac_cal_rf_mode(struct rtw_dev * rtwdev,u32 * i_value,u32 * q_value)334 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
335 u32 *i_value, u32 *q_value)
336 {
337 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
338 u32 rf_a, rf_b;
339
340 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
341 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
342
343 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
345
346 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
347 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
348 }
349
rtw8822c_dac_bb_setting(struct rtw_dev * rtwdev)350 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
351 {
352 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
353 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
354 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
355 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
356 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
357 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
358 rtw_write32(rtwdev, 0x1b00, 0x00000008);
359 rtw_write8(rtwdev, 0x1bcc, 0x3f);
360 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
361 rtw_write8(rtwdev, 0x1bcc, 0x3f);
362 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
363 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
364 }
365
rtw8822c_dac_cal_adc(struct rtw_dev * rtwdev,u8 path,u32 * adc_ic,u32 * adc_qc)366 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
367 u8 path, u32 *adc_ic, u32 *adc_qc)
368 {
369 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
370 u32 ic = 0, qc = 0, temp = 0;
371 u32 base_addr;
372 u32 path_sel;
373 int i;
374
375 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
376
377 base_addr = rtw8822c_get_path_write_addr(path);
378 switch (path) {
379 case RF_PATH_A:
380 path_sel = 0xa0000;
381 break;
382 case RF_PATH_B:
383 path_sel = 0x80000;
384 break;
385 default:
386 WARN_ON(1);
387 return;
388 }
389
390 /* ADCK step1 */
391 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
392 if (path == RF_PATH_B)
393 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
394 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
395 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
396 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
397 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
398 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
399 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
400 for (i = 0; i < 10; i++) {
401 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
402 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
403 rtw_write32(rtwdev, 0x1c24, 0x00010002);
404 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
405 rtw_dbg(rtwdev, RTW_DBG_RFK,
406 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
407
408 /* compensation value */
409 if (ic != 0x0) {
410 ic = 0x400 - ic;
411 *adc_ic = ic;
412 }
413 if (qc != 0x0) {
414 qc = 0x400 - qc;
415 *adc_qc = qc;
416 }
417 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
418 rtw_write32(rtwdev, base_addr + 0x68, temp);
419 dm_info->dack_adck[path] = temp;
420 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
421 base_addr + 0x68, temp);
422 /* check ADC DC offset */
423 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
424 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
425 rtw_dbg(rtwdev, RTW_DBG_RFK,
426 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
427 if (ic >= 0x200)
428 ic = 0x400 - ic;
429 if (qc >= 0x200)
430 qc = 0x400 - qc;
431 if (ic < 5 && qc < 5)
432 break;
433 }
434
435 /* ADCK step2 */
436 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
437 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
438 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
439
440 /* release pull low switch on IQ path */
441 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
442 }
443
rtw8822c_dac_cal_step1(struct rtw_dev * rtwdev,u8 path)444 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
445 {
446 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
447 u32 base_addr;
448 u32 read_addr;
449
450 base_addr = rtw8822c_get_path_write_addr(path);
451 read_addr = rtw8822c_get_path_read_addr(path);
452
453 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
454 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
455 if (path == RF_PATH_A) {
456 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
457 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
458 }
459 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
460 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
461 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
462 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
463 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
464 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
465 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
466 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
467 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
468 mdelay(2);
469 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
470 mdelay(2);
471 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
472 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
473 mdelay(1);
474 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
475 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
476 mdelay(20);
477 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
478 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
479 rtw_err(rtwdev, "failed to wait for dack ready\n");
480 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
481 mdelay(1);
482 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
483 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
484 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
485 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
486 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
487 }
488
rtw8822c_dac_cal_step2(struct rtw_dev * rtwdev,u8 path,u32 * ic_out,u32 * qc_out)489 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
490 u8 path, u32 *ic_out, u32 *qc_out)
491 {
492 u32 base_addr;
493 u32 ic, qc, ic_in, qc_in;
494
495 base_addr = rtw8822c_get_path_write_addr(path);
496 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
497 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
498 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
499 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
500
501 rtw_write32(rtwdev, 0x1b00, 0x00000008);
502 rtw_write8(rtwdev, 0x1bcc, 0x03f);
503 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
504 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
505 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
506
507 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
508 ic = ic_in;
509 qc = qc_in;
510
511 /* compensation value */
512 if (ic != 0x0)
513 ic = 0x400 - ic;
514 if (qc != 0x0)
515 qc = 0x400 - qc;
516 if (ic < 0x300) {
517 ic = ic * 2 * 6 / 5;
518 ic = ic + 0x80;
519 } else {
520 ic = (0x400 - ic) * 2 * 6 / 5;
521 ic = 0x7f - ic;
522 }
523 if (qc < 0x300) {
524 qc = qc * 2 * 6 / 5;
525 qc = qc + 0x80;
526 } else {
527 qc = (0x400 - qc) * 2 * 6 / 5;
528 qc = 0x7f - qc;
529 }
530
531 *ic_out = ic;
532 *qc_out = qc;
533
534 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
535 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
536 }
537
rtw8822c_dac_cal_step3(struct rtw_dev * rtwdev,u8 path,u32 adc_ic,u32 adc_qc,u32 * ic_in,u32 * qc_in,u32 * i_out,u32 * q_out)538 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
539 u32 adc_ic, u32 adc_qc,
540 u32 *ic_in, u32 *qc_in,
541 u32 *i_out, u32 *q_out)
542 {
543 u32 base_addr;
544 u32 read_addr;
545 u32 ic, qc;
546 u32 temp;
547
548 base_addr = rtw8822c_get_path_write_addr(path);
549 read_addr = rtw8822c_get_path_read_addr(path);
550 ic = *ic_in;
551 qc = *qc_in;
552
553 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
554 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
555 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
556 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
557 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
558 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
559 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
560 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
561 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
562 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
563 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
564 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
565 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
566 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
567 mdelay(2);
568 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
569 mdelay(2);
570 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
571 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
572 mdelay(1);
573 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
574 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
575 mdelay(20);
576 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
577 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
578 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
579 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
580 mdelay(1);
581 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
582 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
583
584 /* check DAC DC offset */
585 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
586 rtw_write32(rtwdev, base_addr + 0x68, temp);
587 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
588 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
589 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
590 if (ic >= 0x10)
591 ic = ic - 0x10;
592 else
593 ic = 0x400 - (0x10 - ic);
594
595 if (qc >= 0x10)
596 qc = qc - 0x10;
597 else
598 qc = 0x400 - (0x10 - qc);
599
600 *i_out = ic;
601 *q_out = qc;
602
603 if (ic >= 0x200)
604 ic = 0x400 - ic;
605 if (qc >= 0x200)
606 qc = 0x400 - qc;
607
608 *ic_in = ic;
609 *qc_in = qc;
610
611 rtw_dbg(rtwdev, RTW_DBG_RFK,
612 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
613 }
614
rtw8822c_dac_cal_step4(struct rtw_dev * rtwdev,u8 path)615 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
616 {
617 u32 base_addr = rtw8822c_get_path_write_addr(path);
618
619 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
620 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
621 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
622 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
623 }
624
rtw8822c_dac_cal_backup_vec(struct rtw_dev * rtwdev,u8 path,u8 vec,u32 w_addr,u32 r_addr)625 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
626 u8 path, u8 vec, u32 w_addr, u32 r_addr)
627 {
628 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
629 u16 val;
630 u32 i;
631
632 if (WARN_ON(vec >= 2))
633 return;
634
635 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
636 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
637 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
638 dm_info->dack_msbk[path][vec][i] = val;
639 }
640 }
641
rtw8822c_dac_cal_backup_path(struct rtw_dev * rtwdev,u8 path)642 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
643 {
644 u32 w_off = 0x1c;
645 u32 r_off = 0x2c;
646 u32 w_addr, r_addr;
647
648 if (WARN_ON(path >= 2))
649 return;
650
651 /* backup I vector */
652 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
653 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
654 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
655
656 /* backup Q vector */
657 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
658 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
659 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
660 }
661
rtw8822c_dac_cal_backup_dck(struct rtw_dev * rtwdev)662 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
663 {
664 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
665 u8 val;
666
667 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
668 dm_info->dack_dck[RF_PATH_A][0][0] = val;
669 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
670 dm_info->dack_dck[RF_PATH_A][0][1] = val;
671 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
672 dm_info->dack_dck[RF_PATH_A][1][0] = val;
673 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
674 dm_info->dack_dck[RF_PATH_A][1][1] = val;
675
676 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
677 dm_info->dack_dck[RF_PATH_B][0][0] = val;
678 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
679 dm_info->dack_dck[RF_PATH_B][1][0] = val;
680 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
681 dm_info->dack_dck[RF_PATH_B][0][1] = val;
682 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
683 dm_info->dack_dck[RF_PATH_B][1][1] = val;
684 }
685
rtw8822c_dac_cal_backup(struct rtw_dev * rtwdev)686 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
687 {
688 u32 temp[3];
689
690 temp[0] = rtw_read32(rtwdev, 0x1860);
691 temp[1] = rtw_read32(rtwdev, 0x4160);
692 temp[2] = rtw_read32(rtwdev, 0x9b4);
693
694 /* set clock */
695 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
696
697 /* backup path-A I/Q */
698 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
699 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
700 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
701
702 /* backup path-B I/Q */
703 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
704 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
705 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
706
707 rtw8822c_dac_cal_backup_dck(rtwdev);
708 rtw_write32_set(rtwdev, 0x1830, BIT(30));
709 rtw_write32_set(rtwdev, 0x4130, BIT(30));
710
711 rtw_write32(rtwdev, 0x1860, temp[0]);
712 rtw_write32(rtwdev, 0x4160, temp[1]);
713 rtw_write32(rtwdev, 0x9b4, temp[2]);
714 }
715
rtw8822c_dac_cal_restore_dck(struct rtw_dev * rtwdev)716 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
717 {
718 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
719 u8 val;
720
721 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
722 val = dm_info->dack_dck[RF_PATH_A][0][0];
723 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
724 val = dm_info->dack_dck[RF_PATH_A][0][1];
725 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
726
727 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
728 val = dm_info->dack_dck[RF_PATH_A][1][0];
729 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
730 val = dm_info->dack_dck[RF_PATH_A][1][1];
731 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
732
733 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
734 val = dm_info->dack_dck[RF_PATH_B][0][0];
735 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
736 val = dm_info->dack_dck[RF_PATH_B][0][1];
737 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
738
739 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
740 val = dm_info->dack_dck[RF_PATH_B][1][0];
741 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
742 val = dm_info->dack_dck[RF_PATH_B][1][1];
743 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
744 }
745
rtw8822c_dac_cal_restore_prepare(struct rtw_dev * rtwdev)746 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
747 {
748 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
749
750 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
751 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
752 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
753 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
754
755 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
756 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
757 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
758 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
759
760 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
761 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
762 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
763 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
764
765 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
766 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
767 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
768 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
769
770 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
771 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
772 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
773 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
774
775 rtw8822c_dac_cal_restore_dck(rtwdev);
776
777 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
778 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
779 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
780 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
781
782 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
783 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
784
785 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
786 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
787 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
788 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
789
790 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
791 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
792 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
793 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
794
795 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
796 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
797 }
798
rtw8822c_dac_cal_restore_wait(struct rtw_dev * rtwdev,u32 target_addr,u32 toggle_addr)799 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
800 u32 target_addr, u32 toggle_addr)
801 {
802 u32 cnt = 0;
803
804 do {
805 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
806 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
807
808 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
809 return true;
810
811 } while (cnt++ < 100);
812
813 return false;
814 }
815
rtw8822c_dac_cal_restore_path(struct rtw_dev * rtwdev,u8 path)816 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
817 {
818 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
819 u32 w_off = 0x1c;
820 u32 r_off = 0x2c;
821 u32 w_i, r_i, w_q, r_q;
822 u32 value;
823 u32 i;
824
825 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
826 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
827 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
828 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
829
830 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
831 return false;
832
833 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
834 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
835 value = dm_info->dack_msbk[path][0][i];
836 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
837 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
838 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
839 }
840
841 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
842
843 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
844 return false;
845
846 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
847 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
848 value = dm_info->dack_msbk[path][1][i];
849 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
850 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
851 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
852 }
853 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
854
855 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
856 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
857 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
858 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
859
860 return true;
861 }
862
__rtw8822c_dac_cal_restore(struct rtw_dev * rtwdev)863 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
864 {
865 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
866 return false;
867
868 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
869 return false;
870
871 return true;
872 }
873
rtw8822c_dac_cal_restore(struct rtw_dev * rtwdev)874 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
875 {
876 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
877 u32 temp[3];
878
879 /* sample the first element for both path's IQ vector */
880 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
881 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
882 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
883 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
884 return false;
885
886 temp[0] = rtw_read32(rtwdev, 0x1860);
887 temp[1] = rtw_read32(rtwdev, 0x4160);
888 temp[2] = rtw_read32(rtwdev, 0x9b4);
889
890 rtw8822c_dac_cal_restore_prepare(rtwdev);
891 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
892 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
893 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
894 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
895 return false;
896
897 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
898 rtw_err(rtwdev, "failed to restore dack vectors\n");
899 return false;
900 }
901
902 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
903 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
904 rtw_write32(rtwdev, 0x1860, temp[0]);
905 rtw_write32(rtwdev, 0x4160, temp[1]);
906 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
907 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
908 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
909 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
910 rtw_write32(rtwdev, 0x9b4, temp[2]);
911
912 return true;
913 }
914
rtw8822c_rf_dac_cal(struct rtw_dev * rtwdev)915 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
916 {
917 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
918 struct rtw_backup_info backup[DACK_REG_8822C];
919 u32 ic = 0, qc = 0, i;
920 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
921 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
922 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
923
924 if (rtw8822c_dac_cal_restore(rtwdev))
925 return;
926
927 /* not able to restore, do it */
928
929 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
930
931 rtw8822c_dac_bb_setting(rtwdev);
932
933 /* path-A */
934 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
935 for (i = 0; i < 10; i++) {
936 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
937 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
938 ic_a = ic;
939 qc_a = qc;
940
941 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
942 &ic, &qc, &i_a, &q_a);
943
944 if (ic < 5 && qc < 5)
945 break;
946 }
947 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
948
949 /* path-B */
950 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
951 for (i = 0; i < 10; i++) {
952 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
953 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
954 ic_b = ic;
955 qc_b = qc;
956
957 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
958 &ic, &qc, &i_b, &q_b);
959
960 if (ic < 5 && qc < 5)
961 break;
962 }
963 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
964
965 rtw_write32(rtwdev, 0x1b00, 0x00000008);
966 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
967 rtw_write8(rtwdev, 0x1bcc, 0x0);
968 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
969 rtw_write8(rtwdev, 0x1bcc, 0x0);
970
971 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
972
973 /* backup results to restore, saving a lot of time */
974 rtw8822c_dac_cal_backup(rtwdev);
975
976 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
980 }
981
rtw8822c_rf_x2_check(struct rtw_dev * rtwdev)982 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
983 {
984 u8 x2k_busy;
985
986 mdelay(1);
987 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
988 if (x2k_busy == 1) {
989 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
990 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
991 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
992 mdelay(1);
993 }
994 }
995
rtw8822c_set_power_trim(struct rtw_dev * rtwdev,s8 bb_gain[2][8])996 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8])
997 {
998 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \
999 do { \
1000 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1001 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1002 bb_gain[_path][_idx]); \
1003 } while (0)
1004 u8 path;
1005
1006 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1007 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1008 RF_SET_POWER_TRIM(path, 0x0, 0);
1009 RF_SET_POWER_TRIM(path, 0x1, 1);
1010 RF_SET_POWER_TRIM(path, 0x2, 2);
1011 RF_SET_POWER_TRIM(path, 0x3, 2);
1012 RF_SET_POWER_TRIM(path, 0x4, 3);
1013 RF_SET_POWER_TRIM(path, 0x5, 4);
1014 RF_SET_POWER_TRIM(path, 0x6, 5);
1015 RF_SET_POWER_TRIM(path, 0x7, 6);
1016 RF_SET_POWER_TRIM(path, 0x8, 7);
1017 RF_SET_POWER_TRIM(path, 0x9, 3);
1018 RF_SET_POWER_TRIM(path, 0xa, 4);
1019 RF_SET_POWER_TRIM(path, 0xb, 5);
1020 RF_SET_POWER_TRIM(path, 0xc, 6);
1021 RF_SET_POWER_TRIM(path, 0xd, 7);
1022 RF_SET_POWER_TRIM(path, 0xe, 7);
1023 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1024 }
1025 #undef RF_SET_POWER_TRIM
1026 }
1027
rtw8822c_power_trim(struct rtw_dev * rtwdev)1028 static void rtw8822c_power_trim(struct rtw_dev *rtwdev)
1029 {
1030 u8 pg_pwr = 0xff, i, path, idx;
1031 s8 bb_gain[2][8] = {};
1032 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB};
1033 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA,
1034 PPG_5GM2_TXA, PPG_5GH1_TXA},
1035 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB,
1036 PPG_5GM2_TXB, PPG_5GH1_TXB} };
1037 bool set = false;
1038
1039 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) {
1040 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr);
1041 if (pg_pwr == EFUSE_READ_FAIL)
1042 continue;
1043 set = true;
1044 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr);
1045 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr);
1046 }
1047
1048 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) {
1049 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1050 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1051 &pg_pwr);
1052 if (pg_pwr == EFUSE_READ_FAIL)
1053 continue;
1054 set = true;
1055 idx = i + ARRAY_SIZE(rf_efuse_2g);
1056 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr);
1057 }
1058 }
1059 if (set)
1060 rtw8822c_set_power_trim(rtwdev, bb_gain);
1061
1062 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1063 }
1064
rtw8822c_thermal_trim(struct rtw_dev * rtwdev)1065 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev)
1066 {
1067 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B};
1068 u8 pg_therm = 0xff, thermal[2] = {0}, path;
1069
1070 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1071 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1072 if (pg_therm == EFUSE_READ_FAIL)
1073 return;
1074 /* Efuse value of BIT(0) shall be move to BIT(3), and the value
1075 * of BIT(1) to BIT(3) should be right shifted 1 bit.
1076 */
1077 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm);
1078 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0));
1079 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1080 }
1081 }
1082
rtw8822c_pa_bias(struct rtw_dev * rtwdev)1083 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
1084 {
1085 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB};
1086 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB};
1087 u8 pg_pa_bias = 0xff, path;
1088
1089 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1090 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1091 &pg_pa_bias);
1092 if (pg_pa_bias == EFUSE_READ_FAIL)
1093 return;
1094 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
1095 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias);
1096 }
1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1098 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1099 &pg_pa_bias);
1100 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
1101 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias);
1102 }
1103 }
1104
rtw8822c_rf_init(struct rtw_dev * rtwdev)1105 static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1106 {
1107 rtw8822c_rf_dac_cal(rtwdev);
1108 rtw8822c_rf_x2_check(rtwdev);
1109 rtw8822c_thermal_trim(rtwdev);
1110 rtw8822c_power_trim(rtwdev);
1111 rtw8822c_pa_bias(rtwdev);
1112 }
1113
rtw8822c_pwrtrack_init(struct rtw_dev * rtwdev)1114 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
1115 {
1116 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1117 u8 path;
1118
1119 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) {
1120 dm_info->delta_power_index[path] = 0;
1121 ewma_thermal_init(&dm_info->avg_thermal[path]);
1122 dm_info->thermal_avg[path] = 0xff;
1123 }
1124
1125 dm_info->pwr_trk_triggered = false;
1126 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1127 }
1128
rtw8822c_phy_set_param(struct rtw_dev * rtwdev)1129 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1130 {
1131 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1132 struct rtw_hal *hal = &rtwdev->hal;
1133 u8 crystal_cap;
1134 u8 cck_gi_u_bnd_msb = 0;
1135 u8 cck_gi_u_bnd_lsb = 0;
1136 u8 cck_gi_l_bnd_msb = 0;
1137 u8 cck_gi_l_bnd_lsb = 0;
1138 bool is_tx2_path;
1139
1140 /* power on BB/RF domain */
1141 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1142 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
1143 rtw_write8_set(rtwdev, REG_RF_CTRL,
1144 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
1145 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1146
1147 /* disable low rate DPD */
1148 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1149
1150 /* pre init before header files config */
1151 rtw8822c_header_file_init(rtwdev, true);
1152
1153 rtw_phy_load_tables(rtwdev);
1154
1155 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1156 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1157 crystal_cap | (crystal_cap << 7));
1158
1159 /* post init after header files config */
1160 rtw8822c_header_file_init(rtwdev, false);
1161
1162 is_tx2_path = false;
1163 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1164 is_tx2_path);
1165 rtw_phy_init(rtwdev);
1166
1167 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1168 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1169 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1170 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1171
1172 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1173 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
1174
1175 rtw8822c_rf_init(rtwdev);
1176 rtw8822c_pwrtrack_init(rtwdev);
1177
1178 rtw_bf_phy_init(rtwdev);
1179 }
1180
1181 #define WLAN_TXQ_RPT_EN 0x1F
1182 #define WLAN_SLOT_TIME 0x09
1183 #define WLAN_PIFS_TIME 0x1C
1184 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1185 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1186 #define WLAN_SIFS_CCK_TRX 0x0A
1187 #define WLAN_SIFS_OFDM_TRX 0x10
1188 #define WLAN_NAV_MAX 0xC8
1189 #define WLAN_RDG_NAV 0x05
1190 #define WLAN_TXOP_NAV 0x1B
1191 #define WLAN_CCK_RX_TSF 0x30
1192 #define WLAN_OFDM_RX_TSF 0x30
1193 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1194 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1195 #define WLAN_DRV_EARLY_INT 0x04
1196 #define WLAN_BCN_CTRL_CLT0 0x10
1197 #define WLAN_BCN_DMA_TIME 0x02
1198 #define WLAN_BCN_MAX_ERR 0xFF
1199 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1200 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1201 #define WLAN_SIFS_CCK_CTX 0x0A
1202 #define WLAN_SIFS_CCK_IRX 0x0A
1203 #define WLAN_SIFS_OFDM_CTX 0x0E
1204 #define WLAN_SIFS_OFDM_IRX 0x0E
1205 #define WLAN_EIFS_DUR_TUNE 0x40
1206 #define WLAN_EDCA_VO_PARAM 0x002FA226
1207 #define WLAN_EDCA_VI_PARAM 0x005EA328
1208 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1209 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1210
1211 #define WLAN_RX_FILTER0 0xFFFFFFFF
1212 #define WLAN_RX_FILTER2 0xFFFF
1213 #define WLAN_RCR_CFG 0xE400220E
1214 #define WLAN_RXPKT_MAX_SZ 12288
1215 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
1216
1217 #define WLAN_AMPDU_MAX_TIME 0x70
1218 #define WLAN_RTS_LEN_TH 0xFF
1219 #define WLAN_RTS_TX_TIME_TH 0x08
1220 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1221 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
1222 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1223 #define FAST_EDCA_VO_TH 0x06
1224 #define FAST_EDCA_VI_TH 0x06
1225 #define FAST_EDCA_BE_TH 0x06
1226 #define FAST_EDCA_BK_TH 0x06
1227 #define WLAN_BAR_RETRY_LIMIT 0x01
1228 #define WLAN_BAR_ACK_TYPE 0x05
1229 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1230 #define WLAN_RESP_TXRATE 0x84
1231 #define WLAN_ACK_TO 0x21
1232 #define WLAN_ACK_TO_CCK 0x6A
1233 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1234 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1235 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1236 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1237 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1238 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1239 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1240 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1241 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1242 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1243 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1244 #define WLAN_MULTI_ADDR 0xFFFFFFFF
1245
1246 #define WLAN_TX_FUNC_CFG1 0x30
1247 #define WLAN_TX_FUNC_CFG2 0x30
1248 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1249 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1250 #define WLAN_MAC_OPT_FUNC2 0x30810041
1251 #define WLAN_MAC_INT_MIG_CFG 0x33330000
1252
1253 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
1254 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
1255 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
1256 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
1257
1258 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \
1259 (WLAN_SIFS_OFDM_DUR_TUNE << 8))
1260
1261 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
1262 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
1263
1264 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
1265 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
1266
1267 #define MAC_CLK_SPEED 80 /* 80M */
1268 #define EFUSE_PCB_INFO_OFFSET 0xCA
1269
rtw8822c_mac_init(struct rtw_dev * rtwdev)1270 static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
1271 {
1272 u8 value8;
1273 u16 value16;
1274 u32 value32;
1275 u16 pre_txcnt;
1276
1277 /* txq control */
1278 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
1279 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2));
1280 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
1281 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
1282 /* sifs control */
1283 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
1284 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
1285 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
1286 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);
1287 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
1288 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);
1289 /* rate fallback control */
1290 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
1291 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
1292 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
1293 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
1294 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
1295 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
1296 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
1297 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
1298 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
1299 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
1300 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
1301 /* protocol configuration */
1302 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
1303 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
1304 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
1305 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
1306 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
1307 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
1308 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
1309 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
1310 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
1311 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
1312 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
1313 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
1314 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
1315 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
1316 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
1317 /* close BA parser */
1318 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
1319 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
1320
1321 /* EDCA configuration */
1322 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
1323 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
1324 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
1325 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
1326 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
1327 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
1328 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
1329 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE |
1330 BIT_DIS_STBC_CFE) >> 8);
1331
1332 /* MAC clock configuration */
1333 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
1334 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
1335 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
1336
1337 rtw_write8_set(rtwdev, REG_MISC_CTRL,
1338 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA);
1339 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
1340 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
1341 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
1342 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
1343 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
1344 /* Set beacon cotnrol - enable TSF and other related functions */
1345 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1346 /* Set send beacon related registers */
1347 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
1348 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
1349 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
1350 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
1351 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
1352
1353 /* WMAC configuration */
1354 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
1355 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
1356 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
1357 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
1358 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
1359 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
1360 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
1361 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
1362 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
1363 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
1364 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
1365 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
1366 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
1367 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
1368 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
1369 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
1370 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
1371
1372 /* init low power */
1373 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
1374 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) |
1375 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16;
1376 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
1377 value16 = 0;
1378 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);
1379 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN
1380 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN
1381 | BIT_RXPSF_OFDMRST;
1382 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1383 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
1384 /* rx ignore configuration */
1385 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
1386 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST |
1387 BIT_RXPSF_CONT_ERRCHKEN);
1388 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
1389 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1390
1391 /* Interrupt migration configuration */
1392 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
1393
1394 return 0;
1395 }
1396
rtw8822c_rstb_3wire(struct rtw_dev * rtwdev,bool enable)1397 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable)
1398 {
1399 if (enable) {
1400 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
1401 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
1402 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
1403 } else {
1404 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
1405 }
1406 }
1407
rtw8822c_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)1408 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1409 {
1410 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
1411 #define RF18_BAND_2G (0)
1412 #define RF18_BAND_5G (BIT(16) | BIT(8))
1413 #define RF18_CHANNEL_MASK (MASKBYTE0)
1414 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
1415 #define RF18_RFSI_GE_CH80 (BIT(17))
1416 #define RF18_RFSI_GT_CH140 (BIT(18))
1417 #define RF18_BW_MASK (BIT(13) | BIT(12))
1418 #define RF18_BW_20M (BIT(13) | BIT(12))
1419 #define RF18_BW_40M (BIT(13))
1420 #define RF18_BW_80M (BIT(12))
1421
1422 u32 rf_reg18 = 0;
1423 u32 rf_rxbb = 0;
1424
1425 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
1426
1427 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
1428 RF18_BW_MASK);
1429
1430 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G);
1431 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
1432 if (IS_CH_5G_BAND_4(channel))
1433 rf_reg18 |= RF18_RFSI_GT_CH140;
1434 else if (IS_CH_5G_BAND_3(channel))
1435 rf_reg18 |= RF18_RFSI_GE_CH80;
1436
1437 switch (bw) {
1438 case RTW_CHANNEL_WIDTH_5:
1439 case RTW_CHANNEL_WIDTH_10:
1440 case RTW_CHANNEL_WIDTH_20:
1441 default:
1442 rf_reg18 |= RF18_BW_20M;
1443 rf_rxbb = 0x18;
1444 break;
1445 case RTW_CHANNEL_WIDTH_40:
1446 /* RF bandwidth */
1447 rf_reg18 |= RF18_BW_40M;
1448 rf_rxbb = 0x10;
1449 break;
1450 case RTW_CHANNEL_WIDTH_80:
1451 rf_reg18 |= RF18_BW_80M;
1452 rf_rxbb = 0x8;
1453 break;
1454 }
1455
1456 rtw8822c_rstb_3wire(rtwdev, false);
1457
1458 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
1459 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
1460 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
1461 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
1462
1463 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
1464 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
1465 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
1466 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
1467
1468 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
1469 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
1470
1471 rtw8822c_rstb_3wire(rtwdev, true);
1472 }
1473
rtw8822c_toggle_igi(struct rtw_dev * rtwdev)1474 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
1475 {
1476 u32 igi;
1477
1478 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
1479 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
1480 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
1481 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
1482 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
1483 }
1484
rtw8822c_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)1485 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1486 u8 primary_ch_idx)
1487 {
1488 if (IS_CH_2G_BAND(channel)) {
1489 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1490 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
1491 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1492 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1493 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
1494
1495 switch (bw) {
1496 case RTW_CHANNEL_WIDTH_20:
1497 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1498 0x5);
1499 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1500 0x5);
1501 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1502 0x6);
1503 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1504 0x6);
1505 break;
1506 case RTW_CHANNEL_WIDTH_40:
1507 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1508 0x4);
1509 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1510 0x4);
1511 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1512 0x0);
1513 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1514 0x0);
1515 break;
1516 }
1517 if (channel == 13 || channel == 14)
1518 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
1519 else if (channel == 11 || channel == 12)
1520 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
1521 else
1522 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
1523 if (channel == 14) {
1524 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
1525 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1526 0x4962c931);
1527 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
1528 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
1529 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
1530 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
1531 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1532 0xff012455);
1533 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
1534 } else {
1535 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
1536 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1537 0x3e18fec8);
1538 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
1539 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
1540 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
1541 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
1542 0x00faf0de);
1543 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1544 0x00122344);
1545 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
1546 0x0fffffff);
1547 }
1548 if (channel == 13)
1549 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1550 else
1551 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
1552 } else if (IS_CH_5G_BAND(channel)) {
1553 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1554 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1555 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1556 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
1557 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
1558 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1559 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
1560 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1561 0x1);
1562 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1563 0x1);
1564 } else if (IS_CH_5G_BAND_3(channel)) {
1565 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1566 0x2);
1567 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1568 0x2);
1569 } else if (IS_CH_5G_BAND_4(channel)) {
1570 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1571 0x3);
1572 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1573 0x3);
1574 }
1575
1576 if (channel >= 36 && channel <= 51)
1577 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
1578 else if (channel >= 52 && channel <= 55)
1579 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
1580 else if (channel >= 56 && channel <= 111)
1581 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
1582 else if (channel >= 112 && channel <= 119)
1583 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
1584 else if (channel >= 120 && channel <= 172)
1585 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
1586 else if (channel >= 173 && channel <= 177)
1587 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
1588 }
1589
1590 switch (bw) {
1591 case RTW_CHANNEL_WIDTH_20:
1592 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
1593 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1594 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
1595 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
1596 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
1597 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1598 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1599 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1600 break;
1601 case RTW_CHANNEL_WIDTH_40:
1602 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
1603 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
1604 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
1605 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1606 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1607 (primary_ch_idx | (primary_ch_idx << 4)));
1608 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
1609 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1610 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1611 break;
1612 case RTW_CHANNEL_WIDTH_80:
1613 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
1614 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1616 (primary_ch_idx | (primary_ch_idx << 4)));
1617 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
1618 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1619 break;
1620 case RTW_CHANNEL_WIDTH_5:
1621 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1622 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1623 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
1624 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
1625 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
1626 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1627 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1628 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1629 break;
1630 case RTW_CHANNEL_WIDTH_10:
1631 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1632 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1633 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
1634 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
1635 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
1636 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1637 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1638 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1639 break;
1640 }
1641 }
1642
rtw8822c_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)1643 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1644 u8 primary_chan_idx)
1645 {
1646 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
1647 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
1648 rtw8822c_set_channel_rf(rtwdev, channel, bw);
1649 rtw8822c_toggle_igi(rtwdev);
1650 }
1651
rtw8822c_config_cck_rx_path(struct rtw_dev * rtwdev,u8 rx_path)1652 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1653 {
1654 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1655 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
1656 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
1657 } else if (rx_path == BB_PATH_AB) {
1658 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
1659 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
1660 }
1661
1662 if (rx_path == BB_PATH_A)
1663 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
1664 else if (rx_path == BB_PATH_B)
1665 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
1666 else if (rx_path == BB_PATH_AB)
1667 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
1668 }
1669
rtw8822c_config_ofdm_rx_path(struct rtw_dev * rtwdev,u8 rx_path)1670 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1671 {
1672 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1673 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
1674 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
1675 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
1676 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
1677 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
1678 } else if (rx_path == BB_PATH_AB) {
1679 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
1680 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
1681 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
1682 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
1683 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
1684 }
1685
1686 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
1687 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
1688 }
1689
rtw8822c_config_rx_path(struct rtw_dev * rtwdev,u8 rx_path)1690 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1691 {
1692 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
1693 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
1694 }
1695
rtw8822c_config_cck_tx_path(struct rtw_dev * rtwdev,u8 tx_path,bool is_tx2_path)1696 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1697 bool is_tx2_path)
1698 {
1699 if (tx_path == BB_PATH_A) {
1700 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1701 } else if (tx_path == BB_PATH_B) {
1702 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
1703 } else {
1704 if (is_tx2_path)
1705 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
1706 else
1707 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1708 }
1709 }
1710
rtw8822c_config_ofdm_tx_path(struct rtw_dev * rtwdev,u8 tx_path,bool is_tx2_path)1711 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1712 bool is_tx2_path)
1713 {
1714 if (tx_path == BB_PATH_A) {
1715 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
1716 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1717 } else if (tx_path == BB_PATH_B) {
1718 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
1719 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1720 } else {
1721 if (is_tx2_path) {
1722 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
1723 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
1724 } else {
1725 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
1726 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
1727 }
1728 }
1729 }
1730
rtw8822c_config_tx_path(struct rtw_dev * rtwdev,u8 tx_path,bool is_tx2_path)1731 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1732 bool is_tx2_path)
1733 {
1734 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path);
1735 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path);
1736 }
1737
rtw8822c_config_trx_mode(struct rtw_dev * rtwdev,u8 tx_path,u8 rx_path,bool is_tx2_path)1738 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
1739 u8 rx_path, bool is_tx2_path)
1740 {
1741 if ((tx_path | rx_path) & BB_PATH_A)
1742 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
1743 else
1744 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
1745 if ((tx_path | rx_path) & BB_PATH_B)
1746 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
1747 else
1748 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
1749
1750 rtw8822c_config_rx_path(rtwdev, rx_path);
1751 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path);
1752
1753 rtw8822c_toggle_igi(rtwdev);
1754 }
1755
query_phy_status_page0(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)1756 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
1757 struct rtw_rx_pkt_stat *pkt_stat)
1758 {
1759 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1760 u8 l_bnd, u_bnd;
1761 u8 gain_a, gain_b;
1762 s8 rx_power[RTW_RF_PATH_MAX];
1763 s8 min_rx_power = -120;
1764 u8 rssi;
1765 int path;
1766
1767 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status);
1768 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status);
1769 l_bnd = dm_info->cck_gi_l_bnd;
1770 u_bnd = dm_info->cck_gi_u_bnd;
1771 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status);
1772 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status);
1773 if (gain_a < l_bnd)
1774 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
1775 else if (gain_a > u_bnd)
1776 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
1777 if (gain_b < l_bnd)
1778 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
1779 else if (gain_b > u_bnd)
1780 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
1781
1782 rx_power[RF_PATH_A] -= 110;
1783 rx_power[RF_PATH_B] -= 110;
1784
1785 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
1786 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
1787
1788 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1789 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
1790 dm_info->rssi[path] = rssi;
1791 }
1792
1793 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1794 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1795 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
1796 min_rx_power);
1797 }
1798
query_phy_status_page1(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)1799 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
1800 struct rtw_rx_pkt_stat *pkt_stat)
1801 {
1802 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1803 u8 rxsc, bw;
1804 s8 min_rx_power = -120;
1805 s8 rx_evm;
1806 u8 evm_dbm = 0;
1807 u8 rssi;
1808 int path;
1809
1810 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
1811 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
1812 else
1813 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
1814
1815 if (rxsc >= 9 && rxsc <= 12)
1816 bw = RTW_CHANNEL_WIDTH_40;
1817 else if (rxsc >= 13)
1818 bw = RTW_CHANNEL_WIDTH_80;
1819 else
1820 bw = RTW_CHANNEL_WIDTH_20;
1821
1822 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
1823 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
1824 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
1825 pkt_stat->bw = bw;
1826 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
1827 pkt_stat->rx_power[RF_PATH_B],
1828 min_rx_power);
1829
1830 dm_info->curr_rx_rate = pkt_stat->rate;
1831
1832 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
1833 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
1834
1835 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
1836 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
1837
1838 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
1839 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
1840
1841 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
1842 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
1843 dm_info->rssi[path] = rssi;
1844 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
1845 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
1846
1847 rx_evm = pkt_stat->rx_evm[path];
1848
1849 if (rx_evm < 0) {
1850 if (rx_evm == S8_MIN)
1851 evm_dbm = 0;
1852 else
1853 evm_dbm = ((u8)-rx_evm >> 1);
1854 }
1855 dm_info->rx_evm_dbm[path] = evm_dbm;
1856 }
1857 }
1858
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)1859 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1860 struct rtw_rx_pkt_stat *pkt_stat)
1861 {
1862 u8 page;
1863
1864 page = *phy_status & 0xf;
1865
1866 switch (page) {
1867 case 0:
1868 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
1869 break;
1870 case 1:
1871 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
1872 break;
1873 default:
1874 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
1875 return;
1876 }
1877 }
1878
rtw8822c_query_rx_desc(struct rtw_dev * rtwdev,u8 * rx_desc,struct rtw_rx_pkt_stat * pkt_stat,struct ieee80211_rx_status * rx_status)1879 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
1880 struct rtw_rx_pkt_stat *pkt_stat,
1881 struct ieee80211_rx_status *rx_status)
1882 {
1883 struct ieee80211_hdr *hdr;
1884 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
1885 u8 *phy_status = NULL;
1886
1887 memset(pkt_stat, 0, sizeof(*pkt_stat));
1888
1889 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
1890 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
1891 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
1892 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
1893 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
1894 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
1895 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
1896 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
1897 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
1898 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
1899 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
1900 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
1901 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
1902
1903 /* drv_info_sz is in unit of 8-bytes */
1904 pkt_stat->drv_info_sz *= 8;
1905
1906 /* c2h cmd pkt's rx/phy status is not interested */
1907 if (pkt_stat->is_c2h)
1908 return;
1909
1910 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
1911 pkt_stat->drv_info_sz);
1912 if (pkt_stat->phy_status) {
1913 phy_status = rx_desc + desc_sz + pkt_stat->shift;
1914 query_phy_status(rtwdev, phy_status, pkt_stat);
1915 }
1916
1917 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
1918 }
1919
1920 static void
rtw8822c_set_write_tx_power_ref(struct rtw_dev * rtwdev,u8 * tx_pwr_ref_cck,u8 * tx_pwr_ref_ofdm)1921 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
1922 u8 *tx_pwr_ref_ofdm)
1923 {
1924 struct rtw_hal *hal = &rtwdev->hal;
1925 u32 txref_cck[2] = {0x18a0, 0x41a0};
1926 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
1927 u8 path;
1928
1929 for (path = 0; path < hal->rf_path_num; path++) {
1930 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1931 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
1932 tx_pwr_ref_cck[path]);
1933 }
1934 for (path = 0; path < hal->rf_path_num; path++) {
1935 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1936 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
1937 tx_pwr_ref_ofdm[path]);
1938 }
1939 }
1940
rtw8822c_set_tx_power_diff(struct rtw_dev * rtwdev,u8 rate,s8 * diff_idx)1941 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
1942 s8 *diff_idx)
1943 {
1944 u32 offset_txagc = 0x3a00;
1945 u8 rate_idx = rate & 0xfc;
1946 u8 pwr_idx[4];
1947 u32 phy_pwr_idx;
1948 int i;
1949
1950 for (i = 0; i < 4; i++)
1951 pwr_idx[i] = diff_idx[i] & 0x7f;
1952
1953 phy_pwr_idx = pwr_idx[0] |
1954 (pwr_idx[1] << 8) |
1955 (pwr_idx[2] << 16) |
1956 (pwr_idx[3] << 24);
1957
1958 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
1959 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
1960 phy_pwr_idx);
1961 }
1962
rtw8822c_set_tx_power_index(struct rtw_dev * rtwdev)1963 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
1964 {
1965 struct rtw_hal *hal = &rtwdev->hal;
1966 u8 rs, rate, j;
1967 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
1968 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
1969 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
1970 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
1971 s8 diff_a, diff_b;
1972 u8 pwr_a, pwr_b;
1973 s8 diff_idx[4];
1974
1975 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
1976 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
1977 for (j = 0; j < rtw_rate_size[rs]; j++) {
1978 rate = rtw_rate_section[rs][j];
1979 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
1980 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
1981 if (rs == 0) {
1982 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
1983 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
1984 } else {
1985 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
1986 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
1987 }
1988 diff_idx[rate % 4] = min(diff_a, diff_b);
1989 if (rate % 4 == 3)
1990 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
1991 diff_idx);
1992 }
1993 }
1994 }
1995
rtw8822c_set_antenna(struct rtw_dev * rtwdev,u32 antenna_tx,u32 antenna_rx)1996 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev,
1997 u32 antenna_tx,
1998 u32 antenna_rx)
1999 {
2000 struct rtw_hal *hal = &rtwdev->hal;
2001
2002 switch (antenna_tx) {
2003 case BB_PATH_A:
2004 case BB_PATH_B:
2005 case BB_PATH_AB:
2006 break;
2007 default:
2008 rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2009 return -EINVAL;
2010 }
2011
2012 /* path B only is not available for RX */
2013 switch (antenna_rx) {
2014 case BB_PATH_A:
2015 case BB_PATH_AB:
2016 break;
2017 default:
2018 rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2019 return -EINVAL;
2020 }
2021
2022 hal->antenna_tx = antenna_tx;
2023 hal->antenna_rx = antenna_rx;
2024
2025 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
2026
2027 return 0;
2028 }
2029
rtw8822c_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)2030 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
2031 {
2032 u8 ldo_pwr;
2033
2034 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
2035 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON;
2036 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
2037 }
2038
rtw8822c_false_alarm_statistics(struct rtw_dev * rtwdev)2039 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
2040 {
2041 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2042 u32 cck_enable;
2043 u32 cck_fa_cnt;
2044 u32 crc32_cnt;
2045 u32 cca32_cnt;
2046 u32 ofdm_fa_cnt;
2047 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
2048 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
2049 fast_fsync, crc8_fail_vhta, mcs_fail_vht;
2050
2051 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
2052 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
2053
2054 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
2055 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
2056 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
2057 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
2058 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
2059
2060 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);
2061 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
2062 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);
2063 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
2064 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
2065 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);
2066 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
2067 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);
2068
2069 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta +
2070 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail;
2071
2072 dm_info->cck_fa_cnt = cck_fa_cnt;
2073 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
2074 dm_info->total_fa_cnt = ofdm_fa_cnt;
2075 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2076
2077 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2078 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2079 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2080 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2081 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2082 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2083 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2084 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2085 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2086 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2087 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2088 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2089
2090 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2091 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2092 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2093 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
2094 if (cck_enable)
2095 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
2096
2097 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2098 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
2099 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2100 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
2101
2102 /* disable rx clk gating to reset counters */
2103 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2104 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2105 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2106 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2107 }
2108
rtw8822c_do_iqk(struct rtw_dev * rtwdev)2109 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
2110 {
2111 struct rtw_iqk_para para = {0};
2112 u8 iqk_chk;
2113 int counter;
2114
2115 para.clear = 1;
2116 rtw_fw_do_iqk(rtwdev, ¶);
2117
2118 for (counter = 0; counter < 300; counter++) {
2119 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP);
2120 if (iqk_chk == 0xaa)
2121 break;
2122 msleep(20);
2123 }
2124 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2125
2126 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter);
2127 }
2128
2129 /* for coex */
rtw8822c_coex_cfg_init(struct rtw_dev * rtwdev)2130 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
2131 {
2132 /* enable TBTT nterrupt */
2133 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2134
2135 /* BT report packet sample rate */
2136 /* 0x790[5:0]=0x5 */
2137 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
2138
2139 /* enable BT counter statistics */
2140 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2141
2142 /* enable PTA (3-wire function form BT side) */
2143 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
2144 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
2145
2146 /* enable PTA (tx/rx signal form WiFi side) */
2147 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
2148 /* wl tx signal to PTA not case EDCCA */
2149 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
2150 /* GNT_BT=1 while select both */
2151 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2152 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */
2153 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2154
2155 /* to avoid RF parameter error */
2156 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
2157 }
2158
rtw8822c_coex_cfg_gnt_fix(struct rtw_dev * rtwdev)2159 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2160 {
2161 struct rtw_coex *coex = &rtwdev->coex;
2162 struct rtw_coex_stat *coex_stat = &coex->stat;
2163 struct rtw_efuse *efuse = &rtwdev->efuse;
2164 u32 rf_0x1;
2165
2166 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
2167 return;
2168
2169 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
2170
2171 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
2172 rf_0x1 = 0x40021;
2173 else
2174 rf_0x1 = 0x40000;
2175
2176 /* BT at S1 for Shared-Ant */
2177 if (efuse->share_ant)
2178 rf_0x1 |= BIT(13);
2179
2180 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2181
2182 /* WL-S0 2G RF TRX cannot be masked by GNT_BT
2183 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
2184 * disable:0x1860[3] = 1, enable:0x1860[3] = 0
2185 *
2186 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
2187 * disable 0x1c30[22] = 0,
2188 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
2189 *
2190 * disable WL-S1 BB chage RF mode if GNT_BT
2191 * since RF TRx mask can do it
2192 */
2193 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
2194 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
2195 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
2196 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
2197
2198 /* disable WL-S0 BB chage RF mode if wifi is at 5G,
2199 * or antenna path is separated
2200 */
2201 if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
2202 coex->under_5g || !efuse->share_ant) {
2203 if (coex_stat->kt_ver >= 3) {
2204 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
2205 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
2206 } else {
2207 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
2208 }
2209 } else {
2210 /* shared-antenna */
2211 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
2212 if (coex_stat->kt_ver >= 3)
2213 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
2214 }
2215 }
2216
rtw8822c_coex_cfg_gnt_debug(struct rtw_dev * rtwdev)2217 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
2218 {
2219 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
2220 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
2221 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
2222 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
2223 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
2224 }
2225
rtw8822c_coex_cfg_rfe_type(struct rtw_dev * rtwdev)2226 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
2227 {
2228 struct rtw_coex *coex = &rtwdev->coex;
2229 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
2230 struct rtw_efuse *efuse = &rtwdev->efuse;
2231
2232 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
2233 coex_rfe->ant_switch_polarity = 0;
2234 coex_rfe->ant_switch_exist = false;
2235 coex_rfe->ant_switch_with_bt = false;
2236 coex_rfe->ant_switch_diversity = false;
2237
2238 if (efuse->share_ant)
2239 coex_rfe->wlg_at_btg = true;
2240 else
2241 coex_rfe->wlg_at_btg = false;
2242
2243 /* disable LTE coex in wifi side */
2244 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
2245 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
2246 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
2247 }
2248
rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)2249 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
2250 {
2251 struct rtw_coex *coex = &rtwdev->coex;
2252 struct rtw_coex_dm *coex_dm = &coex->dm;
2253
2254 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
2255 return;
2256
2257 coex_dm->cur_wl_pwr_lvl = wl_pwr;
2258 }
2259
rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)2260 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
2261 {
2262 struct rtw_coex *coex = &rtwdev->coex;
2263 struct rtw_coex_dm *coex_dm = &coex->dm;
2264
2265 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
2266 return;
2267
2268 coex_dm->cur_wl_rx_low_gain_en = low_gain;
2269
2270 if (coex_dm->cur_wl_rx_low_gain_en) {
2271 /* set Rx filter corner RCK offset */
2272 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
2273 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
2274 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
2275 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
2276 } else {
2277 /* set Rx filter corner RCK offset */
2278 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
2279 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
2280 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
2281 }
2282 }
2283
rtw8822c_bf_enable_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)2284 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
2285 struct rtw_vif *vif,
2286 struct rtw_bfee *bfee)
2287 {
2288 u8 csi_rsc = 0;
2289 u32 tmp6dc;
2290
2291 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
2292
2293 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
2294 BIT_WMAC_USE_NDPARATE |
2295 (csi_rsc << 13);
2296 if (vif->net_type == RTW_NET_AP_MODE)
2297 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
2298 else
2299 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
2300
2301 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
2302 }
2303
rtw8822c_bf_config_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)2304 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
2305 struct rtw_vif *vif,
2306 struct rtw_bfee *bfee, bool enable)
2307 {
2308 if (enable)
2309 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
2310 else
2311 rtw_bf_remove_bfee_su(rtwdev, bfee);
2312 }
2313
rtw8822c_bf_config_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)2314 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
2315 struct rtw_vif *vif,
2316 struct rtw_bfee *bfee, bool enable)
2317 {
2318 if (enable)
2319 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
2320 else
2321 rtw_bf_remove_bfee_mu(rtwdev, bfee);
2322 }
2323
rtw8822c_bf_config_bfee(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)2324 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
2325 struct rtw_bfee *bfee, bool enable)
2326 {
2327 if (bfee->role == RTW_BFEE_SU)
2328 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
2329 else if (bfee->role == RTW_BFEE_MU)
2330 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
2331 else
2332 rtw_warn(rtwdev, "wrong bfee role\n");
2333 }
2334
2335 struct dpk_cfg_pair {
2336 u32 addr;
2337 u32 bitmask;
2338 u32 data;
2339 };
2340
rtw8822c_parse_tbl_dpk(struct rtw_dev * rtwdev,const struct rtw_table * tbl)2341 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
2342 const struct rtw_table *tbl)
2343 {
2344 const struct dpk_cfg_pair *p = tbl->data;
2345 const struct dpk_cfg_pair *end = p + tbl->size / 3;
2346
2347 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3);
2348
2349 for (; p < end; p++)
2350 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
2351 }
2352
rtw8822c_dpk_set_gnt_wl(struct rtw_dev * rtwdev,bool is_before_k)2353 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
2354 {
2355 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2356
2357 if (is_before_k) {
2358 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
2359 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
2360 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
2361 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
2362 } else {
2363 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
2364 dpk_info->gnt_value);
2365 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
2366 }
2367 }
2368
2369 static void
rtw8822c_dpk_restore_registers(struct rtw_dev * rtwdev,u32 reg_num,struct rtw_backup_info * bckp)2370 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
2371 struct rtw_backup_info *bckp)
2372 {
2373 rtw_restore_reg(rtwdev, bckp, reg_num);
2374 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2375 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
2376 }
2377
2378 static void
rtw8822c_dpk_backup_registers(struct rtw_dev * rtwdev,u32 * reg,u32 reg_num,struct rtw_backup_info * bckp)2379 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
2380 u32 reg_num, struct rtw_backup_info *bckp)
2381 {
2382 u32 i;
2383
2384 for (i = 0; i < reg_num; i++) {
2385 bckp[i].len = 4;
2386 bckp[i].reg = reg[i];
2387 bckp[i].val = rtw_read32(rtwdev, reg[i]);
2388 }
2389 }
2390
rtw8822c_dpk_backup_rf_registers(struct rtw_dev * rtwdev,u32 * rf_reg,u32 rf_reg_bak[][2])2391 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
2392 u32 *rf_reg,
2393 u32 rf_reg_bak[][2])
2394 {
2395 u32 i;
2396
2397 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2398 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
2399 rf_reg[i], RFREG_MASK);
2400 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
2401 rf_reg[i], RFREG_MASK);
2402 }
2403 }
2404
rtw8822c_dpk_reload_rf_registers(struct rtw_dev * rtwdev,u32 * rf_reg,u32 rf_reg_bak[][2])2405 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
2406 u32 *rf_reg,
2407 u32 rf_reg_bak[][2])
2408 {
2409 u32 i;
2410
2411 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2412 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
2413 rf_reg_bak[i][RF_PATH_A]);
2414 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
2415 rf_reg_bak[i][RF_PATH_B]);
2416 }
2417 }
2418
rtw8822c_dpk_information(struct rtw_dev * rtwdev)2419 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
2420 {
2421 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2422 u32 reg;
2423 u8 band_shift;
2424
2425 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2426
2427 band_shift = FIELD_GET(BIT(16), reg);
2428 dpk_info->dpk_band = 1 << band_shift;
2429 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
2430 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
2431 }
2432
rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev * rtwdev,u8 path)2433 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
2434 {
2435 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2436 udelay(5);
2437 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
2438 usleep_range(600, 610);
2439 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2440 }
2441
rtw8822c_dpk_dc_corr_check(struct rtw_dev * rtwdev,u8 path)2442 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
2443 {
2444 u16 dc_i, dc_q;
2445 u8 corr_val, corr_idx;
2446
2447 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
2448 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2449 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
2450
2451 if (dc_i & BIT(11))
2452 dc_i = 0x1000 - dc_i;
2453 if (dc_q & BIT(11))
2454 dc_q = 0x1000 - dc_q;
2455
2456 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2457 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
2458 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
2459
2460 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65)
2461 return 1;
2462 else
2463 return 0;
2464
2465 }
2466
rtw8822c_dpk_tx_pause(struct rtw_dev * rtwdev)2467 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
2468 {
2469 u8 reg_a, reg_b;
2470 u16 count = 0;
2471
2472 rtw_write8(rtwdev, 0x522, 0xff);
2473 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
2474
2475 do {
2476 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
2477 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
2478 udelay(2);
2479 count++;
2480 } while ((reg_a == 2 || reg_b == 2) && count < 2500);
2481 }
2482
rtw8822c_dpk_mac_bb_setting(struct rtw_dev * rtwdev)2483 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
2484 {
2485 rtw8822c_dpk_tx_pause(rtwdev);
2486 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
2487 }
2488
rtw8822c_dpk_afe_setting(struct rtw_dev * rtwdev,bool is_do_dpk)2489 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
2490 {
2491 if (is_do_dpk)
2492 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
2493 else
2494 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
2495 }
2496
rtw8822c_dpk_pre_setting(struct rtw_dev * rtwdev)2497 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
2498 {
2499 u8 path;
2500
2501 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2502 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
2503 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2504 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
2505 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
2506 else
2507 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
2508 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
2509 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
2510 }
2511 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2512 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
2513 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
2514 }
2515
rtw8822c_dpk_rf_setting(struct rtw_dev * rtwdev,u8 path)2516 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
2517 {
2518 u32 ori_txbb;
2519
2520 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
2521 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
2522
2523 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
2524 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
2525 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);
2526 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
2527
2528 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
2529 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);
2530 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
2531 } else {
2532 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
2533 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
2534 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
2535 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
2536 }
2537
2538 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2539 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
2540 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
2541
2542 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
2543 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
2544 else
2545 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
2546
2547 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
2548
2549 usleep_range(100, 110);
2550
2551 return ori_txbb & 0x1f;
2552 }
2553
rtw8822c_dpk_get_cmd(struct rtw_dev * rtwdev,u8 action,u8 path)2554 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
2555 {
2556 u16 cmd;
2557 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
2558
2559 switch (action) {
2560 case RTW_DPK_GAIN_LOSS:
2561 cmd = 0x14 + path;
2562 break;
2563 case RTW_DPK_DO_DPK:
2564 cmd = 0x16 + path + bw;
2565 break;
2566 case RTW_DPK_DPK_ON:
2567 cmd = 0x1a + path;
2568 break;
2569 case RTW_DPK_DAGC:
2570 cmd = 0x1c + path + bw;
2571 break;
2572 default:
2573 return 0;
2574 }
2575
2576 return (cmd << 8) | 0x48;
2577 }
2578
rtw8822c_dpk_one_shot(struct rtw_dev * rtwdev,u8 path,u8 action)2579 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
2580 {
2581 u16 dpk_cmd;
2582 u8 result = 0;
2583
2584 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
2585
2586 if (action == RTW_DPK_CAL_PWR) {
2587 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
2588 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
2589 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2590 msleep(10);
2591 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
2592 result = 1;
2593 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2594 }
2595 } else {
2596 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2597 0x8 | (path << 1));
2598 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2599
2600 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
2601 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
2602 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
2603 msleep(10);
2604 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
2605 result = 1;
2606 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2607 }
2608 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2609 0x8 | (path << 1));
2610 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2611 }
2612
2613 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
2614
2615 rtw_write8(rtwdev, 0x1b10, 0x0);
2616
2617 return result;
2618 }
2619
rtw8822c_dpk_dgain_read(struct rtw_dev * rtwdev,u8 path)2620 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
2621 {
2622 u16 dgain;
2623
2624 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2625 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
2626
2627 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2628
2629 return dgain;
2630 }
2631
rtw8822c_dpk_thermal_read(struct rtw_dev * rtwdev,u8 path)2632 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
2633 {
2634 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2635 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
2636 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2637 udelay(15);
2638
2639 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
2640 }
2641
rtw8822c_dpk_pas_read(struct rtw_dev * rtwdev,u8 path)2642 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
2643 {
2644 u32 i_val, q_val;
2645
2646 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2647 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2648 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
2649 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2650 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
2651
2652 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
2653 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
2654
2655 if (i_val & BIT(15))
2656 i_val = 0x10000 - i_val;
2657 if (q_val & BIT(15))
2658 q_val = 0x10000 - q_val;
2659
2660 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2661
2662 return i_val * i_val + q_val * q_val;
2663 }
2664
rtw8822c_psd_log2base(u32 val)2665 static u32 rtw8822c_psd_log2base(u32 val)
2666 {
2667 u32 tmp, val_integerd_b, tindex;
2668 u32 result, val_fractiond_b;
2669 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
2670 151, 132, 115, 100, 86, 74, 62, 51,
2671 42, 32, 23, 15, 7, 0};
2672
2673 if (val == 0)
2674 return 0;
2675
2676 val_integerd_b = __fls(val) + 1;
2677
2678 tmp = (val * 100) / (1 << val_integerd_b);
2679 tindex = tmp / 5;
2680
2681 if (tindex >= ARRAY_SIZE(table_fraction))
2682 tindex = ARRAY_SIZE(table_fraction) - 1;
2683
2684 val_fractiond_b = table_fraction[tindex];
2685
2686 result = val_integerd_b * 100 - val_fractiond_b;
2687
2688 return result;
2689 }
2690
rtw8822c_dpk_gainloss_result(struct rtw_dev * rtwdev,u8 path)2691 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
2692 {
2693 u8 result;
2694
2695 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2696 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
2697 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
2698
2699 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
2700
2701 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2702
2703 return result;
2704 }
2705
rtw8822c_dpk_agc_gain_chk(struct rtw_dev * rtwdev,u8 path,u8 limited_pga)2706 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
2707 u8 limited_pga)
2708 {
2709 u8 result = 0;
2710 u16 dgain;
2711
2712 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2713 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
2714
2715 if (dgain > 1535 && !limited_pga)
2716 return RTW_DPK_GAIN_LESS;
2717 else if (dgain < 768 && !limited_pga)
2718 return RTW_DPK_GAIN_LARGE;
2719 else
2720 return result;
2721 }
2722
rtw8822c_dpk_agc_loss_chk(struct rtw_dev * rtwdev,u8 path)2723 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
2724 {
2725 u32 loss, loss_db;
2726
2727 loss = rtw8822c_dpk_pas_read(rtwdev, path);
2728 if (loss < 0x4000000)
2729 return RTW_DPK_GL_LESS;
2730 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870;
2731
2732 if (loss_db > 1000)
2733 return RTW_DPK_GL_LARGE;
2734 else if (loss_db < 250)
2735 return RTW_DPK_GL_LESS;
2736 else
2737 return RTW_DPK_AGC_OUT;
2738 }
2739
2740 struct rtw8822c_dpk_data {
2741 u8 txbb;
2742 u8 pga;
2743 u8 limited_pga;
2744 u8 agc_cnt;
2745 bool loss_only;
2746 bool gain_only;
2747 u8 path;
2748 };
2749
rtw8822c_gain_check_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data)2750 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
2751 struct rtw8822c_dpk_data *data)
2752 {
2753 u8 state;
2754
2755 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
2756 BIT_GAIN_TXBB);
2757 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
2758 BIT_RXAGC);
2759
2760 if (data->loss_only) {
2761 state = RTW_DPK_LOSS_CHECK;
2762 goto check_end;
2763 }
2764
2765 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
2766 data->limited_pga);
2767 if (state == RTW_DPK_GAIN_CHECK && data->gain_only)
2768 state = RTW_DPK_AGC_OUT;
2769 else if (state == RTW_DPK_GAIN_CHECK)
2770 state = RTW_DPK_LOSS_CHECK;
2771
2772 check_end:
2773 data->agc_cnt++;
2774 if (data->agc_cnt >= 6)
2775 state = RTW_DPK_AGC_OUT;
2776
2777 return state;
2778 }
2779
rtw8822c_gain_large_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data)2780 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
2781 struct rtw8822c_dpk_data *data)
2782 {
2783 u8 pga = data->pga;
2784
2785 if (pga > 0xe)
2786 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2787 else if (pga > 0xb && pga < 0xf)
2788 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
2789 else if (pga < 0xc)
2790 data->limited_pga = 1;
2791
2792 return RTW_DPK_GAIN_CHECK;
2793 }
2794
rtw8822c_gain_less_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data)2795 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
2796 struct rtw8822c_dpk_data *data)
2797 {
2798 u8 pga = data->pga;
2799
2800 if (pga < 0xc)
2801 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2802 else if (pga > 0xb && pga < 0xf)
2803 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2804 else if (pga > 0xe)
2805 data->limited_pga = 1;
2806
2807 return RTW_DPK_GAIN_CHECK;
2808 }
2809
rtw8822c_gl_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data,u8 is_large)2810 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
2811 struct rtw8822c_dpk_data *data, u8 is_large)
2812 {
2813 u8 txbb_bound[] = {0x1f, 0};
2814
2815 if (data->txbb == txbb_bound[is_large])
2816 return RTW_DPK_AGC_OUT;
2817
2818 if (is_large == 1)
2819 data->txbb -= 2;
2820 else
2821 data->txbb += 3;
2822
2823 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
2824 data->limited_pga = 0;
2825
2826 return RTW_DPK_GAIN_CHECK;
2827 }
2828
rtw8822c_gl_large_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data)2829 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
2830 struct rtw8822c_dpk_data *data)
2831 {
2832 return rtw8822c_gl_state(rtwdev, data, 1);
2833 }
2834
rtw8822c_gl_less_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data)2835 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
2836 struct rtw8822c_dpk_data *data)
2837 {
2838 return rtw8822c_gl_state(rtwdev, data, 0);
2839 }
2840
rtw8822c_loss_check_state(struct rtw_dev * rtwdev,struct rtw8822c_dpk_data * data)2841 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
2842 struct rtw8822c_dpk_data *data)
2843 {
2844 u8 path = data->path;
2845 u8 state;
2846
2847 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
2848 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
2849
2850 return state;
2851 }
2852
2853 static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
2854 struct rtw8822c_dpk_data *data) = {
2855 rtw8822c_gain_check_state, rtw8822c_gain_large_state,
2856 rtw8822c_gain_less_state, rtw8822c_gl_large_state,
2857 rtw8822c_gl_less_state, rtw8822c_loss_check_state };
2858
rtw8822c_dpk_pas_agc(struct rtw_dev * rtwdev,u8 path,bool gain_only,bool loss_only)2859 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
2860 bool gain_only, bool loss_only)
2861 {
2862 struct rtw8822c_dpk_data data = {0};
2863 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
2864 u8 state = RTW_DPK_GAIN_CHECK;
2865
2866 data.loss_only = loss_only;
2867 data.gain_only = gain_only;
2868 data.path = path;
2869
2870 for (;;) {
2871 func = dpk_state[state];
2872 state = func(rtwdev, &data);
2873 if (state == RTW_DPK_AGC_OUT)
2874 break;
2875 }
2876
2877 return data.txbb;
2878 }
2879
rtw8822c_dpk_coef_iq_check(struct rtw_dev * rtwdev,u16 coef_i,u16 coef_q)2880 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
2881 u16 coef_i, u16 coef_q)
2882 {
2883 if (coef_i == 0x1000 || coef_i == 0x0fff ||
2884 coef_q == 0x1000 || coef_q == 0x0fff)
2885 return true;
2886
2887 return false;
2888 }
2889
rtw8822c_dpk_coef_transfer(struct rtw_dev * rtwdev)2890 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
2891 {
2892 u32 reg = 0;
2893 u16 coef_i = 0, coef_q = 0;
2894
2895 reg = rtw_read32(rtwdev, REG_STAT_RPT);
2896
2897 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
2898 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
2899
2900 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
2901
2902 reg = (coef_i << 16) | coef_q;
2903
2904 return reg;
2905 }
2906
2907 static const u32 rtw8822c_dpk_get_coef_tbl[] = {
2908 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
2909 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
2910 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
2911 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
2912 };
2913
rtw8822c_dpk_coef_tbl_apply(struct rtw_dev * rtwdev,u8 path)2914 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
2915 {
2916 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2917 int i;
2918
2919 for (i = 0; i < 20; i++) {
2920 rtw_write32(rtwdev, REG_RXSRAM_CTL,
2921 rtw8822c_dpk_get_coef_tbl[i]);
2922 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
2923 }
2924 }
2925
rtw8822c_dpk_get_coef(struct rtw_dev * rtwdev,u8 path)2926 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
2927 {
2928 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2929
2930 if (path == RF_PATH_A) {
2931 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
2932 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
2933 } else if (path == RF_PATH_B) {
2934 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
2935 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
2936 }
2937
2938 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
2939 }
2940
rtw8822c_dpk_coef_read(struct rtw_dev * rtwdev,u8 path)2941 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
2942 {
2943 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2944 u8 addr, result = 1;
2945 u16 coef_i, coef_q;
2946
2947 for (addr = 0; addr < 20; addr++) {
2948 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
2949 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
2950
2951 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
2952 result = 0;
2953 break;
2954 }
2955 }
2956 return result;
2957 }
2958
rtw8822c_dpk_coef_write(struct rtw_dev * rtwdev,u8 path,u8 result)2959 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
2960 {
2961 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2962 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64};
2963 u32 coef;
2964 u8 addr;
2965
2966 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2967 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2968
2969 for (addr = 0; addr < 20; addr++) {
2970 if (result == 0) {
2971 if (addr == 3)
2972 coef = 0x04001fff;
2973 else
2974 coef = 0x00001fff;
2975 } else {
2976 coef = dpk_info->coef[path][addr];
2977 }
2978 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
2979 }
2980 }
2981
rtw8822c_dpk_fill_result(struct rtw_dev * rtwdev,u32 dpk_txagc,u8 path,u8 result)2982 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
2983 u8 path, u8 result)
2984 {
2985 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2986
2987 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2988
2989 if (result)
2990 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
2991 else
2992 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
2993
2994 dpk_info->result[path] = result;
2995 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
2996
2997 rtw8822c_dpk_coef_write(rtwdev, path, result);
2998 }
2999
rtw8822c_dpk_gainloss(struct rtw_dev * rtwdev,u8 path)3000 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
3001 {
3002 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3003 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2;
3004
3005 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
3006 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
3007
3008 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3009 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3010 rtw8822c_dpk_dgain_read(rtwdev, path);
3011
3012 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
3013 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3014 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3015 rtw8822c_dpk_dc_corr_check(rtwdev, path);
3016 }
3017
3018 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
3019 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
3020 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
3021
3022 if (tx_bb < tx_agc_search)
3023 tx_bb = 0;
3024 else
3025 tx_bb = tx_bb - tx_agc_search;
3026
3027 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
3028
3029 tx_agc = ori_txagc - (ori_txbb - tx_bb);
3030
3031 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
3032
3033 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
3034
3035 return tx_agc;
3036 }
3037
rtw8822c_dpk_by_path(struct rtw_dev * rtwdev,u32 tx_agc,u8 path)3038 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
3039 {
3040 u8 result;
3041
3042 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
3043
3044 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3045
3046 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
3047
3048 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3049
3050 rtw8822c_dpk_get_coef(rtwdev, path);
3051
3052 return result;
3053 }
3054
rtw8822c_dpk_cal_gs(struct rtw_dev * rtwdev,u8 path)3055 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
3056 {
3057 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3058 u32 tmp_gs = 0;
3059
3060 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3061 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3062 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3063 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3064 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3065 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3066 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3067
3068 if (path == RF_PATH_A) {
3069 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3070 0x1066680);
3071 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3072 } else {
3073 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3074 0x1066680);
3075 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3076 }
3077
3078 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) {
3079 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3080 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3081 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3082 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3083 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3084 rtw_write32(rtwdev, REG_DPD_CTL15,
3085 0x05020000 | (BIT(path) << 28));
3086 } else {
3087 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3088 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3089 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3090 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3091 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3092 rtw_write32(rtwdev, REG_DPD_CTL15,
3093 0x05020008 | (BIT(path) << 28));
3094 }
3095
3096 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3097
3098 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
3099
3100 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3101 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3102 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3103 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3104 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3105
3106 if (path == RF_PATH_A)
3107 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3108 else
3109 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3110
3111 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3112
3113 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
3114 tmp_gs = (tmp_gs * 910) >> 10;
3115 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10);
3116
3117 if (path == RF_PATH_A)
3118 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
3119 else
3120 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
3121
3122 dpk_info->dpk_gs[path] = tmp_gs;
3123 }
3124
rtw8822c_dpk_cal_coef1(struct rtw_dev * rtwdev)3125 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
3126 {
3127 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3128 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58};
3129 u32 i_scaling;
3130 u8 path;
3131
3132 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3133 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3134 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3135 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
3136
3137 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
3138
3139 rtw_write8(rtwdev, 0x1b10, 0x0);
3140 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3141
3142 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3143 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
3144
3145 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
3146 i_scaling);
3147 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3148 GENMASK(31, 28), 0x9);
3149 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3150 GENMASK(31, 28), 0x1);
3151 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
3152 GENMASK(31, 28), 0x0);
3153 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
3154 BIT(14), 0x0);
3155 }
3156 }
3157
rtw8822c_dpk_on(struct rtw_dev * rtwdev,u8 path)3158 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
3159 {
3160 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3161
3162 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3163
3164 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3165 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3166
3167 if (test_bit(path, dpk_info->dpk_path_ok))
3168 rtw8822c_dpk_cal_gs(rtwdev, path);
3169 }
3170
rtw8822c_dpk_check_pass(struct rtw_dev * rtwdev,bool is_fail,u32 dpk_txagc,u8 path)3171 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
3172 u32 dpk_txagc, u8 path)
3173 {
3174 bool result;
3175
3176 if (!is_fail) {
3177 if (rtw8822c_dpk_coef_read(rtwdev, path))
3178 result = true;
3179 else
3180 result = false;
3181 } else {
3182 result = false;
3183 }
3184
3185 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
3186
3187 return result;
3188 }
3189
rtw8822c_dpk_result_reset(struct rtw_dev * rtwdev)3190 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
3191 {
3192 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3193 u8 path;
3194
3195 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3196 clear_bit(path, dpk_info->dpk_path_ok);
3197 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3198 0x8 | (path << 1));
3199 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
3200
3201 dpk_info->dpk_txagc[path] = 0;
3202 dpk_info->result[path] = 0;
3203 dpk_info->dpk_gs[path] = 0x5b;
3204 dpk_info->pre_pwsf[path] = 0;
3205 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
3206 path);
3207 }
3208 }
3209
rtw8822c_dpk_calibrate(struct rtw_dev * rtwdev,u8 path)3210 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
3211 {
3212 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3213 u32 dpk_txagc;
3214 u8 dpk_fail;
3215
3216 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
3217
3218 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
3219
3220 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
3221
3222 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
3223 rtw_err(rtwdev, "failed to do dpk calibration\n");
3224
3225 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
3226
3227 if (dpk_info->result[path])
3228 set_bit(path, dpk_info->dpk_path_ok);
3229 }
3230
rtw8822c_dpk_path_select(struct rtw_dev * rtwdev)3231 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
3232 {
3233 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
3234 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
3235 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
3236 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
3237 rtw8822c_dpk_cal_coef1(rtwdev);
3238 }
3239
rtw8822c_dpk_enable_disable(struct rtw_dev * rtwdev)3240 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
3241 {
3242 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3243 u32 mask = BIT(15) | BIT(14);
3244
3245 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3246
3247 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
3248 dpk_info->is_dpk_pwr_on);
3249 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
3250 dpk_info->is_dpk_pwr_on);
3251
3252 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) {
3253 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
3254 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
3255 }
3256 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) {
3257 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
3258 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
3259 }
3260 }
3261
rtw8822c_dpk_reload_data(struct rtw_dev * rtwdev)3262 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
3263 {
3264 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3265 u8 path;
3266
3267 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) &&
3268 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) &&
3269 dpk_info->dpk_ch == 0)
3270 return;
3271
3272 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3273 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3274 0x8 | (path << 1));
3275 if (dpk_info->dpk_band == RTW_BAND_2G)
3276 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
3277 else
3278 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
3279
3280 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
3281
3282 rtw8822c_dpk_coef_write(rtwdev, path,
3283 test_bit(path, dpk_info->dpk_path_ok));
3284
3285 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3286
3287 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3288
3289 if (path == RF_PATH_A)
3290 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3291 dpk_info->dpk_gs[path]);
3292 else
3293 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3294 dpk_info->dpk_gs[path]);
3295 }
3296 rtw8822c_dpk_cal_coef1(rtwdev);
3297 }
3298
rtw8822c_dpk_reload(struct rtw_dev * rtwdev)3299 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
3300 {
3301 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3302 u8 channel;
3303
3304 dpk_info->is_reload = false;
3305
3306 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
3307
3308 if (channel == dpk_info->dpk_ch) {
3309 rtw_dbg(rtwdev, RTW_DBG_RFK,
3310 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch);
3311 rtw8822c_dpk_reload_data(rtwdev);
3312 dpk_info->is_reload = true;
3313 }
3314
3315 return dpk_info->is_reload;
3316 }
3317
rtw8822c_do_dpk(struct rtw_dev * rtwdev)3318 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
3319 {
3320 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3321 struct rtw_backup_info bckp[DPK_BB_REG_NUM];
3322 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM];
3323 u32 bb_reg[DPK_BB_REG_NUM] = {
3324 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864,
3325 0x4164, 0x180c, 0x410c, 0x186c, 0x416c,
3326 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4};
3327 u32 rf_reg[DPK_RF_REG_NUM] = {
3328 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde};
3329 u8 path;
3330
3331 if (!dpk_info->is_dpk_pwr_on) {
3332 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
3333 return;
3334 } else if (rtw8822c_dpk_reload(rtwdev)) {
3335 return;
3336 }
3337
3338 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++)
3339 ewma_thermal_init(&dpk_info->avg_thermal[path]);
3340
3341 rtw8822c_dpk_information(rtwdev);
3342
3343 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
3344 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3345
3346 rtw8822c_dpk_mac_bb_setting(rtwdev);
3347 rtw8822c_dpk_afe_setting(rtwdev, true);
3348 rtw8822c_dpk_pre_setting(rtwdev);
3349 rtw8822c_dpk_result_reset(rtwdev);
3350 rtw8822c_dpk_path_select(rtwdev);
3351 rtw8822c_dpk_afe_setting(rtwdev, false);
3352 rtw8822c_dpk_enable_disable(rtwdev);
3353
3354 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3355 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
3356 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3357 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
3358 }
3359
rtw8822c_phy_calibration(struct rtw_dev * rtwdev)3360 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
3361 {
3362 rtw8822c_do_iqk(rtwdev);
3363 rtw8822c_do_dpk(rtwdev);
3364 }
3365
rtw8822c_dpk_track(struct rtw_dev * rtwdev)3366 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
3367 {
3368 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3369 u8 path;
3370 u8 thermal_value[DPK_RF_PATH_NUM] = {0};
3371 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM];
3372
3373 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
3374 return;
3375
3376 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
3377 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
3378 ewma_thermal_add(&dpk_info->avg_thermal[path],
3379 thermal_value[path]);
3380 thermal_value[path] =
3381 ewma_thermal_read(&dpk_info->avg_thermal[path]);
3382 delta_dpk[path] = dpk_info->thermal_dpk[path] -
3383 thermal_value[path];
3384 offset[path] = delta_dpk[path] -
3385 dpk_info->thermal_dpk_delta[path];
3386 offset[path] &= 0x7f;
3387
3388 if (offset[path] != dpk_info->pre_pwsf[path]) {
3389 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3390 0x8 | (path << 1));
3391 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
3392 offset[path]);
3393 dpk_info->pre_pwsf[path] = offset[path];
3394 }
3395 }
3396 }
3397
3398 static const struct rtw_phy_cck_pd_reg
3399 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = {
3400 {
3401 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
3402 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
3403 },
3404 {
3405 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
3406 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
3407 },
3408 };
3409
3410 #define RTW_CCK_PD_MAX 255
3411 #define RTW_CCK_CS_MAX 31
3412 #define RTW_CCK_CS_ERR1 27
3413 #define RTW_CCK_CS_ERR2 29
3414 static void
rtw8822c_phy_cck_pd_set_reg(struct rtw_dev * rtwdev,s8 pd_diff,s8 cs_diff,u8 bw,u8 nrx)3415 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
3416 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx)
3417 {
3418 u32 pd, cs;
3419
3420 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX))
3421 return;
3422
3423 pd = rtw_read32_mask(rtwdev,
3424 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3425 rtw8822c_cck_pd_reg[bw][nrx].mask_pd);
3426 cs = rtw_read32_mask(rtwdev,
3427 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3428 rtw8822c_cck_pd_reg[bw][nrx].mask_cs);
3429 pd += pd_diff;
3430 cs += cs_diff;
3431 if (pd > RTW_CCK_PD_MAX)
3432 pd = RTW_CCK_PD_MAX;
3433 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2)
3434 cs++;
3435 else if (cs > RTW_CCK_CS_MAX)
3436 cs = RTW_CCK_CS_MAX;
3437 rtw_write32_mask(rtwdev,
3438 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3439 rtw8822c_cck_pd_reg[bw][nrx].mask_pd,
3440 pd);
3441 rtw_write32_mask(rtwdev,
3442 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3443 rtw8822c_cck_pd_reg[bw][nrx].mask_cs,
3444 cs);
3445 }
3446
rtw8822c_phy_cck_pd_set(struct rtw_dev * rtwdev,u8 new_lvl)3447 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
3448 {
3449 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3450 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8};
3451 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4};
3452 u8 cur_lvl;
3453 u8 nrx, bw;
3454
3455 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
3456 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
3457
3458 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
3459 return;
3460
3461 cur_lvl = dm_info->cck_pd_lv[bw][nrx];
3462
3463 /* update cck pd info */
3464 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
3465
3466 rtw8822c_phy_cck_pd_set_reg(rtwdev,
3467 pd_lvl[new_lvl] - pd_lvl[cur_lvl],
3468 cs_lvl[new_lvl] - cs_lvl[cur_lvl],
3469 bw, nrx);
3470 dm_info->cck_pd_lv[bw][nrx] = new_lvl;
3471 }
3472
3473 #define PWR_TRACK_MASK 0x7f
rtw8822c_pwrtrack_set(struct rtw_dev * rtwdev,u8 rf_path)3474 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path)
3475 {
3476 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3477
3478 switch (rf_path) {
3479 case RF_PATH_A:
3480 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
3481 dm_info->delta_power_index[rf_path]);
3482 break;
3483 case RF_PATH_B:
3484 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
3485 dm_info->delta_power_index[rf_path]);
3486 break;
3487 default:
3488 break;
3489 }
3490 }
3491
rtw8822c_pwr_track_path(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table,u8 path)3492 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev,
3493 struct rtw_swing_table *swing_table,
3494 u8 path)
3495 {
3496 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3497 u8 thermal_value, delta;
3498
3499 if (rtwdev->efuse.thermal_meter[path] == 0xff)
3500 return;
3501
3502 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
3503
3504 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
3505
3506 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
3507
3508 dm_info->delta_power_index[path] =
3509 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
3510 delta);
3511
3512 rtw8822c_pwrtrack_set(rtwdev, path);
3513 }
3514
__rtw8822c_pwr_track(struct rtw_dev * rtwdev)3515 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3516 {
3517 struct rtw_swing_table swing_table;
3518 u8 i;
3519
3520 rtw_phy_config_swing_table(rtwdev, &swing_table);
3521
3522 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
3523 rtw8822c_pwr_track_path(rtwdev, &swing_table, i);
3524
3525 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
3526 rtw8822c_do_iqk(rtwdev);
3527 }
3528
rtw8822c_pwr_track(struct rtw_dev * rtwdev)3529 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev)
3530 {
3531 struct rtw_efuse *efuse = &rtwdev->efuse;
3532 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3533
3534 if (efuse->power_track_type != 0)
3535 return;
3536
3537 if (!dm_info->pwr_trk_triggered) {
3538 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3539 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
3540 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
3541
3542 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3543 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
3544 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
3545
3546 dm_info->pwr_trk_triggered = true;
3547 return;
3548 }
3549
3550 __rtw8822c_pwr_track(rtwdev);
3551 dm_info->pwr_trk_triggered = false;
3552 }
3553
3554 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
3555 {0x0086,
3556 RTW_PWR_CUT_ALL_MSK,
3557 RTW_PWR_INTF_SDIO_MSK,
3558 RTW_PWR_ADDR_SDIO,
3559 RTW_PWR_CMD_WRITE, BIT(0), 0},
3560 {0x0086,
3561 RTW_PWR_CUT_ALL_MSK,
3562 RTW_PWR_INTF_SDIO_MSK,
3563 RTW_PWR_ADDR_SDIO,
3564 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3565 {0x002E,
3566 RTW_PWR_CUT_ALL_MSK,
3567 RTW_PWR_INTF_ALL_MSK,
3568 RTW_PWR_ADDR_MAC,
3569 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3570 {0x002D,
3571 RTW_PWR_CUT_ALL_MSK,
3572 RTW_PWR_INTF_ALL_MSK,
3573 RTW_PWR_ADDR_MAC,
3574 RTW_PWR_CMD_WRITE, BIT(0), 0},
3575 {0x007F,
3576 RTW_PWR_CUT_ALL_MSK,
3577 RTW_PWR_INTF_ALL_MSK,
3578 RTW_PWR_ADDR_MAC,
3579 RTW_PWR_CMD_WRITE, BIT(7), 0},
3580 {0x004A,
3581 RTW_PWR_CUT_ALL_MSK,
3582 RTW_PWR_INTF_USB_MSK,
3583 RTW_PWR_ADDR_MAC,
3584 RTW_PWR_CMD_WRITE, BIT(0), 0},
3585 {0x0005,
3586 RTW_PWR_CUT_ALL_MSK,
3587 RTW_PWR_INTF_ALL_MSK,
3588 RTW_PWR_ADDR_MAC,
3589 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
3590 {0xFFFF,
3591 RTW_PWR_CUT_ALL_MSK,
3592 RTW_PWR_INTF_ALL_MSK,
3593 0,
3594 RTW_PWR_CMD_END, 0, 0},
3595 };
3596
3597 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = {
3598 {0x0000,
3599 RTW_PWR_CUT_ALL_MSK,
3600 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3601 RTW_PWR_ADDR_MAC,
3602 RTW_PWR_CMD_WRITE, BIT(5), 0},
3603 {0x0005,
3604 RTW_PWR_CUT_ALL_MSK,
3605 RTW_PWR_INTF_ALL_MSK,
3606 RTW_PWR_ADDR_MAC,
3607 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
3608 {0x0075,
3609 RTW_PWR_CUT_ALL_MSK,
3610 RTW_PWR_INTF_PCI_MSK,
3611 RTW_PWR_ADDR_MAC,
3612 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3613 {0x0006,
3614 RTW_PWR_CUT_ALL_MSK,
3615 RTW_PWR_INTF_ALL_MSK,
3616 RTW_PWR_ADDR_MAC,
3617 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3618 {0x0075,
3619 RTW_PWR_CUT_ALL_MSK,
3620 RTW_PWR_INTF_PCI_MSK,
3621 RTW_PWR_ADDR_MAC,
3622 RTW_PWR_CMD_WRITE, BIT(0), 0},
3623 {0xFF1A,
3624 RTW_PWR_CUT_ALL_MSK,
3625 RTW_PWR_INTF_USB_MSK,
3626 RTW_PWR_ADDR_MAC,
3627 RTW_PWR_CMD_WRITE, 0xFF, 0},
3628 {0x002E,
3629 RTW_PWR_CUT_ALL_MSK,
3630 RTW_PWR_INTF_ALL_MSK,
3631 RTW_PWR_ADDR_MAC,
3632 RTW_PWR_CMD_WRITE, BIT(3), 0},
3633 {0x0006,
3634 RTW_PWR_CUT_ALL_MSK,
3635 RTW_PWR_INTF_ALL_MSK,
3636 RTW_PWR_ADDR_MAC,
3637 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3638 {0x0005,
3639 RTW_PWR_CUT_ALL_MSK,
3640 RTW_PWR_INTF_ALL_MSK,
3641 RTW_PWR_ADDR_MAC,
3642 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
3643 {0x1018,
3644 RTW_PWR_CUT_ALL_MSK,
3645 RTW_PWR_INTF_ALL_MSK,
3646 RTW_PWR_ADDR_MAC,
3647 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3648 {0x0005,
3649 RTW_PWR_CUT_ALL_MSK,
3650 RTW_PWR_INTF_ALL_MSK,
3651 RTW_PWR_ADDR_MAC,
3652 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3653 {0x0005,
3654 RTW_PWR_CUT_ALL_MSK,
3655 RTW_PWR_INTF_ALL_MSK,
3656 RTW_PWR_ADDR_MAC,
3657 RTW_PWR_CMD_POLLING, BIT(0), 0},
3658 {0x0074,
3659 RTW_PWR_CUT_ALL_MSK,
3660 RTW_PWR_INTF_PCI_MSK,
3661 RTW_PWR_ADDR_MAC,
3662 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3663 {0x0071,
3664 RTW_PWR_CUT_ALL_MSK,
3665 RTW_PWR_INTF_PCI_MSK,
3666 RTW_PWR_ADDR_MAC,
3667 RTW_PWR_CMD_WRITE, BIT(4), 0},
3668 {0x0062,
3669 RTW_PWR_CUT_ALL_MSK,
3670 RTW_PWR_INTF_PCI_MSK,
3671 RTW_PWR_ADDR_MAC,
3672 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
3673 (BIT(7) | BIT(6) | BIT(5))},
3674 {0x0061,
3675 RTW_PWR_CUT_ALL_MSK,
3676 RTW_PWR_INTF_PCI_MSK,
3677 RTW_PWR_ADDR_MAC,
3678 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
3679 {0x001F,
3680 RTW_PWR_CUT_ALL_MSK,
3681 RTW_PWR_INTF_ALL_MSK,
3682 RTW_PWR_ADDR_MAC,
3683 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3684 {0x00EF,
3685 RTW_PWR_CUT_ALL_MSK,
3686 RTW_PWR_INTF_ALL_MSK,
3687 RTW_PWR_ADDR_MAC,
3688 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3689 {0x1045,
3690 RTW_PWR_CUT_ALL_MSK,
3691 RTW_PWR_INTF_ALL_MSK,
3692 RTW_PWR_ADDR_MAC,
3693 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
3694 {0x0010,
3695 RTW_PWR_CUT_ALL_MSK,
3696 RTW_PWR_INTF_ALL_MSK,
3697 RTW_PWR_ADDR_MAC,
3698 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3699 {0x1064,
3700 RTW_PWR_CUT_ALL_MSK,
3701 RTW_PWR_INTF_ALL_MSK,
3702 RTW_PWR_ADDR_MAC,
3703 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
3704 {0xFFFF,
3705 RTW_PWR_CUT_ALL_MSK,
3706 RTW_PWR_INTF_ALL_MSK,
3707 0,
3708 RTW_PWR_CMD_END, 0, 0},
3709 };
3710
3711 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = {
3712 {0x0093,
3713 RTW_PWR_CUT_ALL_MSK,
3714 RTW_PWR_INTF_ALL_MSK,
3715 RTW_PWR_ADDR_MAC,
3716 RTW_PWR_CMD_WRITE, BIT(3), 0},
3717 {0x001F,
3718 RTW_PWR_CUT_ALL_MSK,
3719 RTW_PWR_INTF_ALL_MSK,
3720 RTW_PWR_ADDR_MAC,
3721 RTW_PWR_CMD_WRITE, 0xFF, 0},
3722 {0x00EF,
3723 RTW_PWR_CUT_ALL_MSK,
3724 RTW_PWR_INTF_ALL_MSK,
3725 RTW_PWR_ADDR_MAC,
3726 RTW_PWR_CMD_WRITE, 0xFF, 0},
3727 {0x1045,
3728 RTW_PWR_CUT_ALL_MSK,
3729 RTW_PWR_INTF_ALL_MSK,
3730 RTW_PWR_ADDR_MAC,
3731 RTW_PWR_CMD_WRITE, BIT(4), 0},
3732 {0xFF1A,
3733 RTW_PWR_CUT_ALL_MSK,
3734 RTW_PWR_INTF_USB_MSK,
3735 RTW_PWR_ADDR_MAC,
3736 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
3737 {0x0049,
3738 RTW_PWR_CUT_ALL_MSK,
3739 RTW_PWR_INTF_ALL_MSK,
3740 RTW_PWR_ADDR_MAC,
3741 RTW_PWR_CMD_WRITE, BIT(1), 0},
3742 {0x0006,
3743 RTW_PWR_CUT_ALL_MSK,
3744 RTW_PWR_INTF_ALL_MSK,
3745 RTW_PWR_ADDR_MAC,
3746 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3747 {0x0002,
3748 RTW_PWR_CUT_ALL_MSK,
3749 RTW_PWR_INTF_ALL_MSK,
3750 RTW_PWR_ADDR_MAC,
3751 RTW_PWR_CMD_WRITE, BIT(1), 0},
3752 {0x0005,
3753 RTW_PWR_CUT_ALL_MSK,
3754 RTW_PWR_INTF_ALL_MSK,
3755 RTW_PWR_ADDR_MAC,
3756 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
3757 {0x0005,
3758 RTW_PWR_CUT_ALL_MSK,
3759 RTW_PWR_INTF_ALL_MSK,
3760 RTW_PWR_ADDR_MAC,
3761 RTW_PWR_CMD_POLLING, BIT(1), 0},
3762 {0x0000,
3763 RTW_PWR_CUT_ALL_MSK,
3764 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3765 RTW_PWR_ADDR_MAC,
3766 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3767 {0xFFFF,
3768 RTW_PWR_CUT_ALL_MSK,
3769 RTW_PWR_INTF_ALL_MSK,
3770 0,
3771 RTW_PWR_CMD_END, 0, 0},
3772 };
3773
3774 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = {
3775 {0x0005,
3776 RTW_PWR_CUT_ALL_MSK,
3777 RTW_PWR_INTF_SDIO_MSK,
3778 RTW_PWR_ADDR_MAC,
3779 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
3780 {0x0007,
3781 RTW_PWR_CUT_ALL_MSK,
3782 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3783 RTW_PWR_ADDR_MAC,
3784 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
3785 {0x0067,
3786 RTW_PWR_CUT_ALL_MSK,
3787 RTW_PWR_INTF_ALL_MSK,
3788 RTW_PWR_ADDR_MAC,
3789 RTW_PWR_CMD_WRITE, BIT(5), 0},
3790 {0x004A,
3791 RTW_PWR_CUT_ALL_MSK,
3792 RTW_PWR_INTF_USB_MSK,
3793 RTW_PWR_ADDR_MAC,
3794 RTW_PWR_CMD_WRITE, BIT(0), 0},
3795 {0x0081,
3796 RTW_PWR_CUT_ALL_MSK,
3797 RTW_PWR_INTF_ALL_MSK,
3798 RTW_PWR_ADDR_MAC,
3799 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
3800 {0x0090,
3801 RTW_PWR_CUT_ALL_MSK,
3802 RTW_PWR_INTF_ALL_MSK,
3803 RTW_PWR_ADDR_MAC,
3804 RTW_PWR_CMD_WRITE, BIT(1), 0},
3805 {0x0092,
3806 RTW_PWR_CUT_ALL_MSK,
3807 RTW_PWR_INTF_PCI_MSK,
3808 RTW_PWR_ADDR_MAC,
3809 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
3810 {0x0093,
3811 RTW_PWR_CUT_ALL_MSK,
3812 RTW_PWR_INTF_PCI_MSK,
3813 RTW_PWR_ADDR_MAC,
3814 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
3815 {0x0005,
3816 RTW_PWR_CUT_ALL_MSK,
3817 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3818 RTW_PWR_ADDR_MAC,
3819 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
3820 {0x0005,
3821 RTW_PWR_CUT_ALL_MSK,
3822 RTW_PWR_INTF_PCI_MSK,
3823 RTW_PWR_ADDR_MAC,
3824 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3825 {0x0086,
3826 RTW_PWR_CUT_ALL_MSK,
3827 RTW_PWR_INTF_SDIO_MSK,
3828 RTW_PWR_ADDR_SDIO,
3829 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3830 {0xFFFF,
3831 RTW_PWR_CUT_ALL_MSK,
3832 RTW_PWR_INTF_ALL_MSK,
3833 0,
3834 RTW_PWR_CMD_END, 0, 0},
3835 };
3836
3837 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = {
3838 trans_carddis_to_cardemu_8822c,
3839 trans_cardemu_to_act_8822c,
3840 NULL
3841 };
3842
3843 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = {
3844 trans_act_to_cardemu_8822c,
3845 trans_cardemu_to_carddis_8822c,
3846 NULL
3847 };
3848
3849 static const struct rtw_intf_phy_para usb2_param_8822c[] = {
3850 {0xFFFF, 0x00,
3851 RTW_IP_SEL_PHY,
3852 RTW_INTF_PHY_CUT_ALL,
3853 RTW_INTF_PHY_PLATFORM_ALL},
3854 };
3855
3856 static const struct rtw_intf_phy_para usb3_param_8822c[] = {
3857 {0xFFFF, 0x0000,
3858 RTW_IP_SEL_PHY,
3859 RTW_INTF_PHY_CUT_ALL,
3860 RTW_INTF_PHY_PLATFORM_ALL},
3861 };
3862
3863 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = {
3864 {0xFFFF, 0x0000,
3865 RTW_IP_SEL_PHY,
3866 RTW_INTF_PHY_CUT_ALL,
3867 RTW_INTF_PHY_PLATFORM_ALL},
3868 };
3869
3870 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = {
3871 {0xFFFF, 0x0000,
3872 RTW_IP_SEL_PHY,
3873 RTW_INTF_PHY_CUT_ALL,
3874 RTW_INTF_PHY_PLATFORM_ALL},
3875 };
3876
3877 static const struct rtw_intf_phy_para_table phy_para_table_8822c = {
3878 .usb2_para = usb2_param_8822c,
3879 .usb3_para = usb3_param_8822c,
3880 .gen1_para = pcie_gen1_param_8822c,
3881 .gen2_para = pcie_gen2_param_8822c,
3882 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c),
3883 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c),
3884 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c),
3885 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c),
3886 };
3887
3888 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = {
3889 [0] = RTW_DEF_RFE(8822c, 0, 0),
3890 [1] = RTW_DEF_RFE(8822c, 0, 0),
3891 [2] = RTW_DEF_RFE(8822c, 0, 0),
3892 [5] = RTW_DEF_RFE(8822c, 0, 5),
3893 [6] = RTW_DEF_RFE(8822c, 0, 0),
3894 };
3895
3896 static const struct rtw_hw_reg rtw8822c_dig[] = {
3897 [0] = { .addr = 0x1d70, .mask = 0x7f },
3898 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
3899 };
3900
3901 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = {
3902 .ctrl = LTECOEX_ACCESS_CTRL,
3903 .wdata = LTECOEX_WRITE_DATA,
3904 .rdata = LTECOEX_READ_DATA,
3905 };
3906
3907 static const struct rtw_page_table page_table_8822c[] = {
3908 {64, 64, 64, 64, 1},
3909 {64, 64, 64, 64, 1},
3910 {64, 64, 0, 0, 1},
3911 {64, 64, 64, 0, 1},
3912 {64, 64, 64, 64, 1},
3913 };
3914
3915 static const struct rtw_rqpn rqpn_table_8822c[] = {
3916 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3917 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3918 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3919 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3920 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3921 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3922 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3923 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
3924 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3925 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3926 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3927 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3928 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3929 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3930 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3931 };
3932
3933 static struct rtw_prioq_addrs prioq_addrs_8822c = {
3934 .prio[RTW_DMA_MAPPING_EXTRA] = {
3935 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
3936 },
3937 .prio[RTW_DMA_MAPPING_LOW] = {
3938 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
3939 },
3940 .prio[RTW_DMA_MAPPING_NORMAL] = {
3941 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
3942 },
3943 .prio[RTW_DMA_MAPPING_HIGH] = {
3944 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
3945 },
3946 .wsize = true,
3947 };
3948
3949 static struct rtw_chip_ops rtw8822c_ops = {
3950 .phy_set_param = rtw8822c_phy_set_param,
3951 .read_efuse = rtw8822c_read_efuse,
3952 .query_rx_desc = rtw8822c_query_rx_desc,
3953 .set_channel = rtw8822c_set_channel,
3954 .mac_init = rtw8822c_mac_init,
3955 .read_rf = rtw_phy_read_rf,
3956 .write_rf = rtw_phy_write_rf_reg_mix,
3957 .set_tx_power_index = rtw8822c_set_tx_power_index,
3958 .set_antenna = rtw8822c_set_antenna,
3959 .cfg_ldo25 = rtw8822c_cfg_ldo25,
3960 .false_alarm_statistics = rtw8822c_false_alarm_statistics,
3961 .dpk_track = rtw8822c_dpk_track,
3962 .phy_calibration = rtw8822c_phy_calibration,
3963 .cck_pd_set = rtw8822c_phy_cck_pd_set,
3964 .pwr_track = rtw8822c_pwr_track,
3965 .config_bfee = rtw8822c_bf_config_bfee,
3966 .set_gid_table = rtw_bf_set_gid_table,
3967 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
3968
3969 .coex_set_init = rtw8822c_coex_cfg_init,
3970 .coex_set_ant_switch = NULL,
3971 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix,
3972 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug,
3973 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type,
3974 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power,
3975 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain,
3976 };
3977
3978 /* Shared-Antenna Coex Table */
3979 static const struct coex_table_para table_sant_8822c[] = {
3980 {0xffffffff, 0xffffffff}, /* case-0 */
3981 {0x55555555, 0x55555555},
3982 {0x66555555, 0x66555555},
3983 {0xaaaaaaaa, 0xaaaaaaaa},
3984 {0x5a5a5a5a, 0x5a5a5a5a},
3985 {0xfafafafa, 0xfafafafa}, /* case-5 */
3986 {0x6a5a6a5a, 0xaaaaaaaa},
3987 {0x6a5a56aa, 0x6a5a56aa},
3988 {0x6a5a5a5a, 0x6a5a5a5a},
3989 {0x66555555, 0x5a5a5a5a},
3990 {0x66555555, 0x6a5a5a5a}, /* case-10 */
3991 {0x66555555, 0xfafafafa},
3992 {0x66555555, 0x5a5a5aaa},
3993 {0x66555555, 0x5aaa5aaa},
3994 {0x66555555, 0xaaaa5aaa},
3995 {0x66555555, 0xaaaaaaaa}, /* case-15 */
3996 {0xffff55ff, 0xfafafafa},
3997 {0xffff55ff, 0x6afa5afa},
3998 {0xaaffffaa, 0xfafafafa},
3999 {0xaa5555aa, 0x5a5a5a5a},
4000 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
4001 {0xaa5555aa, 0xaaaaaaaa},
4002 {0xffffffff, 0x5a5a5a5a},
4003 {0xffffffff, 0x6a5a5a5a},
4004 {0xffffffff, 0x55555555},
4005 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
4006 {0x55555555, 0x5a5a5a5a},
4007 {0x55555555, 0xaaaaaaaa},
4008 {0x55555555, 0x6a5a6a5a},
4009 {0x66556655, 0x66556655}
4010 };
4011
4012 /* Non-Shared-Antenna Coex Table */
4013 static const struct coex_table_para table_nsant_8822c[] = {
4014 {0xffffffff, 0xffffffff}, /* case-100 */
4015 {0x55555555, 0x55555555},
4016 {0x66555555, 0x66555555},
4017 {0xaaaaaaaa, 0xaaaaaaaa},
4018 {0x5a5a5a5a, 0x5a5a5a5a},
4019 {0xfafafafa, 0xfafafafa}, /* case-105 */
4020 {0x5afa5afa, 0x5afa5afa},
4021 {0x55555555, 0xfafafafa},
4022 {0x66555555, 0xfafafafa},
4023 {0x66555555, 0x5a5a5a5a},
4024 {0x66555555, 0x6a5a5a5a}, /* case-110 */
4025 {0x66555555, 0xaaaaaaaa},
4026 {0xffff55ff, 0xfafafafa},
4027 {0xffff55ff, 0x5afa5afa},
4028 {0xffff55ff, 0xaaaaaaaa},
4029 {0xaaffffaa, 0xfafafafa}, /* case-115 */
4030 {0xaaffffaa, 0x5afa5afa},
4031 {0xaaffffaa, 0xaaaaaaaa},
4032 {0xffffffff, 0xfafafafa},
4033 {0xffffffff, 0x5afa5afa},
4034 {0xffffffff, 0xaaaaaaaa},/* case-120 */
4035 {0x55ff55ff, 0x5afa5afa},
4036 {0x55ff55ff, 0xaaaaaaaa},
4037 {0x55ff55ff, 0x55ff55ff}
4038 };
4039
4040 /* Shared-Antenna TDMA */
4041 static const struct coex_tdma_para tdma_sant_8822c[] = {
4042 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
4043 { {0x61, 0x45, 0x03, 0x11, 0x11} },
4044 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
4045 { {0x61, 0x30, 0x03, 0x11, 0x11} },
4046 { {0x61, 0x20, 0x03, 0x11, 0x11} },
4047 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
4048 { {0x61, 0x45, 0x03, 0x11, 0x10} },
4049 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
4050 { {0x61, 0x30, 0x03, 0x11, 0x10} },
4051 { {0x61, 0x20, 0x03, 0x11, 0x10} },
4052 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
4053 { {0x61, 0x08, 0x03, 0x11, 0x14} },
4054 { {0x61, 0x08, 0x03, 0x10, 0x14} },
4055 { {0x51, 0x08, 0x03, 0x10, 0x54} },
4056 { {0x51, 0x08, 0x03, 0x10, 0x55} },
4057 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
4058 { {0x51, 0x45, 0x03, 0x10, 0x10} },
4059 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
4060 { {0x51, 0x30, 0x03, 0x10, 0x50} },
4061 { {0x51, 0x20, 0x03, 0x10, 0x50} },
4062 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
4063 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
4064 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
4065 { {0x55, 0x08, 0x03, 0x10, 0x54} },
4066 { {0x65, 0x10, 0x03, 0x11, 0x11} },
4067 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
4068 { {0x51, 0x08, 0x03, 0x10, 0x50} },
4069 { {0x61, 0x08, 0x03, 0x11, 0x11} }
4070 };
4071
4072 /* Non-Shared-Antenna TDMA */
4073 static const struct coex_tdma_para tdma_nsant_8822c[] = {
4074 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
4075 { {0x61, 0x45, 0x03, 0x11, 0x11} },
4076 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
4077 { {0x61, 0x30, 0x03, 0x11, 0x11} },
4078 { {0x61, 0x20, 0x03, 0x11, 0x11} },
4079 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
4080 { {0x61, 0x45, 0x03, 0x11, 0x10} },
4081 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
4082 { {0x61, 0x30, 0x03, 0x11, 0x10} },
4083 { {0x61, 0x20, 0x03, 0x11, 0x10} },
4084 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
4085 { {0x61, 0x08, 0x03, 0x11, 0x14} },
4086 { {0x61, 0x08, 0x03, 0x10, 0x14} },
4087 { {0x51, 0x08, 0x03, 0x10, 0x54} },
4088 { {0x51, 0x08, 0x03, 0x10, 0x55} },
4089 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
4090 { {0x51, 0x45, 0x03, 0x10, 0x50} },
4091 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
4092 { {0x51, 0x30, 0x03, 0x10, 0x50} },
4093 { {0x51, 0x20, 0x03, 0x10, 0x50} },
4094 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */
4095 };
4096
4097 /* rssi in percentage % (dbm = % - 100) */
4098 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};
4099 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};
4100 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
4101
4102 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
4103 static const struct coex_rf_para rf_para_tx_8822c[] = {
4104 {0, 0, false, 7}, /* for normal */
4105 {0, 16, false, 7}, /* for WL-CPT */
4106 {8, 17, true, 4},
4107 {7, 18, true, 4},
4108 {6, 19, true, 4},
4109 {5, 20, true, 4}
4110 };
4111
4112 static const struct coex_rf_para rf_para_rx_8822c[] = {
4113 {0, 0, false, 7}, /* for normal */
4114 {0, 16, false, 7}, /* for WL-CPT */
4115 {3, 24, true, 5},
4116 {2, 26, true, 5},
4117 {1, 27, true, 5},
4118 {0, 28, true, 5}
4119 };
4120
4121 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c));
4122
4123 static const u8
4124 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4125 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
4126 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
4127 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
4128 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
4129 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
4130 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
4131 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
4132 11, 12, 13, 14, 15, 16, 18, 19, 20, 21,
4133 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 },
4134 };
4135
4136 static const u8
4137 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4138 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4139 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4140 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
4141 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4142 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4143 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
4144 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4145 10, 10, 11, 12, 13, 14, 15, 16, 17, 18,
4146 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 },
4147 };
4148
4149 static const u8
4150 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4151 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
4152 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
4153 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
4154 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
4155 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
4156 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
4157 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
4158 11, 13, 14, 15, 16, 17, 18, 19, 20, 21,
4159 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 },
4160 };
4161
4162 static const u8
4163 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
4164 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4165 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
4166 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
4167 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4168 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
4169 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
4170 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4171 10, 11, 12, 13, 14, 15, 16, 17, 18, 20,
4172 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 },
4173 };
4174
4175 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = {
4176 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
4177 9, 9, 10, 11, 12, 13, 14, 15, 15, 16,
4178 17, 18, 19, 20, 20, 21, 22, 23, 24, 25
4179 };
4180
4181 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = {
4182 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4183 10, 11, 12, 13, 14, 14, 15, 16, 17, 18,
4184 19, 20, 21, 22, 23, 24, 25, 26, 27, 28
4185 };
4186
4187 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = {
4188 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
4189 7, 8, 8, 9, 9, 10, 11, 11, 12, 13,
4190 13, 14, 15, 15, 16, 17, 17, 18, 19, 19
4191 };
4192
4193 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = {
4194 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4195 10, 11, 11, 12, 13, 14, 15, 16, 17, 18,
4196 19, 20, 21, 22, 23, 24, 25, 25, 26, 27
4197 };
4198
4199 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = {
4200 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
4201 9, 10, 11, 11, 12, 13, 14, 15, 16, 17,
4202 17, 18, 19, 20, 21, 22, 23, 23, 24, 25
4203 };
4204
4205 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = {
4206 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
4207 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
4208 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
4209 };
4210
4211 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = {
4212 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
4213 8, 9, 9, 10, 11, 12, 12, 13, 14, 15,
4214 15, 16, 17, 18, 18, 19, 20, 21, 21, 22
4215 };
4216
4217 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = {
4218 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
4219 9, 10, 11, 11, 12, 13, 14, 15, 16, 17,
4220 18, 18, 19, 20, 21, 22, 23, 24, 24, 25
4221 };
4222
4223 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = {
4224 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1],
4225 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2],
4226 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3],
4227 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1],
4228 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2],
4229 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3],
4230 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1],
4231 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2],
4232 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3],
4233 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1],
4234 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2],
4235 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3],
4236 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n,
4237 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p,
4238 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n,
4239 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p,
4240 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n,
4241 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p,
4242 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n,
4243 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p,
4244 };
4245
4246 #ifdef CONFIG_PM
4247 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = {
4248 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE |
4249 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY |
4250 WIPHY_WOWLAN_NET_DETECT,
4251 .n_patterns = RTW_MAX_PATTERN_NUM,
4252 .pattern_max_len = RTW_MAX_PATTERN_SIZE,
4253 .pattern_min_len = 1,
4254 .max_nd_match_sets = 4,
4255 };
4256 #endif
4257
4258 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = {
4259 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8},
4260 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8},
4261 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8},
4262 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32},
4263 {0, 0, RTW_REG_DOMAIN_NL},
4264 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
4265 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
4266 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
4267 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
4268 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
4269 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
4270 {0, 0, RTW_REG_DOMAIN_NL},
4271 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
4272 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
4273 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
4274 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
4275 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
4276 {0, 0, RTW_REG_DOMAIN_NL},
4277 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
4278 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
4279 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
4280 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
4281 };
4282
4283 struct rtw_chip_info rtw8822c_hw_spec = {
4284 .ops = &rtw8822c_ops,
4285 .id = RTW_CHIP_TYPE_8822C,
4286 .fw_name = "rtw88/rtw8822c_fw.bin",
4287 .wlan_cpu = RTW_WCPU_11AC,
4288 .tx_pkt_desc_sz = 48,
4289 .tx_buf_desc_sz = 16,
4290 .rx_pkt_desc_sz = 24,
4291 .rx_buf_desc_sz = 8,
4292 .phy_efuse_size = 512,
4293 .log_efuse_size = 768,
4294 .ptct_efuse_size = 124,
4295 .txff_size = 262144,
4296 .rxff_size = 24576,
4297 .fw_rxff_size = 12288,
4298 .txgi_factor = 2,
4299 .is_pwr_by_rate_dec = false,
4300 .max_power_index = 0x7f,
4301 .csi_buf_pg_num = 50,
4302 .band = RTW_BAND_2G | RTW_BAND_5G,
4303 .page_size = 128,
4304 .dig_min = 0x20,
4305 .ht_supported = true,
4306 .vht_supported = true,
4307 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG),
4308 .sys_func_en = 0xD8,
4309 .pwr_on_seq = card_enable_flow_8822c,
4310 .pwr_off_seq = card_disable_flow_8822c,
4311 .page_table = page_table_8822c,
4312 .rqpn_table = rqpn_table_8822c,
4313 .prioq_addrs = &prioq_addrs_8822c,
4314 .intf_table = &phy_para_table_8822c,
4315 .dig = rtw8822c_dig,
4316 .dig_cck = NULL,
4317 .rf_base_addr = {0x3c00, 0x4c00},
4318 .rf_sipi_addr = {0x1808, 0x4108},
4319 .ltecoex_addr = &rtw8822c_ltecoex_addr,
4320 .mac_tbl = &rtw8822c_mac_tbl,
4321 .agc_tbl = &rtw8822c_agc_tbl,
4322 .bb_tbl = &rtw8822c_bb_tbl,
4323 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl,
4324 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl},
4325 .rfe_defs = rtw8822c_rfe_defs,
4326 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
4327 .en_dis_dpd = true,
4328 .dpd_ratemask = DIS_DPD_RATEALL,
4329 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl,
4330 .iqk_threshold = 8,
4331 .bfer_su_max_num = 2,
4332 .bfer_mu_max_num = 1,
4333 .rx_ldpc = true,
4334
4335 #ifdef CONFIG_PM
4336 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin",
4337 .wowlan_stub = &rtw_wowlan_stub_8822c,
4338 .max_sched_scan_ssids = 4,
4339 #endif
4340 .coex_para_ver = 0x20070217,
4341 .bt_desired_ver = 0x17,
4342 .scbd_support = true,
4343 .new_scbd10_def = true,
4344 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
4345 .bt_rssi_type = COEX_BTRSSI_DBM,
4346 .ant_isolation = 15,
4347 .rssi_tolerance = 2,
4348 .wl_rssi_step = wl_rssi_step_8822c,
4349 .bt_rssi_step = bt_rssi_step_8822c,
4350 .table_sant_num = ARRAY_SIZE(table_sant_8822c),
4351 .table_sant = table_sant_8822c,
4352 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c),
4353 .table_nsant = table_nsant_8822c,
4354 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c),
4355 .tdma_sant = tdma_sant_8822c,
4356 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c),
4357 .tdma_nsant = tdma_nsant_8822c,
4358 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c),
4359 .wl_rf_para_tx = rf_para_tx_8822c,
4360 .wl_rf_para_rx = rf_para_rx_8822c,
4361 .bt_afh_span_bw20 = 0x24,
4362 .bt_afh_span_bw40 = 0x36,
4363 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c),
4364 .afh_5g = afh_5g_8822c,
4365
4366 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c),
4367 .coex_info_hw_regs = coex_info_hw_regs_8822c,
4368
4369 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},
4370 };
4371 EXPORT_SYMBOL(rtw8822c_hw_spec);
4372
4373 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin");
4374 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin");
4375
4376 MODULE_AUTHOR("Realtek Corporation");
4377 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver");
4378 MODULE_LICENSE("Dual BSD/GPL");
4379