1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
7 *
8 * Contact Information: wlanfae <wlanfae@realtek.com>
9 */
10 #include "rtl_core.h"
11 #include "r8192E_phy.h"
12 #include "r8192E_phyreg.h"
13 #include "r8190P_rtl8256.h"
14 #include "r8192E_cmdpkt.h"
15 #include "rtl_dm.h"
16 #include "rtl_wx.h"
17
18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
19 EDCAPARA_VO};
20
_rtl92e_update_msr(struct net_device * dev)21 static void _rtl92e_update_msr(struct net_device *dev)
22 {
23 struct r8192_priv *priv = rtllib_priv(dev);
24 u8 msr;
25
26 msr = rtl92e_readb(dev, MSR);
27 msr &= ~MSR_LINK_MASK;
28
29 switch (priv->rtllib->iw_mode) {
30 case IW_MODE_INFRA:
31 if (priv->rtllib->link_state == MAC80211_LINKED)
32 msr |= MSR_LINK_MANAGED;
33 break;
34 default:
35 break;
36 }
37
38 rtl92e_writeb(dev, MSR, msr);
39 }
40
rtl92e_set_reg(struct net_device * dev,u8 variable,u8 * val)41 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
42 {
43 struct r8192_priv *priv = rtllib_priv(dev);
44
45 switch (variable) {
46 case HW_VAR_BSSID:
47 /* BSSIDR 2 byte alignment */
48 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
49 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
50 break;
51
52 case HW_VAR_MEDIA_STATUS:
53 {
54 enum rt_op_mode op_mode = *((enum rt_op_mode *)(val));
55 u8 btMsr = rtl92e_readb(dev, MSR);
56
57 btMsr &= 0xfc;
58
59 switch (op_mode) {
60 case RT_OP_MODE_INFRASTRUCTURE:
61 btMsr |= MSR_INFRA;
62 break;
63
64 case RT_OP_MODE_IBSS:
65 btMsr |= MSR_ADHOC;
66 break;
67
68 case RT_OP_MODE_AP:
69 btMsr |= MSR_AP;
70 break;
71
72 default:
73 btMsr |= MSR_NOLINK;
74 break;
75 }
76
77 rtl92e_writeb(dev, MSR, btMsr);
78 }
79 break;
80
81 case HW_VAR_CECHK_BSSID:
82 {
83 u32 RegRCR, Type;
84
85 Type = val[0];
86 RegRCR = rtl92e_readl(dev, RCR);
87 priv->receive_config = RegRCR;
88
89 if (Type)
90 RegRCR |= (RCR_CBSSID);
91 else
92 RegRCR &= (~RCR_CBSSID);
93
94 rtl92e_writel(dev, RCR, RegRCR);
95 priv->receive_config = RegRCR;
96 }
97 break;
98
99 case HW_VAR_SLOT_TIME:
100
101 priv->slot_time = val[0];
102 rtl92e_writeb(dev, SLOT_TIME, val[0]);
103
104 break;
105
106 case HW_VAR_ACK_PREAMBLE:
107 {
108 u32 regTmp;
109
110 priv->short_preamble = (bool)*val;
111 regTmp = priv->basic_rate;
112 if (priv->short_preamble)
113 regTmp |= BRSR_AckShortPmb;
114 rtl92e_writel(dev, RRSR, regTmp);
115 break;
116 }
117
118 case HW_VAR_CPU_RST:
119 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
120 break;
121
122 case HW_VAR_AC_PARAM:
123 {
124 u8 pAcParam = *val;
125 u32 eACI = pAcParam;
126 u8 u1bAIFS;
127 u32 u4bAcParam;
128 u8 mode = priv->rtllib->mode;
129 struct rtllib_qos_parameters *qop =
130 &priv->rtllib->current_network.qos_data.parameters;
131
132 u1bAIFS = qop->aifs[pAcParam] *
133 ((mode & (WIRELESS_MODE_G | WIRELESS_MODE_N_24G)) ? 9 : 20) + aSifsTime;
134
135 rtl92e_dm_init_edca_turbo(dev);
136
137 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
138 AC_PARAM_TXOP_LIMIT_OFFSET) |
139 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
140 AC_PARAM_ECW_MAX_OFFSET) |
141 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
142 AC_PARAM_ECW_MIN_OFFSET) |
143 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
144
145 switch (eACI) {
146 case AC1_BK:
147 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
148 break;
149
150 case AC0_BE:
151 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
152 break;
153
154 case AC2_VI:
155 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
156 break;
157
158 case AC3_VO:
159 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
160 break;
161
162 default:
163 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
164 eACI);
165 break;
166 }
167 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
168 &pAcParam);
169 break;
170 }
171
172 case HW_VAR_ACM_CTRL:
173 {
174 struct rtllib_qos_parameters *qos_parameters =
175 &priv->rtllib->current_network.qos_data.parameters;
176 u8 pAcParam = *val;
177 u32 eACI = pAcParam;
178 union aci_aifsn *pAciAifsn = (union aci_aifsn *)&
179 (qos_parameters->aifs[0]);
180 u8 acm = pAciAifsn->f.acm;
181 u8 AcmCtrl = rtl92e_readb(dev, ACM_HW_CTRL);
182
183 if (acm) {
184 switch (eACI) {
185 case AC0_BE:
186 AcmCtrl |= ACM_HW_BEQ_EN;
187 break;
188
189 case AC2_VI:
190 AcmCtrl |= ACM_HW_VIQ_EN;
191 break;
192
193 case AC3_VO:
194 AcmCtrl |= ACM_HW_VOQ_EN;
195 break;
196 }
197 } else {
198 switch (eACI) {
199 case AC0_BE:
200 AcmCtrl &= (~ACM_HW_BEQ_EN);
201 break;
202
203 case AC2_VI:
204 AcmCtrl &= (~ACM_HW_VIQ_EN);
205 break;
206
207 case AC3_VO:
208 AcmCtrl &= (~ACM_HW_BEQ_EN);
209 break;
210
211 default:
212 break;
213 }
214 }
215 rtl92e_writeb(dev, ACM_HW_CTRL, AcmCtrl);
216 break;
217 }
218
219 case HW_VAR_SIFS:
220 rtl92e_writeb(dev, SIFS, val[0]);
221 rtl92e_writeb(dev, SIFS + 1, val[0]);
222 break;
223
224 case HW_VAR_RF_TIMING:
225 {
226 u8 Rf_Timing = *val;
227
228 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
229 break;
230 }
231
232 default:
233 break;
234 }
235 }
236
_rtl92e_read_eeprom_info(struct net_device * dev)237 static void _rtl92e_read_eeprom_info(struct net_device *dev)
238 {
239 struct r8192_priv *priv = rtllib_priv(dev);
240 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
241 u8 tempval;
242 u8 ICVer8192, ICVer8256;
243 u16 i, usValue, IC_Version;
244 u16 EEPROMId;
245
246 EEPROMId = rtl92e_eeprom_read(dev, 0);
247 if (EEPROMId != RTL8190_EEPROM_ID) {
248 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
249 EEPROMId);
250 priv->autoload_fail_flag = true;
251 } else {
252 priv->autoload_fail_flag = false;
253 }
254
255 if (!priv->autoload_fail_flag) {
256 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
257 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
258
259 usValue = rtl92e_eeprom_read(dev,
260 (EEPROM_Customer_ID >> 1)) >> 8;
261 priv->eeprom_customer_id = usValue & 0xff;
262 usValue = rtl92e_eeprom_read(dev,
263 EEPROM_ICVersion_ChannelPlan >> 1);
264 IC_Version = (usValue & 0xff00) >> 8;
265
266 ICVer8192 = IC_Version & 0xf;
267 ICVer8256 = (IC_Version & 0xf0) >> 4;
268 if (ICVer8192 == 0x2) {
269 if (ICVer8256 == 0x5)
270 priv->card_8192_version = VERSION_8190_BE;
271 }
272 switch (priv->card_8192_version) {
273 case VERSION_8190_BD:
274 case VERSION_8190_BE:
275 break;
276 default:
277 priv->card_8192_version = VERSION_8190_BD;
278 break;
279 }
280 } else {
281 priv->card_8192_version = VERSION_8190_BD;
282 priv->eeprom_vid = 0;
283 priv->eeprom_did = 0;
284 priv->eeprom_customer_id = 0;
285 }
286
287 if (!priv->autoload_fail_flag) {
288 u8 addr[ETH_ALEN];
289
290 for (i = 0; i < 6; i += 2) {
291 usValue = rtl92e_eeprom_read(dev,
292 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
293 *(u16 *)(&addr[i]) = usValue;
294 }
295 eth_hw_addr_set(dev, addr);
296 } else {
297 eth_hw_addr_set(dev, bMac_Tmp_Addr);
298 }
299
300 if (priv->card_8192_version > VERSION_8190_BD)
301 priv->tx_pwr_data_read_from_eeprom = true;
302 else
303 priv->tx_pwr_data_read_from_eeprom = false;
304
305 if (priv->card_8192_version > VERSION_8190_BD) {
306 if (!priv->autoload_fail_flag) {
307 tempval = (rtl92e_eeprom_read(dev,
308 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
309 priv->eeprom_legacy_ht_tx_pwr_diff = tempval & 0xf;
310 } else {
311 priv->eeprom_legacy_ht_tx_pwr_diff = 0x04;
312 }
313
314 if (!priv->autoload_fail_flag)
315 priv->eeprom_thermal_meter = ((rtl92e_eeprom_read(dev,
316 (EEPROM_ThermalMeter >> 1))) &
317 0xff00) >> 8;
318 else
319 priv->eeprom_thermal_meter = EEPROM_Default_ThermalMeter;
320 priv->tssi_13dBm = priv->eeprom_thermal_meter * 100;
321
322 if (priv->epromtype == EEPROM_93C46) {
323 if (!priv->autoload_fail_flag) {
324 usValue = rtl92e_eeprom_read(dev,
325 EEPROM_TxPwDiff_CrystalCap >> 1);
326 priv->eeprom_ant_pwr_diff = usValue & 0x0fff;
327 priv->eeprom_crystal_cap = (usValue & 0xf000)
328 >> 12;
329 } else {
330 priv->eeprom_ant_pwr_diff =
331 EEPROM_Default_AntTxPowerDiff;
332 priv->eeprom_crystal_cap =
333 EEPROM_Default_TxPwDiff_CrystalCap;
334 }
335
336 for (i = 0; i < 14; i += 2) {
337 if (!priv->autoload_fail_flag)
338 usValue = rtl92e_eeprom_read(dev,
339 (EEPROM_TxPwIndex_CCK + i) >> 1);
340 else
341 usValue = EEPROM_Default_TxPower;
342 *((u16 *)(&priv->eeprom_tx_pwr_level_cck[i])) =
343 usValue;
344 }
345 for (i = 0; i < 14; i += 2) {
346 if (!priv->autoload_fail_flag)
347 usValue = rtl92e_eeprom_read(dev,
348 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
349 else
350 usValue = EEPROM_Default_TxPower;
351 *((u16 *)(&priv->eeprom_tx_pwr_level_ofdm24g[i]))
352 = usValue;
353 }
354 }
355 if (priv->epromtype == EEPROM_93C46) {
356 for (i = 0; i < 14; i++) {
357 priv->tx_pwr_level_cck[i] =
358 priv->eeprom_tx_pwr_level_cck[i];
359 priv->tx_pwr_level_ofdm_24g[i] =
360 priv->eeprom_tx_pwr_level_ofdm24g[i];
361 }
362 priv->legacy_ht_tx_pwr_diff =
363 priv->eeprom_legacy_ht_tx_pwr_diff;
364 priv->antenna_tx_pwr_diff[0] = priv->eeprom_ant_pwr_diff & 0xf;
365 priv->antenna_tx_pwr_diff[1] = (priv->eeprom_ant_pwr_diff &
366 0xf0) >> 4;
367 priv->antenna_tx_pwr_diff[2] = (priv->eeprom_ant_pwr_diff &
368 0xf00) >> 8;
369 priv->crystal_cap = priv->eeprom_crystal_cap;
370 priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf;
371 priv->thermal_meter[1] = (priv->eeprom_thermal_meter &
372 0xf0) >> 4;
373 } else if (priv->epromtype == EEPROM_93C56) {
374 priv->legacy_ht_tx_pwr_diff =
375 priv->eeprom_legacy_ht_tx_pwr_diff;
376 priv->antenna_tx_pwr_diff[0] = 0;
377 priv->antenna_tx_pwr_diff[1] = 0;
378 priv->antenna_tx_pwr_diff[2] = 0;
379 priv->crystal_cap = priv->eeprom_crystal_cap;
380 priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf;
381 priv->thermal_meter[1] = (priv->eeprom_thermal_meter &
382 0xf0) >> 4;
383 }
384 }
385
386 rtl92e_init_adaptive_rate(dev);
387
388 switch (priv->eeprom_customer_id) {
389 case EEPROM_CID_NetCore:
390 priv->customer_id = RT_CID_819X_NETCORE;
391 break;
392 case EEPROM_CID_TOSHIBA:
393 priv->customer_id = RT_CID_TOSHIBA;
394 break;
395 }
396
397 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
398 priv->rtllib->bSupportRemoteWakeUp = true;
399 else
400 priv->rtllib->bSupportRemoteWakeUp = false;
401 }
402
rtl92e_get_eeprom_size(struct net_device * dev)403 void rtl92e_get_eeprom_size(struct net_device *dev)
404 {
405 u16 curCR;
406 struct r8192_priv *priv = rtllib_priv(dev);
407
408 curCR = rtl92e_readw(dev, EPROM_CMD);
409 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
410 EEPROM_93C46;
411 _rtl92e_read_eeprom_info(dev);
412 }
413
_rtl92e_hwconfig(struct net_device * dev)414 static void _rtl92e_hwconfig(struct net_device *dev)
415 {
416 u32 regRATR = 0, regRRSR = 0;
417 u8 regBwOpMode = 0, regTmp = 0;
418 struct r8192_priv *priv = rtllib_priv(dev);
419
420 switch (priv->rtllib->mode) {
421 case WIRELESS_MODE_B:
422 regBwOpMode = BW_OPMODE_20MHZ;
423 regRATR = RATE_ALL_CCK;
424 regRRSR = RATE_ALL_CCK;
425 break;
426 case WIRELESS_MODE_AUTO:
427 case WIRELESS_MODE_N_24G:
428 regBwOpMode = BW_OPMODE_20MHZ;
429 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
430 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
431 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
432 break;
433 case WIRELESS_MODE_G:
434 default:
435 regBwOpMode = BW_OPMODE_20MHZ;
436 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
437 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
438 break;
439 }
440
441 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
442 {
443 u32 ratr_value;
444
445 ratr_value = regRATR;
446 ratr_value &= ~(RATE_ALL_OFDM_2SS);
447 rtl92e_writel(dev, RATR0, ratr_value);
448 rtl92e_writeb(dev, UFWP, 1);
449 }
450 regTmp = rtl92e_readb(dev, 0x313);
451 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
452 rtl92e_writel(dev, RRSR, regRRSR);
453
454 rtl92e_writew(dev, RETRY_LIMIT,
455 priv->short_retry_limit << RETRY_LIMIT_SHORT_SHIFT |
456 priv->long_retry_limit << RETRY_LIMIT_LONG_SHIFT);
457 }
458
rtl92e_start_adapter(struct net_device * dev)459 bool rtl92e_start_adapter(struct net_device *dev)
460 {
461 struct r8192_priv *priv = rtllib_priv(dev);
462 u32 ulRegRead;
463 bool rtStatus = true;
464 u8 tmpvalue;
465 u8 ICVersion, SwitchingRegulatorOutput;
466 bool bfirmwareok = true;
467 u32 tmpRegA, TempCCk;
468 int i = 0;
469 u32 retry_times = 0;
470
471 priv->being_init_adapter = true;
472
473 start:
474 rtl92e_reset_desc_ring(dev);
475 priv->rf_mode = RF_OP_By_SW_3wire;
476
477 rtl92e_writeb(dev, ANAPAR, 0x37);
478 mdelay(500);
479
480 priv->fw_info->status = FW_STATUS_0_INIT;
481
482 ulRegRead = rtl92e_readl(dev, CPU_GEN);
483 if (priv->fw_info->status == FW_STATUS_0_INIT)
484 ulRegRead |= CPU_GEN_SYSTEM_RESET;
485 else if (priv->fw_info->status == FW_STATUS_5_READY)
486 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
487 else
488 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
489 __func__, priv->fw_info->status);
490
491 rtl92e_writel(dev, CPU_GEN, ulRegRead);
492
493 ICVersion = rtl92e_readb(dev, IC_VERRSION);
494 if (ICVersion >= 0x4) {
495 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
496 if (SwitchingRegulatorOutput != 0xb8) {
497 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
498 mdelay(1);
499 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
500 }
501 }
502 rtStatus = rtl92e_config_bb(dev);
503 if (!rtStatus) {
504 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
505 return rtStatus;
506 }
507
508 priv->loopback_mode = RTL819X_NO_LOOPBACK;
509 ulRegRead = rtl92e_readl(dev, CPU_GEN);
510 if (priv->loopback_mode == RTL819X_NO_LOOPBACK)
511 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
512 CPU_GEN_NO_LOOPBACK_SET;
513 else if (priv->loopback_mode == RTL819X_MAC_LOOPBACK)
514 ulRegRead |= CPU_CCK_LOOPBACK;
515 else
516 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
517 __func__);
518
519 rtl92e_writel(dev, CPU_GEN, ulRegRead);
520
521 udelay(500);
522
523 _rtl92e_hwconfig(dev);
524 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
525
526 rtl92e_writeb(dev, PCIF, ((MXDMA2_NO_LIMIT << MXDMA2_RX_SHIFT) |
527 (MXDMA2_NO_LIMIT << MXDMA2_TX_SHIFT)));
528 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
529 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
530 rtl92e_writel(dev, RCR, priv->receive_config);
531
532 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
533 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
534 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
535 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
536 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
537 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
538 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
539 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
540 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
541 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
542 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
543 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
544 RSVD_FW_QUEUE_PAGE_BCN_SHIFT |
545 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
546 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
547
548 rtl92e_tx_enable(dev);
549 rtl92e_rx_enable(dev);
550 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
551 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
552 rtl92e_writel(dev, RRSR, ulRegRead);
553 rtl92e_writel(dev, RATR0 + 4 * 7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
554
555 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
556
557 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
558 rtl92e_cam_reset(dev);
559 {
560 u8 SECR_value = 0x0;
561
562 SECR_value |= SCR_TxEncEnable;
563 SECR_value |= SCR_RxDecEnable;
564 SECR_value |= SCR_NoSKMC;
565 rtl92e_writeb(dev, SECR, SECR_value);
566 }
567 rtl92e_writew(dev, ATIMWND, 2);
568 rtl92e_writew(dev, BCN_INTERVAL, 100);
569
570 for (i = 0; i < QOS_QUEUE_NUM; i++)
571 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
572
573 rtl92e_writeb(dev, 0xbe, 0xc0);
574
575 rtl92e_config_mac(dev);
576
577 if (priv->card_8192_version > VERSION_8190_BD) {
578 rtl92e_get_tx_power(dev);
579 rtl92e_set_tx_power(dev, priv->chan);
580 }
581
582 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
583 priv->ic_cut = tmpvalue;
584
585 bfirmwareok = rtl92e_init_fw(dev);
586 if (!bfirmwareok) {
587 if (retry_times < 10) {
588 retry_times++;
589 goto start;
590 } else {
591 rtStatus = false;
592 goto end;
593 }
594 }
595
596 rtStatus = rtl92e_config_rf(dev);
597 if (!rtStatus) {
598 netdev_info(dev, "RF Config failed\n");
599 return rtStatus;
600 }
601
602 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
603 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
604
605 rtl92e_writeb(dev, 0x87, 0x0);
606
607 if (priv->rtllib->rf_off_reason > RF_CHANGE_BY_PS) {
608 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
609 } else if (priv->rtllib->rf_off_reason >= RF_CHANGE_BY_IPS) {
610 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
611 } else {
612 priv->rtllib->rf_power_state = rf_on;
613 priv->rtllib->rf_off_reason = 0;
614 }
615
616 if (priv->rtllib->FwRWRF)
617 priv->rf_mode = RF_OP_By_FW;
618 else
619 priv->rf_mode = RF_OP_By_SW_3wire;
620
621 rtl92e_dm_init_txpower_tracking(dev);
622
623 if (priv->ic_cut >= IC_VersionCut_D) {
624 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
625 bMaskDWord);
626 rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord);
627
628 for (i = 0; i < TX_BB_GAIN_TABLE_LEN; i++) {
629 if (tmpRegA == dm_tx_bb_gain[i]) {
630 priv->rfa_txpowertrackingindex = i;
631 priv->rfa_txpowertrackingindex_real = i;
632 priv->rfa_txpowertracking_default =
633 priv->rfa_txpowertrackingindex;
634 break;
635 }
636 }
637
638 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
639 bMaskByte2);
640
641 for (i = 0; i < CCK_TX_BB_GAIN_TABLE_LEN; i++) {
642 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
643 priv->cck_present_attn_20m_def = i;
644 break;
645 }
646 }
647 priv->cck_present_attn_40m_def = 0;
648 priv->cck_present_attn_diff = 0;
649 priv->cck_present_attn =
650 priv->cck_present_attn_20m_def;
651 priv->btxpower_tracking = false;
652 }
653 rtl92e_irq_enable(dev);
654 end:
655 priv->being_init_adapter = false;
656 return rtStatus;
657 }
658
_rtl92e_net_update(struct net_device * dev)659 static void _rtl92e_net_update(struct net_device *dev)
660 {
661 struct r8192_priv *priv = rtllib_priv(dev);
662 struct rtllib_network *net;
663 u16 rate_config = 0;
664
665 net = &priv->rtllib->current_network;
666 rtl92e_config_rate(dev, &rate_config);
667 priv->dot11_current_preamble_mode = PREAMBLE_AUTO;
668 priv->basic_rate = rate_config &= 0x15f;
669 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
670 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
671 }
672
rtl92e_link_change(struct net_device * dev)673 void rtl92e_link_change(struct net_device *dev)
674 {
675 struct r8192_priv *priv = rtllib_priv(dev);
676 struct rtllib_device *ieee = priv->rtllib;
677
678 if (!priv->up)
679 return;
680
681 if (ieee->link_state == MAC80211_LINKED) {
682 _rtl92e_net_update(dev);
683 rtl92e_update_ratr_table(dev);
684 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
685 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
686 rtl92e_enable_hw_security_config(dev);
687 } else {
688 rtl92e_writeb(dev, 0x173, 0);
689 }
690 _rtl92e_update_msr(dev);
691
692 if (ieee->iw_mode == IW_MODE_INFRA) {
693 u32 reg;
694
695 reg = rtl92e_readl(dev, RCR);
696 if (priv->rtllib->link_state == MAC80211_LINKED) {
697 priv->receive_config = reg |= RCR_CBSSID;
698 } else {
699 priv->receive_config = reg &= ~RCR_CBSSID;
700 }
701
702 rtl92e_writel(dev, RCR, reg);
703 }
704 }
705
rtl92e_set_monitor_mode(struct net_device * dev,bool bAllowAllDA,bool WriteIntoReg)706 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
707 bool WriteIntoReg)
708 {
709 struct r8192_priv *priv = rtllib_priv(dev);
710
711 if (bAllowAllDA)
712 priv->receive_config |= RCR_AAP;
713 else
714 priv->receive_config &= ~RCR_AAP;
715
716 if (WriteIntoReg)
717 rtl92e_writel(dev, RCR, priv->receive_config);
718 }
719
_rtl92e_rate_mgn_to_hw(u8 rate)720 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
721 {
722 u8 ret = DESC90_RATE1M;
723
724 switch (rate) {
725 case MGN_1M:
726 ret = DESC90_RATE1M;
727 break;
728 case MGN_2M:
729 ret = DESC90_RATE2M;
730 break;
731 case MGN_5_5M:
732 ret = DESC90_RATE5_5M;
733 break;
734 case MGN_11M:
735 ret = DESC90_RATE11M;
736 break;
737 case MGN_6M:
738 ret = DESC90_RATE6M;
739 break;
740 case MGN_9M:
741 ret = DESC90_RATE9M;
742 break;
743 case MGN_12M:
744 ret = DESC90_RATE12M;
745 break;
746 case MGN_18M:
747 ret = DESC90_RATE18M;
748 break;
749 case MGN_24M:
750 ret = DESC90_RATE24M;
751 break;
752 case MGN_36M:
753 ret = DESC90_RATE36M;
754 break;
755 case MGN_48M:
756 ret = DESC90_RATE48M;
757 break;
758 case MGN_54M:
759 ret = DESC90_RATE54M;
760 break;
761 case MGN_MCS0:
762 ret = DESC90_RATEMCS0;
763 break;
764 case MGN_MCS1:
765 ret = DESC90_RATEMCS1;
766 break;
767 case MGN_MCS2:
768 ret = DESC90_RATEMCS2;
769 break;
770 case MGN_MCS3:
771 ret = DESC90_RATEMCS3;
772 break;
773 case MGN_MCS4:
774 ret = DESC90_RATEMCS4;
775 break;
776 case MGN_MCS5:
777 ret = DESC90_RATEMCS5;
778 break;
779 case MGN_MCS6:
780 ret = DESC90_RATEMCS6;
781 break;
782 case MGN_MCS7:
783 ret = DESC90_RATEMCS7;
784 break;
785 case MGN_MCS8:
786 ret = DESC90_RATEMCS8;
787 break;
788 case MGN_MCS9:
789 ret = DESC90_RATEMCS9;
790 break;
791 case MGN_MCS10:
792 ret = DESC90_RATEMCS10;
793 break;
794 case MGN_MCS11:
795 ret = DESC90_RATEMCS11;
796 break;
797 case MGN_MCS12:
798 ret = DESC90_RATEMCS12;
799 break;
800 case MGN_MCS13:
801 ret = DESC90_RATEMCS13;
802 break;
803 case MGN_MCS14:
804 ret = DESC90_RATEMCS14;
805 break;
806 case MGN_MCS15:
807 ret = DESC90_RATEMCS15;
808 break;
809 case (0x80 | 0x20):
810 ret = DESC90_RATEMCS32;
811 break;
812 default:
813 break;
814 }
815 return ret;
816 }
817
_rtl92e_hw_queue_to_fw_queue(struct net_device * dev,u8 QueueID,u8 priority)818 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
819 u8 priority)
820 {
821 u8 QueueSelect = 0x0;
822
823 switch (QueueID) {
824 case BE_QUEUE:
825 QueueSelect = QSLT_BE;
826 break;
827
828 case BK_QUEUE:
829 QueueSelect = QSLT_BK;
830 break;
831
832 case VO_QUEUE:
833 QueueSelect = QSLT_VO;
834 break;
835
836 case VI_QUEUE:
837 QueueSelect = QSLT_VI;
838 break;
839 case MGNT_QUEUE:
840 QueueSelect = QSLT_MGNT;
841 break;
842 case BEACON_QUEUE:
843 QueueSelect = QSLT_BEACON;
844 break;
845 case TXCMD_QUEUE:
846 QueueSelect = QSLT_CMD;
847 break;
848 case HIGH_QUEUE:
849 QueueSelect = QSLT_HIGH;
850 break;
851 default:
852 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
853 __func__, QueueID);
854 break;
855 }
856 return QueueSelect;
857 }
858
_rtl92e_query_is_short(u8 TxHT,u8 TxRate,struct cb_desc * tcb_desc)859 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
860 {
861 u8 tmp_Short;
862
863 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
864 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
865 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
866 tmp_Short = 0;
867
868 return tmp_Short;
869 }
870
rtl92e_fill_tx_desc(struct net_device * dev,struct tx_desc * pdesc,struct cb_desc * cb_desc,struct sk_buff * skb)871 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
872 struct cb_desc *cb_desc, struct sk_buff *skb)
873 {
874 struct r8192_priv *priv = rtllib_priv(dev);
875 dma_addr_t mapping;
876 struct tx_fwinfo_8190pci *pTxFwInfo;
877
878 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
879 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
880 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
881 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw(cb_desc->data_rate);
882 pTxFwInfo->EnableCPUDur = cb_desc->tx_enable_fw_calc_dur;
883 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
884 pTxFwInfo->TxRate, cb_desc);
885
886 if (cb_desc->ampdu_enable) {
887 pTxFwInfo->AllowAggregation = 1;
888 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
889 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
890 } else {
891 pTxFwInfo->AllowAggregation = 0;
892 pTxFwInfo->RxMF = 0;
893 pTxFwInfo->RxAMD = 0;
894 }
895
896 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
897 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
898 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
899 pTxFwInfo->RtsHT = (cb_desc->rts_rate & 0x80) ? 1 : 0;
900 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw(cb_desc->rts_rate);
901 pTxFwInfo->RtsBandwidth = 0;
902 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
903 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
904 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
905 (cb_desc->bRTSUseShortGI ? 1 : 0);
906 if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20_40) {
907 if (cb_desc->bPacketBW) {
908 pTxFwInfo->TxBandwidth = 1;
909 pTxFwInfo->TxSubCarrier = 0;
910 } else {
911 pTxFwInfo->TxBandwidth = 0;
912 pTxFwInfo->TxSubCarrier = priv->n_cur_40mhz_prime_sc;
913 }
914 } else {
915 pTxFwInfo->TxBandwidth = 0;
916 pTxFwInfo->TxSubCarrier = 0;
917 }
918
919 memset((u8 *)pdesc, 0, 12);
920
921 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
922 DMA_TO_DEVICE);
923 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
924 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
925 return;
926 }
927
928 pdesc->LINIP = 0;
929 pdesc->CmdInit = 1;
930 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
931 pdesc->PktSize = skb->len - sizeof(struct tx_fwinfo_8190pci);
932
933 pdesc->SecCAMID = 0;
934 pdesc->RATid = cb_desc->ratr_index;
935
936 pdesc->NoEnc = 1;
937 pdesc->SecType = 0x0;
938 if (cb_desc->bHwSec) {
939 static u8 tmp;
940
941 if (!tmp)
942 tmp = 1;
943 switch (priv->rtllib->pairwise_key_type) {
944 case KEY_TYPE_WEP40:
945 case KEY_TYPE_WEP104:
946 pdesc->SecType = 0x1;
947 pdesc->NoEnc = 0;
948 break;
949 case KEY_TYPE_TKIP:
950 pdesc->SecType = 0x2;
951 pdesc->NoEnc = 0;
952 break;
953 case KEY_TYPE_CCMP:
954 pdesc->SecType = 0x3;
955 pdesc->NoEnc = 0;
956 break;
957 case KEY_TYPE_NA:
958 pdesc->SecType = 0x0;
959 pdesc->NoEnc = 1;
960 break;
961 }
962 }
963
964 pdesc->PktId = 0x0;
965
966 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
967 cb_desc->queue_index,
968 cb_desc->priority);
969 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
970
971 pdesc->DISFB = cb_desc->tx_dis_rate_fallback;
972 pdesc->USERATE = cb_desc->tx_use_drv_assinged_rate;
973
974 pdesc->FirstSeg = 1;
975 pdesc->LastSeg = 1;
976 pdesc->TxBufferSize = skb->len;
977
978 pdesc->TxBuffAddr = mapping;
979 }
980
rtl92e_fill_tx_cmd_desc(struct net_device * dev,struct tx_desc_cmd * entry,struct cb_desc * cb_desc,struct sk_buff * skb)981 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
982 struct cb_desc *cb_desc, struct sk_buff *skb)
983 {
984 struct r8192_priv *priv = rtllib_priv(dev);
985 dma_addr_t mapping = dma_map_single(&priv->pdev->dev, skb->data,
986 skb->len, DMA_TO_DEVICE);
987
988 if (dma_mapping_error(&priv->pdev->dev, mapping))
989 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
990 memset(entry, 0, 12);
991 entry->LINIP = cb_desc->bLastIniPkt;
992 entry->FirstSeg = 1;
993 entry->LastSeg = 1;
994 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
995 entry->CmdInit = DESC_PACKET_TYPE_INIT;
996 } else {
997 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
998
999 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1000 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1001 entry_tmp->PktSize = cb_desc->pkt_size + entry_tmp->Offset;
1002 entry_tmp->QueueSelect = QSLT_CMD;
1003 entry_tmp->TxFWInfoSize = 0x08;
1004 entry_tmp->RATid = DESC_PACKET_TYPE_INIT;
1005 }
1006 entry->TxBufferSize = skb->len;
1007 entry->TxBuffAddr = mapping;
1008 entry->OWN = 1;
1009 }
1010
_rtl92e_rate_hw_to_mgn(bool bIsHT,u8 rate)1011 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1012 {
1013 u8 ret_rate = 0x02;
1014
1015 if (!bIsHT) {
1016 switch (rate) {
1017 case DESC90_RATE1M:
1018 ret_rate = MGN_1M;
1019 break;
1020 case DESC90_RATE2M:
1021 ret_rate = MGN_2M;
1022 break;
1023 case DESC90_RATE5_5M:
1024 ret_rate = MGN_5_5M;
1025 break;
1026 case DESC90_RATE11M:
1027 ret_rate = MGN_11M;
1028 break;
1029 case DESC90_RATE6M:
1030 ret_rate = MGN_6M;
1031 break;
1032 case DESC90_RATE9M:
1033 ret_rate = MGN_9M;
1034 break;
1035 case DESC90_RATE12M:
1036 ret_rate = MGN_12M;
1037 break;
1038 case DESC90_RATE18M:
1039 ret_rate = MGN_18M;
1040 break;
1041 case DESC90_RATE24M:
1042 ret_rate = MGN_24M;
1043 break;
1044 case DESC90_RATE36M:
1045 ret_rate = MGN_36M;
1046 break;
1047 case DESC90_RATE48M:
1048 ret_rate = MGN_48M;
1049 break;
1050 case DESC90_RATE54M:
1051 ret_rate = MGN_54M;
1052 break;
1053 }
1054
1055 } else {
1056 switch (rate) {
1057 case DESC90_RATEMCS0:
1058 ret_rate = MGN_MCS0;
1059 break;
1060 case DESC90_RATEMCS1:
1061 ret_rate = MGN_MCS1;
1062 break;
1063 case DESC90_RATEMCS2:
1064 ret_rate = MGN_MCS2;
1065 break;
1066 case DESC90_RATEMCS3:
1067 ret_rate = MGN_MCS3;
1068 break;
1069 case DESC90_RATEMCS4:
1070 ret_rate = MGN_MCS4;
1071 break;
1072 case DESC90_RATEMCS5:
1073 ret_rate = MGN_MCS5;
1074 break;
1075 case DESC90_RATEMCS6:
1076 ret_rate = MGN_MCS6;
1077 break;
1078 case DESC90_RATEMCS7:
1079 ret_rate = MGN_MCS7;
1080 break;
1081 case DESC90_RATEMCS8:
1082 ret_rate = MGN_MCS8;
1083 break;
1084 case DESC90_RATEMCS9:
1085 ret_rate = MGN_MCS9;
1086 break;
1087 case DESC90_RATEMCS10:
1088 ret_rate = MGN_MCS10;
1089 break;
1090 case DESC90_RATEMCS11:
1091 ret_rate = MGN_MCS11;
1092 break;
1093 case DESC90_RATEMCS12:
1094 ret_rate = MGN_MCS12;
1095 break;
1096 case DESC90_RATEMCS13:
1097 ret_rate = MGN_MCS13;
1098 break;
1099 case DESC90_RATEMCS14:
1100 ret_rate = MGN_MCS14;
1101 break;
1102 case DESC90_RATEMCS15:
1103 ret_rate = MGN_MCS15;
1104 break;
1105 case DESC90_RATEMCS32:
1106 ret_rate = 0x80 | 0x20;
1107 break;
1108 }
1109 }
1110
1111 return ret_rate;
1112 }
1113
_rtl92e_signal_scale_mapping(struct r8192_priv * priv,long currsig)1114 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1115 {
1116 long retsig;
1117
1118 if (currsig >= 61 && currsig <= 100)
1119 retsig = 90 + ((currsig - 60) / 4);
1120 else if (currsig >= 41 && currsig <= 60)
1121 retsig = 78 + ((currsig - 40) / 2);
1122 else if (currsig >= 31 && currsig <= 40)
1123 retsig = 66 + (currsig - 30);
1124 else if (currsig >= 21 && currsig <= 30)
1125 retsig = 54 + (currsig - 20);
1126 else if (currsig >= 5 && currsig <= 20)
1127 retsig = 42 + (((currsig - 5) * 2) / 3);
1128 else if (currsig == 4)
1129 retsig = 36;
1130 else if (currsig == 3)
1131 retsig = 27;
1132 else if (currsig == 2)
1133 retsig = 18;
1134 else if (currsig == 1)
1135 retsig = 9;
1136 else
1137 retsig = currsig;
1138
1139 return retsig;
1140 }
1141
1142 #define rx_hal_is_cck_rate(_pdrvinfo)\
1143 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1144 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1145 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1146 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1147 !_pdrvinfo->RxHT)
1148
_rtl92e_query_rxphystatus(struct r8192_priv * priv,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo,struct rtllib_rx_stats * precord_stats,bool bpacket_match_bssid,bool bpacket_toself,bool bPacketBeacon,bool bToSelfBA)1149 static void _rtl92e_query_rxphystatus(
1150 struct r8192_priv *priv,
1151 struct rtllib_rx_stats *pstats,
1152 struct rx_desc *pdesc,
1153 struct rx_fwinfo *pdrvinfo,
1154 struct rtllib_rx_stats *precord_stats,
1155 bool bpacket_match_bssid,
1156 bool bpacket_toself,
1157 bool bPacketBeacon,
1158 bool bToSelfBA
1159 )
1160 {
1161 struct phy_sts_ofdm_819xpci *pofdm_buf;
1162 struct phy_sts_cck_819xpci *pcck_buf;
1163 u8 *prxpkt;
1164 u8 i, max_spatial_stream, tmp_rxevm;
1165 s8 rx_pwr[4], rx_pwr_all = 0;
1166 s8 rx_evmX;
1167 u8 evm, pwdb_all;
1168 u32 RSSI, total_rssi = 0;
1169 u8 is_cck_rate = 0;
1170 u8 rf_rx_num = 0;
1171 static u8 check_reg824;
1172 static u32 reg824_bit9;
1173
1174 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1175 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1176 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1177 bpacket_match_bssid;
1178 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1179 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1180 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1181 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1182 if (check_reg824 == 0) {
1183 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1184 rFPGA0_XA_HSSIParameter2,
1185 0x200);
1186 check_reg824 = 1;
1187 }
1188
1189 prxpkt = (u8 *)pdrvinfo;
1190
1191 prxpkt += sizeof(struct rx_fwinfo);
1192
1193 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1194 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1195
1196 pstats->RxMIMOSignalQuality[0] = -1;
1197 pstats->RxMIMOSignalQuality[1] = -1;
1198 precord_stats->RxMIMOSignalQuality[0] = -1;
1199 precord_stats->RxMIMOSignalQuality[1] = -1;
1200
1201 if (is_cck_rate) {
1202 u8 report;
1203
1204 if (!reg824_bit9) {
1205 report = pcck_buf->cck_agc_rpt & 0xc0;
1206 report >>= 6;
1207 switch (report) {
1208 case 0x3:
1209 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1210 0x3e);
1211 break;
1212 case 0x2:
1213 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1214 0x3e);
1215 break;
1216 case 0x1:
1217 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1218 0x3e);
1219 break;
1220 case 0x0:
1221 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1222 break;
1223 }
1224 } else {
1225 report = pcck_buf->cck_agc_rpt & 0x60;
1226 report >>= 5;
1227 switch (report) {
1228 case 0x3:
1229 rx_pwr_all = -35 -
1230 ((pcck_buf->cck_agc_rpt &
1231 0x1f) << 1);
1232 break;
1233 case 0x2:
1234 rx_pwr_all = -23 -
1235 ((pcck_buf->cck_agc_rpt &
1236 0x1f) << 1);
1237 break;
1238 case 0x1:
1239 rx_pwr_all = -11 -
1240 ((pcck_buf->cck_agc_rpt &
1241 0x1f) << 1);
1242 break;
1243 case 0x0:
1244 rx_pwr_all = -8 -
1245 ((pcck_buf->cck_agc_rpt &
1246 0x1f) << 1);
1247 break;
1248 }
1249 }
1250
1251 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1252 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1253 pstats->RecvSignalPower = rx_pwr_all;
1254
1255 if (bpacket_match_bssid) {
1256 u8 sq;
1257
1258 if (pstats->RxPWDBAll > 40) {
1259 sq = 100;
1260 } else {
1261 sq = pcck_buf->sq_rpt;
1262
1263 if (pcck_buf->sq_rpt > 64)
1264 sq = 0;
1265 else if (pcck_buf->sq_rpt < 20)
1266 sq = 100;
1267 else
1268 sq = ((64 - sq) * 100) / 44;
1269 }
1270 pstats->SignalQuality = sq;
1271 precord_stats->SignalQuality = sq;
1272 pstats->RxMIMOSignalQuality[0] = sq;
1273 precord_stats->RxMIMOSignalQuality[0] = sq;
1274 pstats->RxMIMOSignalQuality[1] = -1;
1275 precord_stats->RxMIMOSignalQuality[1] = -1;
1276 }
1277 } else {
1278 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1279 if (priv->brfpath_rxenable[i])
1280 rf_rx_num++;
1281
1282 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1283 2) - 110;
1284
1285 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1286 if (priv->brfpath_rxenable[i])
1287 total_rssi += RSSI;
1288
1289 if (bpacket_match_bssid) {
1290 pstats->RxMIMOSignalStrength[i] = RSSI;
1291 precord_stats->RxMIMOSignalStrength[i] = RSSI;
1292 }
1293 }
1294
1295 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1296 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1297
1298 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1299 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1300 pstats->RecvSignalPower = rx_pwr_all;
1301 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1302 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1303 max_spatial_stream = 2;
1304 else
1305 max_spatial_stream = 1;
1306
1307 for (i = 0; i < max_spatial_stream; i++) {
1308 tmp_rxevm = pofdm_buf->rxevm_X[i];
1309 rx_evmX = (s8)(tmp_rxevm);
1310
1311 rx_evmX /= 2;
1312
1313 evm = rtl92e_evm_db_to_percent(rx_evmX);
1314 if (bpacket_match_bssid) {
1315 if (i == 0) {
1316 pstats->SignalQuality = evm & 0xff;
1317 precord_stats->SignalQuality = evm & 0xff;
1318 }
1319 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1320 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
1321 }
1322 }
1323 }
1324
1325 if (is_cck_rate) {
1326 pstats->SignalStrength = precord_stats->SignalStrength =
1327 _rtl92e_signal_scale_mapping(priv,
1328 (long)pwdb_all);
1329
1330 } else {
1331 if (rf_rx_num != 0)
1332 pstats->SignalStrength = precord_stats->SignalStrength =
1333 _rtl92e_signal_scale_mapping(priv,
1334 (long)(total_rssi /= rf_rx_num));
1335 }
1336 }
1337
_rtl92e_process_phyinfo(struct r8192_priv * priv,u8 * buffer,struct rtllib_rx_stats * prev_st,struct rtllib_rx_stats * curr_st)1338 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1339 struct rtllib_rx_stats *prev_st,
1340 struct rtllib_rx_stats *curr_st)
1341 {
1342 bool bcheck = false;
1343 u8 rfpath;
1344 u32 ij, tmp_val;
1345 static u32 slide_rssi_index, slide_rssi_statistics;
1346 static u32 slide_evm_index, slide_evm_statistics;
1347 static u32 last_rssi, last_evm;
1348 static u32 slide_beacon_adc_pwdb_index;
1349 static u32 slide_beacon_adc_pwdb_statistics;
1350 static u32 last_beacon_adc_pwdb;
1351 struct ieee80211_hdr_3addr *hdr;
1352 u16 sc;
1353 unsigned int seq;
1354
1355 hdr = (struct ieee80211_hdr_3addr *)buffer;
1356 sc = le16_to_cpu(hdr->seq_ctrl);
1357 seq = WLAN_GET_SEQ_SEQ(sc);
1358 curr_st->Seq_Num = seq;
1359 if (!prev_st->bIsAMPDU)
1360 bcheck = true;
1361
1362 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1363 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1364 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1365 priv->stats.slide_rssi_total -= last_rssi;
1366 }
1367 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1368
1369 priv->stats.slide_signal_strength[slide_rssi_index++] =
1370 prev_st->SignalStrength;
1371 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1372 slide_rssi_index = 0;
1373
1374 tmp_val = priv->stats.slide_rssi_total / slide_rssi_statistics;
1375 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv, tmp_val);
1376 curr_st->rssi = priv->stats.signal_strength;
1377 if (!prev_st->bPacketMatchBSSID) {
1378 if (!prev_st->bToSelfBA)
1379 return;
1380 }
1381
1382 if (!bcheck)
1383 return;
1384
1385 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1386 for (rfpath = RF90_PATH_A; rfpath < priv->num_total_rf_path; rfpath++) {
1387 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1388 priv->stats.rx_rssi_percentage[rfpath] =
1389 prev_st->RxMIMOSignalStrength[rfpath];
1390 }
1391 if (prev_st->RxMIMOSignalStrength[rfpath] >
1392 priv->stats.rx_rssi_percentage[rfpath]) {
1393 priv->stats.rx_rssi_percentage[rfpath] =
1394 ((priv->stats.rx_rssi_percentage[rfpath]
1395 * (RX_SMOOTH - 1)) +
1396 (prev_st->RxMIMOSignalStrength
1397 [rfpath])) / (RX_SMOOTH);
1398 priv->stats.rx_rssi_percentage[rfpath] =
1399 priv->stats.rx_rssi_percentage[rfpath]
1400 + 1;
1401 } else {
1402 priv->stats.rx_rssi_percentage[rfpath] =
1403 ((priv->stats.rx_rssi_percentage[rfpath] *
1404 (RX_SMOOTH - 1)) +
1405 (prev_st->RxMIMOSignalStrength[rfpath])) /
1406 (RX_SMOOTH);
1407 }
1408 }
1409 }
1410
1411 if (prev_st->bPacketBeacon) {
1412 if (slide_beacon_adc_pwdb_statistics++ >=
1413 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1414 slide_beacon_adc_pwdb_statistics =
1415 PHY_Beacon_RSSI_SLID_WIN_MAX;
1416 last_beacon_adc_pwdb = priv->stats.slide_beacon_pwdb
1417 [slide_beacon_adc_pwdb_index];
1418 priv->stats.slide_beacon_total -= last_beacon_adc_pwdb;
1419 }
1420 priv->stats.slide_beacon_total += prev_st->RxPWDBAll;
1421 priv->stats.slide_beacon_pwdb[slide_beacon_adc_pwdb_index] =
1422 prev_st->RxPWDBAll;
1423 slide_beacon_adc_pwdb_index++;
1424 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1425 slide_beacon_adc_pwdb_index = 0;
1426 prev_st->RxPWDBAll = priv->stats.slide_beacon_total /
1427 slide_beacon_adc_pwdb_statistics;
1428 if (prev_st->RxPWDBAll >= 3)
1429 prev_st->RxPWDBAll -= 3;
1430 }
1431 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1432 prev_st->bToSelfBA) {
1433 if (priv->undecorated_smoothed_pwdb < 0)
1434 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1435 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1436 priv->undecorated_smoothed_pwdb =
1437 (((priv->undecorated_smoothed_pwdb) *
1438 (RX_SMOOTH - 1)) +
1439 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1440 priv->undecorated_smoothed_pwdb =
1441 priv->undecorated_smoothed_pwdb + 1;
1442 } else {
1443 priv->undecorated_smoothed_pwdb =
1444 (((priv->undecorated_smoothed_pwdb) *
1445 (RX_SMOOTH - 1)) +
1446 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1447 }
1448 rtl92e_update_rx_statistics(priv, prev_st);
1449 }
1450
1451 if (prev_st->SignalQuality != 0) {
1452 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1453 prev_st->bToSelfBA) {
1454 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1455 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1456 last_evm =
1457 priv->stats.slide_evm[slide_evm_index];
1458 priv->stats.slide_evm_total -= last_evm;
1459 }
1460
1461 priv->stats.slide_evm_total += prev_st->SignalQuality;
1462
1463 priv->stats.slide_evm[slide_evm_index++] =
1464 prev_st->SignalQuality;
1465 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1466 slide_evm_index = 0;
1467
1468 tmp_val = priv->stats.slide_evm_total /
1469 slide_evm_statistics;
1470 priv->stats.last_signal_strength_inpercent = tmp_val;
1471 }
1472
1473 if (prev_st->bPacketToSelf ||
1474 prev_st->bPacketBeacon ||
1475 prev_st->bToSelfBA) {
1476 for (ij = 0; ij < 2; ij++) {
1477 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1478 if (priv->stats.rx_evm_percentage[ij] == 0)
1479 priv->stats.rx_evm_percentage[ij] =
1480 prev_st->RxMIMOSignalQuality[ij];
1481 priv->stats.rx_evm_percentage[ij] =
1482 ((priv->stats.rx_evm_percentage[ij] *
1483 (RX_SMOOTH - 1)) +
1484 (prev_st->RxMIMOSignalQuality[ij])) /
1485 (RX_SMOOTH);
1486 }
1487 }
1488 }
1489 }
1490 }
1491
_rtl92e_translate_rx_signal_stats(struct net_device * dev,struct sk_buff * skb,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo)1492 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1493 struct sk_buff *skb,
1494 struct rtllib_rx_stats *pstats,
1495 struct rx_desc *pdesc,
1496 struct rx_fwinfo *pdrvinfo)
1497 {
1498 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1499 bool bpacket_match_bssid, bpacket_toself;
1500 bool bPacketBeacon = false;
1501 struct ieee80211_hdr_3addr *hdr;
1502 bool bToSelfBA = false;
1503 static struct rtllib_rx_stats previous_stats;
1504 u16 fc, type;
1505 u8 *tmp_buf;
1506 u8 *praddr;
1507
1508 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1509
1510 hdr = (struct ieee80211_hdr_3addr *)tmp_buf;
1511 fc = le16_to_cpu(hdr->frame_control);
1512 type = WLAN_FC_GET_TYPE(fc);
1513 praddr = hdr->addr1;
1514
1515 bpacket_match_bssid =
1516 ((type != RTLLIB_FTYPE_CTL) &&
1517 ether_addr_equal(priv->rtllib->current_network.bssid,
1518 (fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
1519 (fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
1520 hdr->addr3) &&
1521 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1522 bpacket_toself = bpacket_match_bssid && /* check this */
1523 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1524 if (ieee80211_is_beacon(hdr->frame_control))
1525 bPacketBeacon = true;
1526 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1527 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1528 &previous_stats, bpacket_match_bssid,
1529 bpacket_toself, bPacketBeacon, bToSelfBA);
1530 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1531 }
1532
_rtl92e_update_received_rate_histogram_stats(struct net_device * dev,struct rtllib_rx_stats * pstats)1533 static void _rtl92e_update_received_rate_histogram_stats(
1534 struct net_device *dev,
1535 struct rtllib_rx_stats *pstats)
1536 {
1537 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1538 u32 rcvType = 1;
1539 u32 rateIndex;
1540
1541 if (pstats->bCRC)
1542 rcvType = 2;
1543 else if (pstats->bICV)
1544 rcvType = 3;
1545
1546 switch (pstats->rate) {
1547 case MGN_1M:
1548 rateIndex = 0;
1549 break;
1550 case MGN_2M:
1551 rateIndex = 1;
1552 break;
1553 case MGN_5_5M:
1554 rateIndex = 2;
1555 break;
1556 case MGN_11M:
1557 rateIndex = 3;
1558 break;
1559 case MGN_6M:
1560 rateIndex = 4;
1561 break;
1562 case MGN_9M:
1563 rateIndex = 5;
1564 break;
1565 case MGN_12M:
1566 rateIndex = 6;
1567 break;
1568 case MGN_18M:
1569 rateIndex = 7;
1570 break;
1571 case MGN_24M:
1572 rateIndex = 8;
1573 break;
1574 case MGN_36M:
1575 rateIndex = 9;
1576 break;
1577 case MGN_48M:
1578 rateIndex = 10;
1579 break;
1580 case MGN_54M:
1581 rateIndex = 11;
1582 break;
1583 case MGN_MCS0:
1584 rateIndex = 12;
1585 break;
1586 case MGN_MCS1:
1587 rateIndex = 13;
1588 break;
1589 case MGN_MCS2:
1590 rateIndex = 14;
1591 break;
1592 case MGN_MCS3:
1593 rateIndex = 15;
1594 break;
1595 case MGN_MCS4:
1596 rateIndex = 16;
1597 break;
1598 case MGN_MCS5:
1599 rateIndex = 17;
1600 break;
1601 case MGN_MCS6:
1602 rateIndex = 18;
1603 break;
1604 case MGN_MCS7:
1605 rateIndex = 19;
1606 break;
1607 case MGN_MCS8:
1608 rateIndex = 20;
1609 break;
1610 case MGN_MCS9:
1611 rateIndex = 21;
1612 break;
1613 case MGN_MCS10:
1614 rateIndex = 22;
1615 break;
1616 case MGN_MCS11:
1617 rateIndex = 23;
1618 break;
1619 case MGN_MCS12:
1620 rateIndex = 24;
1621 break;
1622 case MGN_MCS13:
1623 rateIndex = 25;
1624 break;
1625 case MGN_MCS14:
1626 rateIndex = 26;
1627 break;
1628 case MGN_MCS15:
1629 rateIndex = 27;
1630 break;
1631 default:
1632 rateIndex = 28;
1633 break;
1634 }
1635 priv->stats.received_rate_histogram[0][rateIndex]++;
1636 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
1637 }
1638
rtl92e_get_rx_stats(struct net_device * dev,struct rtllib_rx_stats * stats,struct rx_desc * pdesc,struct sk_buff * skb)1639 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
1640 struct rx_desc *pdesc, struct sk_buff *skb)
1641 {
1642 struct rx_fwinfo *pDrvInfo = NULL;
1643
1644 stats->bICV = pdesc->ICV;
1645 stats->bCRC = pdesc->CRC32;
1646 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
1647
1648 stats->Length = pdesc->Length;
1649 if (stats->Length < 24)
1650 stats->bHwError |= 1;
1651
1652 if (stats->bHwError) {
1653 stats->bShift = false;
1654 return false;
1655 }
1656
1657 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
1658 stats->RxBufShift = (pdesc->Shift) & 0x03;
1659 stats->Decrypted = !pdesc->SWDec;
1660
1661 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
1662
1663 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
1664 pDrvInfo->RxRate);
1665 stats->bShortPreamble = pDrvInfo->SPLCP;
1666
1667 _rtl92e_update_received_rate_histogram_stats(dev, stats);
1668
1669 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
1670 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
1671 (pDrvInfo->FirstAGGR == 1);
1672
1673 stats->TimeStampLow = pDrvInfo->TSFL;
1674 stats->TimeStampHigh = rtl92e_readl(dev, TSFR + 4);
1675
1676 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
1677 stats->bShift = 1;
1678
1679 stats->RxIs40MHzPacket = pDrvInfo->BW;
1680
1681 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
1682 skb_trim(skb, skb->len - S_CRC_LEN);
1683
1684
1685 stats->packetlength = stats->Length - 4;
1686 stats->fraglength = stats->packetlength;
1687 stats->fragoffset = 0;
1688 stats->ntotalfrag = 1;
1689 return true;
1690 }
1691
rtl92e_stop_adapter(struct net_device * dev,bool reset)1692 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
1693 {
1694 struct r8192_priv *priv = rtllib_priv(dev);
1695 int i;
1696 u8 op_mode;
1697 u8 u1bTmp;
1698 u32 ulRegRead;
1699
1700 op_mode = RT_OP_MODE_NO_LINK;
1701 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &op_mode);
1702
1703 if (!priv->rtllib->bSupportRemoteWakeUp) {
1704 u1bTmp = 0x0;
1705 rtl92e_writeb(dev, CMDR, u1bTmp);
1706 }
1707
1708 mdelay(20);
1709
1710 if (!reset) {
1711 mdelay(150);
1712
1713 priv->hw_rf_off_action = 2;
1714
1715 if (!priv->rtllib->bSupportRemoteWakeUp) {
1716 rtl92e_set_rf_off(dev);
1717 ulRegRead = rtl92e_readl(dev, CPU_GEN);
1718 ulRegRead |= CPU_GEN_SYSTEM_RESET;
1719 rtl92e_writel(dev, CPU_GEN, ulRegRead);
1720 } else {
1721 rtl92e_writel(dev, WFCRC0, 0xffffffff);
1722 rtl92e_writel(dev, WFCRC1, 0xffffffff);
1723 rtl92e_writel(dev, WFCRC2, 0xffffffff);
1724
1725 rtl92e_writeb(dev, PMR, 0x5);
1726 rtl92e_writeb(dev, MAC_BLK_CTRL, 0xa);
1727 }
1728 }
1729
1730 for (i = 0; i < MAX_QUEUE_SIZE; i++)
1731 skb_queue_purge(&priv->rtllib->skb_waitq[i]);
1732
1733 skb_queue_purge(&priv->skb_queue);
1734 }
1735
rtl92e_update_ratr_table(struct net_device * dev)1736 void rtl92e_update_ratr_table(struct net_device *dev)
1737 {
1738 struct r8192_priv *priv = rtllib_priv(dev);
1739 struct rtllib_device *ieee = priv->rtllib;
1740 u8 *pMcsRate = ieee->dot11ht_oper_rate_set;
1741 u32 ratr_value = 0;
1742 u16 rate_config = 0;
1743 u8 rate_index = 0;
1744
1745 rtl92e_config_rate(dev, &rate_config);
1746 ratr_value = rate_config | *pMcsRate << 12;
1747 switch (ieee->mode) {
1748 case WIRELESS_MODE_B:
1749 ratr_value &= 0x0000000F;
1750 break;
1751 case WIRELESS_MODE_G:
1752 case WIRELESS_MODE_G | WIRELESS_MODE_B:
1753 ratr_value &= 0x00000FF7;
1754 break;
1755 case WIRELESS_MODE_N_24G:
1756 ratr_value &= 0x000FF007;
1757 break;
1758 default:
1759 break;
1760 }
1761 ratr_value &= 0x0FFFFFFF;
1762 if (ieee->ht_info->cur_tx_bw40mhz &&
1763 ieee->ht_info->cur_short_gi_40mhz)
1764 ratr_value |= 0x80000000;
1765 else if (!ieee->ht_info->cur_tx_bw40mhz &&
1766 ieee->ht_info->cur_short_gi_20mhz)
1767 ratr_value |= 0x80000000;
1768 rtl92e_writel(dev, RATR0 + rate_index * 4, ratr_value);
1769 rtl92e_writeb(dev, UFWP, 1);
1770 }
1771
1772 void
rtl92e_init_variables(struct net_device * dev)1773 rtl92e_init_variables(struct net_device *dev)
1774 {
1775 struct r8192_priv *priv = rtllib_priv(dev);
1776
1777 strscpy(priv->nick, "rtl8192E", sizeof(priv->nick));
1778
1779 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
1780 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
1781 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
1782
1783 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
1784
1785 priv->short_retry_limit = 0x30;
1786 priv->long_retry_limit = 0x30;
1787
1788 priv->receive_config = RCR_ADD3 |
1789 RCR_AMF | RCR_ADF |
1790 RCR_AICV |
1791 RCR_AB | RCR_AM | RCR_APM |
1792 RCR_AAP | ((u32)7 << RCR_MXDMA_OFFSET) |
1793 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
1794
1795 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
1796 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
1797 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
1798 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
1799 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
1800 IMR_TBDOK | IMR_TBDER);
1801
1802 priv->bfirst_after_down = false;
1803 }
1804
rtl92e_irq_enable(struct net_device * dev)1805 void rtl92e_irq_enable(struct net_device *dev)
1806 {
1807 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1808
1809 priv->irq_enabled = 1;
1810
1811 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
1812 }
1813
rtl92e_irq_disable(struct net_device * dev)1814 void rtl92e_irq_disable(struct net_device *dev)
1815 {
1816 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1817
1818 rtl92e_writel(dev, INTA_MASK, 0);
1819
1820 priv->irq_enabled = 0;
1821 }
1822
rtl92e_enable_rx(struct net_device * dev)1823 void rtl92e_enable_rx(struct net_device *dev)
1824 {
1825 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1826
1827 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma);
1828 }
1829
1830 static const u32 TX_DESC_BASE[] = {
1831 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
1832 };
1833
rtl92e_enable_tx(struct net_device * dev)1834 void rtl92e_enable_tx(struct net_device *dev)
1835 {
1836 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1837 u32 i;
1838
1839 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
1840 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
1841 }
1842
rtl92e_ack_irq(struct net_device * dev,u32 * p_inta)1843 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta)
1844 {
1845 *p_inta = rtl92e_readl(dev, ISR);
1846 rtl92e_writel(dev, ISR, *p_inta);
1847 }
1848
rtl92e_is_rx_stuck(struct net_device * dev)1849 bool rtl92e_is_rx_stuck(struct net_device *dev)
1850 {
1851 struct r8192_priv *priv = rtllib_priv(dev);
1852 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
1853 bool bStuck = false;
1854 static u8 rx_chk_cnt;
1855 u32 SlotIndex = 0, TotalRxStuckCount = 0;
1856 u8 i;
1857 u8 SilentResetRxSoltNum = 4;
1858
1859 rx_chk_cnt++;
1860 if (priv->undecorated_smoothed_pwdb >= (RATE_ADAPTIVE_TH_HIGH + 5)) {
1861 rx_chk_cnt = 0;
1862 } else if ((priv->undecorated_smoothed_pwdb < (RATE_ADAPTIVE_TH_HIGH + 5))
1863 && (((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) &&
1864 (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_40M))
1865 || ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) &&
1866 (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_20M)))) {
1867 if (rx_chk_cnt < 2)
1868 return bStuck;
1869 rx_chk_cnt = 0;
1870 } else if ((((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) &&
1871 (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_40M)) ||
1872 ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) &&
1873 (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_20M))) &&
1874 priv->undecorated_smoothed_pwdb >= VERY_LOW_RSSI) {
1875 if (rx_chk_cnt < 4)
1876 return bStuck;
1877 rx_chk_cnt = 0;
1878 } else {
1879 if (rx_chk_cnt < 8)
1880 return bStuck;
1881 rx_chk_cnt = 0;
1882 }
1883
1884
1885 SlotIndex = (priv->silent_reset_rx_slot_index++) % SilentResetRxSoltNum;
1886
1887 if (priv->rx_ctr == RegRxCounter) {
1888 priv->silent_reset_rx_stuck_event[SlotIndex] = 1;
1889
1890 for (i = 0; i < SilentResetRxSoltNum; i++)
1891 TotalRxStuckCount += priv->silent_reset_rx_stuck_event[i];
1892
1893 if (TotalRxStuckCount == SilentResetRxSoltNum) {
1894 bStuck = true;
1895 for (i = 0; i < SilentResetRxSoltNum; i++)
1896 TotalRxStuckCount +=
1897 priv->silent_reset_rx_stuck_event[i];
1898 }
1899 } else {
1900 priv->silent_reset_rx_stuck_event[SlotIndex] = 0;
1901 }
1902
1903 priv->rx_ctr = RegRxCounter;
1904
1905 return bStuck;
1906 }
1907
rtl92e_is_tx_stuck(struct net_device * dev)1908 bool rtl92e_is_tx_stuck(struct net_device *dev)
1909 {
1910 struct r8192_priv *priv = rtllib_priv(dev);
1911 bool bStuck = false;
1912 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
1913
1914 if (priv->tx_counter == RegTxCounter)
1915 bStuck = true;
1916
1917 priv->tx_counter = RegTxCounter;
1918
1919 return bStuck;
1920 }
1921
rtl92e_get_nmode_support_by_sec(struct net_device * dev)1922 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
1923 {
1924 struct r8192_priv *priv = rtllib_priv(dev);
1925 struct rtllib_device *ieee = priv->rtllib;
1926
1927 if (ieee->rtllib_ap_sec_type &&
1928 (ieee->rtllib_ap_sec_type(priv->rtllib) & (SEC_ALG_WEP |
1929 SEC_ALG_TKIP))) {
1930 return false;
1931 } else {
1932 return true;
1933 }
1934 }
1935
rtl92e_is_halfn_supported_by_ap(struct net_device * dev)1936 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
1937 {
1938 struct r8192_priv *priv = rtllib_priv(dev);
1939 struct rtllib_device *ieee = priv->rtllib;
1940
1941 return ieee->bHalfWirelessN24GMode;
1942 }
1943