1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29
30 #include "dcn20/dcn20_clk_mgr.h"
31 #include "rn_clk_mgr.h"
32
33
34 #include "dce100/dce_clk_mgr.h"
35 #include "rn_clk_mgr_vbios_smu.h"
36 #include "reg_helper.h"
37 #include "core_types.h"
38 #include "dm_helpers.h"
39
40 #include "atomfirmware.h"
41 #include "clk/clk_10_0_2_offset.h"
42 #include "clk/clk_10_0_2_sh_mask.h"
43 #include "renoir_ip_offset.h"
44
45
46 /* Constants */
47
48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
49 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */
50
51 /* Macros */
52
53 #define REG(reg_name) \
54 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
55
56
57 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
rn_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)58 int rn_get_active_display_cnt_wa(
59 struct dc *dc,
60 struct dc_state *context)
61 {
62 int i, display_count;
63 bool tmds_present = false;
64
65 display_count = 0;
66 for (i = 0; i < context->stream_count; i++) {
67 const struct dc_stream_state *stream = context->streams[i];
68
69 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
70 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
71 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
72 tmds_present = true;
73 }
74
75 for (i = 0; i < dc->link_count; i++) {
76 const struct dc_link *link = dc->links[i];
77
78 /*
79 * Only notify active stream or virtual stream.
80 * Need to notify virtual stream to work around
81 * headless case. HPD does not fire when system is in
82 * S0i2.
83 */
84 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
85 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
86 link->link_enc->funcs->is_dig_enabled(link->link_enc))
87 display_count++;
88 }
89
90 /* WA for hang on HDMI after display off back back on*/
91 if (display_count == 0 && tmds_present)
92 display_count = 1;
93
94 return display_count;
95 }
96
rn_set_low_power_state(struct clk_mgr * clk_mgr_base)97 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
98 {
99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
100
101 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
102 /* update power state */
103 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
104 }
105
rn_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)106 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
107 struct dc_state *context,
108 bool safe_to_lower)
109 {
110 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
111 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
112 struct dc *dc = clk_mgr_base->ctx->dc;
113 int display_count;
114 bool update_dppclk = false;
115 bool update_dispclk = false;
116 bool dpp_clock_lowered = false;
117
118 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
119
120 if (dc->work_arounds.skip_clock_update)
121 return;
122
123 /*
124 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
125 * also if safe to lower is false, we just go in the higher state
126 */
127 if (safe_to_lower) {
128 /* check that we're not already in lower */
129 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
130
131 display_count = rn_get_active_display_cnt_wa(dc, context);
132 /* if we can go lower, go lower */
133 if (display_count == 0) {
134 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
135 /* update power state */
136 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
137 }
138 }
139 } else {
140 /* check that we're not already in D0 */
141 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
142 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
143 /* update power state */
144 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
145 }
146 }
147
148 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
149 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
151 }
152
153 if (should_set_clock(safe_to_lower,
154 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
155 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
156 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
157 }
158
159 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
160 // Do not adjust dppclk if dppclk is 0 to avoid unexpected result
161 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
162 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
163 new_clocks->dppclk_khz = 100000;
164 }
165
166 /*
167 * Temporally ignore thew 0 cases for disp and dpp clks.
168 * We may have a new feature that requires 0 clks in the future.
169 */
170 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
171 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
172 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
173 }
174
175 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
176 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
177 dpp_clock_lowered = true;
178 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
179 update_dppclk = true;
180 }
181
182 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
183 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
184 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
185
186 update_dispclk = true;
187 }
188
189 if (dpp_clock_lowered) {
190 // increase per DPP DTO before lowering global dppclk
191 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
192 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
193 } else {
194 // increase global DPPCLK before lowering per DPP DTO
195 if (update_dppclk || update_dispclk)
196 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
197 // always update dtos unless clock is lowered and not safe to lower
198 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
199 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
200 }
201
202 if (update_dispclk &&
203 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
204 /*update dmcu for wait_loop count*/
205 dmcu->funcs->set_psr_wait_loop(dmcu,
206 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
207 }
208 }
209
210
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)211 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
212 {
213 /* get FbMult value */
214 struct fixed31_32 pll_req;
215 unsigned int fbmult_frac_val = 0;
216 unsigned int fbmult_int_val = 0;
217
218
219 /*
220 * Register value of fbmult is in 8.16 format, we are converting to 31.32
221 * to leverage the fix point operations available in driver
222 */
223
224 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
225 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
226
227 pll_req = dc_fixpt_from_int(fbmult_int_val);
228
229 /*
230 * since fractional part is only 16 bit in register definition but is 32 bit
231 * in our fix point definiton, need to shift left by 16 to obtain correct value
232 */
233 pll_req.value |= fbmult_frac_val << 16;
234
235 /* multiply by REFCLK period */
236 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
237
238 /* integer part is now VCO frequency in kHz */
239 return dc_fixpt_floor(pll_req);
240 }
241
rn_dump_clk_registers_internal(struct rn_clk_internal * internal,struct clk_mgr * clk_mgr_base)242 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
243 {
244 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
245
246 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
247 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
248
249 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider
250 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
251
252 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
253 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
254
255 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
256 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
257
258 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
259 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
260 }
261
262 /* This function collect raw clk register values */
rn_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)263 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
264 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
265 {
266 struct rn_clk_internal internal = {0};
267 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
268 unsigned int chars_printed = 0;
269 unsigned int remaining_buffer = log_info->bufSize;
270
271 rn_dump_clk_registers_internal(&internal, clk_mgr_base);
272
273 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
274 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
275 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
276 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
277 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
278 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
279
280 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
281 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
282 regs_and_bypass->dppclk_bypass = 0;
283 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
284 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
285 regs_and_bypass->dcfclk_bypass = 0;
286 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
287 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
288 regs_and_bypass->dispclk_bypass = 0;
289 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
290 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
291 regs_and_bypass->dprefclk_bypass = 0;
292
293 if (log_info->enabled) {
294 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
295 remaining_buffer -= chars_printed;
296 *log_info->sum_chars_printed += chars_printed;
297 log_info->pBuf += chars_printed;
298
299 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
300 regs_and_bypass->dcfclk,
301 regs_and_bypass->dcf_deep_sleep_divider,
302 regs_and_bypass->dcf_deep_sleep_allow,
303 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
304 remaining_buffer -= chars_printed;
305 *log_info->sum_chars_printed += chars_printed;
306 log_info->pBuf += chars_printed;
307
308 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
309 regs_and_bypass->dprefclk,
310 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
311 remaining_buffer -= chars_printed;
312 *log_info->sum_chars_printed += chars_printed;
313 log_info->pBuf += chars_printed;
314
315 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
316 regs_and_bypass->dispclk,
317 bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
318 remaining_buffer -= chars_printed;
319 *log_info->sum_chars_printed += chars_printed;
320 log_info->pBuf += chars_printed;
321
322 //split
323 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
324 remaining_buffer -= chars_printed;
325 *log_info->sum_chars_printed += chars_printed;
326 log_info->pBuf += chars_printed;
327
328 // REGISTER VALUES
329 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
330 remaining_buffer -= chars_printed;
331 *log_info->sum_chars_printed += chars_printed;
332 log_info->pBuf += chars_printed;
333
334 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
335 internal.CLK1_CLK3_CURRENT_CNT);
336 remaining_buffer -= chars_printed;
337 *log_info->sum_chars_printed += chars_printed;
338 log_info->pBuf += chars_printed;
339
340 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
341 internal.CLK1_CLK3_DS_CNTL);
342 remaining_buffer -= chars_printed;
343 *log_info->sum_chars_printed += chars_printed;
344 log_info->pBuf += chars_printed;
345
346 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
347 internal.CLK1_CLK3_ALLOW_DS);
348 remaining_buffer -= chars_printed;
349 *log_info->sum_chars_printed += chars_printed;
350 log_info->pBuf += chars_printed;
351
352 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
353 internal.CLK1_CLK2_CURRENT_CNT);
354 remaining_buffer -= chars_printed;
355 *log_info->sum_chars_printed += chars_printed;
356 log_info->pBuf += chars_printed;
357
358 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
359 internal.CLK1_CLK0_CURRENT_CNT);
360 remaining_buffer -= chars_printed;
361 *log_info->sum_chars_printed += chars_printed;
362 log_info->pBuf += chars_printed;
363
364 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
365 internal.CLK1_CLK1_CURRENT_CNT);
366 remaining_buffer -= chars_printed;
367 *log_info->sum_chars_printed += chars_printed;
368 log_info->pBuf += chars_printed;
369
370 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
371 internal.CLK1_CLK3_BYPASS_CNTL);
372 remaining_buffer -= chars_printed;
373 *log_info->sum_chars_printed += chars_printed;
374 log_info->pBuf += chars_printed;
375
376 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
377 internal.CLK1_CLK2_BYPASS_CNTL);
378 remaining_buffer -= chars_printed;
379 *log_info->sum_chars_printed += chars_printed;
380 log_info->pBuf += chars_printed;
381
382 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
383 internal.CLK1_CLK0_BYPASS_CNTL);
384 remaining_buffer -= chars_printed;
385 *log_info->sum_chars_printed += chars_printed;
386 log_info->pBuf += chars_printed;
387
388 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
389 internal.CLK1_CLK1_BYPASS_CNTL);
390 remaining_buffer -= chars_printed;
391 *log_info->sum_chars_printed += chars_printed;
392 log_info->pBuf += chars_printed;
393 }
394 }
395
396 /* This function produce translated logical clk state values*/
rn_get_clk_states(struct clk_mgr * clk_mgr_base,struct clk_states * s)397 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
398 {
399 struct clk_state_registers_and_bypass sb = { 0 };
400 struct clk_log_info log_info = { 0 };
401
402 rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
403
404 s->dprefclk_khz = sb.dprefclk * 1000;
405 }
406
rn_enable_pme_wa(struct clk_mgr * clk_mgr_base)407 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
408 {
409 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
410
411 rn_vbios_smu_enable_pme_wa(clk_mgr);
412 }
413
rn_init_clocks(struct clk_mgr * clk_mgr)414 void rn_init_clocks(struct clk_mgr *clk_mgr)
415 {
416 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
417 // Assumption is that boot state always supports pstate
418 clk_mgr->clks.p_state_change_support = true;
419 clk_mgr->clks.prev_p_state_change_support = true;
420 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
421 }
422
build_watermark_ranges(struct clk_bw_params * bw_params,struct pp_smu_wm_range_sets * ranges)423 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
424 {
425 int i, num_valid_sets;
426
427 num_valid_sets = 0;
428
429 for (i = 0; i < WM_SET_COUNT; i++) {
430 /* skip empty entries, the smu array has no holes*/
431 if (!bw_params->wm_table.entries[i].valid)
432 continue;
433
434 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
435 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
436 /* We will not select WM based on fclk, so leave it as unconstrained */
437 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
438 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
439 /* dcfclk wil be used to select WM*/
440
441 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
442 if (i == 0)
443 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
444 else {
445 /* add 1 to make it non-overlapping with next lvl */
446 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
447 }
448 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
449
450 } else {
451 /* unconstrained for memory retraining */
452 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
453 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
454
455 /* Modify previous watermark range to cover up to max */
456 ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
457 }
458 num_valid_sets++;
459 }
460
461 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
462 ranges->num_reader_wm_sets = num_valid_sets;
463
464 /* modify the min and max to make sure we cover the whole range*/
465 ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
466 ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
467 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
468 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
469
470 /* This is for writeback only, does not matter currently as no writeback support*/
471 ranges->num_writer_wm_sets = 1;
472 ranges->writer_wm_sets[0].wm_inst = WM_A;
473 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
474 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
475 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
476 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
477
478 }
479
rn_notify_wm_ranges(struct clk_mgr * clk_mgr_base)480 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
481 {
482 struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
483 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
484 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
485
486 if (!debug->disable_pplib_wm_range) {
487 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
488
489 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
490 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
491 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);
492 }
493
494 }
495
rn_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)496 static bool rn_are_clock_states_equal(struct dc_clocks *a,
497 struct dc_clocks *b)
498 {
499 if (a->dispclk_khz != b->dispclk_khz)
500 return false;
501 else if (a->dppclk_khz != b->dppclk_khz)
502 return false;
503 else if (a->dcfclk_khz != b->dcfclk_khz)
504 return false;
505 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
506 return false;
507
508 return true;
509 }
510
511
512 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
rn_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link)513 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
514 {
515 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
516 unsigned int i, max_phyclk_req = 0;
517
518 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
519
520 for (i = 0; i < MAX_PIPES * 2; i++) {
521 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
522 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
523 }
524
525 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
526 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
527 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
528 }
529 }
530
531 static struct clk_mgr_funcs dcn21_funcs = {
532 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
533 .update_clocks = rn_update_clocks,
534 .init_clocks = rn_init_clocks,
535 .enable_pme_wa = rn_enable_pme_wa,
536 .are_clock_states_equal = rn_are_clock_states_equal,
537 .set_low_power_state = rn_set_low_power_state,
538 .notify_wm_ranges = rn_notify_wm_ranges,
539 .notify_link_rate_change = rn_notify_link_rate_change,
540 };
541
542 static struct clk_bw_params rn_bw_params = {
543 .vram_type = Ddr4MemType,
544 .num_channels = 1,
545 .clk_table = {
546 .entries = {
547 {
548 .voltage = 0,
549 .dcfclk_mhz = 400,
550 .fclk_mhz = 400,
551 .memclk_mhz = 800,
552 .socclk_mhz = 0,
553 },
554 {
555 .voltage = 0,
556 .dcfclk_mhz = 483,
557 .fclk_mhz = 800,
558 .memclk_mhz = 1600,
559 .socclk_mhz = 0,
560 },
561 {
562 .voltage = 0,
563 .dcfclk_mhz = 602,
564 .fclk_mhz = 1067,
565 .memclk_mhz = 1067,
566 .socclk_mhz = 0,
567 },
568 {
569 .voltage = 0,
570 .dcfclk_mhz = 738,
571 .fclk_mhz = 1333,
572 .memclk_mhz = 1600,
573 .socclk_mhz = 0,
574 },
575 },
576
577 .num_entries = 4,
578 },
579
580 };
581
582 static struct wm_table ddr4_wm_table_gs = {
583 .entries = {
584 {
585 .wm_inst = WM_A,
586 .wm_type = WM_TYPE_PSTATE_CHG,
587 .pstate_latency_us = 11.72,
588 .sr_exit_time_us = 6.09,
589 .sr_enter_plus_exit_time_us = 7.14,
590 .valid = true,
591 },
592 {
593 .wm_inst = WM_B,
594 .wm_type = WM_TYPE_PSTATE_CHG,
595 .pstate_latency_us = 11.72,
596 .sr_exit_time_us = 10.12,
597 .sr_enter_plus_exit_time_us = 11.48,
598 .valid = true,
599 },
600 {
601 .wm_inst = WM_C,
602 .wm_type = WM_TYPE_PSTATE_CHG,
603 .pstate_latency_us = 11.72,
604 .sr_exit_time_us = 10.12,
605 .sr_enter_plus_exit_time_us = 11.48,
606 .valid = true,
607 },
608 {
609 .wm_inst = WM_D,
610 .wm_type = WM_TYPE_PSTATE_CHG,
611 .pstate_latency_us = 11.72,
612 .sr_exit_time_us = 10.12,
613 .sr_enter_plus_exit_time_us = 11.48,
614 .valid = true,
615 },
616 }
617 };
618
619 static struct wm_table lpddr4_wm_table_gs = {
620 .entries = {
621 {
622 .wm_inst = WM_A,
623 .wm_type = WM_TYPE_PSTATE_CHG,
624 .pstate_latency_us = 11.65333,
625 .sr_exit_time_us = 5.32,
626 .sr_enter_plus_exit_time_us = 6.38,
627 .valid = true,
628 },
629 {
630 .wm_inst = WM_B,
631 .wm_type = WM_TYPE_PSTATE_CHG,
632 .pstate_latency_us = 11.65333,
633 .sr_exit_time_us = 9.82,
634 .sr_enter_plus_exit_time_us = 11.196,
635 .valid = true,
636 },
637 {
638 .wm_inst = WM_C,
639 .wm_type = WM_TYPE_PSTATE_CHG,
640 .pstate_latency_us = 11.65333,
641 .sr_exit_time_us = 9.89,
642 .sr_enter_plus_exit_time_us = 11.24,
643 .valid = true,
644 },
645 {
646 .wm_inst = WM_D,
647 .wm_type = WM_TYPE_PSTATE_CHG,
648 .pstate_latency_us = 11.65333,
649 .sr_exit_time_us = 9.748,
650 .sr_enter_plus_exit_time_us = 11.102,
651 .valid = true,
652 },
653 }
654 };
655
656 static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
657 .entries = {
658 {
659 .wm_inst = WM_A,
660 .wm_type = WM_TYPE_PSTATE_CHG,
661 .pstate_latency_us = 11.65333,
662 .sr_exit_time_us = 8.32,
663 .sr_enter_plus_exit_time_us = 9.38,
664 .valid = true,
665 },
666 {
667 .wm_inst = WM_B,
668 .wm_type = WM_TYPE_PSTATE_CHG,
669 .pstate_latency_us = 11.65333,
670 .sr_exit_time_us = 9.82,
671 .sr_enter_plus_exit_time_us = 11.196,
672 .valid = true,
673 },
674 {
675 .wm_inst = WM_C,
676 .wm_type = WM_TYPE_PSTATE_CHG,
677 .pstate_latency_us = 11.65333,
678 .sr_exit_time_us = 9.89,
679 .sr_enter_plus_exit_time_us = 11.24,
680 .valid = true,
681 },
682 {
683 .wm_inst = WM_D,
684 .wm_type = WM_TYPE_PSTATE_CHG,
685 .pstate_latency_us = 11.65333,
686 .sr_exit_time_us = 9.748,
687 .sr_enter_plus_exit_time_us = 11.102,
688 .valid = true,
689 },
690 }
691 };
692
693 static struct wm_table ddr4_wm_table_rn = {
694 .entries = {
695 {
696 .wm_inst = WM_A,
697 .wm_type = WM_TYPE_PSTATE_CHG,
698 .pstate_latency_us = 11.72,
699 .sr_exit_time_us = 9.09,
700 .sr_enter_plus_exit_time_us = 10.14,
701 .valid = true,
702 },
703 {
704 .wm_inst = WM_B,
705 .wm_type = WM_TYPE_PSTATE_CHG,
706 .pstate_latency_us = 11.72,
707 .sr_exit_time_us = 10.12,
708 .sr_enter_plus_exit_time_us = 11.48,
709 .valid = true,
710 },
711 {
712 .wm_inst = WM_C,
713 .wm_type = WM_TYPE_PSTATE_CHG,
714 .pstate_latency_us = 11.72,
715 .sr_exit_time_us = 10.12,
716 .sr_enter_plus_exit_time_us = 11.48,
717 .valid = true,
718 },
719 {
720 .wm_inst = WM_D,
721 .wm_type = WM_TYPE_PSTATE_CHG,
722 .pstate_latency_us = 11.72,
723 .sr_exit_time_us = 10.12,
724 .sr_enter_plus_exit_time_us = 11.48,
725 .valid = true,
726 },
727 }
728 };
729
730 static struct wm_table lpddr4_wm_table_rn = {
731 .entries = {
732 {
733 .wm_inst = WM_A,
734 .wm_type = WM_TYPE_PSTATE_CHG,
735 .pstate_latency_us = 11.65333,
736 .sr_exit_time_us = 7.32,
737 .sr_enter_plus_exit_time_us = 8.38,
738 .valid = true,
739 },
740 {
741 .wm_inst = WM_B,
742 .wm_type = WM_TYPE_PSTATE_CHG,
743 .pstate_latency_us = 11.65333,
744 .sr_exit_time_us = 9.82,
745 .sr_enter_plus_exit_time_us = 11.196,
746 .valid = true,
747 },
748 {
749 .wm_inst = WM_C,
750 .wm_type = WM_TYPE_PSTATE_CHG,
751 .pstate_latency_us = 11.65333,
752 .sr_exit_time_us = 9.89,
753 .sr_enter_plus_exit_time_us = 11.24,
754 .valid = true,
755 },
756 {
757 .wm_inst = WM_D,
758 .wm_type = WM_TYPE_PSTATE_CHG,
759 .pstate_latency_us = 11.65333,
760 .sr_exit_time_us = 9.748,
761 .sr_enter_plus_exit_time_us = 11.102,
762 .valid = true,
763 },
764 }
765 };
766
find_dcfclk_for_voltage(struct dpm_clocks * clock_table,unsigned int voltage)767 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
768 {
769 int i;
770
771 for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
772 if (clock_table->DcfClocks[i].Vol == voltage)
773 return clock_table->DcfClocks[i].Freq;
774 }
775
776 ASSERT(0);
777 return 0;
778 }
779
rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params * bw_params,struct dpm_clocks * clock_table,struct integrated_info * bios_info)780 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
781 {
782 int i, j = 0;
783
784 j = -1;
785
786 ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
787
788 /* Find lowest DPM, FCLK is filled in reverse order*/
789
790 for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
791 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) {
792 j = i;
793 break;
794 }
795 }
796
797 if (j == -1) {
798 /* clock table is all 0s, just use our own hardcode */
799 ASSERT(0);
800 return;
801 }
802
803 bw_params->clk_table.num_entries = j + 1;
804
805 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
806 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
807 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
808 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
809 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
810 }
811
812 bw_params->vram_type = bios_info->memory_type;
813 bw_params->num_channels = bios_info->ma_channel_number;
814
815 for (i = 0; i < WM_SET_COUNT; i++) {
816 bw_params->wm_table.entries[i].wm_inst = i;
817
818 if (i >= bw_params->clk_table.num_entries) {
819 bw_params->wm_table.entries[i].valid = false;
820 continue;
821 }
822
823 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
824 bw_params->wm_table.entries[i].valid = true;
825 }
826
827 if (bw_params->vram_type == LpDdr4MemType) {
828 /*
829 * WM set D will be re-purposed for memory retraining
830 */
831 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
832 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
833 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
834 bw_params->wm_table.entries[WM_D].valid = true;
835 }
836
837 }
838
rn_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)839 void rn_clk_mgr_construct(
840 struct dc_context *ctx,
841 struct clk_mgr_internal *clk_mgr,
842 struct pp_smu_funcs *pp_smu,
843 struct dccg *dccg)
844 {
845 struct dc_debug_options *debug = &ctx->dc->debug;
846 struct dpm_clocks clock_table = { 0 };
847 enum pp_smu_status status = 0;
848 int is_green_sardine = 0;
849
850 #if defined(CONFIG_DRM_AMD_DC_DCN)
851 is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
852 #endif
853
854 clk_mgr->base.ctx = ctx;
855 clk_mgr->base.funcs = &dcn21_funcs;
856
857 clk_mgr->pp_smu = pp_smu;
858
859 clk_mgr->dccg = dccg;
860 clk_mgr->dfs_bypass_disp_clk = 0;
861
862 clk_mgr->dprefclk_ss_percentage = 0;
863 clk_mgr->dprefclk_ss_divider = 1000;
864 clk_mgr->ss_on_dprefclk = false;
865 clk_mgr->dfs_ref_freq_khz = 48000;
866
867 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
868
869 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
870 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
871 clk_mgr->base.dentist_vco_freq_khz = 3600000;
872 } else {
873 struct clk_log_info log_info = {0};
874
875 clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
876
877 /* SMU Version 55.51.0 and up no longer have an issue
878 * that needs to limit minimum dispclk */
879 if (clk_mgr->smu_ver >= SMU_VER_55_51_0)
880 debug->min_disp_clk_khz = 0;
881
882 /* TODO: Check we get what we expect during bringup */
883 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
884
885 /* in case we don't get a value from the register, use default */
886 if (clk_mgr->base.dentist_vco_freq_khz == 0)
887 clk_mgr->base.dentist_vco_freq_khz = 3600000;
888
889 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
890 if (clk_mgr->periodic_retraining_disabled) {
891 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
892 } else {
893 if (is_green_sardine)
894 rn_bw_params.wm_table = lpddr4_wm_table_gs;
895 else
896 rn_bw_params.wm_table = lpddr4_wm_table_rn;
897 }
898 } else {
899 if (is_green_sardine)
900 rn_bw_params.wm_table = ddr4_wm_table_gs;
901 else
902 rn_bw_params.wm_table = ddr4_wm_table_rn;
903 }
904 /* Saved clocks configured at boot for debug purposes */
905 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
906 }
907
908 clk_mgr->base.dprefclk_khz = 600000;
909 dce_clock_read_ss_info(clk_mgr);
910
911
912 clk_mgr->base.bw_params = &rn_bw_params;
913
914 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
915 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
916
917 if (status == PP_SMU_RESULT_OK &&
918 ctx->dc_bios && ctx->dc_bios->integrated_info) {
919 rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
920 }
921 }
922
923 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
924 /* enable powerfeatures when displaycount goes to 0 */
925 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
926 }
927 }
928
929