1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "rk3399_vpu_regs.h"
14
15 #define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
16
17 /*
18 * Supported formats.
19 */
20
21 static const struct hantro_fmt rk3399_vpu_enc_fmts[] = {
22 {
23 .fourcc = V4L2_PIX_FMT_YUV420M,
24 .codec_mode = HANTRO_MODE_NONE,
25 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
26 },
27 {
28 .fourcc = V4L2_PIX_FMT_NV12M,
29 .codec_mode = HANTRO_MODE_NONE,
30 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
31 },
32 {
33 .fourcc = V4L2_PIX_FMT_YUYV,
34 .codec_mode = HANTRO_MODE_NONE,
35 .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
36 },
37 {
38 .fourcc = V4L2_PIX_FMT_UYVY,
39 .codec_mode = HANTRO_MODE_NONE,
40 .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
41 },
42 {
43 .fourcc = V4L2_PIX_FMT_JPEG,
44 .codec_mode = HANTRO_MODE_JPEG_ENC,
45 .max_depth = 2,
46 .header_size = JPEG_HEADER_SIZE,
47 .frmsize = {
48 .min_width = 96,
49 .max_width = 8192,
50 .step_width = MB_DIM,
51 .min_height = 32,
52 .max_height = 8192,
53 .step_height = MB_DIM,
54 },
55 },
56 };
57
58 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
59 {
60 .fourcc = V4L2_PIX_FMT_NV12,
61 .codec_mode = HANTRO_MODE_NONE,
62 },
63 {
64 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
65 .codec_mode = HANTRO_MODE_MPEG2_DEC,
66 .max_depth = 2,
67 .frmsize = {
68 .min_width = 48,
69 .max_width = 1920,
70 .step_width = MB_DIM,
71 .min_height = 48,
72 .max_height = 1088,
73 .step_height = MB_DIM,
74 },
75 },
76 {
77 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
78 .codec_mode = HANTRO_MODE_VP8_DEC,
79 .max_depth = 2,
80 .frmsize = {
81 .min_width = 48,
82 .max_width = 3840,
83 .step_width = MB_DIM,
84 .min_height = 48,
85 .max_height = 2160,
86 .step_height = MB_DIM,
87 },
88 },
89 };
90
rk3399_vepu_irq(int irq,void * dev_id)91 static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)
92 {
93 struct hantro_dev *vpu = dev_id;
94 enum vb2_buffer_state state;
95 u32 status;
96
97 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
98 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
99 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
100
101 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
102 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
103
104 hantro_irq_done(vpu, state);
105
106 return IRQ_HANDLED;
107 }
108
rk3399_vdpu_irq(int irq,void * dev_id)109 static irqreturn_t rk3399_vdpu_irq(int irq, void *dev_id)
110 {
111 struct hantro_dev *vpu = dev_id;
112 enum vb2_buffer_state state;
113 u32 status;
114
115 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
116 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
117 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
118
119 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
120 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
121
122 hantro_irq_done(vpu, state);
123
124 return IRQ_HANDLED;
125 }
126
rk3399_vpu_hw_init(struct hantro_dev * vpu)127 static int rk3399_vpu_hw_init(struct hantro_dev *vpu)
128 {
129 /* Bump ACLK to max. possible freq. to improve performance. */
130 clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
131 return 0;
132 }
133
rk3399_vpu_enc_reset(struct hantro_ctx * ctx)134 static void rk3399_vpu_enc_reset(struct hantro_ctx *ctx)
135 {
136 struct hantro_dev *vpu = ctx->dev;
137
138 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
139 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
140 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
141 }
142
rk3399_vpu_dec_reset(struct hantro_ctx * ctx)143 static void rk3399_vpu_dec_reset(struct hantro_ctx *ctx)
144 {
145 struct hantro_dev *vpu = ctx->dev;
146
147 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
148 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
149 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
150 }
151
152 /*
153 * Supported codec ops.
154 */
155
156 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
157 [HANTRO_MODE_JPEG_ENC] = {
158 .run = rk3399_vpu_jpeg_enc_run,
159 .reset = rk3399_vpu_enc_reset,
160 .init = hantro_jpeg_enc_init,
161 .exit = hantro_jpeg_enc_exit,
162 },
163 [HANTRO_MODE_MPEG2_DEC] = {
164 .run = rk3399_vpu_mpeg2_dec_run,
165 .reset = rk3399_vpu_dec_reset,
166 .init = hantro_mpeg2_dec_init,
167 .exit = hantro_mpeg2_dec_exit,
168 },
169 [HANTRO_MODE_VP8_DEC] = {
170 .run = rk3399_vpu_vp8_dec_run,
171 .reset = rk3399_vpu_dec_reset,
172 .init = hantro_vp8_dec_init,
173 .exit = hantro_vp8_dec_exit,
174 },
175 };
176
177 /*
178 * VPU variant.
179 */
180
181 static const struct hantro_irq rk3399_irqs[] = {
182 { "vepu", rk3399_vepu_irq },
183 { "vdpu", rk3399_vdpu_irq },
184 };
185
186 static const char * const rk3399_clk_names[] = {
187 "aclk", "hclk"
188 };
189
190 const struct hantro_variant rk3399_vpu_variant = {
191 .enc_offset = 0x0,
192 .enc_fmts = rk3399_vpu_enc_fmts,
193 .num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
194 .dec_offset = 0x400,
195 .dec_fmts = rk3399_vpu_dec_fmts,
196 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
197 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
198 HANTRO_VP8_DECODER,
199 .codec_ops = rk3399_vpu_codec_ops,
200 .irqs = rk3399_irqs,
201 .num_irqs = ARRAY_SIZE(rk3399_irqs),
202 .init = rk3399_vpu_hw_init,
203 .clk_names = rk3399_clk_names,
204 .num_clocks = ARRAY_SIZE(rk3399_clk_names)
205 };
206
207 static const struct hantro_irq rk3328_irqs[] = {
208 { "vdpu", rk3399_vdpu_irq },
209 };
210
211 const struct hantro_variant rk3328_vpu_variant = {
212 .dec_offset = 0x400,
213 .dec_fmts = rk3399_vpu_dec_fmts,
214 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
215 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
216 .codec_ops = rk3399_vpu_codec_ops,
217 .irqs = rk3328_irqs,
218 .num_irqs = ARRAY_SIZE(rk3328_irqs),
219 .init = rk3399_vpu_hw_init,
220 .clk_names = rk3399_clk_names,
221 .num_clocks = ARRAY_SIZE(rk3399_clk_names),
222 };
223