1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <linux/soc/mediatek/mtk_wed.h> 18 #include <net/mac80211.h> 19 #include <net/page_pool/helpers.h> 20 #include "util.h" 21 #include "testmode.h" 22 23 #define MT_MCU_RING_SIZE 32 24 #define MT_RX_BUF_SIZE 2048 25 #define MT_SKB_HEAD_LEN 256 26 27 #define MT_MAX_NON_AQL_PKT 16 28 #define MT_TXQ_FREE_THR 32 29 30 #define MT76_TOKEN_FREE_THR 64 31 32 #define MT_QFLAG_WED_RING GENMASK(1, 0) 33 #define MT_QFLAG_WED_TYPE GENMASK(4, 2) 34 #define MT_QFLAG_WED BIT(5) 35 #define MT_QFLAG_WED_RRO BIT(6) 36 #define MT_QFLAG_WED_RRO_EN BIT(7) 37 #define MT_QFLAG_EMI_EN BIT(8) 38 #define MT_QFLAG_NPU BIT(9) 39 40 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 41 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 42 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 43 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n)) 44 45 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 46 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 47 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 48 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 49 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 50 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 51 #define MT_WED_RRO_Q_RXDMAD_C __MT_WED_RRO_Q(MT76_WED_RRO_Q_RXDMAD_C, 0) 52 53 #define __MT_NPU_Q(_type, _n) (MT_QFLAG_NPU | \ 54 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 55 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 56 #define MT_NPU_Q_TX(_n) __MT_NPU_Q(MT76_WED_Q_TX, _n) 57 #define MT_NPU_Q_RX(_n) __MT_NPU_Q(MT76_WED_Q_RX, _n) 58 #define MT_NPU_Q_TXFREE(_n) (FIELD_PREP(MT_QFLAG_WED_TYPE, MT76_WED_Q_TXFREE) | \ 59 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 60 61 struct mt76_dev; 62 struct mt76_phy; 63 struct mt76_wcid; 64 struct mt76s_intr; 65 struct mt76_chanctx; 66 struct mt76_vif_link; 67 68 struct mt76_reg_pair { 69 u32 reg; 70 u32 value; 71 }; 72 73 enum mt76_bus_type { 74 MT76_BUS_MMIO, 75 MT76_BUS_USB, 76 MT76_BUS_SDIO, 77 }; 78 79 enum mt76_wed_type { 80 MT76_WED_Q_TX, 81 MT76_WED_Q_TXFREE, 82 MT76_WED_Q_RX, 83 MT76_WED_RRO_Q_DATA, 84 MT76_WED_RRO_Q_MSDU_PG, 85 MT76_WED_RRO_Q_IND, 86 MT76_WED_RRO_Q_RXDMAD_C, 87 }; 88 89 enum mt76_hwrro_mode { 90 MT76_HWRRO_OFF, 91 MT76_HWRRO_V3, 92 MT76_HWRRO_V3_1, 93 }; 94 95 struct mt76_bus_ops { 96 u32 (*rr)(struct mt76_dev *dev, u32 offset); 97 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 98 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 99 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 100 int len); 101 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 102 int len); 103 int (*wr_rp)(struct mt76_dev *dev, u32 base, 104 const struct mt76_reg_pair *rp, int len); 105 int (*rd_rp)(struct mt76_dev *dev, u32 base, 106 struct mt76_reg_pair *rp, int len); 107 enum mt76_bus_type type; 108 }; 109 110 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 111 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 112 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 113 114 enum mt76_txq_id { 115 MT_TXQ_VO = IEEE80211_AC_VO, 116 MT_TXQ_VI = IEEE80211_AC_VI, 117 MT_TXQ_BE = IEEE80211_AC_BE, 118 MT_TXQ_BK = IEEE80211_AC_BK, 119 MT_TXQ_PSD, 120 MT_TXQ_BEACON, 121 MT_TXQ_CAB, 122 __MT_TXQ_MAX 123 }; 124 125 enum mt76_mcuq_id { 126 MT_MCUQ_WM, 127 MT_MCUQ_WA, 128 MT_MCUQ_FWDL, 129 __MT_MCUQ_MAX 130 }; 131 132 enum mt76_rxq_id { 133 MT_RXQ_MAIN, 134 MT_RXQ_MCU, 135 MT_RXQ_MCU_WA, 136 MT_RXQ_BAND1, 137 MT_RXQ_BAND1_WA, 138 MT_RXQ_MAIN_WA, 139 MT_RXQ_BAND2, 140 MT_RXQ_BAND2_WA, 141 MT_RXQ_RRO_BAND0, 142 MT_RXQ_RRO_BAND1, 143 MT_RXQ_RRO_BAND2, 144 MT_RXQ_MSDU_PAGE_BAND0, 145 MT_RXQ_MSDU_PAGE_BAND1, 146 MT_RXQ_MSDU_PAGE_BAND2, 147 MT_RXQ_TXFREE_BAND0, 148 MT_RXQ_TXFREE_BAND1, 149 MT_RXQ_TXFREE_BAND2, 150 MT_RXQ_RRO_IND, 151 MT_RXQ_RRO_RXDMAD_C, 152 MT_RXQ_NPU0, 153 MT_RXQ_NPU1, 154 __MT_RXQ_MAX 155 }; 156 157 enum mt76_band_id { 158 MT_BAND0, 159 MT_BAND1, 160 MT_BAND2, 161 __MT_MAX_BAND 162 }; 163 164 enum mt76_cipher_type { 165 MT_CIPHER_NONE, 166 MT_CIPHER_WEP40, 167 MT_CIPHER_TKIP, 168 MT_CIPHER_TKIP_NO_MIC, 169 MT_CIPHER_AES_CCMP, 170 MT_CIPHER_WEP104, 171 MT_CIPHER_BIP_CMAC_128, 172 MT_CIPHER_WEP128, 173 MT_CIPHER_WAPI, 174 MT_CIPHER_CCMP_CCX, 175 MT_CIPHER_CCMP_256, 176 MT_CIPHER_GCMP, 177 MT_CIPHER_GCMP_256, 178 }; 179 180 enum mt76_dfs_state { 181 MT_DFS_STATE_UNKNOWN, 182 MT_DFS_STATE_DISABLED, 183 MT_DFS_STATE_CAC, 184 MT_DFS_STATE_ACTIVE, 185 }; 186 187 #define MT76_RNR_SCAN_MAX_BSSIDS 16 188 struct mt76_scan_rnr_param { 189 u8 bssid[MT76_RNR_SCAN_MAX_BSSIDS][ETH_ALEN]; 190 u8 channel[MT76_RNR_SCAN_MAX_BSSIDS]; 191 u8 random_mac[ETH_ALEN]; 192 u8 seq_num; 193 u8 bssid_num; 194 u32 sreq_flag; 195 }; 196 197 struct mt76_queue_buf { 198 dma_addr_t addr; 199 u16 len:15, 200 skip_unmap:1; 201 }; 202 203 struct mt76_tx_info { 204 struct mt76_queue_buf buf[32]; 205 struct sk_buff *skb; 206 int nbuf; 207 u32 info; 208 }; 209 210 struct mt76_queue_entry { 211 union { 212 void *buf; 213 struct sk_buff *skb; 214 }; 215 union { 216 struct mt76_txwi_cache *txwi; 217 struct urb *urb; 218 int buf_sz; 219 }; 220 dma_addr_t dma_addr[2]; 221 u16 dma_len[2]; 222 u16 wcid; 223 bool skip_buf0:1; 224 bool skip_buf1:1; 225 bool done:1; 226 }; 227 228 struct mt76_queue_regs { 229 u32 desc_base; 230 u32 ring_size; 231 u32 cpu_idx; 232 u32 dma_idx; 233 } __packed __aligned(4); 234 235 struct mt76_queue { 236 struct mt76_queue_regs __iomem *regs; 237 238 spinlock_t lock; 239 spinlock_t cleanup_lock; 240 struct mt76_queue_entry *entry; 241 struct mt76_rro_desc *rro_desc; 242 struct mt76_desc *desc; 243 244 u16 first; 245 u16 head; 246 u16 tail; 247 u8 hw_idx; 248 u8 ep; 249 int ndesc; 250 int queued; 251 int buf_size; 252 bool stopped; 253 bool blocked; 254 255 u8 buf_offset; 256 u16 flags; 257 u8 magic_cnt; 258 259 __le16 *emi_cpu_idx; 260 261 struct mtk_wed_device *wed; 262 struct mt76_dev *dev; 263 u32 wed_regs; 264 265 dma_addr_t desc_dma; 266 struct sk_buff *rx_head; 267 struct page_pool *page_pool; 268 }; 269 270 struct mt76_mcu_ops { 271 unsigned int max_retry; 272 u32 headroom; 273 u32 tailroom; 274 275 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 276 int len, bool wait_resp); 277 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb, 278 int cmd, int *seq); 279 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 280 int cmd, int *seq); 281 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 282 struct sk_buff *skb, int seq); 283 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 284 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 285 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 286 const struct mt76_reg_pair *rp, int len); 287 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 288 struct mt76_reg_pair *rp, int len); 289 int (*mcu_restart)(struct mt76_dev *dev); 290 }; 291 292 struct mt76_queue_ops { 293 int (*init)(struct mt76_dev *dev, 294 int (*poll)(struct napi_struct *napi, int budget)); 295 296 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 297 int idx, int n_desc, int bufsize, 298 u32 ring_base); 299 300 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q, 301 enum mt76_txq_id qid, struct sk_buff *skb, 302 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 303 304 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 305 struct sk_buff *skb, u32 tx_info); 306 307 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 308 int *len, u32 *info, bool *more); 309 310 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 311 312 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 313 bool flush); 314 315 void (*rx_queue_init)(struct mt76_dev *dev, enum mt76_rxq_id qid, 316 int (*poll)(struct napi_struct *napi, int budget)); 317 318 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 319 320 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 321 322 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q, 323 bool reset_idx); 324 }; 325 326 enum mt76_phy_type { 327 MT_PHY_TYPE_CCK, 328 MT_PHY_TYPE_OFDM, 329 MT_PHY_TYPE_HT, 330 MT_PHY_TYPE_HT_GF, 331 MT_PHY_TYPE_VHT, 332 MT_PHY_TYPE_HE_SU = 8, 333 MT_PHY_TYPE_HE_EXT_SU, 334 MT_PHY_TYPE_HE_TB, 335 MT_PHY_TYPE_HE_MU, 336 MT_PHY_TYPE_EHT_SU = 13, 337 MT_PHY_TYPE_EHT_TRIG, 338 MT_PHY_TYPE_EHT_MU, 339 __MT_PHY_TYPE_MAX, 340 }; 341 342 struct mt76_sta_stats { 343 u64 tx_mode[__MT_PHY_TYPE_MAX]; 344 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 345 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 346 u64 tx_mcs[16]; /* mcs idx */ 347 u64 tx_bytes; 348 /* WED TX */ 349 u32 tx_packets; /* unit: MSDU */ 350 u32 tx_retries; 351 u32 tx_failed; 352 /* WED RX */ 353 u64 rx_bytes; 354 u32 rx_packets; 355 u32 rx_errors; 356 u32 rx_drops; 357 }; 358 359 enum mt76_wcid_flags { 360 MT_WCID_FLAG_CHECK_PS, 361 MT_WCID_FLAG_PS, 362 MT_WCID_FLAG_4ADDR, 363 MT_WCID_FLAG_HDR_TRANS, 364 }; 365 366 #define MT76_N_WCIDS 1088 367 #define MT76_BEACON_MON_MAX_MISS 7 368 369 /* stored in ieee80211_tx_info::hw_queue */ 370 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 371 372 DECLARE_EWMA(signal, 10, 8); 373 374 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 375 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 376 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 377 #define MT_WCID_TX_INFO_SET BIT(31) 378 379 struct mt76_wcid { 380 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 381 382 atomic_t non_aql_packets; 383 unsigned long flags; 384 385 struct ewma_signal rssi; 386 int inactive_count; 387 388 struct rate_info rate; 389 unsigned long ampdu_state; 390 391 u16 idx; 392 u8 hw_key_idx; 393 u8 hw_key_idx2; 394 395 u8 offchannel:1; 396 u8 sta:1; 397 u8 sta_disabled:1; 398 u8 amsdu:1; 399 u8 phy_idx:2; 400 u8 link_id:4; 401 bool link_valid; 402 403 u8 rx_check_pn; 404 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 405 u16 cipher; 406 407 u32 tx_info; 408 bool sw_iv; 409 410 struct list_head tx_list; 411 struct sk_buff_head tx_pending; 412 struct sk_buff_head tx_offchannel; 413 414 struct list_head list; 415 struct idr pktid; 416 417 struct mt76_sta_stats stats; 418 419 struct list_head poll_list; 420 421 struct mt76_wcid *def_wcid; 422 }; 423 424 struct mt76_txq { 425 u16 wcid; 426 427 u16 agg_ssn; 428 bool send_bar; 429 bool aggr; 430 }; 431 432 /* data0 */ 433 #define RRO_IND_DATA0_IND_REASON_MASK GENMASK(31, 28) 434 #define RRO_IND_DATA0_START_SEQ_MASK GENMASK(27, 16) 435 #define RRO_IND_DATA0_SEQ_ID_MASK GENMASK(11, 0) 436 /* data1 */ 437 #define RRO_IND_DATA1_MAGIC_CNT_MASK GENMASK(31, 29) 438 #define RRO_IND_DATA1_IND_COUNT_MASK GENMASK(12, 0) 439 struct mt76_wed_rro_ind { 440 __le32 data0; 441 __le32 data1; 442 }; 443 444 struct mt76_txwi_cache { 445 struct list_head list; 446 dma_addr_t dma_addr; 447 448 union { 449 struct sk_buff *skb; 450 void *ptr; 451 }; 452 453 u8 qid; 454 u8 phy_idx; 455 }; 456 457 struct mt76_rx_tid { 458 struct rcu_head rcu_head; 459 460 struct mt76_dev *dev; 461 462 spinlock_t lock; 463 struct delayed_work reorder_work; 464 465 u16 id; 466 u16 head; 467 u16 size; 468 u16 nframes; 469 470 u8 num; 471 472 u8 started:1, stopped:1, timer_pending:1; 473 474 struct sk_buff *reorder_buf[] __counted_by(size); 475 }; 476 477 #define MT_TX_CB_DMA_DONE BIT(0) 478 #define MT_TX_CB_TXS_DONE BIT(1) 479 #define MT_TX_CB_TXS_FAILED BIT(2) 480 481 #define MT_PACKET_ID_MASK GENMASK(6, 0) 482 #define MT_PACKET_ID_NO_ACK 0 483 #define MT_PACKET_ID_NO_SKB 1 484 #define MT_PACKET_ID_WED 2 485 #define MT_PACKET_ID_FIRST 3 486 #define MT_PACKET_ID_HAS_RATE BIT(7) 487 /* This is timer for when to give up when waiting for TXS callback, 488 * with starting time being the time at which the DMA_DONE callback 489 * was seen (so, we know packet was processed then, it should not take 490 * long after that for firmware to send the TXS callback if it is going 491 * to do so.) 492 */ 493 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 494 495 struct mt76_tx_cb { 496 unsigned long jiffies; 497 u16 wcid; 498 u8 pktid; 499 u8 flags; 500 }; 501 502 enum { 503 MT76_STATE_INITIALIZED, 504 MT76_STATE_REGISTERED, 505 MT76_STATE_RUNNING, 506 MT76_STATE_MCU_RUNNING, 507 MT76_SCANNING, 508 MT76_HW_SCANNING, 509 MT76_HW_SCHED_SCANNING, 510 MT76_RESTART, 511 MT76_RESET, 512 MT76_MCU_RESET, 513 MT76_REMOVED, 514 MT76_READING_STATS, 515 MT76_STATE_POWER_OFF, 516 MT76_STATE_SUSPEND, 517 MT76_STATE_ROC, 518 MT76_STATE_PM, 519 MT76_STATE_WED_RESET, 520 }; 521 522 enum mt76_sta_event { 523 MT76_STA_EVENT_ASSOC, 524 MT76_STA_EVENT_AUTHORIZE, 525 MT76_STA_EVENT_DISASSOC, 526 }; 527 528 struct mt76_hw_cap { 529 bool has_2ghz; 530 bool has_5ghz; 531 bool has_6ghz; 532 }; 533 534 #define MT_DRV_TXWI_NO_FREE BIT(0) 535 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 536 #define MT_DRV_SW_RX_AIRTIME BIT(2) 537 #define MT_DRV_RX_DMA_HDR BIT(3) 538 #define MT_DRV_HW_MGMT_TXQ BIT(4) 539 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 540 #define MT_DRV_IGNORE_TXS_FAILED BIT(6) 541 542 struct mt76_driver_ops { 543 u32 drv_flags; 544 u32 survey_flags; 545 u16 txwi_size; 546 u16 token_size; 547 548 unsigned int link_data_size; 549 550 void (*update_survey)(struct mt76_phy *phy); 551 int (*set_channel)(struct mt76_phy *phy); 552 553 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 554 enum mt76_txq_id qid, struct mt76_wcid *wcid, 555 struct ieee80211_sta *sta, 556 struct mt76_tx_info *tx_info); 557 558 void (*tx_complete_skb)(struct mt76_dev *dev, 559 struct mt76_queue_entry *e); 560 561 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 562 563 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 564 565 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 566 struct sk_buff *skb, u32 *info); 567 568 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 569 570 void (*rx_rro_ind_process)(struct mt76_dev *dev, void *data); 571 int (*rx_rro_add_msdu_page)(struct mt76_dev *dev, struct mt76_queue *q, 572 dma_addr_t p, void *data); 573 574 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 575 bool ps); 576 577 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 578 struct ieee80211_sta *sta); 579 580 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif, 581 struct ieee80211_sta *sta, enum mt76_sta_event ev); 582 583 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 584 struct ieee80211_sta *sta); 585 586 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif, 587 struct ieee80211_bss_conf *link_conf, 588 struct mt76_vif_link *mlink); 589 590 void (*vif_link_remove)(struct mt76_phy *phy, 591 struct ieee80211_vif *vif, 592 struct ieee80211_bss_conf *link_conf, 593 struct mt76_vif_link *mlink); 594 }; 595 596 struct mt76_channel_state { 597 u64 cc_active; 598 u64 cc_busy; 599 u64 cc_rx; 600 u64 cc_bss_rx; 601 u64 cc_tx; 602 603 s8 noise; 604 }; 605 606 struct mt76_sband { 607 struct ieee80211_supported_band sband; 608 struct mt76_channel_state *chan; 609 }; 610 611 /* addr req mask */ 612 #define MT_VEND_TYPE_EEPROM BIT(31) 613 #define MT_VEND_TYPE_CFG BIT(30) 614 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 615 616 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 617 enum mt_vendor_req { 618 MT_VEND_DEV_MODE = 0x1, 619 MT_VEND_WRITE = 0x2, 620 MT_VEND_POWER_ON = 0x4, 621 MT_VEND_MULTI_WRITE = 0x6, 622 MT_VEND_MULTI_READ = 0x7, 623 MT_VEND_READ_EEPROM = 0x9, 624 MT_VEND_WRITE_FCE = 0x42, 625 MT_VEND_WRITE_CFG = 0x46, 626 MT_VEND_READ_CFG = 0x47, 627 MT_VEND_READ_EXT = 0x63, 628 MT_VEND_WRITE_EXT = 0x66, 629 MT_VEND_FEATURE_SET = 0x91, 630 }; 631 632 enum mt76u_in_ep { 633 MT_EP_IN_PKT_RX, 634 MT_EP_IN_CMD_RESP, 635 __MT_EP_IN_MAX, 636 }; 637 638 enum mt76u_out_ep { 639 MT_EP_OUT_INBAND_CMD, 640 MT_EP_OUT_AC_BE, 641 MT_EP_OUT_AC_BK, 642 MT_EP_OUT_AC_VI, 643 MT_EP_OUT_AC_VO, 644 MT_EP_OUT_HCCA, 645 __MT_EP_OUT_MAX, 646 }; 647 648 struct mt76_mcu { 649 struct mutex mutex; 650 u32 msg_seq; 651 int timeout; 652 653 struct sk_buff_head res_q; 654 wait_queue_head_t wait; 655 }; 656 657 #define MT_TX_SG_MAX_SIZE 8 658 #define MT_RX_SG_MAX_SIZE 4 659 #define MT_NUM_TX_ENTRIES 256 660 #define MT_NUM_RX_ENTRIES 128 661 #define MCU_RESP_URB_SIZE 1024 662 struct mt76_usb { 663 struct mutex usb_ctrl_mtx; 664 u8 *data; 665 u16 data_len; 666 667 struct mt76_worker status_worker; 668 struct mt76_worker rx_worker; 669 670 struct work_struct stat_work; 671 672 u8 out_ep[__MT_EP_OUT_MAX]; 673 u8 in_ep[__MT_EP_IN_MAX]; 674 bool sg_en; 675 676 struct mt76u_mcu { 677 u8 *data; 678 /* multiple reads */ 679 struct mt76_reg_pair *rp; 680 int rp_len; 681 u32 base; 682 } mcu; 683 }; 684 685 #define MT76S_XMIT_BUF_SZ 0x3fe00 686 #define MT76S_NUM_TX_ENTRIES 256 687 #define MT76S_NUM_RX_ENTRIES 512 688 struct mt76_sdio { 689 struct mt76_worker txrx_worker; 690 struct mt76_worker status_worker; 691 struct mt76_worker net_worker; 692 struct mt76_worker stat_worker; 693 694 u8 *xmit_buf; 695 u32 xmit_buf_sz; 696 697 struct sdio_func *func; 698 void *intr_data; 699 u8 hw_ver; 700 wait_queue_head_t wait; 701 702 int pse_mcu_quota_max; 703 struct { 704 int pse_data_quota; 705 int ple_data_quota; 706 int pse_mcu_quota; 707 int pse_page_size; 708 int deficit; 709 } sched; 710 711 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 712 }; 713 714 struct mt76_mmio { 715 void __iomem *regs; 716 spinlock_t irq_lock; 717 u32 irqmask; 718 719 struct mtk_wed_device wed; 720 struct mtk_wed_device wed_hif2; 721 struct completion wed_reset; 722 struct completion wed_reset_complete; 723 724 struct airoha_ppe_dev __rcu *ppe_dev; 725 struct airoha_npu __rcu *npu; 726 phys_addr_t phy_addr; 727 int npu_type; 728 }; 729 730 struct mt76_rx_status { 731 union { 732 struct mt76_wcid *wcid; 733 u16 wcid_idx; 734 }; 735 736 u32 reorder_time; 737 738 u32 ampdu_ref; 739 u32 timestamp; 740 741 u8 iv[6]; 742 743 u8 phy_idx:2; 744 u8 aggr:1; 745 u8 qos_ctl; 746 u16 seqno; 747 748 u16 freq; 749 u32 flag; 750 u8 enc_flags; 751 u8 encoding:3, bw:4; 752 union { 753 struct { 754 u8 he_ru:3; 755 u8 he_gi:2; 756 u8 he_dcm:1; 757 }; 758 struct { 759 u8 ru:4; 760 u8 gi:2; 761 } eht; 762 }; 763 764 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 765 u8 rate_idx; 766 u8 nss:5, band:3; 767 s8 signal; 768 u8 chains; 769 s8 chain_signal[IEEE80211_MAX_CHAINS]; 770 }; 771 772 struct mt76_freq_range_power { 773 const struct cfg80211_sar_freq_ranges *range; 774 s8 power; 775 }; 776 777 struct mt76_testmode_ops { 778 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 779 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 780 enum mt76_testmode_state new_state); 781 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 782 }; 783 784 struct mt76_testmode_data { 785 enum mt76_testmode_state state; 786 787 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 788 struct sk_buff *tx_skb; 789 790 u32 tx_count; 791 u16 tx_mpdu_len; 792 793 u8 tx_rate_mode; 794 u8 tx_rate_idx; 795 u8 tx_rate_nss; 796 u8 tx_rate_sgi; 797 u8 tx_rate_ldpc; 798 u8 tx_rate_stbc; 799 u8 tx_ltf; 800 801 u8 tx_antenna_mask; 802 u8 tx_spe_idx; 803 804 u8 tx_duty_cycle; 805 u32 tx_time; 806 u32 tx_ipg; 807 808 u32 freq_offset; 809 810 u8 tx_power[4]; 811 u8 tx_power_control; 812 813 u8 addr[3][ETH_ALEN]; 814 815 u32 tx_pending; 816 u32 tx_queued; 817 u16 tx_queued_limit; 818 u32 tx_done; 819 struct { 820 u64 packets[__MT_RXQ_MAX]; 821 u64 fcs_error[__MT_RXQ_MAX]; 822 } rx_stats; 823 }; 824 825 struct mt76_vif_link { 826 u8 idx; 827 u8 link_idx; 828 u8 omac_idx; 829 u8 band_idx; 830 u8 wmm_idx; 831 u8 scan_seq_num; 832 u8 cipher; 833 u8 basic_rates_idx; 834 u8 mcast_rates_idx; 835 u8 beacon_rates_idx; 836 bool offchannel; 837 unsigned long beacon_mon_last; 838 u16 beacon_mon_interval; 839 struct ieee80211_chanctx_conf *ctx; 840 struct mt76_wcid *wcid; 841 struct mt76_vif_data *mvif; 842 struct rcu_head rcu_head; 843 }; 844 845 struct mt76_vif_data { 846 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 847 struct mt76_vif_link __rcu *offchannel_link; 848 849 struct mt76_phy *roc_phy; 850 u16 valid_links; 851 u8 deflink_id; 852 }; 853 854 struct mt76_phy { 855 struct ieee80211_hw *hw; 856 struct mt76_dev *dev; 857 void *priv; 858 859 unsigned long state; 860 unsigned int num_sta; 861 u8 band_idx; 862 863 spinlock_t tx_lock; 864 struct list_head tx_list; 865 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 866 867 atomic_t mgmt_tx_pending; 868 869 struct cfg80211_chan_def chandef; 870 struct cfg80211_chan_def main_chandef; 871 bool offchannel; 872 bool radar_enabled; 873 874 struct delayed_work roc_work; 875 struct ieee80211_vif *roc_vif; 876 struct mt76_vif_link *roc_link; 877 878 struct mt76_chanctx *chanctx; 879 880 struct mt76_channel_state *chan_state; 881 enum mt76_dfs_state dfs_state; 882 ktime_t survey_time; 883 884 u32 aggr_stats[32]; 885 886 struct mt76_hw_cap cap; 887 struct mt76_sband sband_2g; 888 struct mt76_sband sband_5g; 889 struct mt76_sband sband_6g; 890 891 u8 macaddr[ETH_ALEN]; 892 893 int txpower_cur; 894 u8 antenna_mask; 895 u16 chainmask; 896 897 #ifdef CONFIG_NL80211_TESTMODE 898 struct mt76_testmode_data test; 899 #endif 900 901 struct delayed_work mac_work; 902 u8 mac_work_count; 903 904 struct { 905 struct sk_buff *head; 906 struct sk_buff **tail; 907 u16 seqno; 908 } rx_amsdu[__MT_RXQ_MAX]; 909 910 struct mt76_freq_range_power *frp; 911 912 struct { 913 struct led_classdev cdev; 914 char name[32]; 915 bool al; 916 u8 pin; 917 } leds; 918 }; 919 920 struct mt76_dev { 921 struct mt76_phy phy; /* must be first */ 922 struct mt76_phy *phys[__MT_MAX_BAND]; 923 struct mt76_phy *band_phys[NUM_NL80211_BANDS]; 924 925 struct ieee80211_hw *hw; 926 927 spinlock_t wed_lock; 928 spinlock_t lock; 929 spinlock_t cc_lock; 930 931 u32 cur_cc_bss_rx; 932 933 struct mt76_rx_status rx_ampdu_status; 934 u32 rx_ampdu_len; 935 u32 rx_ampdu_ref; 936 937 struct mutex mutex; 938 939 const struct mt76_bus_ops *bus; 940 const struct mt76_driver_ops *drv; 941 const struct mt76_mcu_ops *mcu_ops; 942 struct device *dev; 943 struct device *dma_dev; 944 945 struct mt76_mcu mcu; 946 947 struct net_device *napi_dev; 948 struct net_device *tx_napi_dev; 949 spinlock_t rx_lock; 950 struct napi_struct napi[__MT_RXQ_MAX]; 951 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 952 struct tasklet_struct irq_tasklet; 953 954 struct list_head txwi_cache; 955 struct list_head rxwi_cache; 956 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 957 struct mt76_queue q_rx[__MT_RXQ_MAX]; 958 const struct mt76_queue_ops *queue_ops; 959 int tx_dma_idx[4]; 960 enum mt76_hwrro_mode hwrro_mode; 961 962 struct mt76_worker tx_worker; 963 struct napi_struct tx_napi; 964 965 spinlock_t token_lock; 966 struct idr token; 967 u16 wed_token_count; 968 u16 token_count; 969 u16 token_start; 970 u16 token_size; 971 972 spinlock_t rx_token_lock; 973 struct idr rx_token; 974 u16 rx_token_size; 975 976 wait_queue_head_t tx_wait; 977 /* spinclock used to protect wcid pktid linked list */ 978 spinlock_t status_lock; 979 980 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 981 982 u64 vif_mask; 983 984 struct mt76_wcid global_wcid; 985 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 986 struct list_head wcid_list; 987 988 struct list_head sta_poll_list; 989 spinlock_t sta_poll_lock; 990 991 u32 rev; 992 993 struct tasklet_struct pre_tbtt_tasklet; 994 int beacon_int; 995 u8 beacon_mask; 996 997 struct debugfs_blob_wrapper eeprom; 998 struct debugfs_blob_wrapper otp; 999 1000 char alpha2[3]; 1001 enum nl80211_dfs_regions region; 1002 1003 struct mt76_scan_rnr_param rnr; 1004 1005 u32 debugfs_reg; 1006 1007 u8 csa_complete; 1008 1009 u32 rxfilter; 1010 1011 struct delayed_work scan_work; 1012 spinlock_t scan_lock; 1013 struct { 1014 struct cfg80211_scan_request *req; 1015 struct ieee80211_channel *chan; 1016 struct ieee80211_vif *vif; 1017 struct mt76_vif_link *mlink; 1018 struct mt76_phy *phy; 1019 int chan_idx; 1020 bool beacon_wait; 1021 bool beacon_received; 1022 } scan; 1023 1024 #ifdef CONFIG_NL80211_TESTMODE 1025 const struct mt76_testmode_ops *test_ops; 1026 struct { 1027 const char *name; 1028 u32 offset; 1029 } test_mtd; 1030 #endif 1031 struct workqueue_struct *wq; 1032 1033 union { 1034 struct mt76_mmio mmio; 1035 struct mt76_usb usb; 1036 struct mt76_sdio sdio; 1037 }; 1038 1039 atomic_t bus_hung; 1040 }; 1041 1042 /* per-phy stats. */ 1043 struct mt76_mib_stats { 1044 u32 ack_fail_cnt; 1045 u32 fcs_err_cnt; 1046 u32 rts_cnt; 1047 u32 rts_retries_cnt; 1048 u32 ba_miss_cnt; 1049 u32 tx_bf_cnt; 1050 u32 tx_mu_bf_cnt; 1051 u32 tx_mu_mpdu_cnt; 1052 u32 tx_mu_acked_mpdu_cnt; 1053 u32 tx_su_acked_mpdu_cnt; 1054 u32 tx_bf_ibf_ppdu_cnt; 1055 u32 tx_bf_ebf_ppdu_cnt; 1056 1057 u32 tx_bf_rx_fb_all_cnt; 1058 u32 tx_bf_rx_fb_eht_cnt; 1059 u32 tx_bf_rx_fb_he_cnt; 1060 u32 tx_bf_rx_fb_vht_cnt; 1061 u32 tx_bf_rx_fb_ht_cnt; 1062 1063 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 1064 u32 tx_bf_rx_fb_nc_cnt; 1065 u32 tx_bf_rx_fb_nr_cnt; 1066 u32 tx_bf_fb_cpl_cnt; 1067 u32 tx_bf_fb_trig_cnt; 1068 1069 u32 tx_ampdu_cnt; 1070 u32 tx_stop_q_empty_cnt; 1071 u32 tx_mpdu_attempts_cnt; 1072 u32 tx_mpdu_success_cnt; 1073 u32 tx_pkt_ebf_cnt; 1074 u32 tx_pkt_ibf_cnt; 1075 1076 u32 tx_rwp_fail_cnt; 1077 u32 tx_rwp_need_cnt; 1078 1079 /* rx stats */ 1080 u32 rx_fifo_full_cnt; 1081 u32 channel_idle_cnt; 1082 u32 primary_cca_busy_time; 1083 u32 secondary_cca_busy_time; 1084 u32 primary_energy_detect_time; 1085 u32 cck_mdrdy_time; 1086 u32 ofdm_mdrdy_time; 1087 u32 green_mdrdy_time; 1088 u32 rx_vector_mismatch_cnt; 1089 u32 rx_delimiter_fail_cnt; 1090 u32 rx_mrdy_cnt; 1091 u32 rx_len_mismatch_cnt; 1092 u32 rx_mpdu_cnt; 1093 u32 rx_ampdu_cnt; 1094 u32 rx_ampdu_bytes_cnt; 1095 u32 rx_ampdu_valid_subframe_cnt; 1096 u32 rx_ampdu_valid_subframe_bytes_cnt; 1097 u32 rx_pfdrop_cnt; 1098 u32 rx_vec_queue_overflow_drop_cnt; 1099 u32 rx_ba_cnt; 1100 1101 u32 tx_amsdu[8]; 1102 u32 tx_amsdu_cnt; 1103 1104 /* mcu_muru_stats */ 1105 u32 dl_cck_cnt; 1106 u32 dl_ofdm_cnt; 1107 u32 dl_htmix_cnt; 1108 u32 dl_htgf_cnt; 1109 u32 dl_vht_su_cnt; 1110 u32 dl_vht_2mu_cnt; 1111 u32 dl_vht_3mu_cnt; 1112 u32 dl_vht_4mu_cnt; 1113 u32 dl_he_su_cnt; 1114 u32 dl_he_ext_su_cnt; 1115 u32 dl_he_2ru_cnt; 1116 u32 dl_he_2mu_cnt; 1117 u32 dl_he_3ru_cnt; 1118 u32 dl_he_3mu_cnt; 1119 u32 dl_he_4ru_cnt; 1120 u32 dl_he_4mu_cnt; 1121 u32 dl_he_5to8ru_cnt; 1122 u32 dl_he_9to16ru_cnt; 1123 u32 dl_he_gtr16ru_cnt; 1124 1125 u32 ul_hetrig_su_cnt; 1126 u32 ul_hetrig_2ru_cnt; 1127 u32 ul_hetrig_3ru_cnt; 1128 u32 ul_hetrig_4ru_cnt; 1129 u32 ul_hetrig_5to8ru_cnt; 1130 u32 ul_hetrig_9to16ru_cnt; 1131 u32 ul_hetrig_gtr16ru_cnt; 1132 u32 ul_hetrig_2mu_cnt; 1133 u32 ul_hetrig_3mu_cnt; 1134 u32 ul_hetrig_4mu_cnt; 1135 }; 1136 1137 struct mt76_power_limits { 1138 s8 cck[4]; 1139 s8 ofdm[8]; 1140 s8 mcs[4][10]; 1141 s8 ru[7][12]; 1142 s8 eht[16][16]; 1143 1144 struct { 1145 s8 cck[4]; 1146 s8 ofdm[4]; 1147 s8 ofdm_bf[4]; 1148 s8 ru[7][10]; 1149 s8 ru_bf[7][10]; 1150 } path; 1151 }; 1152 1153 struct mt76_ethtool_worker_info { 1154 u64 *data; 1155 int idx; 1156 int initial_stat_idx; 1157 int worker_stat_count; 1158 int sta_count; 1159 }; 1160 1161 struct mt76_chanctx { 1162 struct mt76_phy *phy; 1163 }; 1164 1165 #define CCK_RATE(_idx, _rate) { \ 1166 .bitrate = _rate, \ 1167 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 1168 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 1169 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 1170 } 1171 1172 #define OFDM_RATE(_idx, _rate) { \ 1173 .bitrate = _rate, \ 1174 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1175 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1176 } 1177 1178 extern struct ieee80211_rate mt76_rates[12]; 1179 1180 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1181 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1182 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1183 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1184 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1185 1186 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1187 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1188 1189 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1190 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1191 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1192 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1193 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1194 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1195 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1196 1197 1198 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1199 1200 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1201 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1202 1203 #define mt76_get_field(_dev, _reg, _field) \ 1204 FIELD_GET(_field, mt76_rr(dev, _reg)) 1205 1206 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1207 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1208 1209 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1210 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1211 1212 #define mt76_hw(dev) (dev)->mphy.hw 1213 1214 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1215 int timeout); 1216 1217 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1218 1219 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1220 int timeout, int kick); 1221 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1222 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1223 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1224 1225 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1226 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1227 bool mt76_pci_aspm_supported(struct pci_dev *pdev); 1228 1229 static inline u16 mt76_chip(struct mt76_dev *dev) 1230 { 1231 return dev->rev >> 16; 1232 } 1233 1234 static inline u16 mt76_rev(struct mt76_dev *dev) 1235 { 1236 return dev->rev & 0xffff; 1237 } 1238 1239 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed); 1240 void mt76_wed_offload_disable(struct mtk_wed_device *wed); 1241 void mt76_wed_reset_complete(struct mtk_wed_device *wed); 1242 void mt76_wed_dma_reset(struct mt76_dev *dev); 1243 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1244 struct net_device *netdev, enum tc_setup_type type, 1245 void *type_data); 1246 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1247 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size); 1248 int mt76_wed_offload_enable(struct mtk_wed_device *wed); 1249 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); 1250 #else 1251 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size) 1252 { 1253 return 0; 1254 } 1255 1256 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed) 1257 { 1258 return 0; 1259 } 1260 1261 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, 1262 bool reset) 1263 { 1264 return 0; 1265 } 1266 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1267 1268 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1269 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1270 1271 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1272 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1273 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1274 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1275 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1276 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1277 #define mt76_queue_rx_init(dev, ...) (dev)->mt76.queue_ops->rx_queue_init(&((dev)->mt76), __VA_ARGS__) 1278 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1279 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1280 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1281 1282 #define mt76_for_each_q_rx(dev, i) \ 1283 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1284 if ((dev)->q_rx[i].ndesc) 1285 1286 1287 #define mt76_dereference(p, dev) \ 1288 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex)) 1289 1290 static inline struct mt76_dev *mt76_wed_to_dev(struct mtk_wed_device *wed) 1291 { 1292 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1293 if (wed->wlan.hif2) 1294 return container_of(wed, struct mt76_dev, mmio.wed_hif2); 1295 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1296 return container_of(wed, struct mt76_dev, mmio.wed); 1297 } 1298 1299 static inline struct mt76_wcid * 1300 __mt76_wcid_ptr(struct mt76_dev *dev, u16 idx) 1301 { 1302 if (idx >= ARRAY_SIZE(dev->wcid)) 1303 return NULL; 1304 return rcu_dereference(dev->wcid[idx]); 1305 } 1306 1307 #define mt76_wcid_ptr(dev, idx) __mt76_wcid_ptr(&(dev)->mt76, idx) 1308 1309 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1310 const struct ieee80211_ops *ops, 1311 const struct mt76_driver_ops *drv_ops); 1312 int mt76_register_device(struct mt76_dev *dev, bool vht, 1313 struct ieee80211_rate *rates, int n_rates); 1314 void mt76_unregister_device(struct mt76_dev *dev); 1315 void mt76_free_device(struct mt76_dev *dev); 1316 void mt76_reset_device(struct mt76_dev *dev); 1317 void mt76_unregister_phy(struct mt76_phy *phy); 1318 1319 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size, 1320 u8 band_idx); 1321 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1322 const struct ieee80211_ops *ops, 1323 u8 band_idx); 1324 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1325 struct ieee80211_rate *rates, int n_rates); 1326 struct mt76_phy *mt76_vif_phy(struct ieee80211_hw *hw, 1327 struct ieee80211_vif *vif); 1328 1329 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1330 const struct file_operations *ops); 1331 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1332 { 1333 return mt76_register_debugfs_fops(&dev->phy, NULL); 1334 } 1335 1336 int mt76_queues_read(struct seq_file *s, void *data); 1337 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1338 s8 *val, int len); 1339 1340 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1341 int mt76_eeprom_override(struct mt76_phy *phy); 1342 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1343 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1344 const char *cell_name, int len); 1345 1346 struct mt76_queue * 1347 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1348 int ring_base, void *wed, u32 flags); 1349 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1350 int n_desc, int ring_base, void *wed, 1351 u32 flags) 1352 { 1353 struct mt76_queue *q; 1354 1355 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags); 1356 if (IS_ERR(q)) 1357 return PTR_ERR(q); 1358 1359 phy->q_tx[qid] = q; 1360 1361 return 0; 1362 } 1363 1364 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1365 int n_desc, int ring_base) 1366 { 1367 struct mt76_queue *q; 1368 1369 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0); 1370 if (IS_ERR(q)) 1371 return PTR_ERR(q); 1372 1373 dev->q_mcu[qid] = q; 1374 1375 return 0; 1376 } 1377 1378 static inline struct mt76_phy * 1379 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1380 { 1381 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1382 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1383 return dev->phys[phy_idx]; 1384 1385 return &dev->phy; 1386 } 1387 1388 static inline struct ieee80211_hw * 1389 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1390 { 1391 return mt76_dev_phy(dev, phy_idx)->hw; 1392 } 1393 1394 static inline u8 * 1395 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1396 { 1397 return (u8 *)t - dev->drv->txwi_size; 1398 } 1399 1400 /* increment with wrap-around */ 1401 static inline int mt76_incr(int val, int size) 1402 { 1403 return (val + 1) & (size - 1); 1404 } 1405 1406 /* decrement with wrap-around */ 1407 static inline int mt76_decr(int val, int size) 1408 { 1409 return (val - 1) & (size - 1); 1410 } 1411 1412 u8 mt76_ac_to_hwq(u8 ac); 1413 1414 static inline struct ieee80211_txq * 1415 mtxq_to_txq(struct mt76_txq *mtxq) 1416 { 1417 void *ptr = mtxq; 1418 1419 return container_of(ptr, struct ieee80211_txq, drv_priv); 1420 } 1421 1422 static inline struct ieee80211_sta * 1423 wcid_to_sta(struct mt76_wcid *wcid) 1424 { 1425 void *ptr = wcid; 1426 1427 if (!wcid || !wcid->sta) 1428 return NULL; 1429 1430 if (wcid->def_wcid) 1431 ptr = wcid->def_wcid; 1432 1433 return container_of(ptr, struct ieee80211_sta, drv_priv); 1434 } 1435 1436 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1437 { 1438 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1439 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1440 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1441 } 1442 1443 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1444 { 1445 struct mt76_rx_status mstat; 1446 u8 *data = skb->data; 1447 1448 /* Alignment concerns */ 1449 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1450 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1451 1452 mstat = *((struct mt76_rx_status *)skb->cb); 1453 1454 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1455 data += sizeof(struct ieee80211_radiotap_he); 1456 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1457 data += sizeof(struct ieee80211_radiotap_he_mu); 1458 1459 return data; 1460 } 1461 1462 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1463 { 1464 int len = ieee80211_get_hdrlen_from_skb(skb); 1465 1466 if (len % 4 == 0) 1467 return; 1468 1469 skb_push(skb, 2); 1470 memmove(skb->data, skb->data + 2, len); 1471 1472 skb->data[len] = 0; 1473 skb->data[len + 1] = 0; 1474 } 1475 1476 static inline bool mt76_is_skb_pktid(u8 pktid) 1477 { 1478 if (pktid & MT_PACKET_ID_HAS_RATE) 1479 return false; 1480 1481 return pktid >= MT_PACKET_ID_FIRST; 1482 } 1483 1484 static inline u8 mt76_tx_power_path_delta(u8 path) 1485 { 1486 static const u8 path_delta[5] = { 0, 6, 9, 12, 14 }; 1487 u8 idx = path - 1; 1488 1489 return (idx < ARRAY_SIZE(path_delta)) ? path_delta[idx] : 0; 1490 } 1491 1492 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1493 { 1494 #ifdef CONFIG_NL80211_TESTMODE 1495 return phy->test.state != MT76_TM_STATE_OFF; 1496 #else 1497 return false; 1498 #endif 1499 } 1500 1501 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1502 struct sk_buff *skb, 1503 struct ieee80211_hw **hw) 1504 { 1505 #ifdef CONFIG_NL80211_TESTMODE 1506 int i; 1507 1508 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1509 struct mt76_phy *phy = dev->phys[i]; 1510 1511 if (phy && skb == phy->test.tx_skb) { 1512 *hw = dev->phys[i]->hw; 1513 return true; 1514 } 1515 } 1516 return false; 1517 #else 1518 return false; 1519 #endif 1520 } 1521 1522 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1523 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1524 struct mt76_wcid *wcid, struct sk_buff *skb); 1525 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1526 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1527 bool send_bar); 1528 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1529 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1530 void mt76_txq_schedule_all(struct mt76_phy *phy); 1531 void mt76_txq_schedule_pending(struct mt76_phy *phy); 1532 void mt76_tx_worker_run(struct mt76_dev *dev); 1533 void mt76_tx_worker(struct mt76_worker *w); 1534 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1535 struct ieee80211_sta *sta, 1536 u16 tids, int nframes, 1537 enum ieee80211_frame_release_type reason, 1538 bool more_data); 1539 bool mt76_has_tx_pending(struct mt76_phy *phy); 1540 int mt76_update_channel(struct mt76_phy *phy); 1541 void mt76_update_survey(struct mt76_phy *phy); 1542 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1543 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1544 struct survey_info *survey); 1545 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1546 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1547 1548 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1549 u16 ssn, u16 size); 1550 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1551 1552 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1553 struct ieee80211_key_conf *key); 1554 1555 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1556 __acquires(&dev->status_lock); 1557 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1558 __releases(&dev->status_lock); 1559 1560 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1561 struct sk_buff *skb); 1562 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1563 struct mt76_wcid *wcid, int pktid, 1564 struct sk_buff_head *list); 1565 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1566 struct sk_buff_head *list); 1567 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1568 struct list_head *free_list); 1569 static inline void 1570 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1571 { 1572 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1573 } 1574 1575 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1576 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1577 struct ieee80211_sta *sta, 1578 enum ieee80211_sta_state old_state, 1579 enum ieee80211_sta_state new_state); 1580 void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif, 1581 struct ieee80211_sta *sta); 1582 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1583 struct ieee80211_sta *sta); 1584 1585 int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx); 1586 1587 s8 mt76_get_power_bound(struct mt76_phy *phy, s8 txpower); 1588 1589 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1590 unsigned int link_id, int *dbm); 1591 int mt76_init_sar_power(struct ieee80211_hw *hw, 1592 const struct cfg80211_sar_specs *sar); 1593 int mt76_get_sar_power(struct mt76_phy *phy, 1594 struct ieee80211_channel *chan, 1595 int power); 1596 1597 void mt76_csa_check(struct mt76_dev *dev); 1598 void mt76_csa_finish(struct mt76_dev *dev); 1599 1600 int mt76_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant, 1601 u32 *rx_ant); 1602 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1603 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1604 int mt76_get_rate(struct mt76_dev *dev, 1605 struct ieee80211_supported_band *sband, 1606 int idx, bool cck); 1607 int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1608 struct ieee80211_scan_request *hw_req); 1609 void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1610 void mt76_scan_rx_beacon(struct mt76_dev *dev, struct ieee80211_channel *chan); 1611 void mt76_rx_beacon(struct mt76_phy *phy, struct sk_buff *skb); 1612 void mt76_beacon_mon_check(struct mt76_phy *phy); 1613 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1614 const u8 *mac); 1615 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1616 struct ieee80211_vif *vif); 1617 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1618 int mt76_add_chanctx(struct ieee80211_hw *hw, 1619 struct ieee80211_chanctx_conf *conf); 1620 void mt76_remove_chanctx(struct ieee80211_hw *hw, 1621 struct ieee80211_chanctx_conf *conf); 1622 void mt76_change_chanctx(struct ieee80211_hw *hw, 1623 struct ieee80211_chanctx_conf *conf, 1624 u32 changed); 1625 int mt76_assign_vif_chanctx(struct ieee80211_hw *hw, 1626 struct ieee80211_vif *vif, 1627 struct ieee80211_bss_conf *link_conf, 1628 struct ieee80211_chanctx_conf *conf); 1629 void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw, 1630 struct ieee80211_vif *vif, 1631 struct ieee80211_bss_conf *link_conf, 1632 struct ieee80211_chanctx_conf *conf); 1633 int mt76_switch_vif_chanctx(struct ieee80211_hw *hw, 1634 struct ieee80211_vif_chanctx_switch *vifs, 1635 int n_vifs, 1636 enum ieee80211_chanctx_switch_mode mode); 1637 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1638 struct ieee80211_channel *chan, int duration, 1639 enum ieee80211_roc_type type); 1640 int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw, 1641 struct ieee80211_vif *vif); 1642 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1643 void *data, int len); 1644 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1645 struct netlink_callback *cb, void *data, int len); 1646 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1647 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1648 1649 #ifdef CONFIG_MT76_NPU 1650 void mt76_npu_check_ppe(struct mt76_dev *dev, struct sk_buff *skb, 1651 u32 info); 1652 int mt76_npu_dma_add_buf(struct mt76_phy *phy, struct mt76_queue *q, 1653 struct sk_buff *skb, struct mt76_queue_buf *buf, 1654 void *txwi_ptr); 1655 int mt76_npu_rx_queue_init(struct mt76_dev *dev, struct mt76_queue *q); 1656 int mt76_npu_fill_rx_queue(struct mt76_dev *dev, struct mt76_queue *q); 1657 void mt76_npu_queue_cleanup(struct mt76_dev *dev, struct mt76_queue *q); 1658 void mt76_npu_disable_irqs(struct mt76_dev *dev); 1659 int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr, int type); 1660 void mt76_npu_deinit(struct mt76_dev *dev); 1661 void mt76_npu_queue_setup(struct mt76_dev *dev, struct mt76_queue *q); 1662 void mt76_npu_txdesc_cleanup(struct mt76_queue *q, int index); 1663 int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1664 struct net_device *dev, enum tc_setup_type type, 1665 void *type_data); 1666 int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex, 1667 u32 direction, u32 i_count_addr, 1668 u32 o_status_addr, u32 o_count_addr); 1669 #else 1670 static inline void mt76_npu_check_ppe(struct mt76_dev *dev, 1671 struct sk_buff *skb, u32 info) 1672 { 1673 } 1674 1675 static inline int mt76_npu_dma_add_buf(struct mt76_phy *phy, 1676 struct mt76_queue *q, 1677 struct sk_buff *skb, 1678 struct mt76_queue_buf *buf, 1679 void *txwi_ptr) 1680 { 1681 return -EOPNOTSUPP; 1682 } 1683 1684 static inline int mt76_npu_fill_rx_queue(struct mt76_dev *dev, 1685 struct mt76_queue *q) 1686 { 1687 return 0; 1688 } 1689 1690 static inline void mt76_npu_queue_cleanup(struct mt76_dev *dev, 1691 struct mt76_queue *q) 1692 { 1693 } 1694 1695 static inline void mt76_npu_disable_irqs(struct mt76_dev *dev) 1696 { 1697 } 1698 1699 static inline int mt76_npu_init(struct mt76_dev *dev, phys_addr_t phy_addr, 1700 int type) 1701 { 1702 return 0; 1703 } 1704 1705 static inline void mt76_npu_deinit(struct mt76_dev *dev) 1706 { 1707 } 1708 1709 static inline void mt76_npu_queue_setup(struct mt76_dev *dev, 1710 struct mt76_queue *q) 1711 { 1712 } 1713 1714 static inline void mt76_npu_txdesc_cleanup(struct mt76_queue *q, 1715 int index) 1716 { 1717 } 1718 1719 static inline int mt76_npu_net_setup_tc(struct ieee80211_hw *hw, 1720 struct ieee80211_vif *vif, 1721 struct net_device *dev, 1722 enum tc_setup_type type, 1723 void *type_data) 1724 { 1725 return -EOPNOTSUPP; 1726 } 1727 1728 static inline int mt76_npu_send_txrx_addr(struct mt76_dev *dev, int ifindex, 1729 u32 direction, u32 i_count_addr, 1730 u32 o_status_addr, u32 o_count_addr) 1731 { 1732 return -EOPNOTSUPP; 1733 } 1734 #endif /* CONFIG_MT76_NPU */ 1735 1736 static inline bool mt76_npu_device_active(struct mt76_dev *dev) 1737 { 1738 return !!rcu_access_pointer(dev->mmio.npu); 1739 } 1740 1741 static inline bool mt76_ppe_device_active(struct mt76_dev *dev) 1742 { 1743 return !!rcu_access_pointer(dev->mmio.ppe_dev); 1744 } 1745 1746 static inline int mt76_npu_send_msg(struct airoha_npu *npu, int ifindex, 1747 enum airoha_npu_wlan_set_cmd cmd, 1748 u32 val, gfp_t gfp) 1749 { 1750 return airoha_npu_wlan_send_msg(npu, ifindex, cmd, &val, sizeof(val), 1751 gfp); 1752 } 1753 1754 static inline int mt76_npu_get_msg(struct airoha_npu *npu, int ifindex, 1755 enum airoha_npu_wlan_get_cmd cmd, 1756 u32 *val, gfp_t gfp) 1757 { 1758 return airoha_npu_wlan_get_msg(npu, ifindex, cmd, val, sizeof(*val), 1759 gfp); 1760 } 1761 1762 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1763 { 1764 #ifdef CONFIG_NL80211_TESTMODE 1765 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1766 1767 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1768 state = MT76_TM_STATE_OFF; 1769 1770 mt76_testmode_set_state(phy, state); 1771 #endif 1772 } 1773 1774 1775 /* internal */ 1776 static inline struct ieee80211_hw * 1777 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1778 { 1779 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1780 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1781 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1782 1783 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1784 1785 return hw; 1786 } 1787 1788 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1789 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1790 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1791 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1792 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1793 struct napi_struct *napi); 1794 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1795 struct napi_struct *napi); 1796 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1797 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1798 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1799 struct mt76_queue_entry *e); 1800 int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1801 bool offchannel); 1802 1803 static inline bool 1804 mt76_offchannel_chandef(struct mt76_phy *phy, struct ieee80211_channel *chan, 1805 struct cfg80211_chan_def *chandef) 1806 { 1807 cfg80211_chandef_create(chandef, chan, NL80211_CHAN_HT20); 1808 if (phy->main_chandef.chan != chan) 1809 return true; 1810 1811 *chandef = phy->main_chandef; 1812 return false; 1813 } 1814 int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1815 bool offchannel); 1816 void mt76_scan_work(struct work_struct *work); 1817 void mt76_abort_scan(struct mt76_dev *dev); 1818 void mt76_roc_complete_work(struct work_struct *work); 1819 void mt76_roc_complete(struct mt76_phy *phy); 1820 void mt76_abort_roc(struct mt76_phy *phy); 1821 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy, 1822 struct ieee80211_vif *vif); 1823 void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif, 1824 struct mt76_vif_link *mlink); 1825 void mt76_offchannel_notify(struct mt76_phy *phy, bool offchannel); 1826 1827 /* usb */ 1828 static inline bool mt76u_urb_error(struct urb *urb) 1829 { 1830 return urb->status && 1831 urb->status != -ECONNRESET && 1832 urb->status != -ESHUTDOWN && 1833 urb->status != -ENOENT; 1834 } 1835 1836 static inline int 1837 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1838 int timeout, int ep) 1839 { 1840 struct usb_interface *uintf = to_usb_interface(dev->dev); 1841 struct usb_device *udev = interface_to_usbdev(uintf); 1842 struct mt76_usb *usb = &dev->usb; 1843 unsigned int pipe; 1844 1845 if (actual_len) 1846 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1847 else 1848 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1849 1850 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1851 } 1852 1853 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1854 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1855 struct mt76_sta_stats *stats, bool eht); 1856 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1857 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1858 u16 val, u16 offset, void *buf, size_t len); 1859 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1860 u8 req_type, u16 val, u16 offset, 1861 void *buf, size_t len); 1862 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1863 const u16 offset, const u32 val); 1864 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1865 void *data, int len); 1866 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1867 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1868 u32 addr, u32 val); 1869 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1870 struct mt76_bus_ops *ops); 1871 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1872 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1873 int mt76u_alloc_queues(struct mt76_dev *dev); 1874 void mt76u_stop_tx(struct mt76_dev *dev); 1875 void mt76u_stop_rx(struct mt76_dev *dev); 1876 int mt76u_resume_rx(struct mt76_dev *dev); 1877 void mt76u_queues_deinit(struct mt76_dev *dev); 1878 1879 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1880 const struct mt76_bus_ops *bus_ops); 1881 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1882 int mt76s_alloc_tx(struct mt76_dev *dev); 1883 void mt76s_deinit(struct mt76_dev *dev); 1884 void mt76s_sdio_irq(struct sdio_func *func); 1885 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1886 bool mt76s_txqs_empty(struct mt76_dev *dev); 1887 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1888 int hw_ver); 1889 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1890 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1891 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1892 u32 mt76s_read_pcr(struct mt76_dev *dev); 1893 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1894 const void *data, int len); 1895 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1896 void *data, int len); 1897 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1898 const struct mt76_reg_pair *data, 1899 int len); 1900 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1901 struct mt76_reg_pair *data, int len); 1902 1903 struct sk_buff * 1904 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1905 int len, int data_len, gfp_t gfp); 1906 static inline struct sk_buff * 1907 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1908 int data_len) 1909 { 1910 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1911 } 1912 1913 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1914 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1915 unsigned long expires); 1916 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1917 int len, bool wait_resp, struct sk_buff **ret); 1918 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1919 int cmd, bool wait_resp, struct sk_buff **ret); 1920 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1921 int len, int max_len); 1922 static inline int 1923 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1924 int len) 1925 { 1926 int max_len = 4096 - dev->mcu_ops->headroom; 1927 1928 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1929 } 1930 1931 static inline int 1932 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1933 bool wait_resp) 1934 { 1935 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1936 } 1937 1938 static inline int 1939 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1940 bool wait_resp) 1941 { 1942 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1943 } 1944 1945 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1946 1947 struct device_node * 1948 mt76_find_power_limits_node(struct mt76_dev *dev); 1949 struct device_node * 1950 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1951 1952 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1953 struct ieee80211_channel *chan, 1954 struct mt76_power_limits *dest, 1955 s8 target_power); 1956 1957 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q) 1958 { 1959 int i; 1960 1961 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 1962 if (q == &dev->q_rx[i]) 1963 return true; 1964 } 1965 1966 return false; 1967 } 1968 1969 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q) 1970 { 1971 return (q->flags & MT_QFLAG_WED) && 1972 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 1973 } 1974 1975 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q) 1976 { 1977 return q->flags & MT_QFLAG_WED_RRO; 1978 } 1979 1980 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q) 1981 { 1982 return mt76_queue_is_wed_rro(q) && 1983 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1984 } 1985 1986 static inline bool mt76_queue_is_wed_rro_rxdmad_c(struct mt76_queue *q) 1987 { 1988 return mt76_queue_is_wed_rro(q) && 1989 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_RXDMAD_C; 1990 } 1991 1992 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1993 { 1994 return mt76_queue_is_wed_rro(q) && 1995 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA; 1996 } 1997 1998 static inline bool mt76_queue_is_wed_rro_msdu_pg(struct mt76_queue *q) 1999 { 2000 return mt76_queue_is_wed_rro(q) && 2001 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == 2002 MT76_WED_RRO_Q_MSDU_PG; 2003 } 2004 2005 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 2006 { 2007 return (q->flags & MT_QFLAG_WED) && 2008 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 2009 } 2010 2011 static inline bool mt76_queue_is_emi(struct mt76_queue *q) 2012 { 2013 return q->flags & MT_QFLAG_EMI_EN; 2014 } 2015 2016 static inline bool mt76_queue_is_npu(struct mt76_queue *q) 2017 { 2018 return q->flags & MT_QFLAG_NPU; 2019 } 2020 2021 static inline bool mt76_queue_is_npu_tx(struct mt76_queue *q) 2022 { 2023 return mt76_queue_is_npu(q) && 2024 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TX; 2025 } 2026 2027 static inline bool mt76_queue_is_npu_rx(struct mt76_queue *q) 2028 { 2029 return mt76_queue_is_npu(q) && 2030 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 2031 } 2032 2033 static inline bool mt76_queue_is_npu_txfree(struct mt76_queue *q) 2034 { 2035 if (q->flags & MT_QFLAG_WED) 2036 return false; 2037 2038 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 2039 } 2040 2041 struct mt76_txwi_cache * 2042 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 2043 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 2044 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 2045 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 2046 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 2047 struct mt76_txwi_cache *r, dma_addr_t phys); 2048 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 2049 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 2050 { 2051 struct page *page = virt_to_head_page(buf); 2052 2053 page_pool_put_full_page(pp_page_to_nmdesc(page)->pp, page, 2054 allow_direct); 2055 } 2056 2057 static inline void * 2058 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 2059 { 2060 struct page *page; 2061 2062 page = page_pool_alloc_frag(q->page_pool, offset, size, 2063 GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32); 2064 if (!page) 2065 return NULL; 2066 2067 return page_address(page) + *offset; 2068 } 2069 2070 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 2071 { 2072 spin_lock_bh(&dev->token_lock); 2073 __mt76_set_tx_blocked(dev, blocked); 2074 spin_unlock_bh(&dev->token_lock); 2075 } 2076 2077 static inline int 2078 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 2079 { 2080 int token; 2081 2082 spin_lock_bh(&dev->token_lock); 2083 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 2084 spin_unlock_bh(&dev->token_lock); 2085 2086 return token; 2087 } 2088 2089 static inline struct mt76_txwi_cache * 2090 mt76_token_put(struct mt76_dev *dev, int token) 2091 { 2092 struct mt76_txwi_cache *txwi; 2093 2094 spin_lock_bh(&dev->token_lock); 2095 txwi = idr_remove(&dev->token, token); 2096 spin_unlock_bh(&dev->token_lock); 2097 2098 return txwi; 2099 } 2100 2101 void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx); 2102 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 2103 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid); 2104 2105 static inline void 2106 mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif) 2107 { 2108 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 2109 2110 mlink->mvif = mvif; 2111 rcu_assign_pointer(mvif->link[0], mlink); 2112 } 2113 2114 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif); 2115 u16 mt76_select_links(struct ieee80211_vif *vif, int max_active_links); 2116 2117 static inline struct mt76_vif_link * 2118 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id) 2119 { 2120 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 2121 struct mt76_vif_data *mvif = mlink->mvif; 2122 2123 if (!link_id) 2124 return mlink; 2125 2126 return mt76_dereference(mvif->link[link_id], dev); 2127 } 2128 2129 static inline struct mt76_vif_link * 2130 mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif, 2131 struct ieee80211_bss_conf *link_conf) 2132 { 2133 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 2134 struct mt76_vif_data *mvif = mlink->mvif; 2135 2136 if (link_conf == &vif->bss_conf || !link_conf->link_id) 2137 return mlink; 2138 2139 return mt76_dereference(mvif->link[link_conf->link_id], dev); 2140 } 2141 2142 static inline struct mt76_phy * 2143 mt76_vif_link_phy(struct mt76_vif_link *mlink) 2144 { 2145 struct mt76_chanctx *ctx; 2146 2147 if (!mlink->ctx) 2148 return NULL; 2149 2150 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv; 2151 2152 return ctx->phy; 2153 } 2154 2155 #endif 2156