1 #ifndef __iop_spu_defs_h 2 #define __iop_spu_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_spu.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:08:46 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r 11 * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 /* Main access macros */ 17 #ifndef REG_RD 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #endif 22 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #endif 28 29 #ifndef REG_RD_VECT 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34 #endif 35 36 #ifndef REG_WR_VECT 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41 #endif 42 43 #ifndef REG_RD_INT 44 #define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46 #endif 47 48 #ifndef REG_WR_INT 49 #define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51 #endif 52 53 #ifndef REG_RD_INT_VECT 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57 #endif 58 59 #ifndef REG_WR_INT_VECT 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63 #endif 64 65 #ifndef REG_TYPE_CONV 66 #define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68 #endif 69 70 #ifndef reg_page_size 71 #define reg_page_size 8192 72 #endif 73 74 #ifndef REG_ADDR 75 #define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77 #endif 78 79 #ifndef REG_ADDR_VECT 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83 #endif 84 85 /* C-code for register scope iop_spu */ 86 87 #define STRIDE_iop_spu_rw_r 4 88 /* Register rw_r, scope iop_spu, type rw */ 89 typedef unsigned int reg_iop_spu_rw_r; 90 #define REG_RD_ADDR_iop_spu_rw_r 0 91 #define REG_WR_ADDR_iop_spu_rw_r 0 92 93 /* Register rw_seq_pc, scope iop_spu, type rw */ 94 typedef struct { 95 unsigned int addr : 12; 96 unsigned int dummy1 : 20; 97 } reg_iop_spu_rw_seq_pc; 98 #define REG_RD_ADDR_iop_spu_rw_seq_pc 64 99 #define REG_WR_ADDR_iop_spu_rw_seq_pc 64 100 101 /* Register rw_fsm_pc, scope iop_spu, type rw */ 102 typedef struct { 103 unsigned int addr : 12; 104 unsigned int dummy1 : 20; 105 } reg_iop_spu_rw_fsm_pc; 106 #define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 107 #define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 108 109 /* Register rw_ctrl, scope iop_spu, type rw */ 110 typedef struct { 111 unsigned int fsm : 1; 112 unsigned int en : 1; 113 unsigned int dummy1 : 30; 114 } reg_iop_spu_rw_ctrl; 115 #define REG_RD_ADDR_iop_spu_rw_ctrl 72 116 #define REG_WR_ADDR_iop_spu_rw_ctrl 72 117 118 /* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ 119 typedef struct { 120 unsigned int val0 : 5; 121 unsigned int src0 : 3; 122 unsigned int val1 : 5; 123 unsigned int src1 : 3; 124 unsigned int val2 : 5; 125 unsigned int src2 : 3; 126 unsigned int val3 : 5; 127 unsigned int src3 : 3; 128 } reg_iop_spu_rw_fsm_inputs3_0; 129 #define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 130 #define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 131 132 /* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ 133 typedef struct { 134 unsigned int val4 : 5; 135 unsigned int src4 : 3; 136 unsigned int val5 : 5; 137 unsigned int src5 : 3; 138 unsigned int val6 : 5; 139 unsigned int src6 : 3; 140 unsigned int val7 : 5; 141 unsigned int src7 : 3; 142 } reg_iop_spu_rw_fsm_inputs7_4; 143 #define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 144 #define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 145 146 /* Register rw_gio_out, scope iop_spu, type rw */ 147 typedef unsigned int reg_iop_spu_rw_gio_out; 148 #define REG_RD_ADDR_iop_spu_rw_gio_out 84 149 #define REG_WR_ADDR_iop_spu_rw_gio_out 84 150 151 /* Register rw_bus0_out, scope iop_spu, type rw */ 152 typedef unsigned int reg_iop_spu_rw_bus0_out; 153 #define REG_RD_ADDR_iop_spu_rw_bus0_out 88 154 #define REG_WR_ADDR_iop_spu_rw_bus0_out 88 155 156 /* Register rw_bus1_out, scope iop_spu, type rw */ 157 typedef unsigned int reg_iop_spu_rw_bus1_out; 158 #define REG_RD_ADDR_iop_spu_rw_bus1_out 92 159 #define REG_WR_ADDR_iop_spu_rw_bus1_out 92 160 161 /* Register r_gio_in, scope iop_spu, type r */ 162 typedef unsigned int reg_iop_spu_r_gio_in; 163 #define REG_RD_ADDR_iop_spu_r_gio_in 96 164 165 /* Register r_bus0_in, scope iop_spu, type r */ 166 typedef unsigned int reg_iop_spu_r_bus0_in; 167 #define REG_RD_ADDR_iop_spu_r_bus0_in 100 168 169 /* Register r_bus1_in, scope iop_spu, type r */ 170 typedef unsigned int reg_iop_spu_r_bus1_in; 171 #define REG_RD_ADDR_iop_spu_r_bus1_in 104 172 173 /* Register rw_gio_out_set, scope iop_spu, type rw */ 174 typedef unsigned int reg_iop_spu_rw_gio_out_set; 175 #define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 176 #define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 177 178 /* Register rw_gio_out_clr, scope iop_spu, type rw */ 179 typedef unsigned int reg_iop_spu_rw_gio_out_clr; 180 #define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 181 #define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 182 183 /* Register rs_wr_stat, scope iop_spu, type rs */ 184 typedef struct { 185 unsigned int r0 : 1; 186 unsigned int r1 : 1; 187 unsigned int r2 : 1; 188 unsigned int r3 : 1; 189 unsigned int r4 : 1; 190 unsigned int r5 : 1; 191 unsigned int r6 : 1; 192 unsigned int r7 : 1; 193 unsigned int r8 : 1; 194 unsigned int r9 : 1; 195 unsigned int r10 : 1; 196 unsigned int r11 : 1; 197 unsigned int r12 : 1; 198 unsigned int r13 : 1; 199 unsigned int r14 : 1; 200 unsigned int r15 : 1; 201 unsigned int dummy1 : 16; 202 } reg_iop_spu_rs_wr_stat; 203 #define REG_RD_ADDR_iop_spu_rs_wr_stat 116 204 205 /* Register r_wr_stat, scope iop_spu, type r */ 206 typedef struct { 207 unsigned int r0 : 1; 208 unsigned int r1 : 1; 209 unsigned int r2 : 1; 210 unsigned int r3 : 1; 211 unsigned int r4 : 1; 212 unsigned int r5 : 1; 213 unsigned int r6 : 1; 214 unsigned int r7 : 1; 215 unsigned int r8 : 1; 216 unsigned int r9 : 1; 217 unsigned int r10 : 1; 218 unsigned int r11 : 1; 219 unsigned int r12 : 1; 220 unsigned int r13 : 1; 221 unsigned int r14 : 1; 222 unsigned int r15 : 1; 223 unsigned int dummy1 : 16; 224 } reg_iop_spu_r_wr_stat; 225 #define REG_RD_ADDR_iop_spu_r_wr_stat 120 226 227 /* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ 228 typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; 229 #define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 230 231 /* Register r_stat_in, scope iop_spu, type r */ 232 typedef struct { 233 unsigned int timer_grp_lo : 4; 234 unsigned int fifo_out_last : 1; 235 unsigned int fifo_out_rdy : 1; 236 unsigned int fifo_out_all : 1; 237 unsigned int fifo_in_rdy : 1; 238 unsigned int dmc_out_all : 1; 239 unsigned int dmc_out_dth : 1; 240 unsigned int dmc_out_eop : 1; 241 unsigned int dmc_out_dv : 1; 242 unsigned int dmc_out_last : 1; 243 unsigned int dmc_out_cmd_rq : 1; 244 unsigned int dmc_out_cmd_rdy : 1; 245 unsigned int pcrc_correct : 1; 246 unsigned int timer_grp_hi : 4; 247 unsigned int dmc_in_sth : 1; 248 unsigned int dmc_in_full : 1; 249 unsigned int dmc_in_cmd_rdy : 1; 250 unsigned int spu_gio_out : 4; 251 unsigned int sync_clk12 : 1; 252 unsigned int scrc_out_data : 1; 253 unsigned int scrc_in_err : 1; 254 unsigned int mc_busy : 1; 255 unsigned int mc_owned : 1; 256 } reg_iop_spu_r_stat_in; 257 #define REG_RD_ADDR_iop_spu_r_stat_in 128 258 259 /* Register r_trigger_in, scope iop_spu, type r */ 260 typedef unsigned int reg_iop_spu_r_trigger_in; 261 #define REG_RD_ADDR_iop_spu_r_trigger_in 132 262 263 /* Register r_special_stat, scope iop_spu, type r */ 264 typedef struct { 265 unsigned int c_flag : 1; 266 unsigned int v_flag : 1; 267 unsigned int z_flag : 1; 268 unsigned int n_flag : 1; 269 unsigned int xor_bus0_r2_0 : 1; 270 unsigned int xor_bus1_r3_0 : 1; 271 unsigned int xor_bus0m_r2_0 : 1; 272 unsigned int xor_bus1m_r3_0 : 1; 273 unsigned int fsm_in0 : 1; 274 unsigned int fsm_in1 : 1; 275 unsigned int fsm_in2 : 1; 276 unsigned int fsm_in3 : 1; 277 unsigned int fsm_in4 : 1; 278 unsigned int fsm_in5 : 1; 279 unsigned int fsm_in6 : 1; 280 unsigned int fsm_in7 : 1; 281 unsigned int event0 : 1; 282 unsigned int event1 : 1; 283 unsigned int event2 : 1; 284 unsigned int event3 : 1; 285 unsigned int dummy1 : 12; 286 } reg_iop_spu_r_special_stat; 287 #define REG_RD_ADDR_iop_spu_r_special_stat 136 288 289 /* Register rw_reg_access, scope iop_spu, type rw */ 290 typedef struct { 291 unsigned int addr : 13; 292 unsigned int dummy1 : 3; 293 unsigned int imm_hi : 16; 294 } reg_iop_spu_rw_reg_access; 295 #define REG_RD_ADDR_iop_spu_rw_reg_access 140 296 #define REG_WR_ADDR_iop_spu_rw_reg_access 140 297 298 #define STRIDE_iop_spu_rw_event_cfg 4 299 /* Register rw_event_cfg, scope iop_spu, type rw */ 300 typedef struct { 301 unsigned int addr : 12; 302 unsigned int src : 2; 303 unsigned int eq_en : 1; 304 unsigned int eq_inv : 1; 305 unsigned int gt_en : 1; 306 unsigned int gt_inv : 1; 307 unsigned int dummy1 : 14; 308 } reg_iop_spu_rw_event_cfg; 309 #define REG_RD_ADDR_iop_spu_rw_event_cfg 144 310 #define REG_WR_ADDR_iop_spu_rw_event_cfg 144 311 312 #define STRIDE_iop_spu_rw_event_mask 4 313 /* Register rw_event_mask, scope iop_spu, type rw */ 314 typedef unsigned int reg_iop_spu_rw_event_mask; 315 #define REG_RD_ADDR_iop_spu_rw_event_mask 160 316 #define REG_WR_ADDR_iop_spu_rw_event_mask 160 317 318 #define STRIDE_iop_spu_rw_event_val 4 319 /* Register rw_event_val, scope iop_spu, type rw */ 320 typedef unsigned int reg_iop_spu_rw_event_val; 321 #define REG_RD_ADDR_iop_spu_rw_event_val 176 322 #define REG_WR_ADDR_iop_spu_rw_event_val 176 323 324 /* Register rw_event_ret, scope iop_spu, type rw */ 325 typedef struct { 326 unsigned int addr : 12; 327 unsigned int dummy1 : 20; 328 } reg_iop_spu_rw_event_ret; 329 #define REG_RD_ADDR_iop_spu_rw_event_ret 192 330 #define REG_WR_ADDR_iop_spu_rw_event_ret 192 331 332 /* Register r_trace, scope iop_spu, type r */ 333 typedef struct { 334 unsigned int fsm : 1; 335 unsigned int en : 1; 336 unsigned int c_flag : 1; 337 unsigned int v_flag : 1; 338 unsigned int z_flag : 1; 339 unsigned int n_flag : 1; 340 unsigned int seq_addr : 12; 341 unsigned int dummy1 : 2; 342 unsigned int fsm_addr : 12; 343 } reg_iop_spu_r_trace; 344 #define REG_RD_ADDR_iop_spu_r_trace 196 345 346 /* Register r_fsm_trace, scope iop_spu, type r */ 347 typedef struct { 348 unsigned int fsm : 1; 349 unsigned int en : 1; 350 unsigned int tmr_done : 1; 351 unsigned int inp0 : 1; 352 unsigned int inp1 : 1; 353 unsigned int inp2 : 1; 354 unsigned int inp3 : 1; 355 unsigned int event0 : 1; 356 unsigned int event1 : 1; 357 unsigned int event2 : 1; 358 unsigned int event3 : 1; 359 unsigned int gio_out : 8; 360 unsigned int dummy1 : 1; 361 unsigned int fsm_addr : 12; 362 } reg_iop_spu_r_fsm_trace; 363 #define REG_RD_ADDR_iop_spu_r_fsm_trace 200 364 365 #define STRIDE_iop_spu_rw_brp 4 366 /* Register rw_brp, scope iop_spu, type rw */ 367 typedef struct { 368 unsigned int addr : 12; 369 unsigned int fsm : 1; 370 unsigned int en : 1; 371 unsigned int dummy1 : 18; 372 } reg_iop_spu_rw_brp; 373 #define REG_RD_ADDR_iop_spu_rw_brp 204 374 #define REG_WR_ADDR_iop_spu_rw_brp 204 375 376 377 /* Constants */ 378 enum { 379 regk_iop_spu_attn_hi = 0x00000005, 380 regk_iop_spu_attn_lo = 0x00000005, 381 regk_iop_spu_attn_r0 = 0x00000000, 382 regk_iop_spu_attn_r1 = 0x00000001, 383 regk_iop_spu_attn_r10 = 0x00000002, 384 regk_iop_spu_attn_r11 = 0x00000003, 385 regk_iop_spu_attn_r12 = 0x00000004, 386 regk_iop_spu_attn_r13 = 0x00000005, 387 regk_iop_spu_attn_r14 = 0x00000006, 388 regk_iop_spu_attn_r15 = 0x00000007, 389 regk_iop_spu_attn_r2 = 0x00000002, 390 regk_iop_spu_attn_r3 = 0x00000003, 391 regk_iop_spu_attn_r4 = 0x00000004, 392 regk_iop_spu_attn_r5 = 0x00000005, 393 regk_iop_spu_attn_r6 = 0x00000006, 394 regk_iop_spu_attn_r7 = 0x00000007, 395 regk_iop_spu_attn_r8 = 0x00000000, 396 regk_iop_spu_attn_r9 = 0x00000001, 397 regk_iop_spu_c = 0x00000000, 398 regk_iop_spu_flag = 0x00000002, 399 regk_iop_spu_gio_in = 0x00000000, 400 regk_iop_spu_gio_out = 0x00000005, 401 regk_iop_spu_gio_out0 = 0x00000008, 402 regk_iop_spu_gio_out1 = 0x00000009, 403 regk_iop_spu_gio_out2 = 0x0000000a, 404 regk_iop_spu_gio_out3 = 0x0000000b, 405 regk_iop_spu_gio_out4 = 0x0000000c, 406 regk_iop_spu_gio_out5 = 0x0000000d, 407 regk_iop_spu_gio_out6 = 0x0000000e, 408 regk_iop_spu_gio_out7 = 0x0000000f, 409 regk_iop_spu_n = 0x00000003, 410 regk_iop_spu_no = 0x00000000, 411 regk_iop_spu_r0 = 0x00000008, 412 regk_iop_spu_r1 = 0x00000009, 413 regk_iop_spu_r10 = 0x0000000a, 414 regk_iop_spu_r11 = 0x0000000b, 415 regk_iop_spu_r12 = 0x0000000c, 416 regk_iop_spu_r13 = 0x0000000d, 417 regk_iop_spu_r14 = 0x0000000e, 418 regk_iop_spu_r15 = 0x0000000f, 419 regk_iop_spu_r2 = 0x0000000a, 420 regk_iop_spu_r3 = 0x0000000b, 421 regk_iop_spu_r4 = 0x0000000c, 422 regk_iop_spu_r5 = 0x0000000d, 423 regk_iop_spu_r6 = 0x0000000e, 424 regk_iop_spu_r7 = 0x0000000f, 425 regk_iop_spu_r8 = 0x00000008, 426 regk_iop_spu_r9 = 0x00000009, 427 regk_iop_spu_reg_hi = 0x00000002, 428 regk_iop_spu_reg_lo = 0x00000002, 429 regk_iop_spu_rw_brp_default = 0x00000000, 430 regk_iop_spu_rw_brp_size = 0x00000004, 431 regk_iop_spu_rw_ctrl_default = 0x00000000, 432 regk_iop_spu_rw_event_cfg_size = 0x00000004, 433 regk_iop_spu_rw_event_mask_size = 0x00000004, 434 regk_iop_spu_rw_event_val_size = 0x00000004, 435 regk_iop_spu_rw_gio_out_default = 0x00000000, 436 regk_iop_spu_rw_r_size = 0x00000010, 437 regk_iop_spu_rw_reg_access_default = 0x00000000, 438 regk_iop_spu_stat_in = 0x00000002, 439 regk_iop_spu_statin_hi = 0x00000004, 440 regk_iop_spu_statin_lo = 0x00000004, 441 regk_iop_spu_trig = 0x00000003, 442 regk_iop_spu_trigger = 0x00000006, 443 regk_iop_spu_v = 0x00000001, 444 regk_iop_spu_wsts_gioout_spec = 0x00000001, 445 regk_iop_spu_xor = 0x00000003, 446 regk_iop_spu_xor_bus0_r2_0 = 0x00000000, 447 regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, 448 regk_iop_spu_xor_bus1_r3_0 = 0x00000001, 449 regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, 450 regk_iop_spu_yes = 0x00000001, 451 regk_iop_spu_z = 0x00000002 452 }; 453 #endif /* __iop_spu_defs_h */ 454