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Searched defs:regUVD_MPC_SET_MUXA0 (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1042 #define regUVD_MPC_SET_MUXA0 0x02ce macro
H A Dvcn_4_0_5_offset.h441 #define regUVD_MPC_SET_MUXA0 0x01d6 macro
H A Dvcn_4_0_0_offset.h458 #define regUVD_MPC_SET_MUXA0 0x01d6 macro
H A Dvcn_4_0_3_offset.h460 #define regUVD_MPC_SET_MUXA0 0x01d6 macro