1 /*
2 * SMP support for R-Mobile / SH-Mobile - r8a7779 portion
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/smp.h>
23 #include <linux/spinlock.h>
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <mach/common.h>
27 #include <mach/r8a7779.h>
28 #include <asm/smp_plat.h>
29 #include <asm/smp_scu.h>
30 #include <asm/smp_twd.h>
31 #include <asm/hardware/gic.h>
32
33 #define AVECR 0xfe700040
34
35 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
36 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
37 .chan_bit = 1, /* ARM1 */
38 .isr_bit = 1, /* ARM1 */
39 };
40
41 static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
42 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
43 .chan_bit = 2, /* ARM2 */
44 .isr_bit = 2, /* ARM2 */
45 };
46
47 static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
48 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
49 .chan_bit = 3, /* ARM3 */
50 .isr_bit = 3, /* ARM3 */
51 };
52
53 static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
54 [1] = &r8a7779_ch_cpu1,
55 [2] = &r8a7779_ch_cpu2,
56 [3] = &r8a7779_ch_cpu3,
57 };
58
scu_base_addr(void)59 static void __iomem *scu_base_addr(void)
60 {
61 return (void __iomem *)0xf0000000;
62 }
63
64 static DEFINE_SPINLOCK(scu_lock);
65 static unsigned long tmp;
66
modify_scu_cpu_psr(unsigned long set,unsigned long clr)67 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
68 {
69 void __iomem *scu_base = scu_base_addr();
70
71 spin_lock(&scu_lock);
72 tmp = __raw_readl(scu_base + 8);
73 tmp &= ~clr;
74 tmp |= set;
75 spin_unlock(&scu_lock);
76
77 /* disable cache coherency after releasing the lock */
78 __raw_writel(tmp, scu_base + 8);
79 }
80
r8a7779_get_core_count(void)81 unsigned int __init r8a7779_get_core_count(void)
82 {
83 void __iomem *scu_base = scu_base_addr();
84
85 #ifdef CONFIG_HAVE_ARM_TWD
86 /* twd_base needs to be initialized before percpu_timer_setup() */
87 twd_base = (void __iomem *)0xf0000600;
88 #endif
89
90 return scu_get_core_count(scu_base);
91 }
92
r8a7779_platform_cpu_kill(unsigned int cpu)93 int r8a7779_platform_cpu_kill(unsigned int cpu)
94 {
95 struct r8a7779_pm_ch *ch = NULL;
96 int ret = -EIO;
97
98 cpu = cpu_logical_map(cpu);
99
100 /* disable cache coherency */
101 modify_scu_cpu_psr(3 << (cpu * 8), 0);
102
103 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
104 ch = r8a7779_ch_cpu[cpu];
105
106 if (ch)
107 ret = r8a7779_sysc_power_down(ch);
108
109 return ret ? ret : 1;
110 }
111
r8a7779_secondary_init(unsigned int cpu)112 void __cpuinit r8a7779_secondary_init(unsigned int cpu)
113 {
114 gic_secondary_init(0);
115 }
116
r8a7779_boot_secondary(unsigned int cpu)117 int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
118 {
119 struct r8a7779_pm_ch *ch = NULL;
120 int ret = -EIO;
121
122 cpu = cpu_logical_map(cpu);
123
124 /* enable cache coherency */
125 modify_scu_cpu_psr(0, 3 << (cpu * 8));
126
127 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
128 ch = r8a7779_ch_cpu[cpu];
129
130 if (ch)
131 ret = r8a7779_sysc_power_up(ch);
132
133 return ret;
134 }
135
r8a7779_smp_prepare_cpus(void)136 void __init r8a7779_smp_prepare_cpus(void)
137 {
138 int cpu = cpu_logical_map(0);
139
140 scu_enable(scu_base_addr());
141
142 /* Map the reset vector (in headsmp.S) */
143 __raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
144
145 /* enable cache coherency on CPU0 */
146 modify_scu_cpu_psr(0, 3 << (cpu * 8));
147
148 r8a7779_pm_init();
149
150 /* power off secondary CPUs */
151 r8a7779_platform_cpu_kill(1);
152 r8a7779_platform_cpu_kill(2);
153 r8a7779_platform_cpu_kill(3);
154 }
155