1 /*
2 * R8A66597 UDC
3 *
4 * Copyright (C) 2007-2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13 #ifndef __R8A66597_H__
14 #define __R8A66597_H__
15
16 #ifdef CONFIG_HAVE_CLK
17 #include <linux/clk.h>
18 #endif
19
20 #include <linux/usb/r8a66597.h>
21
22 #define R8A66597_MAX_SAMPLING 10
23
24 #define R8A66597_MAX_NUM_PIPE 8
25 #define R8A66597_MAX_NUM_BULK 3
26 #define R8A66597_MAX_NUM_ISOC 2
27 #define R8A66597_MAX_NUM_INT 2
28
29 #define R8A66597_BASE_PIPENUM_BULK 3
30 #define R8A66597_BASE_PIPENUM_ISOC 1
31 #define R8A66597_BASE_PIPENUM_INT 6
32
33 #define R8A66597_BASE_BUFNUM 6
34 #define R8A66597_MAX_BUFNUM 0x4F
35
36 #define is_bulk_pipe(pipenum) \
37 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
38 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
39 #define is_interrupt_pipe(pipenum) \
40 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
41 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
42 #define is_isoc_pipe(pipenum) \
43 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
44 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
45
46 #define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
47 struct r8a66597_pipe_info {
48 u16 pipe;
49 u16 epnum;
50 u16 maxpacket;
51 u16 type;
52 u16 interval;
53 u16 dir_in;
54 };
55
56 struct r8a66597_request {
57 struct usb_request req;
58 struct list_head queue;
59 };
60
61 struct r8a66597_ep {
62 struct usb_ep ep;
63 struct r8a66597 *r8a66597;
64 struct r8a66597_dma *dma;
65
66 struct list_head queue;
67 unsigned busy:1;
68 unsigned wedge:1;
69 unsigned internal_ccpl:1; /* use only control */
70
71 /* this member can able to after r8a66597_enable */
72 unsigned use_dma:1;
73 u16 pipenum;
74 u16 type;
75 const struct usb_endpoint_descriptor *desc;
76 /* register address */
77 unsigned char fifoaddr;
78 unsigned char fifosel;
79 unsigned char fifoctr;
80 unsigned char pipectr;
81 unsigned char pipetre;
82 unsigned char pipetrn;
83 };
84
85 struct r8a66597_dma {
86 unsigned used:1;
87 unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
88 };
89
90 struct r8a66597 {
91 spinlock_t lock;
92 void __iomem *reg;
93 void __iomem *sudmac_reg;
94
95 #ifdef CONFIG_HAVE_CLK
96 struct clk *clk;
97 #endif
98 struct r8a66597_platdata *pdata;
99
100 struct usb_gadget gadget;
101 struct usb_gadget_driver *driver;
102
103 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
104 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
105 struct r8a66597_ep *epaddr2ep[16];
106 struct r8a66597_dma dma;
107
108 struct timer_list timer;
109 struct usb_request *ep0_req; /* for internal request */
110 u16 ep0_data; /* for internal request */
111 u16 old_vbus;
112 u16 scount;
113 u16 old_dvsq;
114
115 /* pipe config */
116 unsigned char bulk;
117 unsigned char interrupt;
118 unsigned char isochronous;
119 unsigned char num_dma;
120
121 unsigned irq_sense_low:1;
122 };
123
124 #define gadget_to_r8a66597(_gadget) \
125 container_of(_gadget, struct r8a66597, gadget)
126 #define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
127 #define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent)
128
r8a66597_read(struct r8a66597 * r8a66597,unsigned long offset)129 static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
130 {
131 return ioread16(r8a66597->reg + offset);
132 }
133
r8a66597_read_fifo(struct r8a66597 * r8a66597,unsigned long offset,unsigned char * buf,int len)134 static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
135 unsigned long offset,
136 unsigned char *buf,
137 int len)
138 {
139 void __iomem *fifoaddr = r8a66597->reg + offset;
140 unsigned int data = 0;
141 int i;
142
143 if (r8a66597->pdata->on_chip) {
144 /* 32-bit accesses for on_chip controllers */
145
146 /* aligned buf case */
147 if (len >= 4 && !((unsigned long)buf & 0x03)) {
148 ioread32_rep(fifoaddr, buf, len / 4);
149 buf += len & ~0x03;
150 len &= 0x03;
151 }
152
153 /* unaligned buf case */
154 for (i = 0; i < len; i++) {
155 if (!(i & 0x03))
156 data = ioread32(fifoaddr);
157
158 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
159 }
160 } else {
161 /* 16-bit accesses for external controllers */
162
163 /* aligned buf case */
164 if (len >= 2 && !((unsigned long)buf & 0x01)) {
165 ioread16_rep(fifoaddr, buf, len / 2);
166 buf += len & ~0x01;
167 len &= 0x01;
168 }
169
170 /* unaligned buf case */
171 for (i = 0; i < len; i++) {
172 if (!(i & 0x01))
173 data = ioread16(fifoaddr);
174
175 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
176 }
177 }
178 }
179
r8a66597_write(struct r8a66597 * r8a66597,u16 val,unsigned long offset)180 static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
181 unsigned long offset)
182 {
183 iowrite16(val, r8a66597->reg + offset);
184 }
185
r8a66597_mdfy(struct r8a66597 * r8a66597,u16 val,u16 pat,unsigned long offset)186 static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
187 u16 val, u16 pat, unsigned long offset)
188 {
189 u16 tmp;
190 tmp = r8a66597_read(r8a66597, offset);
191 tmp = tmp & (~pat);
192 tmp = tmp | val;
193 r8a66597_write(r8a66597, tmp, offset);
194 }
195
196 #define r8a66597_bclr(r8a66597, val, offset) \
197 r8a66597_mdfy(r8a66597, 0, val, offset)
198 #define r8a66597_bset(r8a66597, val, offset) \
199 r8a66597_mdfy(r8a66597, val, 0, offset)
200
r8a66597_write_fifo(struct r8a66597 * r8a66597,struct r8a66597_ep * ep,unsigned char * buf,int len)201 static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
202 struct r8a66597_ep *ep,
203 unsigned char *buf,
204 int len)
205 {
206 void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr;
207 int adj = 0;
208 int i;
209
210 if (r8a66597->pdata->on_chip) {
211 /* 32-bit access only if buf is 32-bit aligned */
212 if (len >= 4 && !((unsigned long)buf & 0x03)) {
213 iowrite32_rep(fifoaddr, buf, len / 4);
214 buf += len & ~0x03;
215 len &= 0x03;
216 }
217 } else {
218 /* 16-bit access only if buf is 16-bit aligned */
219 if (len >= 2 && !((unsigned long)buf & 0x01)) {
220 iowrite16_rep(fifoaddr, buf, len / 2);
221 buf += len & ~0x01;
222 len &= 0x01;
223 }
224 }
225
226 /* adjust fifo address in the little endian case */
227 if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
228 if (r8a66597->pdata->on_chip)
229 adj = 0x03; /* 32-bit wide */
230 else
231 adj = 0x01; /* 16-bit wide */
232 }
233
234 if (r8a66597->pdata->wr0_shorted_to_wr1)
235 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
236 for (i = 0; i < len; i++)
237 iowrite8(buf[i], fifoaddr + adj - (i & adj));
238 if (r8a66597->pdata->wr0_shorted_to_wr1)
239 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
240 }
241
get_xtal_from_pdata(struct r8a66597_platdata * pdata)242 static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
243 {
244 u16 clock = 0;
245
246 switch (pdata->xtal) {
247 case R8A66597_PLATDATA_XTAL_12MHZ:
248 clock = XTAL12;
249 break;
250 case R8A66597_PLATDATA_XTAL_24MHZ:
251 clock = XTAL24;
252 break;
253 case R8A66597_PLATDATA_XTAL_48MHZ:
254 clock = XTAL48;
255 break;
256 default:
257 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
258 break;
259 }
260
261 return clock;
262 }
263
r8a66597_sudmac_read(struct r8a66597 * r8a66597,unsigned long offset)264 static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
265 unsigned long offset)
266 {
267 return ioread32(r8a66597->sudmac_reg + offset);
268 }
269
r8a66597_sudmac_write(struct r8a66597 * r8a66597,u32 val,unsigned long offset)270 static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
271 unsigned long offset)
272 {
273 iowrite32(val, r8a66597->sudmac_reg + offset);
274 }
275
276 #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
277 #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
278 #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
279
280 #define enable_irq_ready(r8a66597, pipenum) \
281 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
282 #define disable_irq_ready(r8a66597, pipenum) \
283 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
284 #define enable_irq_empty(r8a66597, pipenum) \
285 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
286 #define disable_irq_empty(r8a66597, pipenum) \
287 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
288 #define enable_irq_nrdy(r8a66597, pipenum) \
289 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
290 #define disable_irq_nrdy(r8a66597, pipenum) \
291 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
292
293 #endif /* __R8A66597_H__ */
294
295