1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #include <rm/rm.h> 6 7 #include "nvrm/gsp.h" 8 9 static const struct nvkm_rm_wpr 10 r570_wpr_libos2 = { 11 .os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS2, 12 .base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X, 13 .heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB, 14 }; 15 16 static const struct nvkm_rm_wpr 17 r570_wpr_libos3 = { 18 .os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL, 19 .base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_TU10X, 20 .heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB, 21 }; 22 23 static const struct nvkm_rm_wpr 24 r570_wpr_libos3_gh100 = { 25 .os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL, 26 .base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100, 27 .heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB, 28 .heap_size_non_wpr = 0x200000, 29 .offset_set_by_acr = true, 30 }; 31 32 static const struct nvkm_rm_wpr 33 r570_wpr_libos3_gb10x = { 34 .os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL, 35 .base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100, 36 .heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB, 37 .heap_size_non_wpr = 0x200000, 38 .rsvd_size_pmu = ALIGN(0x0800000 + 0x1000000 + 0x0001000, 0x20000), 39 .offset_set_by_acr = true, 40 }; 41 42 static const struct nvkm_rm_wpr 43 r570_wpr_libos3_gb20x = { 44 .os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL, 45 .base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100, 46 .heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB, 47 .heap_size_non_wpr = 0x220000, 48 .rsvd_size_pmu = ALIGN(0x0800000 + 0x1000000 + 0x0001000, 0x20000), 49 .offset_set_by_acr = true, 50 }; 51 52 static const struct nvkm_rm_api 53 r570_api = { 54 .gsp = &r570_gsp, 55 .rpc = &r535_rpc, 56 .ctrl = &r535_ctrl, 57 .alloc = &r535_alloc, 58 .client = &r570_client, 59 .device = &r535_device, 60 .fbsr = &r570_fbsr, 61 .disp = &r570_disp, 62 .fifo = &r570_fifo, 63 .ce = &r535_ce, 64 .gr = &r570_gr, 65 .nvdec = &r535_nvdec, 66 .nvenc = &r535_nvenc, 67 .nvjpg = &r535_nvjpg, 68 .ofa = &r570_ofa, 69 }; 70 71 const struct nvkm_rm_impl 72 r570_rm_tu102 = { 73 .wpr = &r570_wpr_libos2, 74 .api = &r570_api, 75 }; 76 77 const struct nvkm_rm_impl 78 r570_rm_ga102 = { 79 .wpr = &r570_wpr_libos3, 80 .api = &r570_api, 81 }; 82 83 const struct nvkm_rm_impl 84 r570_rm_gh100 = { 85 .wpr = &r570_wpr_libos3_gh100, 86 .api = &r570_api, 87 }; 88 89 const struct nvkm_rm_impl 90 r570_rm_gb10x = { 91 .wpr = &r570_wpr_libos3_gb10x, 92 .api = &r570_api, 93 }; 94 95 const struct nvkm_rm_impl 96 r570_rm_gb20x = { 97 .wpr = &r570_wpr_libos3_gb20x, 98 .api = &r570_api, 99 }; 100