1 /*
2 * Copyright 2023 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include <engine/fifo/priv.h>
23 #include <engine/fifo/cgrp.h>
24 #include <engine/fifo/chan.h>
25 #include <engine/fifo/chid.h>
26 #include <engine/fifo/runl.h>
27
28 #include <core/gpuobj.h>
29 #include <subdev/gsp.h>
30 #include <subdev/mmu.h>
31 #include <subdev/vfn.h>
32 #include <engine/gr.h>
33
34 #include <rm/engine.h>
35
36 #include <nvhw/drf.h>
37
38 #include "nvrm/fifo.h"
39 #include "nvrm/engine.h"
40
41 static u32
r535_chan_doorbell_handle(struct nvkm_chan * chan)42 r535_chan_doorbell_handle(struct nvkm_chan *chan)
43 {
44 struct nvkm_gsp *gsp = chan->rm.object.client->gsp;
45
46 return gsp->rm->gpu->fifo.chan.doorbell_handle(chan);
47 }
48
49 static void
r535_chan_stop(struct nvkm_chan * chan)50 r535_chan_stop(struct nvkm_chan *chan)
51 {
52 }
53
54 static void
r535_chan_start(struct nvkm_chan * chan)55 r535_chan_start(struct nvkm_chan *chan)
56 {
57 }
58
59 static void
r535_chan_ramfc_clear(struct nvkm_chan * chan)60 r535_chan_ramfc_clear(struct nvkm_chan *chan)
61 {
62 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
63
64 nvkm_gsp_rm_free(&chan->rm.object);
65
66 dma_free_coherent(fifo->engine.subdev.device->dev, fifo->rm.mthdbuf_size,
67 chan->rm.mthdbuf.ptr, chan->rm.mthdbuf.addr);
68
69 nvkm_cgrp_vctx_put(chan->cgrp, &chan->rm.grctx);
70 }
71
72 #define CHID_PER_USERD 8
73
74 static int
r535_chan_alloc(struct nvkm_gsp_device * device,u32 handle,u32 nv2080_engine_type,u8 runq,bool priv,int chid,u64 inst_addr,u64 userd_addr,u64 mthdbuf_addr,struct nvkm_vmm * vmm,u64 gpfifo_offset,u32 gpfifo_length,struct nvkm_gsp_object * chan)75 r535_chan_alloc(struct nvkm_gsp_device *device, u32 handle, u32 nv2080_engine_type, u8 runq,
76 bool priv, int chid, u64 inst_addr, u64 userd_addr, u64 mthdbuf_addr,
77 struct nvkm_vmm *vmm, u64 gpfifo_offset, u32 gpfifo_length,
78 struct nvkm_gsp_object *chan)
79 {
80 struct nvkm_gsp *gsp = device->object.client->gsp;
81 struct nvkm_fifo *fifo = gsp->subdev.device->fifo;
82 const int userd_p = chid / CHID_PER_USERD;
83 const int userd_i = chid % CHID_PER_USERD;
84 NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS *args;
85
86 args = nvkm_gsp_rm_alloc_get(&device->object, handle,
87 fifo->func->chan.user.oclass, sizeof(*args), chan);
88 if (WARN_ON(IS_ERR(args)))
89 return PTR_ERR(args);
90
91 args->gpFifoOffset = gpfifo_offset;
92 args->gpFifoEntries = gpfifo_length / 8;
93
94 args->flags = NVDEF(NVOS04, FLAGS, CHANNEL_TYPE, PHYSICAL);
95 args->flags |= NVDEF(NVOS04, FLAGS, VPR, FALSE);
96 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_MAP_REFCOUNTING, FALSE);
97 args->flags |= NVVAL(NVOS04, FLAGS, GROUP_CHANNEL_RUNQUEUE, runq);
98 if (!priv)
99 args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, FALSE);
100 else
101 args->flags |= NVDEF(NVOS04, FLAGS, PRIVILEGED_CHANNEL, TRUE);
102 args->flags |= NVDEF(NVOS04, FLAGS, DELAY_CHANNEL_SCHEDULING, FALSE);
103 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_PHYSICAL_MODE_CE, FALSE);
104
105 args->flags |= NVVAL(NVOS04, FLAGS, CHANNEL_USERD_INDEX_VALUE, userd_i);
106 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_FIXED, FALSE);
107 args->flags |= NVVAL(NVOS04, FLAGS, CHANNEL_USERD_INDEX_PAGE_VALUE, userd_p);
108 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_USERD_INDEX_PAGE_FIXED, TRUE);
109
110 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_DENY_AUTH_LEVEL_PRIV, FALSE);
111 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_SKIP_SCRUBBER, FALSE);
112 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_CLIENT_MAP_FIFO, FALSE);
113 args->flags |= NVDEF(NVOS04, FLAGS, SET_EVICT_LAST_CE_PREFETCH_CHANNEL, FALSE);
114 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_VGPU_PLUGIN_CONTEXT, FALSE);
115 args->flags |= NVDEF(NVOS04, FLAGS, CHANNEL_PBDMA_ACQUIRE_TIMEOUT, FALSE);
116 args->flags |= NVDEF(NVOS04, FLAGS, GROUP_CHANNEL_THREAD, DEFAULT);
117 args->flags |= NVDEF(NVOS04, FLAGS, MAP_CHANNEL, FALSE);
118 args->flags |= NVDEF(NVOS04, FLAGS, SKIP_CTXBUFFER_ALLOC, FALSE);
119
120 args->hVASpace = vmm->rm.object.handle;
121 args->engineType = nv2080_engine_type;
122
123 args->instanceMem.base = inst_addr;
124 args->instanceMem.size = fifo->func->chan.func->inst->size;
125 args->instanceMem.addressSpace = 2;
126 args->instanceMem.cacheAttrib = 1;
127
128 args->userdMem.base = userd_addr;
129 args->userdMem.size = fifo->func->chan.func->userd->size;
130 args->userdMem.addressSpace = 2;
131 args->userdMem.cacheAttrib = 1;
132
133 args->ramfcMem.base = inst_addr;
134 args->ramfcMem.size = 0x200;
135 args->ramfcMem.addressSpace = 2;
136 args->ramfcMem.cacheAttrib = 1;
137
138 args->mthdbufMem.base = mthdbuf_addr;
139 args->mthdbufMem.size = fifo->rm.mthdbuf_size;
140 args->mthdbufMem.addressSpace = 1;
141 args->mthdbufMem.cacheAttrib = 0;
142
143 if (!priv)
144 args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, USER);
145 else
146 args->internalFlags = NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, PRIVILEGE, ADMIN);
147 args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ERROR_NOTIFIER_TYPE, NONE);
148 args->internalFlags |= NVDEF(NV_KERNELCHANNEL, ALLOC_INTERNALFLAGS, ECC_ERROR_NOTIFIER_TYPE, NONE);
149
150 return nvkm_gsp_rm_alloc_wr(chan, args);
151 }
152
153 static int
r535_chan_ramfc_write(struct nvkm_chan * chan,u64 offset,u64 length,u32 devm,bool priv)154 r535_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
155 {
156 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo;
157 struct nvkm_engn *engn;
158 struct nvkm_device *device = fifo->engine.subdev.device;
159 const struct nvkm_rm_api *rmapi = device->gsp->rm->api;
160 u32 eT = ~0;
161 int ret;
162
163 if (unlikely(device->gr && !device->gr->engine.subdev.oneinit)) {
164 ret = nvkm_subdev_oneinit(&device->gr->engine.subdev);
165 if (ret)
166 return ret;
167 }
168
169 nvkm_runl_foreach_engn(engn, chan->cgrp->runl) {
170 eT = engn->id;
171 break;
172 }
173
174 if (WARN_ON(eT == ~0))
175 return -EINVAL;
176
177 chan->rm.mthdbuf.ptr = dma_alloc_coherent(fifo->engine.subdev.device->dev,
178 fifo->rm.mthdbuf_size,
179 &chan->rm.mthdbuf.addr, GFP_KERNEL);
180 if (!chan->rm.mthdbuf.ptr)
181 return -ENOMEM;
182
183 ret = rmapi->fifo->chan.alloc(&chan->vmm->rm.device, NVKM_RM_CHAN(chan->id),
184 eT, chan->runq, priv, chan->id, chan->inst->addr,
185 nvkm_memory_addr(chan->userd.mem) + chan->userd.base,
186 chan->rm.mthdbuf.addr, chan->vmm, offset, length,
187 &chan->rm.object);
188 if (ret)
189 return ret;
190
191 if (1) {
192 NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS *ctrl;
193
194 if (1) {
195 NVA06F_CTRL_BIND_PARAMS *ctrl;
196
197 ctrl = nvkm_gsp_rm_ctrl_get(&chan->rm.object,
198 NVA06F_CTRL_CMD_BIND, sizeof(*ctrl));
199 if (WARN_ON(IS_ERR(ctrl)))
200 return PTR_ERR(ctrl);
201
202 ctrl->engineType = eT;
203
204 ret = nvkm_gsp_rm_ctrl_wr(&chan->rm.object, ctrl);
205 if (ret)
206 return ret;
207 }
208
209 ctrl = nvkm_gsp_rm_ctrl_get(&chan->rm.object,
210 NVA06F_CTRL_CMD_GPFIFO_SCHEDULE, sizeof(*ctrl));
211 if (WARN_ON(IS_ERR(ctrl)))
212 return PTR_ERR(ctrl);
213
214 ctrl->bEnable = 1;
215 ret = nvkm_gsp_rm_ctrl_wr(&chan->rm.object, ctrl);
216 }
217
218 return ret;
219 }
220
221 static const struct nvkm_chan_func_ramfc
222 r535_chan_ramfc = {
223 .write = r535_chan_ramfc_write,
224 .clear = r535_chan_ramfc_clear,
225 .devm = 0xfff,
226 .priv = true,
227 };
228
229 static const struct nvkm_chan_func
230 r535_chan = {
231 .inst = &gf100_chan_inst,
232 .userd = &gv100_chan_userd,
233 .ramfc = &r535_chan_ramfc,
234 .start = r535_chan_start,
235 .stop = r535_chan_stop,
236 .doorbell_handle = r535_chan_doorbell_handle,
237 };
238
239 static int
r535_engn_nonstall(struct nvkm_engn * engn)240 r535_engn_nonstall(struct nvkm_engn *engn)
241 {
242 struct nvkm_subdev *subdev = &engn->engine->subdev;
243 int ret;
244
245 ret = nvkm_gsp_intr_nonstall(subdev->device->gsp, subdev->type, subdev->inst);
246 WARN_ON(ret == -ENOENT);
247 return ret;
248 }
249
250 static const struct nvkm_engn_func
251 r535_engn_ce = {
252 .nonstall = r535_engn_nonstall,
253 };
254
255 static int
r535_gr_ctor(struct nvkm_engn * engn,struct nvkm_vctx * vctx,struct nvkm_chan * chan)256 r535_gr_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx, struct nvkm_chan *chan)
257 {
258 /* RM requires GR context buffers to remain mapped until after the
259 * channel has been destroyed (as opposed to after the last gr obj
260 * has been deleted).
261 *
262 * Take an extra ref here, which will be released once the channel
263 * object has been deleted.
264 */
265 refcount_inc(&vctx->refs);
266 chan->rm.grctx = vctx;
267 return 0;
268 }
269
270 static const struct nvkm_engn_func
271 r535_engn_gr = {
272 .nonstall = r535_engn_nonstall,
273 .ctor2 = r535_gr_ctor,
274 };
275
276 static int
r535_flcn_bind(struct nvkm_engn * engn,struct nvkm_vctx * vctx,struct nvkm_chan * chan)277 r535_flcn_bind(struct nvkm_engn *engn, struct nvkm_vctx *vctx, struct nvkm_chan *chan)
278 {
279 struct nvkm_gsp_client *client = &chan->vmm->rm.client;
280 NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS *ctrl;
281
282 ctrl = nvkm_gsp_rm_ctrl_get(&chan->vmm->rm.device.subdevice,
283 NV2080_CTRL_CMD_GPU_PROMOTE_CTX, sizeof(*ctrl));
284 if (IS_ERR(ctrl))
285 return PTR_ERR(ctrl);
286
287 ctrl->hClient = client->object.handle;
288 ctrl->hObject = chan->rm.object.handle;
289 ctrl->hChanClient = client->object.handle;
290 ctrl->virtAddress = vctx->vma->addr;
291 ctrl->size = vctx->inst->size;
292 ctrl->engineType = engn->id;
293 ctrl->ChID = chan->id;
294
295 return nvkm_gsp_rm_ctrl_wr(&chan->vmm->rm.device.subdevice, ctrl);
296 }
297
298 static int
r535_flcn_ctor(struct nvkm_engn * engn,struct nvkm_vctx * vctx,struct nvkm_chan * chan)299 r535_flcn_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx, struct nvkm_chan *chan)
300 {
301 int ret;
302
303 if (WARN_ON(!engn->rm.size))
304 return -EINVAL;
305
306 ret = nvkm_gpuobj_new(engn->engine->subdev.device, engn->rm.size, 0, true, NULL,
307 &vctx->inst);
308 if (ret)
309 return ret;
310
311 ret = nvkm_vmm_get(vctx->vmm, 12, vctx->inst->size, &vctx->vma);
312 if (ret)
313 return ret;
314
315 ret = nvkm_memory_map(vctx->inst, 0, vctx->vmm, vctx->vma, NULL, 0);
316 if (ret)
317 return ret;
318
319 return r535_flcn_bind(engn, vctx, chan);
320 }
321
322 static const struct nvkm_engn_func
323 r535_flcn = {
324 .nonstall = r535_engn_nonstall,
325 .ctor2 = r535_flcn_ctor,
326 };
327
328 static void
r535_runl_allow(struct nvkm_runl * runl,u32 engm)329 r535_runl_allow(struct nvkm_runl *runl, u32 engm)
330 {
331 }
332
333 static void
r535_runl_block(struct nvkm_runl * runl,u32 engm)334 r535_runl_block(struct nvkm_runl *runl, u32 engm)
335 {
336 }
337
338 static const struct nvkm_runl_func
339 r535_runl = {
340 .block = r535_runl_block,
341 .allow = r535_runl_allow,
342 };
343
344 void
r535_fifo_rc_chid(struct nvkm_fifo * fifo,int chid)345 r535_fifo_rc_chid(struct nvkm_fifo *fifo, int chid)
346 {
347 struct nvkm_chan *chan;
348 unsigned long flags;
349
350 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags);
351 if (!chan) {
352 nvkm_error(&fifo->engine.subdev, "rc: chid %d not found!\n", chid);
353 return;
354 }
355
356 nvkm_chan_error(chan, false);
357 nvkm_chan_put(&chan, flags);
358 }
359
360 static int
r535_fifo_rc_triggered(void * priv,u32 fn,void * repv,u32 repc)361 r535_fifo_rc_triggered(void *priv, u32 fn, void *repv, u32 repc)
362 {
363 rpc_rc_triggered_v17_02 *msg = repv;
364 struct nvkm_gsp *gsp = priv;
365
366 if (WARN_ON(repc < sizeof(*msg)))
367 return -EINVAL;
368
369 nvkm_error(&gsp->subdev, "rc: engn:%08x chid:%d type:%d scope:%d part:%d\n",
370 msg->nv2080EngineType, msg->chid, msg->exceptType, msg->scope,
371 msg->partitionAttributionId);
372
373 r535_fifo_rc_chid(gsp->subdev.device->fifo, msg->chid);
374 return 0;
375 }
376
377 static int
r535_fifo_xlat_rm_engine_type(u32 rm,enum nvkm_subdev_type * ptype,int * p2080)378 r535_fifo_xlat_rm_engine_type(u32 rm, enum nvkm_subdev_type *ptype, int *p2080)
379 {
380 #define RM_ENGINE_TYPE(RM,NVKM,INST) \
381 RM_ENGINE_TYPE_##RM: \
382 *ptype = NVKM_ENGINE_##NVKM; \
383 *p2080 = NV2080_ENGINE_TYPE_##RM; \
384 return INST
385
386 switch (rm) {
387 case RM_ENGINE_TYPE( GR0, GR, 0);
388 case RM_ENGINE_TYPE( COPY0, CE, 0);
389 case RM_ENGINE_TYPE( COPY1, CE, 1);
390 case RM_ENGINE_TYPE( COPY2, CE, 2);
391 case RM_ENGINE_TYPE( COPY3, CE, 3);
392 case RM_ENGINE_TYPE( COPY4, CE, 4);
393 case RM_ENGINE_TYPE( COPY5, CE, 5);
394 case RM_ENGINE_TYPE( COPY6, CE, 6);
395 case RM_ENGINE_TYPE( COPY7, CE, 7);
396 case RM_ENGINE_TYPE( COPY8, CE, 8);
397 case RM_ENGINE_TYPE( COPY9, CE, 9);
398 case RM_ENGINE_TYPE( NVDEC0, NVDEC, 0);
399 case RM_ENGINE_TYPE( NVDEC1, NVDEC, 1);
400 case RM_ENGINE_TYPE( NVDEC2, NVDEC, 2);
401 case RM_ENGINE_TYPE( NVDEC3, NVDEC, 3);
402 case RM_ENGINE_TYPE( NVDEC4, NVDEC, 4);
403 case RM_ENGINE_TYPE( NVDEC5, NVDEC, 5);
404 case RM_ENGINE_TYPE( NVDEC6, NVDEC, 6);
405 case RM_ENGINE_TYPE( NVDEC7, NVDEC, 7);
406 case RM_ENGINE_TYPE( NVENC0, NVENC, 0);
407 case RM_ENGINE_TYPE( NVENC1, NVENC, 1);
408 case RM_ENGINE_TYPE( NVENC2, NVENC, 2);
409 case RM_ENGINE_TYPE(NVJPEG0, NVJPG, 0);
410 case RM_ENGINE_TYPE(NVJPEG1, NVJPG, 1);
411 case RM_ENGINE_TYPE(NVJPEG2, NVJPG, 2);
412 case RM_ENGINE_TYPE(NVJPEG3, NVJPG, 3);
413 case RM_ENGINE_TYPE(NVJPEG4, NVJPG, 4);
414 case RM_ENGINE_TYPE(NVJPEG5, NVJPG, 5);
415 case RM_ENGINE_TYPE(NVJPEG6, NVJPG, 6);
416 case RM_ENGINE_TYPE(NVJPEG7, NVJPG, 7);
417 case RM_ENGINE_TYPE( SW, SW, 0);
418 case RM_ENGINE_TYPE( SEC2, SEC2, 0);
419 case RM_ENGINE_TYPE( OFA, OFA, 0);
420 default:
421 return -EINVAL;
422 }
423 #undef RM_ENGINE_TYPE
424 }
425
426 static int
r535_fifo_ectx_size(struct nvkm_fifo * fifo)427 r535_fifo_ectx_size(struct nvkm_fifo *fifo)
428 {
429 NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS *ctrl;
430 struct nvkm_gsp *gsp = fifo->engine.subdev.device->gsp;
431 struct nvkm_runl *runl;
432 struct nvkm_engn *engn;
433
434 ctrl = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
435 NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO,
436 sizeof(*ctrl));
437 if (WARN_ON(IS_ERR(ctrl)))
438 return PTR_ERR(ctrl);
439
440 for (int i = 0; i < ctrl->numConstructedFalcons; i++) {
441 nvkm_runl_foreach(runl, fifo) {
442 nvkm_runl_foreach_engn(engn, runl) {
443 if (engn->rm.desc == ctrl->constructedFalconsTable[i].engDesc) {
444 engn->rm.size =
445 ctrl->constructedFalconsTable[i].ctxBufferSize;
446 break;
447 }
448 }
449 }
450 }
451
452 nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
453 return 0;
454 }
455
456 static int
r535_fifo_runl_ctor(struct nvkm_fifo * fifo)457 r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
458 {
459 struct nvkm_subdev *subdev = &fifo->engine.subdev;
460 struct nvkm_device *device = subdev->device;
461 struct nvkm_gsp *gsp = device->gsp;
462 struct nvkm_rm *rm = gsp->rm;
463 struct nvkm_runl *runl;
464 struct nvkm_engn *engn;
465 u32 chids = 2048;
466 u32 first = rm->api->fifo->rsvd_chids;
467 u32 count = chids - first;
468 int ret;
469 NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS *ctrl;
470
471 if ((ret = nvkm_chid_new(&nvkm_chan_event, subdev, chids, first, count, &fifo->cgid)) ||
472 (ret = nvkm_chid_new(&nvkm_chan_event, subdev, chids, first, count, &fifo->chid)))
473 return ret;
474
475 ctrl = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
476 NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE, sizeof(*ctrl));
477 if (WARN_ON(IS_ERR(ctrl)))
478 return PTR_ERR(ctrl);
479
480 for (int i = 0; i < ctrl->numEntries; i++) {
481 const u32 addr = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_RUNLIST_PRI_BASE];
482 const u32 id = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_RUNLIST];
483
484 runl = nvkm_runl_get(fifo, id, addr);
485 if (!runl) {
486 runl = nvkm_runl_new(fifo, id, addr, 0);
487 if (WARN_ON(IS_ERR(runl)))
488 continue;
489 }
490 }
491
492 for (int i = 0; i < ctrl->numEntries; i++) {
493 const u32 addr = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_RUNLIST_PRI_BASE];
494 const u32 rmid = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_RM_ENGINE_TYPE];
495 const u32 id = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_RUNLIST];
496 enum nvkm_subdev_type type;
497 int inst, nv2080;
498
499 runl = nvkm_runl_get(fifo, id, addr);
500 if (!runl)
501 continue;
502
503 inst = rm->api->fifo->xlat_rm_engine_type(rmid, &type, &nv2080);
504 if (inst < 0) {
505 nvkm_warn(subdev, "RM_ENGINE_TYPE 0x%x\n", rmid);
506 nvkm_runl_del(runl);
507 continue;
508 }
509
510 /* Skip SW engine - there's currently no support for NV SW classes. */
511 if (type == NVKM_ENGINE_SW)
512 continue;
513
514 /* Skip lone GRCEs (ones not paired with GR on a runlist), as they
515 * don't appear to function as async copy engines.
516 */
517 if (type == NVKM_ENGINE_CE &&
518 rm->gpu->ce.grce_mask &&
519 (rm->gpu->ce.grce_mask(device) & BIT(inst)) &&
520 !nvkm_runl_find_engn(engn, runl, engn->engine->subdev.type == NVKM_ENGINE_GR)) {
521 RUNL_DEBUG(runl, "skip LCE %d - GRCE without GR", inst);
522 nvkm_runl_del(runl);
523 continue;
524 }
525
526 ret = nvkm_rm_engine_new(gsp->rm, type, inst);
527 if (ret) {
528 nvkm_runl_del(runl);
529 continue;
530 }
531
532 engn = NULL;
533
534 switch (type) {
535 case NVKM_ENGINE_CE:
536 engn = nvkm_runl_add(runl, nv2080, &r535_engn_ce, type, inst);
537 break;
538 case NVKM_ENGINE_GR:
539 engn = nvkm_runl_add(runl, nv2080, &r535_engn_gr, type, inst);
540 break;
541 case NVKM_ENGINE_NVDEC:
542 case NVKM_ENGINE_NVENC:
543 case NVKM_ENGINE_NVJPG:
544 case NVKM_ENGINE_OFA:
545 engn = nvkm_runl_add(runl, nv2080, &r535_flcn, type, inst);
546 break;
547 case NVKM_ENGINE_SW:
548 continue;
549 default:
550 engn = NULL;
551 break;
552 }
553
554 if (!engn) {
555 nvkm_runl_del(runl);
556 continue;
557 }
558
559 engn->rm.desc = ctrl->entries[i].engineData[ENGINE_INFO_TYPE_ENG_DESC];
560 }
561
562 nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
563
564 {
565 NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS *ctrl;
566
567 ctrl = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
568 NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE,
569 sizeof(*ctrl));
570 if (IS_ERR(ctrl))
571 return PTR_ERR(ctrl);
572
573 fifo->rm.mthdbuf_size = ctrl->size;
574
575 nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, ctrl);
576 }
577
578 return rm->api->fifo->ectx_size(fifo);
579 }
580
581 static void
r535_fifo_dtor(struct nvkm_fifo * fifo)582 r535_fifo_dtor(struct nvkm_fifo *fifo)
583 {
584 kfree(fifo->func);
585 }
586
587 int
r535_fifo_new(const struct nvkm_fifo_func * hw,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)588 r535_fifo_new(const struct nvkm_fifo_func *hw, struct nvkm_device *device,
589 enum nvkm_subdev_type type, int inst, struct nvkm_fifo **pfifo)
590 {
591 const struct nvkm_rm_gpu *gpu = device->gsp->rm->gpu;
592 struct nvkm_fifo_func *rm;
593
594 if (!(rm = kzalloc(sizeof(*rm), GFP_KERNEL)))
595 return -ENOMEM;
596
597 rm->dtor = r535_fifo_dtor;
598 rm->runl_ctor = r535_fifo_runl_ctor;
599 rm->runl = &r535_runl;
600 rm->chan.user.oclass = gpu->fifo.chan.class;
601 rm->chan.func = &r535_chan;
602 rm->nonstall = &ga100_fifo_nonstall;
603 rm->nonstall_ctor = ga100_fifo_nonstall_ctor;
604
605 return nvkm_fifo_new_(rm, device, type, inst, pfifo);
606 }
607
608 const struct nvkm_rm_api_fifo
609 r535_fifo = {
610 .xlat_rm_engine_type = r535_fifo_xlat_rm_engine_type,
611 .ectx_size = r535_fifo_ectx_size,
612 .rc_triggered = r535_fifo_rc_triggered,
613 .chan = {
614 .alloc = r535_chan_alloc,
615 },
616 };
617