1 #ifndef B43legacy_H_
2 #define B43legacy_H_
3
4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <linux/atomic.h>
12 #include <linux/io.h>
13
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
16
17 #include <net/mac80211.h>
18
19 #include "debugfs.h"
20 #include "leds.h"
21 #include "rfkill.h"
22 #include "phy.h"
23
24
25 #define B43legacy_IRQWAIT_MAX_RETRIES 20
26
27 /* MMIO offsets */
28 #define B43legacy_MMIO_DMA0_REASON 0x20
29 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
30 #define B43legacy_MMIO_DMA1_REASON 0x28
31 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
32 #define B43legacy_MMIO_DMA2_REASON 0x30
33 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
34 #define B43legacy_MMIO_DMA3_REASON 0x38
35 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
36 #define B43legacy_MMIO_DMA4_REASON 0x40
37 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
38 #define B43legacy_MMIO_DMA5_REASON 0x48
39 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
40 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
41 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
42 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
43 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
44 #define B43legacy_MMIO_RAM_CONTROL 0x130
45 #define B43legacy_MMIO_RAM_DATA 0x134
46 #define B43legacy_MMIO_PS_STATUS 0x140
47 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
48 #define B43legacy_MMIO_SHM_CONTROL 0x160
49 #define B43legacy_MMIO_SHM_DATA 0x164
50 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
51 #define B43legacy_MMIO_XMITSTAT_0 0x170
52 #define B43legacy_MMIO_XMITSTAT_1 0x174
53 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
54 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
55 #define B43legacy_MMIO_TSF_CFP_REP 0x188
56 #define B43legacy_MMIO_TSF_CFP_START 0x18C
57 /* 32-bit DMA */
58 #define B43legacy_MMIO_DMA32_BASE0 0x200
59 #define B43legacy_MMIO_DMA32_BASE1 0x220
60 #define B43legacy_MMIO_DMA32_BASE2 0x240
61 #define B43legacy_MMIO_DMA32_BASE3 0x260
62 #define B43legacy_MMIO_DMA32_BASE4 0x280
63 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
64 /* 64-bit DMA */
65 #define B43legacy_MMIO_DMA64_BASE0 0x200
66 #define B43legacy_MMIO_DMA64_BASE1 0x240
67 #define B43legacy_MMIO_DMA64_BASE2 0x280
68 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
69 #define B43legacy_MMIO_DMA64_BASE4 0x300
70 #define B43legacy_MMIO_DMA64_BASE5 0x340
71 /* PIO */
72 #define B43legacy_MMIO_PIO1_BASE 0x300
73 #define B43legacy_MMIO_PIO2_BASE 0x310
74 #define B43legacy_MMIO_PIO3_BASE 0x320
75 #define B43legacy_MMIO_PIO4_BASE 0x330
76
77 #define B43legacy_MMIO_PHY_VER 0x3E0
78 #define B43legacy_MMIO_PHY_RADIO 0x3E2
79 #define B43legacy_MMIO_PHY0 0x3E6
80 #define B43legacy_MMIO_ANTENNA 0x3E8
81 #define B43legacy_MMIO_CHANNEL 0x3F0
82 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
83 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
84 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
85 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
86 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
87 #define B43legacy_MMIO_PHY_DATA 0x3FE
88 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
89 #define B43legacy_MMIO_MACFILTER_DATA 0x422
90 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
91 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
92 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
93 #define B43legacy_MMIO_GPIO_MASK 0x49E
94 #define B43legacy_MMIO_TSF_CFP_PRETBTT 0x612
95 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
96 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
97 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
98 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
99 #define B43legacy_MMIO_RNG 0x65A
100 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
101
102 /* SPROM boardflags_lo values */
103 #define B43legacy_BFL_PACTRL 0x0002
104 #define B43legacy_BFL_RSSI 0x0008
105 #define B43legacy_BFL_EXTLNA 0x1000
106
107 /* GPIO register offset, in both ChipCommon and PCI core. */
108 #define B43legacy_GPIO_CONTROL 0x6c
109
110 /* SHM Routing */
111 #define B43legacy_SHM_SHARED 0x0001
112 #define B43legacy_SHM_WIRELESS 0x0002
113 #define B43legacy_SHM_HW 0x0004
114 #define B43legacy_SHM_UCODE 0x0300
115
116 /* SHM Routing modifiers */
117 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
118 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
119 #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
120 B43legacy_SHM_AUTOINC_W)
121
122 /* Misc SHM_SHARED offsets */
123 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
124 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
125 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
126 /* SHM_SHARED crypto engine */
127 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
128 /* SHM_SHARED beacon/AP variables */
129 #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
130 #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
131 #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
132 #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
133 #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
134 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
135 /* SHM_SHARED ACK/CTS control */
136 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
137 /* SHM_SHARED probe response variables */
138 #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
139 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
140 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
141 /* SHM_SHARED rate tables */
142 #define B43legacy_SHM_SH_OFDMDIRECT 0x0480 /* Pointer to OFDM direct map */
143 #define B43legacy_SHM_SH_OFDMBASIC 0x04A0 /* Pointer to OFDM basic rate map */
144 #define B43legacy_SHM_SH_CCKDIRECT 0x04C0 /* Pointer to CCK direct map */
145 #define B43legacy_SHM_SH_CCKBASIC 0x04E0 /* Pointer to CCK basic rate map */
146 /* SHM_SHARED microcode soft registers */
147 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
148 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
149 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
150 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
151 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
152 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
153
154 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
155
156 /* Hardware Radio Enable masks */
157 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
158 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
159
160 /* HostFlags. See b43legacy_hf_read/write() */
161 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
162 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
163 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
164 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
165
166 /* MacFilter offsets. */
167 #define B43legacy_MACFILTER_SELF 0x0000
168 #define B43legacy_MACFILTER_BSSID 0x0003
169 #define B43legacy_MACFILTER_MAC 0x0010
170
171 /* PHYVersioning */
172 #define B43legacy_PHYTYPE_B 0x01
173 #define B43legacy_PHYTYPE_G 0x02
174
175 /* PHYRegisters */
176 #define B43legacy_PHY_G_LO_CONTROL 0x0810
177 #define B43legacy_PHY_ILT_G_CTRL 0x0472
178 #define B43legacy_PHY_ILT_G_DATA1 0x0473
179 #define B43legacy_PHY_ILT_G_DATA2 0x0474
180 #define B43legacy_PHY_G_PCTL 0x0029
181 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
182 #define B43legacy_PHY_G_CRS 0x0429
183 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
184 #define B43legacy_PHY_NRSSILT_DATA 0x0804
185
186 /* RadioRegisters */
187 #define B43legacy_RADIOCTL_ID 0x01
188
189 /* MAC Control bitfield */
190 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
191 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
192 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
193 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
194 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
195 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
196 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
197 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
198 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
199 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
200 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
201 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
202 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
203 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
204 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
205 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
206 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
207 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
208
209 /* MAC Command bitfield */
210 #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
211 #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
212 #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
213 #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
214 #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
215
216 /* 802.11 core specific TM State Low flags */
217 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
218 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
219 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
220 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
221 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
222
223 /* 802.11 core specific TM State High flags */
224 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
225 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
226
227 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
228
229 /* Generic-Interrupt reasons. */
230 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
231 #define B43legacy_IRQ_BEACON 0x00000002
232 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
233 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
234 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
235 #define B43legacy_IRQ_ATIM_END 0x00000020
236 #define B43legacy_IRQ_PMQ 0x00000040
237 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
238 #define B43legacy_IRQ_MAC_TXERR 0x00000200
239 #define B43legacy_IRQ_PHY_TXERR 0x00000800
240 #define B43legacy_IRQ_PMEVENT 0x00001000
241 #define B43legacy_IRQ_TIMER0 0x00002000
242 #define B43legacy_IRQ_TIMER1 0x00004000
243 #define B43legacy_IRQ_DMA 0x00008000
244 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
245 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
246 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
247 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
248 #define B43legacy_IRQ_RFKILL 0x10000000
249 #define B43legacy_IRQ_TX_OK 0x20000000
250 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
251 #define B43legacy_IRQ_TIMEOUT 0x80000000
252
253 #define B43legacy_IRQ_ALL 0xFFFFFFFF
254 #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
255 B43legacy_IRQ_TBTT_INDI | \
256 B43legacy_IRQ_ATIM_END | \
257 B43legacy_IRQ_PMQ | \
258 B43legacy_IRQ_MAC_TXERR | \
259 B43legacy_IRQ_PHY_TXERR | \
260 B43legacy_IRQ_DMA | \
261 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
262 B43legacy_IRQ_NOISESAMPLE_OK | \
263 B43legacy_IRQ_UCODE_DEBUG | \
264 B43legacy_IRQ_RFKILL | \
265 B43legacy_IRQ_TX_OK)
266
267 /* Device specific rate values.
268 * The actual values defined here are (rate_in_mbps * 2).
269 * Some code depends on this. Don't change it. */
270 #define B43legacy_CCK_RATE_1MB 2
271 #define B43legacy_CCK_RATE_2MB 4
272 #define B43legacy_CCK_RATE_5MB 11
273 #define B43legacy_CCK_RATE_11MB 22
274 #define B43legacy_OFDM_RATE_6MB 12
275 #define B43legacy_OFDM_RATE_9MB 18
276 #define B43legacy_OFDM_RATE_12MB 24
277 #define B43legacy_OFDM_RATE_18MB 36
278 #define B43legacy_OFDM_RATE_24MB 48
279 #define B43legacy_OFDM_RATE_36MB 72
280 #define B43legacy_OFDM_RATE_48MB 96
281 #define B43legacy_OFDM_RATE_54MB 108
282 /* Convert a b43legacy rate value to a rate in 100kbps */
283 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
284
285
286 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
287 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
288
289 #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
290
291 /* Max size of a security key */
292 #define B43legacy_SEC_KEYSIZE 16
293 /* Security algorithms. */
294 enum {
295 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
296 B43legacy_SEC_ALGO_WEP40,
297 B43legacy_SEC_ALGO_TKIP,
298 B43legacy_SEC_ALGO_AES,
299 B43legacy_SEC_ALGO_WEP104,
300 B43legacy_SEC_ALGO_AES_LEGACY,
301 };
302
303 /* Core Information Registers */
304 #define B43legacy_CIR_BASE 0xf00
305 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
306 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
307 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
308 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
309 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
310 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
311 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
312
313 /* sbtmstatehigh state flags */
314 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
315 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
316 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
317 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
318 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
319 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
320 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
321 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
322 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
323
324 /* sbimstate flags */
325 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
326 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
327
328 #define PFX KBUILD_MODNAME ": "
329 #ifdef assert
330 # undef assert
331 #endif
332 #ifdef CONFIG_B43LEGACY_DEBUG
333 # define B43legacy_WARN_ON(x) WARN_ON(x)
334 # define B43legacy_BUG_ON(expr) \
335 do { \
336 if (unlikely((expr))) { \
337 printk(KERN_INFO PFX "Test (%s) failed\n", \
338 #expr); \
339 BUG_ON(expr); \
340 } \
341 } while (0)
342 # define B43legacy_DEBUG 1
343 #else
344 /* This will evaluate the argument even if debugging is disabled. */
__b43legacy_warn_on_dummy(bool x)345 static inline bool __b43legacy_warn_on_dummy(bool x) { return x; }
346 # define B43legacy_WARN_ON(x) __b43legacy_warn_on_dummy(unlikely(!!(x)))
347 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
348 # define B43legacy_DEBUG 0
349 #endif
350
351
352 struct net_device;
353 struct pci_dev;
354 struct b43legacy_dmaring;
355 struct b43legacy_pioqueue;
356
357 /* The firmware file header */
358 #define B43legacy_FW_TYPE_UCODE 'u'
359 #define B43legacy_FW_TYPE_PCM 'p'
360 #define B43legacy_FW_TYPE_IV 'i'
361 struct b43legacy_fw_header {
362 /* File type */
363 u8 type;
364 /* File format version */
365 u8 ver;
366 u8 __padding[2];
367 /* Size of the data. For ucode and PCM this is in bytes.
368 * For IV this is number-of-ivs. */
369 __be32 size;
370 } __packed;
371
372 /* Initial Value file format */
373 #define B43legacy_IV_OFFSET_MASK 0x7FFF
374 #define B43legacy_IV_32BIT 0x8000
375 struct b43legacy_iv {
376 __be16 offset_size;
377 union {
378 __be16 d16;
379 __be32 d32;
380 } data __packed;
381 } __packed;
382
383 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
384 #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
385 ((B43legacy_PHYTYPE_B))
386 #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
387 ((B43legacy_PHYTYPE_G))
388
389 /* Value pair to measure the LocalOscillator. */
390 struct b43legacy_lopair {
391 s8 low;
392 s8 high;
393 u8 used:1;
394 };
395 #define B43legacy_LO_COUNT (14*4)
396
397 struct b43legacy_phy {
398 /* Possible PHYMODEs on this PHY */
399 u8 possible_phymodes;
400 /* GMODE bit enabled in MACCTL? */
401 bool gmode;
402
403 /* Analog Type */
404 u8 analog;
405 /* B43legacy_PHYTYPE_ */
406 u8 type;
407 /* PHY revision number. */
408 u8 rev;
409
410 u16 antenna_diversity;
411 u16 savedpctlreg;
412 /* Radio versioning */
413 u16 radio_manuf; /* Radio manufacturer */
414 u16 radio_ver; /* Radio version */
415 u8 calibrated:1;
416 u8 radio_rev; /* Radio revision */
417
418 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
419
420 /* ACI (adjacent channel interference) flags. */
421 bool aci_enable;
422 bool aci_wlan_automatic;
423 bool aci_hw_rssi;
424
425 /* Radio switched on/off */
426 bool radio_on;
427 struct {
428 /* Values saved when turning the radio off.
429 * They are needed when turning it on again. */
430 bool valid;
431 u16 rfover;
432 u16 rfoverval;
433 } radio_off_context;
434
435 u16 minlowsig[2];
436 u16 minlowsigpos[2];
437
438 /* LO Measurement Data.
439 * Use b43legacy_get_lopair() to get a value.
440 */
441 struct b43legacy_lopair *_lo_pairs;
442 /* TSSI to dBm table in use */
443 const s8 *tssi2dbm;
444 /* idle TSSI value */
445 s8 idle_tssi;
446 /* Target idle TSSI */
447 int tgt_idle_tssi;
448 /* Current idle TSSI */
449 int cur_idle_tssi;
450
451 /* LocalOscillator control values. */
452 struct b43legacy_txpower_lo_control *lo_control;
453 /* Values from b43legacy_calc_loopback_gain() */
454 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
455 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
456 s16 lna_lod_gain; /* LNA lod */
457 s16 lna_gain; /* LNA */
458 s16 pga_gain; /* PGA */
459
460 /* Desired TX power level (in dBm). This is set by the user and
461 * adjusted in b43legacy_phy_xmitpower(). */
462 u8 power_level;
463
464 /* Values from b43legacy_calc_loopback_gain() */
465 u16 loopback_gain[2];
466
467 /* TX Power control values. */
468 /* B/G PHY */
469 struct {
470 /* Current Radio Attenuation for TXpower recalculation. */
471 u16 rfatt;
472 /* Current Baseband Attenuation for TXpower recalculation. */
473 u16 bbatt;
474 /* Current TXpower control value for TXpower recalculation. */
475 u16 txctl1;
476 u16 txctl2;
477 };
478 /* A PHY */
479 struct {
480 u16 txpwr_offset;
481 };
482
483 /* Current Interference Mitigation mode */
484 int interfmode;
485 /* Stack of saved values from the Interference Mitigation code.
486 * Each value in the stack is laid out as follows:
487 * bit 0-11: offset
488 * bit 12-15: register ID
489 * bit 16-32: value
490 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
491 */
492 #define B43legacy_INTERFSTACK_SIZE 26
493 u32 interfstack[B43legacy_INTERFSTACK_SIZE];
494
495 /* Saved values from the NRSSI Slope calculation */
496 s16 nrssi[2];
497 s32 nrssislope;
498 /* In memory nrssi lookup table. */
499 s8 nrssi_lt[64];
500
501 /* current channel */
502 u8 channel;
503
504 u16 lofcal;
505
506 u16 initval;
507
508 /* PHY TX errors counter. */
509 atomic_t txerr_cnt;
510
511 #if B43legacy_DEBUG
512 /* Manual TX-power control enabled? */
513 bool manual_txpower_control;
514 /* PHY registers locked by b43legacy_phy_lock()? */
515 bool phy_locked;
516 #endif /* B43legacy_DEBUG */
517 };
518
519 /* Data structures for DMA transmission, per 80211 core. */
520 struct b43legacy_dma {
521 struct b43legacy_dmaring *tx_ring0;
522 struct b43legacy_dmaring *tx_ring1;
523 struct b43legacy_dmaring *tx_ring2;
524 struct b43legacy_dmaring *tx_ring3;
525 struct b43legacy_dmaring *tx_ring4;
526 struct b43legacy_dmaring *tx_ring5;
527
528 struct b43legacy_dmaring *rx_ring0;
529 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
530
531 u32 translation; /* Routing bits */
532 };
533
534 /* Data structures for PIO transmission, per 80211 core. */
535 struct b43legacy_pio {
536 struct b43legacy_pioqueue *queue0;
537 struct b43legacy_pioqueue *queue1;
538 struct b43legacy_pioqueue *queue2;
539 struct b43legacy_pioqueue *queue3;
540 };
541
542 /* Context information for a noise calculation (Link Quality). */
543 struct b43legacy_noise_calculation {
544 u8 channel_at_start;
545 bool calculation_running;
546 u8 nr_samples;
547 s8 samples[8][4];
548 };
549
550 struct b43legacy_stats {
551 u8 link_noise;
552 /* Store the last TX/RX times here for updating the leds. */
553 unsigned long last_tx;
554 unsigned long last_rx;
555 };
556
557 struct b43legacy_key {
558 void *keyconf;
559 bool enabled;
560 u8 algorithm;
561 };
562
563 #define B43legacy_QOS_QUEUE_NUM 4
564
565 struct b43legacy_wldev;
566
567 /* QOS parameters for a queue. */
568 struct b43legacy_qos_params {
569 /* The QOS parameters */
570 struct ieee80211_tx_queue_params p;
571 };
572
573 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
574 struct b43legacy_wl {
575 /* Pointer to the active wireless device on this chip */
576 struct b43legacy_wldev *current_dev;
577 /* Pointer to the ieee80211 hardware data structure */
578 struct ieee80211_hw *hw;
579
580 spinlock_t irq_lock; /* locks IRQ */
581 struct mutex mutex; /* locks wireless core state */
582 spinlock_t leds_lock; /* lock for leds */
583
584 /* We can only have one operating interface (802.11 core)
585 * at a time. General information about this interface follows.
586 */
587
588 struct ieee80211_vif *vif;
589 /* MAC address (can be NULL). */
590 u8 mac_addr[ETH_ALEN];
591 /* Current BSSID (can be NULL). */
592 u8 bssid[ETH_ALEN];
593 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
594 int if_type;
595 /* Is the card operating in AP, STA or IBSS mode? */
596 bool operating;
597 /* filter flags */
598 unsigned int filter_flags;
599 /* Stats about the wireless interface */
600 struct ieee80211_low_level_stats ieee_stats;
601
602 #ifdef CONFIG_B43LEGACY_HWRNG
603 struct hwrng rng;
604 u8 rng_initialized;
605 char rng_name[30 + 1];
606 #endif
607
608 /* List of all wireless devices on this chip */
609 struct list_head devlist;
610 u8 nr_devs;
611
612 bool radiotap_enabled;
613 bool radio_enabled;
614
615 /* The beacon we are currently using (AP or IBSS mode).
616 * This beacon stuff is protected by the irq_lock. */
617 struct sk_buff *current_beacon;
618 bool beacon0_uploaded;
619 bool beacon1_uploaded;
620 bool beacon_templates_virgin; /* Never wrote the templates? */
621 struct work_struct beacon_update_trigger;
622 /* The current QOS parameters for the 4 queues. */
623 struct b43legacy_qos_params qos_params[B43legacy_QOS_QUEUE_NUM];
624
625 /* Packet transmit work */
626 struct work_struct tx_work;
627
628 /* Queue of packets to be transmitted. */
629 struct sk_buff_head tx_queue[B43legacy_QOS_QUEUE_NUM];
630
631 /* Flag that implement the queues stopping. */
632 bool tx_queue_stopped[B43legacy_QOS_QUEUE_NUM];
633
634 };
635
636 /* Pointers to the firmware data and meta information about it. */
637 struct b43legacy_firmware {
638 /* Microcode */
639 const struct firmware *ucode;
640 /* PCM code */
641 const struct firmware *pcm;
642 /* Initial MMIO values for the firmware */
643 const struct firmware *initvals;
644 /* Initial MMIO values for the firmware, band-specific */
645 const struct firmware *initvals_band;
646 /* Firmware revision */
647 u16 rev;
648 /* Firmware patchlevel */
649 u16 patch;
650 };
651
652 /* Device (802.11 core) initialization status. */
653 enum {
654 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
655 B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
656 B43legacy_STAT_STARTED = 2, /* Up and running. */
657 };
658 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
659 #define b43legacy_set_status(wldev, stat) do { \
660 atomic_set(&(wldev)->__init_status, (stat)); \
661 smp_wmb(); \
662 } while (0)
663
664 /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
665 *
666 * You should always acquire both, wl->mutex and wl->irq_lock unless:
667 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
668 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
669 * and packet TX path (and _ONLY_ there.)
670 */
671
672 /* Data structure for one wireless device (802.11 core) */
673 struct b43legacy_wldev {
674 struct ssb_device *dev;
675 struct b43legacy_wl *wl;
676
677 /* The device initialization status.
678 * Use b43legacy_status() to query. */
679 atomic_t __init_status;
680 /* Saved init status for handling suspend. */
681 int suspend_init_status;
682
683 bool __using_pio; /* Using pio rather than dma. */
684 bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
685 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */
686 bool short_preamble; /* TRUE if using short preamble. */
687 bool radio_hw_enable; /* State of radio hardware enable bit. */
688
689 /* PHY/Radio device. */
690 struct b43legacy_phy phy;
691 union {
692 /* DMA engines. */
693 struct b43legacy_dma dma;
694 /* PIO engines. */
695 struct b43legacy_pio pio;
696 };
697
698 /* Various statistics about the physical device. */
699 struct b43legacy_stats stats;
700
701 /* The device LEDs. */
702 struct b43legacy_led led_tx;
703 struct b43legacy_led led_rx;
704 struct b43legacy_led led_assoc;
705 struct b43legacy_led led_radio;
706
707 /* Reason code of the last interrupt. */
708 u32 irq_reason;
709 u32 dma_reason[6];
710 /* The currently active generic-interrupt mask. */
711 u32 irq_mask;
712 /* Link Quality calculation context. */
713 struct b43legacy_noise_calculation noisecalc;
714 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
715 int mac_suspended;
716
717 /* Interrupt Service Routine tasklet (bottom-half) */
718 struct tasklet_struct isr_tasklet;
719
720 /* Periodic tasks */
721 struct delayed_work periodic_work;
722 unsigned int periodic_state;
723
724 struct work_struct restart_work;
725
726 /* encryption/decryption */
727 u16 ktp; /* Key table pointer */
728 u8 max_nr_keys;
729 struct b43legacy_key key[58];
730
731 /* Firmware data */
732 struct b43legacy_firmware fw;
733
734 /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
735 struct list_head list;
736
737 /* Debugging stuff follows. */
738 #ifdef CONFIG_B43LEGACY_DEBUG
739 struct b43legacy_dfsentry *dfsentry;
740 #endif
741 };
742
743
744 static inline
hw_to_b43legacy_wl(struct ieee80211_hw * hw)745 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
746 {
747 return hw->priv;
748 }
749
750 /* Helper function, which returns a boolean.
751 * TRUE, if PIO is used; FALSE, if DMA is used.
752 */
753 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
754 static inline
b43legacy_using_pio(struct b43legacy_wldev * dev)755 int b43legacy_using_pio(struct b43legacy_wldev *dev)
756 {
757 return dev->__using_pio;
758 }
759 #elif defined(CONFIG_B43LEGACY_DMA)
760 static inline
b43legacy_using_pio(struct b43legacy_wldev * dev)761 int b43legacy_using_pio(struct b43legacy_wldev *dev)
762 {
763 return 0;
764 }
765 #elif defined(CONFIG_B43LEGACY_PIO)
766 static inline
b43legacy_using_pio(struct b43legacy_wldev * dev)767 int b43legacy_using_pio(struct b43legacy_wldev *dev)
768 {
769 return 1;
770 }
771 #else
772 # error "Using neither DMA nor PIO? Confused..."
773 #endif
774
775
776 static inline
dev_to_b43legacy_wldev(struct device * dev)777 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
778 {
779 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
780 return ssb_get_drvdata(ssb_dev);
781 }
782
783 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
784 static inline
b43legacy_is_mode(struct b43legacy_wl * wl,int type)785 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
786 {
787 return (wl->operating &&
788 wl->if_type == type);
789 }
790
791 static inline
is_bcm_board_vendor(struct b43legacy_wldev * dev)792 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
793 {
794 return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
795 }
796
797 static inline
b43legacy_read16(struct b43legacy_wldev * dev,u16 offset)798 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
799 {
800 return ssb_read16(dev->dev, offset);
801 }
802
803 static inline
b43legacy_write16(struct b43legacy_wldev * dev,u16 offset,u16 value)804 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
805 {
806 ssb_write16(dev->dev, offset, value);
807 }
808
809 static inline
b43legacy_read32(struct b43legacy_wldev * dev,u16 offset)810 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
811 {
812 return ssb_read32(dev->dev, offset);
813 }
814
815 static inline
b43legacy_write32(struct b43legacy_wldev * dev,u16 offset,u32 value)816 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
817 {
818 ssb_write32(dev->dev, offset, value);
819 }
820
821 static inline
b43legacy_get_lopair(struct b43legacy_phy * phy,u16 radio_attenuation,u16 baseband_attenuation)822 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
823 u16 radio_attenuation,
824 u16 baseband_attenuation)
825 {
826 return phy->_lo_pairs + (radio_attenuation
827 + 14 * (baseband_attenuation / 2));
828 }
829
830
831
832 /* Message printing */
833 __printf(2, 3)
834 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...);
835 __printf(2, 3)
836 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...);
837 __printf(2, 3)
838 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...);
839 #if B43legacy_DEBUG
840 __printf(2, 3)
841 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...);
842 #else /* DEBUG */
843 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
844 #endif /* DEBUG */
845
846 /* Macros for printing a value in Q5.2 format */
847 #define Q52_FMT "%u.%u"
848 #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
849
850 #endif /* B43legacy_H_ */
851