xref: /linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_HW_CATALOG_H
8 #define _DPU_HW_CATALOG_H
9 
10 #include <linux/kernel.h>
11 #include <linux/bug.h>
12 #include <linux/bitmap.h>
13 #include <linux/err.h>
14 
15 /**
16  * Max hardware block count: For ex: max 12 SSPP pipes or
17  * 5 ctl paths. In all cases, it can have max 12 hardware blocks
18  * based on current design
19  */
20 #define MAX_BLOCKS    12
21 
22 #define DPU_HW_BLK_NAME_LEN	16
23 
24 #define DPU_MAX_IMG_WIDTH 0x3fff
25 #define DPU_MAX_IMG_HEIGHT 0x3fff
26 
27 #define CRTC_DUAL_MIXERS	2
28 
29 #define MAX_XIN_COUNT 16
30 
31 /**
32  * SSPP sub-blocks/features
33  * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
34  * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE,  QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4)
35  * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
36  * @DPU_SSPP_CSC,            Support of Color space converion
37  * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
38  * @DPU_SSPP_CURSOR,         SSPP can be used as a cursor layer
39  * @DPU_SSPP_QOS,            SSPP support QoS control, danger/safe/creq
40  * @DPU_SSPP_EXCL_RECT,      SSPP supports exclusion rect
41  * @DPU_SSPP_SMART_DMA_V1,   SmartDMA 1.0 support
42  * @DPU_SSPP_SMART_DMA_V2,   SmartDMA 2.0 support
43  * @DPU_SSPP_TS_PREFILL      Supports prefill with traffic shaper
44  * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
45  * @DPU_SSPP_CDP             Supports client driven prefetch
46  * @DPU_SSPP_INLINE_ROTATION Support inline rotation
47  * @DPU_SSPP_MAX             maximum value
48  */
49 enum {
50 	DPU_SSPP_SCALER_QSEED2 = 0x1,
51 	DPU_SSPP_SCALER_QSEED3_COMPATIBLE,
52 	DPU_SSPP_SCALER_RGB,
53 	DPU_SSPP_CSC,
54 	DPU_SSPP_CSC_10BIT,
55 	DPU_SSPP_CURSOR,
56 	DPU_SSPP_QOS,
57 	DPU_SSPP_EXCL_RECT,
58 	DPU_SSPP_SMART_DMA_V1,
59 	DPU_SSPP_SMART_DMA_V2,
60 	DPU_SSPP_TS_PREFILL,
61 	DPU_SSPP_TS_PREFILL_REC1,
62 	DPU_SSPP_CDP,
63 	DPU_SSPP_INLINE_ROTATION,
64 	DPU_SSPP_MAX
65 };
66 
67 /*
68  * MIXER sub-blocks/features
69  * @DPU_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration
70  * @DPU_MIXER_MAX             maximum value
71  */
72 enum {
73 	DPU_MIXER_SOURCESPLIT = 0x1,
74 	DPU_MIXER_MAX,
75 };
76 
77 /**
78  * DSPP sub-blocks
79  * @DPU_DSPP_PCC             Panel color correction block
80  */
81 enum {
82 	DPU_DSPP_PCC = 0x1,
83 	DPU_DSPP_MAX
84 };
85 
86 /**
87  * CTL sub-blocks
88  * @DPU_CTL_SPLIT_DISPLAY:	CTL supports video mode split display
89  * @DPU_CTL_MAX
90  */
91 enum {
92 	DPU_CTL_SPLIT_DISPLAY = 0x1,
93 	DPU_CTL_MAX
94 };
95 
96 /**
97   * WB sub-blocks and features
98   * @DPU_WB_LINE_MODE        Writeback module supports line/linear mode
99   * @DPU_WB_BLOCK_MODE       Writeback module supports block mode read
100   * @DPU_WB_CHROMA_DOWN,     Writeback chroma down block,
101   * @DPU_WB_DOWNSCALE,       Writeback integer downscaler,
102   * @DPU_WB_DITHER,          Dither block
103   * @DPU_WB_TRAFFIC_SHAPER,  Writeback traffic shaper bloc
104   * @DPU_WB_UBWC,            Writeback Universal bandwidth compression
105   * @DPU_WB_YUV_CONFIG       Writeback supports output of YUV colorspace
106   * @DPU_WB_PIPE_ALPHA       Writeback supports pipe alpha
107   * @DPU_WB_XY_ROI_OFFSET    Writeback supports x/y-offset of out ROI in
108   *                          the destination image
109   * @DPU_WB_QOS,             Writeback supports QoS control, danger/safe/creq
110   * @DPU_WB_QOS_8LVL,        Writeback supports 8-level QoS control
111   * @DPU_WB_CDP              Writeback supports client driven prefetch
112   * @DPU_WB_CROP             CWB supports cropping
113   * @DPU_WB_MAX              maximum value
114   */
115 enum {
116 	DPU_WB_LINE_MODE = 0x1,
117 	DPU_WB_BLOCK_MODE,
118 	DPU_WB_UBWC,
119 	DPU_WB_YUV_CONFIG,
120 	DPU_WB_PIPE_ALPHA,
121 	DPU_WB_XY_ROI_OFFSET,
122 	DPU_WB_QOS,
123 	DPU_WB_QOS_8LVL,
124 	DPU_WB_CDP,
125 	DPU_WB_CROP,
126 	DPU_WB_MAX
127 };
128 
129 /**
130  * VBIF sub-blocks and features
131  * @DPU_VBIF_QOS_OTLIM        VBIF supports OT Limit
132  * @DPU_VBIF_QOS_REMAP        VBIF supports QoS priority remap
133  * @DPU_VBIF_MAX              maximum value
134  */
135 enum {
136 	DPU_VBIF_QOS_OTLIM = 0x1,
137 	DPU_VBIF_QOS_REMAP,
138 	DPU_VBIF_MAX
139 };
140 
141 /**
142  * DSC sub-blocks/features
143  * @DPU_DSC_NATIVE_42x_EN     Supports NATIVE_422_EN and NATIVE_420_EN encoding
144  * @DPU_DSC_MAX
145  */
146 enum {
147 	DPU_DSC_NATIVE_42x_EN = 0x1,
148 	DPU_DSC_MAX
149 };
150 
151 /**
152  * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
153  * @name:              string name for debug purposes
154  * @id:                enum identifying this block
155  * @base:              register base offset to mdss
156  * @len:               length of hardware block
157  */
158 #define DPU_HW_BLK_INFO \
159 	char name[DPU_HW_BLK_NAME_LEN]; \
160 	u32 id; \
161 	u32 base; \
162 	u32 len
163 
164 /**
165  * struct dpu_scaler_blk: Scaler information
166  * @name: string name for debug purposes
167  * @base: offset of this sub-block relative to the block offset
168  * @len: register block length of this sub-block
169  * @version: qseed block revision, on QSEED3+ platforms this is the value of
170  *           scaler_blk.base + QSEED3_HW_VERSION registers.
171  */
172 struct dpu_scaler_blk {
173 	char name[DPU_HW_BLK_NAME_LEN];
174 	u32 base;
175 	u32 len;
176 	u32 version;
177 };
178 
179 struct dpu_csc_blk {
180 	char name[DPU_HW_BLK_NAME_LEN];
181 	u32 base;
182 	u32 len;
183 };
184 
185 /**
186  * struct dpu_pp_blk : Pixel processing sub-blk information
187  * @name: string name for debug purposes
188  * @base: offset of this sub-block relative to the block offset
189  * @len: register block length of this sub-block
190  * @version: HW Algorithm version
191  */
192 struct dpu_pp_blk {
193 	char name[DPU_HW_BLK_NAME_LEN];
194 	u32 base;
195 	u32 len;
196 	u32 version;
197 };
198 
199 /**
200  * struct dpu_dsc_blk - DSC Encoder sub-blk information
201  * @name: string name for debug purposes
202  * @base: offset of this sub-block relative to the block offset
203  * @len: register block length of this sub-block
204  */
205 struct dpu_dsc_blk {
206 	char name[DPU_HW_BLK_NAME_LEN];
207 	u32 base;
208 	u32 len;
209 };
210 
211 /**
212  * enum dpu_qos_lut_usage - define QoS LUT use cases
213  */
214 enum dpu_qos_lut_usage {
215 	DPU_QOS_LUT_USAGE_LINEAR,
216 	DPU_QOS_LUT_USAGE_MACROTILE,
217 	DPU_QOS_LUT_USAGE_NRT,
218 	DPU_QOS_LUT_USAGE_MAX,
219 };
220 
221 /**
222  * struct dpu_qos_lut_entry - define QoS LUT table entry
223  * @fl: fill level, or zero on last entry to indicate default lut
224  * @lut: lut to use if equal to or less than fill level
225  */
226 struct dpu_qos_lut_entry {
227 	u32 fl;
228 	u64 lut;
229 };
230 
231 /**
232  * struct dpu_qos_lut_tbl - define QoS LUT table
233  * @nentry: number of entry in this table
234  * @entries: Pointer to table entries
235  */
236 struct dpu_qos_lut_tbl {
237 	u32 nentry;
238 	const struct dpu_qos_lut_entry *entries;
239 };
240 
241 /**
242  * struct dpu_rotation_cfg - define inline rotation config
243  * @rot_maxheight: max pre rotated height allowed for rotation
244  * @rot_num_formats: number of elements in @rot_format_list
245  * @rot_format_list: list of supported rotator formats
246  */
247 struct dpu_rotation_cfg {
248 	u32 rot_maxheight;
249 	size_t rot_num_formats;
250 	const u32 *rot_format_list;
251 };
252 
253 /**
254  * struct dpu_caps - define DPU capabilities
255  * @max_mixer_width    max layer mixer line width support.
256  * @max_mixer_blendstages max layer mixer blend stages or
257  *                       supported z order
258  * @has_src_split      source split feature status
259  * @has_dim_layer      dim layer feature status
260  * @has_idle_pc        indicate if idle power collapse feature is supported
261  * @has_3d_merge       indicate if 3D merge is supported
262  * @max_linewidth      max linewidth for sspp
263  * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
264  * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
265  * @max_vdeci_exp      max vertical decimation supported (max is 2^value)
266  */
267 struct dpu_caps {
268 	u32 max_mixer_width;
269 	u32 max_mixer_blendstages;
270 	bool has_src_split;
271 	bool has_dim_layer;
272 	bool has_idle_pc;
273 	bool has_3d_merge;
274 	/* SSPP limits */
275 	u32 max_linewidth;
276 	u32 pixel_ram_size;
277 	u32 max_hdeci_exp;
278 	u32 max_vdeci_exp;
279 };
280 
281 /**
282  * struct dpu_sspp_sub_blks : SSPP sub-blocks
283  * common: Pointer to common configurations shared by sub blocks
284  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
285  * @qseed_ver: qseed version
286  * @scaler_blk:
287  * @csc_blk:
288  * @format_list: Pointer to list of supported formats
289  * @num_formats: Number of supported formats
290  * @dpu_rotation_cfg: inline rotation configuration
291  */
292 struct dpu_sspp_sub_blks {
293 	u32 max_per_pipe_bw;
294 	u32 qseed_ver;
295 	struct dpu_scaler_blk scaler_blk;
296 	struct dpu_pp_blk csc_blk;
297 
298 	const u32 *format_list;
299 	u32 num_formats;
300 	const struct dpu_rotation_cfg *rotation_cfg;
301 };
302 
303 /**
304  * struct dpu_lm_sub_blks:      information of mixer block
305  * @maxwidth:               Max pixel width supported by this mixer
306  * @maxblendstages:         Max number of blend-stages supported
307  * @blendstage_base:        Blend-stage register base offset
308  */
309 struct dpu_lm_sub_blks {
310 	u32 maxwidth;
311 	u32 maxblendstages;
312 	u32 blendstage_base[MAX_BLOCKS];
313 };
314 
315 /**
316  * struct dpu_dspp_sub_blks: Information of DSPP block
317  * @pcc: pixel color correction block
318  */
319 struct dpu_dspp_sub_blks {
320 	struct dpu_pp_blk pcc;
321 };
322 
323 struct dpu_pingpong_sub_blks {
324 	struct dpu_pp_blk dither;
325 };
326 
327 /**
328  * struct dpu_dsc_sub_blks - DSC sub-blks
329  * @enc: DSC encoder sub-block
330  * @ctl: DSC controller sub-block
331  */
332 struct dpu_dsc_sub_blks {
333 	struct dpu_dsc_blk enc;
334 	struct dpu_dsc_blk ctl;
335 };
336 
337 /**
338  * dpu_clk_ctrl_type - Defines top level clock control signals
339  */
340 enum dpu_clk_ctrl_type {
341 	DPU_CLK_CTRL_NONE,
342 	DPU_CLK_CTRL_VIG0,
343 	DPU_CLK_CTRL_VIG1,
344 	DPU_CLK_CTRL_VIG2,
345 	DPU_CLK_CTRL_VIG3,
346 	DPU_CLK_CTRL_VIG4,
347 	DPU_CLK_CTRL_RGB0,
348 	DPU_CLK_CTRL_RGB1,
349 	DPU_CLK_CTRL_RGB2,
350 	DPU_CLK_CTRL_RGB3,
351 	DPU_CLK_CTRL_DMA0,
352 	DPU_CLK_CTRL_DMA1,
353 	DPU_CLK_CTRL_DMA2,
354 	DPU_CLK_CTRL_DMA3,
355 	DPU_CLK_CTRL_DMA4,
356 	DPU_CLK_CTRL_DMA5,
357 	DPU_CLK_CTRL_CURSOR0,
358 	DPU_CLK_CTRL_CURSOR1,
359 	DPU_CLK_CTRL_INLINE_ROT0_SSPP,
360 	DPU_CLK_CTRL_REG_DMA,
361 	DPU_CLK_CTRL_WB2,
362 	DPU_CLK_CTRL_MAX,
363 };
364 
365 /* struct dpu_clk_ctrl_reg : Clock control register
366  * @reg_off:           register offset
367  * @bit_off:           bit offset
368  */
369 struct dpu_clk_ctrl_reg {
370 	u32 reg_off;
371 	u32 bit_off;
372 };
373 
374 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
375  * @id:                index identifying this block
376  * @base:              register base offset to mdss
377  * @clk_ctrls          clock control register definition
378  */
379 struct dpu_mdp_cfg {
380 	DPU_HW_BLK_INFO;
381 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
382 };
383 
384 /* struct dpu_ctl_cfg : MDP CTL instance info
385  * @id:                index identifying this block
386  * @base:              register base offset to mdss
387  * @features           bit mask identifying sub-blocks/features
388  * @intr_start:        interrupt index for CTL_START
389  */
390 struct dpu_ctl_cfg {
391 	DPU_HW_BLK_INFO;
392 	unsigned long features;
393 	unsigned int intr_start;
394 };
395 
396 /**
397  * struct dpu_sspp_cfg - information of source pipes
398  * @id:                index identifying this block
399  * @base               register offset of this block
400  * @features           bit mask identifying sub-blocks/features
401  * @sblk:              SSPP sub-blocks information
402  * @xin_id:            bus client identifier
403  * @clk_ctrl           clock control identifier
404  * @type               sspp type identifier
405  */
406 struct dpu_sspp_cfg {
407 	DPU_HW_BLK_INFO;
408 	unsigned long features;
409 	const struct dpu_sspp_sub_blks *sblk;
410 	u32 xin_id;
411 	enum dpu_clk_ctrl_type clk_ctrl;
412 	u32 type;
413 };
414 
415 /**
416  * struct dpu_lm_cfg - information of layer mixer blocks
417  * @id:                index identifying this block
418  * @base               register offset of this block
419  * @features           bit mask identifying sub-blocks/features
420  * @sblk:              LM Sub-blocks information
421  * @pingpong:          ID of connected PingPong, PINGPONG_NONE if unsupported
422  * @lm_pair:           ID of LM that can be controlled by same CTL
423  */
424 struct dpu_lm_cfg {
425 	DPU_HW_BLK_INFO;
426 	unsigned long features;
427 	const struct dpu_lm_sub_blks *sblk;
428 	u32 pingpong;
429 	u32 dspp;
430 	unsigned long lm_pair;
431 };
432 
433 /**
434  * struct dpu_dspp_cfg - information of DSPP blocks
435  * @id                 enum identifying this block
436  * @base               register offset of this block
437  *                     supported by this block
438  * @sblk               sub-blocks information
439  */
440 struct dpu_dspp_cfg  {
441 	DPU_HW_BLK_INFO;
442 	const struct dpu_dspp_sub_blks *sblk;
443 };
444 
445 /**
446  * struct dpu_pingpong_cfg - information of PING-PONG blocks
447  * @id                 enum identifying this block
448  * @base               register offset of this block
449  * @intr_done:         index for PINGPONG done interrupt
450  * @intr_rdptr:        index for PINGPONG readpointer done interrupt
451  * @sblk               sub-blocks information
452  */
453 struct dpu_pingpong_cfg  {
454 	DPU_HW_BLK_INFO;
455 	u32 merge_3d;
456 	unsigned int intr_done;
457 	unsigned int intr_rdptr;
458 	const struct dpu_pingpong_sub_blks *sblk;
459 };
460 
461 /**
462  * struct dpu_merge_3d_cfg - information of DSPP blocks
463  * @id                 enum identifying this block
464  * @base               register offset of this block
465  * @sblk               sub-blocks information
466  */
467 struct dpu_merge_3d_cfg  {
468 	DPU_HW_BLK_INFO;
469 	const struct dpu_merge_3d_sub_blks *sblk;
470 };
471 
472 /**
473  * struct dpu_dsc_cfg - information of DSC blocks
474  * @id                 enum identifying this block
475  * @base               register offset of this block
476  * @len:               length of hardware block
477  * @features           bit mask identifying sub-blocks/features
478  * @sblk:              sub-blocks information
479  */
480 struct dpu_dsc_cfg {
481 	DPU_HW_BLK_INFO;
482 	unsigned long features;
483 	const struct dpu_dsc_sub_blks *sblk;
484 };
485 
486 /**
487  * struct dpu_intf_cfg - information of timing engine blocks
488  * @id                 enum identifying this block
489  * @base               register offset of this block
490  * @type:              Interface type(DSI, DP, HDMI)
491  * @controller_id:     Controller Instance ID in case of multiple of intf type
492  * @prog_fetch_lines_worst_case	Worst case latency num lines needed to prefetch
493  * @intr_underrun:	index for INTF underrun interrupt
494  * @intr_vsync:	        index for INTF VSYNC interrupt
495  * @intr_tear_rd_ptr:  Index for INTF TEAR_RD_PTR interrupt
496  */
497 struct dpu_intf_cfg  {
498 	DPU_HW_BLK_INFO;
499 	u32 type;   /* interface type*/
500 	u32 controller_id;
501 	u32 prog_fetch_lines_worst_case;
502 	unsigned int intr_underrun;
503 	unsigned int intr_vsync;
504 	unsigned int intr_tear_rd_ptr;
505 };
506 
507 /**
508  * struct dpu_wb_cfg - information of writeback blocks
509  * @DPU_HW_BLK_INFO:    refer to the description above for DPU_HW_BLK_INFO
510  * @vbif_idx:           vbif client index
511  * @maxlinewidth:       max line width supported by writeback block
512  * @xin_id:             bus client identifier
513  * @intr_wb_done:       interrupt index for WB_DONE
514  * @format_list:	    list of formats supported by this writeback block
515  * @num_formats:	    number of formats supported by this writeback block
516  * @clk_ctrl:	        clock control identifier
517  */
518 struct dpu_wb_cfg {
519 	DPU_HW_BLK_INFO;
520 	unsigned long features;
521 	u8 vbif_idx;
522 	u32 maxlinewidth;
523 	u32 xin_id;
524 	unsigned int intr_wb_done;
525 	const u32 *format_list;
526 	u32 num_formats;
527 	enum dpu_clk_ctrl_type clk_ctrl;
528 };
529 
530 /*
531  * struct dpu_cwb_cfg : MDP CWB mux instance info
532  * @id:                enum identifying this block
533  * @base:              register base offset to mdss
534  * @features           bit mask identifying sub-blocks/features
535  */
536 struct dpu_cwb_cfg {
537 	DPU_HW_BLK_INFO;
538 };
539 
540 /**
541  * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
542  * @pps                pixel per seconds
543  * @ot_limit           OT limit to use up to specified pixel per second
544  */
545 struct dpu_vbif_dynamic_ot_cfg {
546 	u64 pps;
547 	u32 ot_limit;
548 };
549 
550 /**
551  * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
552  * @count              length of cfg
553  * @cfg                pointer to array of configuration settings with
554  *                     ascending requirements
555  */
556 struct dpu_vbif_dynamic_ot_tbl {
557 	u32 count;
558 	const struct dpu_vbif_dynamic_ot_cfg *cfg;
559 };
560 
561 /**
562  * struct dpu_vbif_qos_tbl - QoS priority table
563  * @npriority_lvl      num of priority level
564  * @priority_lvl       pointer to array of priority level in ascending order
565  */
566 struct dpu_vbif_qos_tbl {
567 	u32 npriority_lvl;
568 	const u32 *priority_lvl;
569 };
570 
571 /**
572  * struct dpu_vbif_cfg - information of VBIF blocks
573  * @id                 enum identifying this block
574  * @base               register offset of this block
575  * @features           bit mask identifying sub-blocks/features
576  * @ot_rd_limit        default OT read limit
577  * @ot_wr_limit        default OT write limit
578  * @xin_halt_timeout   maximum time (in usec) for xin to halt
579  * @qos_rp_remap_size  size of VBIF_XINL_QOS_RP_REMAP register space
580  * @dynamic_ot_rd_tbl  dynamic OT read configuration table
581  * @dynamic_ot_wr_tbl  dynamic OT write configuration table
582  * @qos_rt_tbl         real-time QoS priority table
583  * @qos_nrt_tbl        non-real-time QoS priority table
584  * @memtype_count      number of defined memtypes
585  * @memtype            array of xin memtype definitions
586  */
587 struct dpu_vbif_cfg {
588 	DPU_HW_BLK_INFO;
589 	unsigned long features;
590 	u32 default_ot_rd_limit;
591 	u32 default_ot_wr_limit;
592 	u32 xin_halt_timeout;
593 	u32 qos_rp_remap_size;
594 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
595 	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
596 	struct dpu_vbif_qos_tbl qos_rt_tbl;
597 	struct dpu_vbif_qos_tbl qos_nrt_tbl;
598 	u32 memtype_count;
599 	u32 memtype[MAX_XIN_COUNT];
600 };
601 
602 /**
603  * struct dpu_cdm_cfg - information of chroma down blocks
604  * @name               string name for debug purposes
605  * @id                 enum identifying this block
606  * @base               register offset of this block
607  */
608 struct dpu_cdm_cfg {
609 	DPU_HW_BLK_INFO;
610 };
611 
612 /**
613  * Define CDP use cases
614  * @DPU_PERF_CDP_UDAGE_RT: real-time use cases
615  * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
616  */
617 enum {
618 	DPU_PERF_CDP_USAGE_RT,
619 	DPU_PERF_CDP_USAGE_NRT,
620 	DPU_PERF_CDP_USAGE_MAX
621 };
622 
623 /**
624  * struct dpu_perf_cdp_cfg - define CDP use case configuration
625  * @rd_enable: true if read pipe CDP is enabled
626  * @wr_enable: true if write pipe CDP is enabled
627  */
628 struct dpu_perf_cdp_cfg {
629 	bool rd_enable;
630 	bool wr_enable;
631 };
632 
633 /**
634  * struct dpu_mdss_version - DPU's major and minor versions
635  * @core_major_ver: DPU core's major version
636  * @core_minor_ver: DPU core's minor version
637  */
638 struct dpu_mdss_version {
639 	u8 core_major_ver;
640 	u8 core_minor_ver;
641 };
642 
643 /**
644  * struct dpu_perf_cfg - performance control settings
645  * @max_bw_low         low threshold of maximum bandwidth (kbps)
646  * @max_bw_high        high threshold of maximum bandwidth (kbps)
647  * @min_core_ib        minimum bandwidth for core (kbps)
648  * @min_core_ib        minimum mnoc ib vote in kbps
649  * @min_llcc_ib        minimum llcc ib vote in kbps
650  * @min_dram_ib        minimum dram ib vote in kbps
651  * @undersized_prefill_lines   undersized prefill in lines
652  * @xtra_prefill_lines         extra prefill latency in lines
653  * @dest_scale_prefill_lines   destination scaler latency in lines
654  * @macrotile_perfill_lines    macrotile latency in lines
655  * @yuv_nv12_prefill_lines     yuv_nv12 latency in lines
656  * @linear_prefill_lines       linear latency in lines
657  * @downscaling_prefill_lines  downscaling latency in lines
658  * @amortizable_theshold minimum y position for traffic shaping prefill
659  * @min_prefill_lines  minimum pipeline latency in lines
660  * @clk_inefficiency_factor DPU src clock inefficiency factor
661  * @bw_inefficiency_factor DPU axi bus bw inefficiency factor
662  * @safe_lut_tbl: LUT tables for safe signals
663  * @danger_lut_tbl: LUT tables for danger signals
664  * @qos_lut_tbl: LUT tables for QoS signals
665  * @cdp_cfg            cdp use case configurations
666  */
667 struct dpu_perf_cfg {
668 	u32 max_bw_low;
669 	u32 max_bw_high;
670 	u32 min_core_ib;
671 	u32 min_llcc_ib;
672 	u32 min_dram_ib;
673 	u32 undersized_prefill_lines;
674 	u32 xtra_prefill_lines;
675 	u32 dest_scale_prefill_lines;
676 	u32 macrotile_prefill_lines;
677 	u32 yuv_nv12_prefill_lines;
678 	u32 linear_prefill_lines;
679 	u32 downscaling_prefill_lines;
680 	u32 amortizable_threshold;
681 	u32 min_prefill_lines;
682 	u32 clk_inefficiency_factor;
683 	u32 bw_inefficiency_factor;
684 	u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
685 	u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
686 	struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
687 	struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
688 };
689 
690 /**
691  * struct dpu_mdss_cfg - information of MDSS HW
692  * This is the main catalog data structure representing
693  * this HW version. Contains dpu's major and minor versions,
694  * number of instances, register offsets, capabilities of the
695  * all MDSS HW sub-blocks.
696  *
697  * @dma_formats        Supported formats for dma pipe
698  * @cursor_formats     Supported formats for cursor pipe
699  * @vig_formats        Supported formats for vig pipe
700  */
701 struct dpu_mdss_cfg {
702 	const struct dpu_mdss_version *mdss_ver;
703 
704 	const struct dpu_caps *caps;
705 
706 	const struct dpu_mdp_cfg *mdp;
707 
708 	u32 ctl_count;
709 	const struct dpu_ctl_cfg *ctl;
710 
711 	u32 sspp_count;
712 	const struct dpu_sspp_cfg *sspp;
713 
714 	u32 mixer_count;
715 	const struct dpu_lm_cfg *mixer;
716 
717 	u32 pingpong_count;
718 	const struct dpu_pingpong_cfg *pingpong;
719 
720 	u32 merge_3d_count;
721 	const struct dpu_merge_3d_cfg *merge_3d;
722 
723 	u32 dsc_count;
724 	const struct dpu_dsc_cfg *dsc;
725 
726 	u32 intf_count;
727 	const struct dpu_intf_cfg *intf;
728 
729 	u32 vbif_count;
730 	const struct dpu_vbif_cfg *vbif;
731 
732 	u32 wb_count;
733 	const struct dpu_wb_cfg *wb;
734 
735 	const struct dpu_cdm_cfg *cdm;
736 
737 	u32 ad_count;
738 
739 	u32 dspp_count;
740 	const struct dpu_dspp_cfg *dspp;
741 
742 	u32 cwb_count;
743 	const struct dpu_cwb_cfg *cwb;
744 
745 	/* Add additional block data structures here */
746 
747 	const struct dpu_perf_cfg *perf;
748 	const struct dpu_format_extended *dma_formats;
749 	const struct dpu_format_extended *cursor_formats;
750 	const struct dpu_format_extended *vig_formats;
751 };
752 
753 extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
754 extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
755 extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
756 extern const struct dpu_mdss_cfg dpu_msm8996_cfg;
757 extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
758 extern const struct dpu_mdss_cfg dpu_sar2130p_cfg;
759 extern const struct dpu_mdss_cfg dpu_sdm630_cfg;
760 extern const struct dpu_mdss_cfg dpu_sdm660_cfg;
761 extern const struct dpu_mdss_cfg dpu_sdm845_cfg;
762 extern const struct dpu_mdss_cfg dpu_sdm670_cfg;
763 extern const struct dpu_mdss_cfg dpu_sm8150_cfg;
764 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
765 extern const struct dpu_mdss_cfg dpu_sm7150_cfg;
766 extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
767 extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
768 extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
769 extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
770 extern const struct dpu_mdss_cfg dpu_sm6150_cfg;
771 extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
772 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
773 extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
774 extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
775 extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
776 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
777 extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
778 extern const struct dpu_mdss_cfg dpu_sa8775p_cfg;
779 extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
780 extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
781 extern const struct dpu_mdss_cfg dpu_sm8750_cfg;
782 extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
783 
784 #endif /* _DPU_HW_CATALOG_H */
785