1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17
18 #include <scsi/scsi_tcq.h>
19 #include <scsi/scsicam.h>
20 #include <scsi/scsi_transport.h>
21 #include <scsi/scsi_transport_fc.h>
22
23 #include "qla_target.h"
24
25 /*
26 * Driver version
27 */
28 char qla2x00_version_str[40];
29
30 static int apidev_major;
31
32 /*
33 * SRB allocation cache
34 */
35 struct kmem_cache *srb_cachep;
36
37 int ql2xfulldump_on_mpifail;
38 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
39 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
40 "Set this to take full dump on MPI hang.");
41
42 int ql2xenforce_iocb_limit = 1;
43 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
45 "Enforce IOCB throttling, to avoid FW congestion. (default: 0)");
46
47 /*
48 * CT6 CTX allocation cache
49 */
50 static struct kmem_cache *ctx_cachep;
51 /*
52 * error level for logging
53 */
54 uint ql_errlev = 0x8001;
55
56 static int ql2xenableclass2;
57 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
58 MODULE_PARM_DESC(ql2xenableclass2,
59 "Specify if Class 2 operations are supported from the very "
60 "beginning. Default is 0 - class 2 not supported.");
61
62
63 int ql2xlogintimeout = 20;
64 module_param(ql2xlogintimeout, int, S_IRUGO);
65 MODULE_PARM_DESC(ql2xlogintimeout,
66 "Login timeout value in seconds.");
67
68 int qlport_down_retry;
69 module_param(qlport_down_retry, int, S_IRUGO);
70 MODULE_PARM_DESC(qlport_down_retry,
71 "Maximum number of command retries to a port that returns "
72 "a PORT-DOWN status.");
73
74 int ql2xplogiabsentdevice;
75 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
76 MODULE_PARM_DESC(ql2xplogiabsentdevice,
77 "Option to enable PLOGI to devices that are not present after "
78 "a Fabric scan. This is needed for several broken switches. "
79 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
80
81 int ql2xloginretrycount;
82 module_param(ql2xloginretrycount, int, S_IRUGO);
83 MODULE_PARM_DESC(ql2xloginretrycount,
84 "Specify an alternate value for the NVRAM login retry count.");
85
86 int ql2xallocfwdump = 1;
87 module_param(ql2xallocfwdump, int, S_IRUGO);
88 MODULE_PARM_DESC(ql2xallocfwdump,
89 "Option to enable allocation of memory for a firmware dump "
90 "during HBA initialization. Memory allocation requirements "
91 "vary by ISP type. Default is 1 - allocate memory.");
92
93 int ql2xextended_error_logging;
94 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
95 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
96 MODULE_PARM_DESC(ql2xextended_error_logging,
97 "Option to enable extended error logging,\n"
98 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
99 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
100 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
101 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
102 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
103 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
104 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
105 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
106 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
107 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
108 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
109 "\t\t0x1e400000 - Preferred value for capturing essential "
110 "debug information (equivalent to old "
111 "ql2xextended_error_logging=1).\n"
112 "\t\tDo LOGICAL OR of the value to enable more than one level");
113
114 int ql2xshiftctondsd = 6;
115 module_param(ql2xshiftctondsd, int, S_IRUGO);
116 MODULE_PARM_DESC(ql2xshiftctondsd,
117 "Set to control shifting of command type processing "
118 "based on total number of SG elements.");
119
120 int ql2xfdmienable = 1;
121 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
122 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
123 MODULE_PARM_DESC(ql2xfdmienable,
124 "Enables FDMI registrations. "
125 "0 - no FDMI registrations. "
126 "1 - provide FDMI registrations (default).");
127
128 #define MAX_Q_DEPTH 64
129 static int ql2xmaxqdepth = MAX_Q_DEPTH;
130 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
131 MODULE_PARM_DESC(ql2xmaxqdepth,
132 "Maximum queue depth to set for each LUN. "
133 "Default is 64.");
134
135 int ql2xenabledif = 2;
136 module_param(ql2xenabledif, int, S_IRUGO);
137 MODULE_PARM_DESC(ql2xenabledif,
138 " Enable T10-CRC-DIF:\n"
139 " Default is 2.\n"
140 " 0 -- No DIF Support\n"
141 " 1 -- Enable DIF for all types\n"
142 " 2 -- Enable DIF for all types, except Type 0.\n");
143
144 #if (IS_ENABLED(CONFIG_NVME_FC))
145 int ql2xnvmeenable = 1;
146 #else
147 int ql2xnvmeenable;
148 #endif
149 module_param(ql2xnvmeenable, int, 0644);
150 MODULE_PARM_DESC(ql2xnvmeenable,
151 "Enables NVME support. "
152 "0 - no NVMe. Default is Y");
153
154 int ql2xenablehba_err_chk = 2;
155 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
156 MODULE_PARM_DESC(ql2xenablehba_err_chk,
157 " Enable T10-CRC-DIF Error isolation by HBA:\n"
158 " Default is 2.\n"
159 " 0 -- Error isolation disabled\n"
160 " 1 -- Error isolation enabled only for DIX Type 0\n"
161 " 2 -- Error isolation enabled for all Types\n");
162
163 int ql2xiidmaenable = 1;
164 module_param(ql2xiidmaenable, int, S_IRUGO);
165 MODULE_PARM_DESC(ql2xiidmaenable,
166 "Enables iIDMA settings "
167 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
168
169 int ql2xmqsupport = 1;
170 module_param(ql2xmqsupport, int, S_IRUGO);
171 MODULE_PARM_DESC(ql2xmqsupport,
172 "Enable on demand multiple queue pairs support "
173 "Default is 1 for supported. "
174 "Set it to 0 to turn off mq qpair support.");
175
176 int ql2xfwloadbin;
177 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
178 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
179 MODULE_PARM_DESC(ql2xfwloadbin,
180 "Option to specify location from which to load ISP firmware:.\n"
181 " 2 -- load firmware via the request_firmware() (hotplug).\n"
182 " interface.\n"
183 " 1 -- load firmware from flash.\n"
184 " 0 -- use default semantics.\n");
185
186 int ql2xetsenable;
187 module_param(ql2xetsenable, int, S_IRUGO);
188 MODULE_PARM_DESC(ql2xetsenable,
189 "Enables firmware ETS burst."
190 "Default is 0 - skip ETS enablement.");
191
192 int ql2xdbwr = 1;
193 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
194 MODULE_PARM_DESC(ql2xdbwr,
195 "Option to specify scheme for request queue posting.\n"
196 " 0 -- Regular doorbell.\n"
197 " 1 -- CAMRAM doorbell (faster).\n");
198
199 int ql2xtargetreset = 1;
200 module_param(ql2xtargetreset, int, S_IRUGO);
201 MODULE_PARM_DESC(ql2xtargetreset,
202 "Enable target reset."
203 "Default is 1 - use hw defaults.");
204
205 int ql2xgffidenable;
206 module_param(ql2xgffidenable, int, S_IRUGO);
207 MODULE_PARM_DESC(ql2xgffidenable,
208 "Enables GFF_ID checks of port type. "
209 "Default is 0 - Do not use GFF_ID information.");
210
211 int ql2xasynctmfenable = 1;
212 module_param(ql2xasynctmfenable, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xasynctmfenable,
214 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
215 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
216
217 int ql2xdontresethba;
218 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
219 MODULE_PARM_DESC(ql2xdontresethba,
220 "Option to specify reset behaviour.\n"
221 " 0 (Default) -- Reset on failure.\n"
222 " 1 -- Do not reset on failure.\n");
223
224 uint64_t ql2xmaxlun = MAX_LUNS;
225 module_param(ql2xmaxlun, ullong, S_IRUGO);
226 MODULE_PARM_DESC(ql2xmaxlun,
227 "Defines the maximum LU number to register with the SCSI "
228 "midlayer. Default is 65535.");
229
230 int ql2xmdcapmask = 0x1F;
231 module_param(ql2xmdcapmask, int, S_IRUGO);
232 MODULE_PARM_DESC(ql2xmdcapmask,
233 "Set the Minidump driver capture mask level. "
234 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
235
236 int ql2xmdenable = 1;
237 module_param(ql2xmdenable, int, S_IRUGO);
238 MODULE_PARM_DESC(ql2xmdenable,
239 "Enable/disable MiniDump. "
240 "0 - MiniDump disabled. "
241 "1 (Default) - MiniDump enabled.");
242
243 int ql2xexlogins;
244 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
245 MODULE_PARM_DESC(ql2xexlogins,
246 "Number of extended Logins. "
247 "0 (Default)- Disabled.");
248
249 int ql2xexchoffld = 1024;
250 module_param(ql2xexchoffld, uint, 0644);
251 MODULE_PARM_DESC(ql2xexchoffld,
252 "Number of target exchanges.");
253
254 int ql2xiniexchg = 1024;
255 module_param(ql2xiniexchg, uint, 0644);
256 MODULE_PARM_DESC(ql2xiniexchg,
257 "Number of initiator exchanges.");
258
259 int ql2xfwholdabts;
260 module_param(ql2xfwholdabts, int, S_IRUGO);
261 MODULE_PARM_DESC(ql2xfwholdabts,
262 "Allow FW to hold status IOCB until ABTS rsp received. "
263 "0 (Default) Do not set fw option. "
264 "1 - Set fw option to hold ABTS.");
265
266 int ql2xmvasynctoatio = 1;
267 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
268 MODULE_PARM_DESC(ql2xmvasynctoatio,
269 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
270 "0 (Default). Do not move IOCBs"
271 "1 - Move IOCBs.");
272
273 int ql2xautodetectsfp = 1;
274 module_param(ql2xautodetectsfp, int, 0444);
275 MODULE_PARM_DESC(ql2xautodetectsfp,
276 "Detect SFP range and set appropriate distance.\n"
277 "1 (Default): Enable\n");
278
279 int ql2xenablemsix = 1;
280 module_param(ql2xenablemsix, int, 0444);
281 MODULE_PARM_DESC(ql2xenablemsix,
282 "Set to enable MSI or MSI-X interrupt mechanism.\n"
283 " Default is 1, enable MSI-X interrupt mechanism.\n"
284 " 0 -- enable traditional pin-based mechanism.\n"
285 " 1 -- enable MSI-X interrupt mechanism.\n"
286 " 2 -- enable MSI interrupt mechanism.\n");
287
288 int qla2xuseresexchforels;
289 module_param(qla2xuseresexchforels, int, 0444);
290 MODULE_PARM_DESC(qla2xuseresexchforels,
291 "Reserve 1/2 of emergency exchanges for ELS.\n"
292 " 0 (default): disabled");
293
294 static int ql2xprotmask;
295 module_param(ql2xprotmask, int, 0644);
296 MODULE_PARM_DESC(ql2xprotmask,
297 "Override DIF/DIX protection capabilities mask\n"
298 "Default is 0 which sets protection mask based on "
299 "capabilities reported by HBA firmware.\n");
300
301 static int ql2xprotguard;
302 module_param(ql2xprotguard, int, 0644);
303 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
304 " 0 -- Let HBA firmware decide\n"
305 " 1 -- Force T10 CRC\n"
306 " 2 -- Force IP checksum\n");
307
308 int ql2xdifbundlinginternalbuffers;
309 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
310 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
311 "Force using internal buffers for DIF information\n"
312 "0 (Default). Based on check.\n"
313 "1 Force using internal buffers\n");
314
315 int ql2xsmartsan;
316 module_param(ql2xsmartsan, int, 0444);
317 module_param_named(smartsan, ql2xsmartsan, int, 0444);
318 MODULE_PARM_DESC(ql2xsmartsan,
319 "Send SmartSAN Management Attributes for FDMI Registration."
320 " Default is 0 - No SmartSAN registration,"
321 " 1 - Register SmartSAN Management Attributes.");
322
323 int ql2xrdpenable;
324 module_param(ql2xrdpenable, int, 0444);
325 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
326 MODULE_PARM_DESC(ql2xrdpenable,
327 "Enables RDP responses. "
328 "0 - no RDP responses (default). "
329 "1 - provide RDP responses.");
330
331 static void qla2x00_clear_drv_active(struct qla_hw_data *);
332 static void qla2x00_free_device(scsi_qla_host_t *);
333 static int qla2xxx_map_queues(struct Scsi_Host *shost);
334 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
335
336
337 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
338 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
339
340 /* TODO Convert to inlines
341 *
342 * Timer routines
343 */
344
345 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)346 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
347 {
348 timer_setup(&vha->timer, qla2x00_timer, 0);
349 vha->timer.expires = jiffies + interval * HZ;
350 add_timer(&vha->timer);
351 vha->timer_active = 1;
352 }
353
354 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)355 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
356 {
357 /* Currently used for 82XX only. */
358 if (vha->device_flags & DFLG_DEV_FAILED) {
359 ql_dbg(ql_dbg_timer, vha, 0x600d,
360 "Device in a failed state, returning.\n");
361 return;
362 }
363
364 mod_timer(&vha->timer, jiffies + interval * HZ);
365 }
366
367 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)368 qla2x00_stop_timer(scsi_qla_host_t *vha)
369 {
370 del_timer_sync(&vha->timer);
371 vha->timer_active = 0;
372 }
373
374 static int qla2x00_do_dpc(void *data);
375
376 static void qla2x00_rst_aen(scsi_qla_host_t *);
377
378 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
379 struct req_que **, struct rsp_que **);
380 static void qla2x00_free_fw_dump(struct qla_hw_data *);
381 static void qla2x00_mem_free(struct qla_hw_data *);
382 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
383 struct qla_qpair *qpair);
384
385 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)386 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
387 struct rsp_que *rsp)
388 {
389 struct qla_hw_data *ha = vha->hw;
390
391 rsp->qpair = ha->base_qpair;
392 rsp->req = req;
393 ha->base_qpair->hw = ha;
394 ha->base_qpair->req = req;
395 ha->base_qpair->rsp = rsp;
396 ha->base_qpair->vha = vha;
397 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
398 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
399 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
400 ha->base_qpair->srb_mempool = ha->srb_mempool;
401 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
402 ha->base_qpair->enable_class_2 = ql2xenableclass2;
403 /* init qpair to this cpu. Will adjust at run time. */
404 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
405 ha->base_qpair->pdev = ha->pdev;
406
407 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
408 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
409 }
410
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)411 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
412 struct rsp_que *rsp)
413 {
414 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
415
416 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
417 GFP_KERNEL);
418 if (!ha->req_q_map) {
419 ql_log(ql_log_fatal, vha, 0x003b,
420 "Unable to allocate memory for request queue ptrs.\n");
421 goto fail_req_map;
422 }
423
424 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
425 GFP_KERNEL);
426 if (!ha->rsp_q_map) {
427 ql_log(ql_log_fatal, vha, 0x003c,
428 "Unable to allocate memory for response queue ptrs.\n");
429 goto fail_rsp_map;
430 }
431
432 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
433 if (ha->base_qpair == NULL) {
434 ql_log(ql_log_warn, vha, 0x00e0,
435 "Failed to allocate base queue pair memory.\n");
436 goto fail_base_qpair;
437 }
438
439 qla_init_base_qpair(vha, req, rsp);
440
441 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
442 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
443 GFP_KERNEL);
444 if (!ha->queue_pair_map) {
445 ql_log(ql_log_fatal, vha, 0x0180,
446 "Unable to allocate memory for queue pair ptrs.\n");
447 goto fail_qpair_map;
448 }
449 }
450
451 /*
452 * Make sure we record at least the request and response queue zero in
453 * case we need to free them if part of the probe fails.
454 */
455 ha->rsp_q_map[0] = rsp;
456 ha->req_q_map[0] = req;
457 set_bit(0, ha->rsp_qid_map);
458 set_bit(0, ha->req_qid_map);
459 return 0;
460
461 fail_qpair_map:
462 kfree(ha->base_qpair);
463 ha->base_qpair = NULL;
464 fail_base_qpair:
465 kfree(ha->rsp_q_map);
466 ha->rsp_q_map = NULL;
467 fail_rsp_map:
468 kfree(ha->req_q_map);
469 ha->req_q_map = NULL;
470 fail_req_map:
471 return -ENOMEM;
472 }
473
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)474 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
475 {
476 if (IS_QLAFX00(ha)) {
477 if (req && req->ring_fx00)
478 dma_free_coherent(&ha->pdev->dev,
479 (req->length_fx00 + 1) * sizeof(request_t),
480 req->ring_fx00, req->dma_fx00);
481 } else if (req && req->ring)
482 dma_free_coherent(&ha->pdev->dev,
483 (req->length + 1) * sizeof(request_t),
484 req->ring, req->dma);
485
486 if (req)
487 kfree(req->outstanding_cmds);
488
489 kfree(req);
490 }
491
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)492 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
493 {
494 if (IS_QLAFX00(ha)) {
495 if (rsp && rsp->ring_fx00)
496 dma_free_coherent(&ha->pdev->dev,
497 (rsp->length_fx00 + 1) * sizeof(request_t),
498 rsp->ring_fx00, rsp->dma_fx00);
499 } else if (rsp && rsp->ring) {
500 dma_free_coherent(&ha->pdev->dev,
501 (rsp->length + 1) * sizeof(response_t),
502 rsp->ring, rsp->dma);
503 }
504 kfree(rsp);
505 }
506
qla2x00_free_queues(struct qla_hw_data * ha)507 static void qla2x00_free_queues(struct qla_hw_data *ha)
508 {
509 struct req_que *req;
510 struct rsp_que *rsp;
511 int cnt;
512 unsigned long flags;
513
514 if (ha->queue_pair_map) {
515 kfree(ha->queue_pair_map);
516 ha->queue_pair_map = NULL;
517 }
518 if (ha->base_qpair) {
519 kfree(ha->base_qpair);
520 ha->base_qpair = NULL;
521 }
522
523 spin_lock_irqsave(&ha->hardware_lock, flags);
524 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
525 if (!test_bit(cnt, ha->req_qid_map))
526 continue;
527
528 req = ha->req_q_map[cnt];
529 clear_bit(cnt, ha->req_qid_map);
530 ha->req_q_map[cnt] = NULL;
531
532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533 qla2x00_free_req_que(ha, req);
534 spin_lock_irqsave(&ha->hardware_lock, flags);
535 }
536 spin_unlock_irqrestore(&ha->hardware_lock, flags);
537
538 kfree(ha->req_q_map);
539 ha->req_q_map = NULL;
540
541
542 spin_lock_irqsave(&ha->hardware_lock, flags);
543 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
544 if (!test_bit(cnt, ha->rsp_qid_map))
545 continue;
546
547 rsp = ha->rsp_q_map[cnt];
548 clear_bit(cnt, ha->rsp_qid_map);
549 ha->rsp_q_map[cnt] = NULL;
550 spin_unlock_irqrestore(&ha->hardware_lock, flags);
551 qla2x00_free_rsp_que(ha, rsp);
552 spin_lock_irqsave(&ha->hardware_lock, flags);
553 }
554 spin_unlock_irqrestore(&ha->hardware_lock, flags);
555
556 kfree(ha->rsp_q_map);
557 ha->rsp_q_map = NULL;
558 }
559
560 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)561 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
562 {
563 struct qla_hw_data *ha = vha->hw;
564 static const char *const pci_bus_modes[] = {
565 "33", "66", "100", "133",
566 };
567 uint16_t pci_bus;
568
569 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
570 if (pci_bus) {
571 snprintf(str, str_len, "PCI-X (%s MHz)",
572 pci_bus_modes[pci_bus]);
573 } else {
574 pci_bus = (ha->pci_attr & BIT_8) >> 8;
575 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
576 }
577
578 return str;
579 }
580
581 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)582 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
583 {
584 static const char *const pci_bus_modes[] = {
585 "33", "66", "100", "133",
586 };
587 struct qla_hw_data *ha = vha->hw;
588 uint32_t pci_bus;
589
590 if (pci_is_pcie(ha->pdev)) {
591 uint32_t lstat, lspeed, lwidth;
592 const char *speed_str;
593
594 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
595 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
596 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
597
598 switch (lspeed) {
599 case 1:
600 speed_str = "2.5GT/s";
601 break;
602 case 2:
603 speed_str = "5.0GT/s";
604 break;
605 case 3:
606 speed_str = "8.0GT/s";
607 break;
608 case 4:
609 speed_str = "16.0GT/s";
610 break;
611 default:
612 speed_str = "<unknown>";
613 break;
614 }
615 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
616
617 return str;
618 }
619
620 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
621 if (pci_bus == 0 || pci_bus == 8)
622 snprintf(str, str_len, "PCI (%s MHz)",
623 pci_bus_modes[pci_bus >> 3]);
624 else
625 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
626 pci_bus & 4 ? 2 : 1,
627 pci_bus_modes[pci_bus & 3]);
628
629 return str;
630 }
631
632 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)633 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
634 {
635 char un_str[10];
636 struct qla_hw_data *ha = vha->hw;
637
638 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
639 ha->fw_minor_version, ha->fw_subminor_version);
640
641 if (ha->fw_attributes & BIT_9) {
642 strcat(str, "FLX");
643 return (str);
644 }
645
646 switch (ha->fw_attributes & 0xFF) {
647 case 0x7:
648 strcat(str, "EF");
649 break;
650 case 0x17:
651 strcat(str, "TP");
652 break;
653 case 0x37:
654 strcat(str, "IP");
655 break;
656 case 0x77:
657 strcat(str, "VI");
658 break;
659 default:
660 sprintf(un_str, "(%x)", ha->fw_attributes);
661 strcat(str, un_str);
662 break;
663 }
664 if (ha->fw_attributes & 0x100)
665 strcat(str, "X");
666
667 return (str);
668 }
669
670 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)671 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
672 {
673 struct qla_hw_data *ha = vha->hw;
674
675 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
676 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
677 return str;
678 }
679
qla2x00_sp_free_dma(srb_t * sp)680 void qla2x00_sp_free_dma(srb_t *sp)
681 {
682 struct qla_hw_data *ha = sp->vha->hw;
683 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
684
685 if (sp->flags & SRB_DMA_VALID) {
686 scsi_dma_unmap(cmd);
687 sp->flags &= ~SRB_DMA_VALID;
688 }
689
690 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
691 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
692 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
693 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
694 }
695
696 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
697 /* List assured to be having elements */
698 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
699 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
700 }
701
702 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
703 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
704
705 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
706 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
707 }
708
709 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
710 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
711
712 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
713 ctx1->fcp_cmnd_dma);
714 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
715 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
716 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
717 mempool_free(ctx1, ha->ctx_mempool);
718 }
719 }
720
qla2x00_sp_compl(srb_t * sp,int res)721 void qla2x00_sp_compl(srb_t *sp, int res)
722 {
723 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
724 struct completion *comp = sp->comp;
725
726 sp->free(sp);
727 cmd->result = res;
728 CMD_SP(cmd) = NULL;
729 cmd->scsi_done(cmd);
730 if (comp)
731 complete(comp);
732 }
733
qla2xxx_qpair_sp_free_dma(srb_t * sp)734 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
735 {
736 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
737 struct qla_hw_data *ha = sp->fcport->vha->hw;
738
739 if (sp->flags & SRB_DMA_VALID) {
740 scsi_dma_unmap(cmd);
741 sp->flags &= ~SRB_DMA_VALID;
742 }
743
744 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
745 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
746 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
747 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
748 }
749
750 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
751 /* List assured to be having elements */
752 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
753 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
754 }
755
756 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
757 struct crc_context *difctx = sp->u.scmd.crc_ctx;
758 struct dsd_dma *dif_dsd, *nxt_dsd;
759
760 list_for_each_entry_safe(dif_dsd, nxt_dsd,
761 &difctx->ldif_dma_hndl_list, list) {
762 list_del(&dif_dsd->list);
763 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
764 dif_dsd->dsd_list_dma);
765 kfree(dif_dsd);
766 difctx->no_dif_bundl--;
767 }
768
769 list_for_each_entry_safe(dif_dsd, nxt_dsd,
770 &difctx->ldif_dsd_list, list) {
771 list_del(&dif_dsd->list);
772 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
773 dif_dsd->dsd_list_dma);
774 kfree(dif_dsd);
775 difctx->no_ldif_dsd--;
776 }
777
778 if (difctx->no_ldif_dsd) {
779 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
780 "%s: difctx->no_ldif_dsd=%x\n",
781 __func__, difctx->no_ldif_dsd);
782 }
783
784 if (difctx->no_dif_bundl) {
785 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
786 "%s: difctx->no_dif_bundl=%x\n",
787 __func__, difctx->no_dif_bundl);
788 }
789 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
790 }
791
792 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
793 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
794
795 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
796 ctx1->fcp_cmnd_dma);
797 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
798 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
799 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
800 mempool_free(ctx1, ha->ctx_mempool);
801 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
802 }
803
804 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
805 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
806
807 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
808 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
809 }
810 }
811
qla2xxx_qpair_sp_compl(srb_t * sp,int res)812 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
813 {
814 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
815 struct completion *comp = sp->comp;
816
817 sp->free(sp);
818 cmd->result = res;
819 CMD_SP(cmd) = NULL;
820 cmd->scsi_done(cmd);
821 if (comp)
822 complete(comp);
823 }
824
825 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)826 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
827 {
828 scsi_qla_host_t *vha = shost_priv(host);
829 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
830 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
831 struct qla_hw_data *ha = vha->hw;
832 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
833 srb_t *sp;
834 int rval;
835
836 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
837 WARN_ON_ONCE(!rport)) {
838 cmd->result = DID_NO_CONNECT << 16;
839 goto qc24_fail_command;
840 }
841
842 if (ha->mqenable) {
843 uint32_t tag;
844 uint16_t hwq;
845 struct qla_qpair *qpair = NULL;
846
847 tag = blk_mq_unique_tag(cmd->request);
848 hwq = blk_mq_unique_tag_to_hwq(tag);
849 qpair = ha->queue_pair_map[hwq];
850
851 if (qpair)
852 return qla2xxx_mqueuecommand(host, cmd, qpair);
853 }
854
855 if (ha->flags.eeh_busy) {
856 if (ha->flags.pci_channel_io_perm_failure) {
857 ql_dbg(ql_dbg_aer, vha, 0x9010,
858 "PCI Channel IO permanent failure, exiting "
859 "cmd=%p.\n", cmd);
860 cmd->result = DID_NO_CONNECT << 16;
861 } else {
862 ql_dbg(ql_dbg_aer, vha, 0x9011,
863 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
864 cmd->result = DID_REQUEUE << 16;
865 }
866 goto qc24_fail_command;
867 }
868
869 rval = fc_remote_port_chkready(rport);
870 if (rval) {
871 cmd->result = rval;
872 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
873 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
874 cmd, rval);
875 goto qc24_fail_command;
876 }
877
878 if (!vha->flags.difdix_supported &&
879 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
880 ql_dbg(ql_dbg_io, vha, 0x3004,
881 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
882 cmd);
883 cmd->result = DID_NO_CONNECT << 16;
884 goto qc24_fail_command;
885 }
886
887 if (!fcport) {
888 cmd->result = DID_NO_CONNECT << 16;
889 goto qc24_fail_command;
890 }
891
892 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
893 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
894 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
895 ql_dbg(ql_dbg_io, vha, 0x3005,
896 "Returning DNC, fcport_state=%d loop_state=%d.\n",
897 atomic_read(&fcport->state),
898 atomic_read(&base_vha->loop_state));
899 cmd->result = DID_NO_CONNECT << 16;
900 goto qc24_fail_command;
901 }
902 goto qc24_target_busy;
903 }
904
905 /*
906 * Return target busy if we've received a non-zero retry_delay_timer
907 * in a FCP_RSP.
908 */
909 if (fcport->retry_delay_timestamp == 0) {
910 /* retry delay not set */
911 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
912 fcport->retry_delay_timestamp = 0;
913 else
914 goto qc24_target_busy;
915
916 sp = scsi_cmd_priv(cmd);
917 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
918
919 sp->u.scmd.cmd = cmd;
920 sp->type = SRB_SCSI_CMD;
921
922 CMD_SP(cmd) = (void *)sp;
923 sp->free = qla2x00_sp_free_dma;
924 sp->done = qla2x00_sp_compl;
925
926 rval = ha->isp_ops->start_scsi(sp);
927 if (rval != QLA_SUCCESS) {
928 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
929 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
930 goto qc24_host_busy_free_sp;
931 }
932
933 return 0;
934
935 qc24_host_busy_free_sp:
936 sp->free(sp);
937
938 qc24_target_busy:
939 return SCSI_MLQUEUE_TARGET_BUSY;
940
941 qc24_fail_command:
942 cmd->scsi_done(cmd);
943
944 return 0;
945 }
946
947 /* For MQ supported I/O */
948 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)949 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
950 struct qla_qpair *qpair)
951 {
952 scsi_qla_host_t *vha = shost_priv(host);
953 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
954 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
955 struct qla_hw_data *ha = vha->hw;
956 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
957 srb_t *sp;
958 int rval;
959
960 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
961 if (rval) {
962 cmd->result = rval;
963 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
964 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
965 cmd, rval);
966 goto qc24_fail_command;
967 }
968
969 if (!fcport) {
970 cmd->result = DID_NO_CONNECT << 16;
971 goto qc24_fail_command;
972 }
973
974 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
975 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
976 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
977 ql_dbg(ql_dbg_io, vha, 0x3077,
978 "Returning DNC, fcport_state=%d loop_state=%d.\n",
979 atomic_read(&fcport->state),
980 atomic_read(&base_vha->loop_state));
981 cmd->result = DID_NO_CONNECT << 16;
982 goto qc24_fail_command;
983 }
984 goto qc24_target_busy;
985 }
986
987 /*
988 * Return target busy if we've received a non-zero retry_delay_timer
989 * in a FCP_RSP.
990 */
991 if (fcport->retry_delay_timestamp == 0) {
992 /* retry delay not set */
993 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
994 fcport->retry_delay_timestamp = 0;
995 else
996 goto qc24_target_busy;
997
998 sp = scsi_cmd_priv(cmd);
999 qla2xxx_init_sp(sp, vha, qpair, fcport);
1000
1001 sp->u.scmd.cmd = cmd;
1002 sp->type = SRB_SCSI_CMD;
1003 CMD_SP(cmd) = (void *)sp;
1004 sp->free = qla2xxx_qpair_sp_free_dma;
1005 sp->done = qla2xxx_qpair_sp_compl;
1006
1007 rval = ha->isp_ops->start_scsi_mq(sp);
1008 if (rval != QLA_SUCCESS) {
1009 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1010 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1011 if (rval == QLA_INTERFACE_ERROR)
1012 goto qc24_free_sp_fail_command;
1013 goto qc24_host_busy_free_sp;
1014 }
1015
1016 return 0;
1017
1018 qc24_host_busy_free_sp:
1019 sp->free(sp);
1020
1021 qc24_target_busy:
1022 return SCSI_MLQUEUE_TARGET_BUSY;
1023
1024 qc24_free_sp_fail_command:
1025 sp->free(sp);
1026 CMD_SP(cmd) = NULL;
1027 qla2xxx_rel_qpair_sp(sp->qpair, sp);
1028
1029 qc24_fail_command:
1030 cmd->scsi_done(cmd);
1031
1032 return 0;
1033 }
1034
1035 /*
1036 * qla2x00_eh_wait_on_command
1037 * Waits for the command to be returned by the Firmware for some
1038 * max time.
1039 *
1040 * Input:
1041 * cmd = Scsi Command to wait on.
1042 *
1043 * Return:
1044 * Completed in time : QLA_SUCCESS
1045 * Did not complete in time : QLA_FUNCTION_FAILED
1046 */
1047 static int
qla2x00_eh_wait_on_command(struct scsi_cmnd * cmd)1048 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1049 {
1050 #define ABORT_POLLING_PERIOD 1000
1051 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1052 unsigned long wait_iter = ABORT_WAIT_ITER;
1053 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1054 struct qla_hw_data *ha = vha->hw;
1055 int ret = QLA_SUCCESS;
1056
1057 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1058 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1059 "Return:eh_wait.\n");
1060 return ret;
1061 }
1062
1063 while (CMD_SP(cmd) && wait_iter--) {
1064 msleep(ABORT_POLLING_PERIOD);
1065 }
1066 if (CMD_SP(cmd))
1067 ret = QLA_FUNCTION_FAILED;
1068
1069 return ret;
1070 }
1071
1072 /*
1073 * qla2x00_wait_for_hba_online
1074 * Wait till the HBA is online after going through
1075 * <= MAX_RETRIES_OF_ISP_ABORT or
1076 * finally HBA is disabled ie marked offline
1077 *
1078 * Input:
1079 * ha - pointer to host adapter structure
1080 *
1081 * Note:
1082 * Does context switching-Release SPIN_LOCK
1083 * (if any) before calling this routine.
1084 *
1085 * Return:
1086 * Success (Adapter is online) : 0
1087 * Failed (Adapter is offline/disabled) : 1
1088 */
1089 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1090 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1091 {
1092 int return_status;
1093 unsigned long wait_online;
1094 struct qla_hw_data *ha = vha->hw;
1095 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1096
1097 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1098 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1099 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1100 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1101 ha->dpc_active) && time_before(jiffies, wait_online)) {
1102
1103 msleep(1000);
1104 }
1105 if (base_vha->flags.online)
1106 return_status = QLA_SUCCESS;
1107 else
1108 return_status = QLA_FUNCTION_FAILED;
1109
1110 return (return_status);
1111 }
1112
test_fcport_count(scsi_qla_host_t * vha)1113 static inline int test_fcport_count(scsi_qla_host_t *vha)
1114 {
1115 struct qla_hw_data *ha = vha->hw;
1116 unsigned long flags;
1117 int res;
1118
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1120 ql_dbg(ql_dbg_init, vha, 0x00ec,
1121 "tgt %p, fcport_count=%d\n",
1122 vha, vha->fcport_count);
1123 res = (vha->fcport_count == 0);
1124 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1125
1126 return res;
1127 }
1128
1129 /*
1130 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1131 * it has dependency on UNLOADING flag to stop device discovery
1132 */
1133 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1134 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1135 {
1136 u8 i;
1137
1138 qla2x00_mark_all_devices_lost(vha);
1139
1140 for (i = 0; i < 10; i++) {
1141 if (wait_event_timeout(vha->fcport_waitQ,
1142 test_fcport_count(vha), HZ) > 0)
1143 break;
1144 }
1145
1146 flush_workqueue(vha->hw->wq);
1147 }
1148
1149 /*
1150 * qla2x00_wait_for_hba_ready
1151 * Wait till the HBA is ready before doing driver unload
1152 *
1153 * Input:
1154 * ha - pointer to host adapter structure
1155 *
1156 * Note:
1157 * Does context switching-Release SPIN_LOCK
1158 * (if any) before calling this routine.
1159 *
1160 */
1161 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1162 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1163 {
1164 struct qla_hw_data *ha = vha->hw;
1165 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1166
1167 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1168 ha->flags.mbox_busy) ||
1169 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1170 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1171 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1172 break;
1173 msleep(1000);
1174 }
1175 }
1176
1177 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1178 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1179 {
1180 int return_status;
1181 unsigned long wait_reset;
1182 struct qla_hw_data *ha = vha->hw;
1183 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1184
1185 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1186 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1187 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1188 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1189 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1190
1191 msleep(1000);
1192
1193 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1194 ha->flags.chip_reset_done)
1195 break;
1196 }
1197 if (ha->flags.chip_reset_done)
1198 return_status = QLA_SUCCESS;
1199 else
1200 return_status = QLA_FUNCTION_FAILED;
1201
1202 return return_status;
1203 }
1204
1205 #define ISP_REG_DISCONNECT 0xffffffffU
1206 /**************************************************************************
1207 * qla2x00_isp_reg_stat
1208 *
1209 * Description:
1210 * Read the host status register of ISP before aborting the command.
1211 *
1212 * Input:
1213 * ha = pointer to host adapter structure.
1214 *
1215 *
1216 * Returns:
1217 * Either true or false.
1218 *
1219 * Note: Return true if there is register disconnect.
1220 **************************************************************************/
1221 static inline
qla2x00_isp_reg_stat(struct qla_hw_data * ha)1222 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1223 {
1224 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1225 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1226
1227 if (IS_P3P_TYPE(ha))
1228 return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT);
1229 else
1230 return ((rd_reg_dword(®->host_status)) ==
1231 ISP_REG_DISCONNECT);
1232 }
1233
1234 /**************************************************************************
1235 * qla2xxx_eh_abort
1236 *
1237 * Description:
1238 * The abort function will abort the specified command.
1239 *
1240 * Input:
1241 * cmd = Linux SCSI command packet to be aborted.
1242 *
1243 * Returns:
1244 * Either SUCCESS or FAILED.
1245 *
1246 * Note:
1247 * Only return FAILED if command not returned by firmware.
1248 **************************************************************************/
1249 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1250 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1251 {
1252 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1253 DECLARE_COMPLETION_ONSTACK(comp);
1254 srb_t *sp;
1255 int ret;
1256 unsigned int id;
1257 uint64_t lun;
1258 int rval;
1259 struct qla_hw_data *ha = vha->hw;
1260 uint32_t ratov_j;
1261 struct qla_qpair *qpair;
1262 unsigned long flags;
1263
1264 if (qla2x00_isp_reg_stat(ha)) {
1265 ql_log(ql_log_info, vha, 0x8042,
1266 "PCI/Register disconnect, exiting.\n");
1267 return FAILED;
1268 }
1269
1270 ret = fc_block_scsi_eh(cmd);
1271 if (ret != 0)
1272 return ret;
1273
1274 sp = scsi_cmd_priv(cmd);
1275 qpair = sp->qpair;
1276
1277 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1278 return SUCCESS;
1279
1280 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1281 sp->comp = ∁
1282 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1283
1284
1285 id = cmd->device->id;
1286 lun = cmd->device->lun;
1287
1288 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1289 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1290 vha->host_no, id, lun, sp, cmd, sp->handle);
1291
1292 /*
1293 * Abort will release the original Command/sp from FW. Let the
1294 * original command call scsi_done. In return, he will wakeup
1295 * this sleeping thread.
1296 */
1297 rval = ha->isp_ops->abort_command(sp);
1298
1299 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1300 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1301
1302 /* Wait for the command completion. */
1303 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1304 ratov_j = msecs_to_jiffies(ratov_j);
1305 switch (rval) {
1306 case QLA_SUCCESS:
1307 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1308 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1309 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1310 __func__, ha->r_a_tov/10);
1311 ret = FAILED;
1312 } else {
1313 ret = SUCCESS;
1314 }
1315 break;
1316 default:
1317 ret = FAILED;
1318 break;
1319 }
1320
1321 sp->comp = NULL;
1322
1323 ql_log(ql_log_info, vha, 0x801c,
1324 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1325 vha->host_no, id, lun, ret);
1326
1327 return ret;
1328 }
1329
1330 /*
1331 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1332 */
1333 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1334 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1335 uint64_t l, enum nexus_wait_type type)
1336 {
1337 int cnt, match, status;
1338 unsigned long flags;
1339 struct qla_hw_data *ha = vha->hw;
1340 struct req_que *req;
1341 srb_t *sp;
1342 struct scsi_cmnd *cmd;
1343
1344 status = QLA_SUCCESS;
1345
1346 spin_lock_irqsave(&ha->hardware_lock, flags);
1347 req = vha->req;
1348 for (cnt = 1; status == QLA_SUCCESS &&
1349 cnt < req->num_outstanding_cmds; cnt++) {
1350 sp = req->outstanding_cmds[cnt];
1351 if (!sp)
1352 continue;
1353 if (sp->type != SRB_SCSI_CMD)
1354 continue;
1355 if (vha->vp_idx != sp->vha->vp_idx)
1356 continue;
1357 match = 0;
1358 cmd = GET_CMD_SP(sp);
1359 switch (type) {
1360 case WAIT_HOST:
1361 match = 1;
1362 break;
1363 case WAIT_TARGET:
1364 match = cmd->device->id == t;
1365 break;
1366 case WAIT_LUN:
1367 match = (cmd->device->id == t &&
1368 cmd->device->lun == l);
1369 break;
1370 }
1371 if (!match)
1372 continue;
1373
1374 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1375 status = qla2x00_eh_wait_on_command(cmd);
1376 spin_lock_irqsave(&ha->hardware_lock, flags);
1377 }
1378 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1379
1380 return status;
1381 }
1382
1383 static char *reset_errors[] = {
1384 "HBA not online",
1385 "HBA not ready",
1386 "Task management failed",
1387 "Waiting for command completions",
1388 };
1389
1390 static int
__qla2xxx_eh_generic_reset(char * name,enum nexus_wait_type type,struct scsi_cmnd * cmd,int (* do_reset)(struct fc_port *,uint64_t,int))1391 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1392 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1393 {
1394 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1395 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1396 int err;
1397
1398 if (!fcport) {
1399 return FAILED;
1400 }
1401
1402 err = fc_block_scsi_eh(cmd);
1403 if (err != 0)
1404 return err;
1405
1406 if (fcport->deleted)
1407 return SUCCESS;
1408
1409 ql_log(ql_log_info, vha, 0x8009,
1410 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1411 cmd->device->id, cmd->device->lun, cmd);
1412
1413 err = 0;
1414 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1415 ql_log(ql_log_warn, vha, 0x800a,
1416 "Wait for hba online failed for cmd=%p.\n", cmd);
1417 goto eh_reset_failed;
1418 }
1419 err = 2;
1420 if (do_reset(fcport, cmd->device->lun, 1)
1421 != QLA_SUCCESS) {
1422 ql_log(ql_log_warn, vha, 0x800c,
1423 "do_reset failed for cmd=%p.\n", cmd);
1424 goto eh_reset_failed;
1425 }
1426 err = 3;
1427 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1428 cmd->device->lun, type) != QLA_SUCCESS) {
1429 ql_log(ql_log_warn, vha, 0x800d,
1430 "wait for pending cmds failed for cmd=%p.\n", cmd);
1431 goto eh_reset_failed;
1432 }
1433
1434 ql_log(ql_log_info, vha, 0x800e,
1435 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1436 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1437
1438 return SUCCESS;
1439
1440 eh_reset_failed:
1441 ql_log(ql_log_info, vha, 0x800f,
1442 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1443 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1444 cmd);
1445 return FAILED;
1446 }
1447
1448 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1449 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1450 {
1451 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1452 struct qla_hw_data *ha = vha->hw;
1453
1454 if (qla2x00_isp_reg_stat(ha)) {
1455 ql_log(ql_log_info, vha, 0x803e,
1456 "PCI/Register disconnect, exiting.\n");
1457 return FAILED;
1458 }
1459
1460 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1461 ha->isp_ops->lun_reset);
1462 }
1463
1464 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1465 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1466 {
1467 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1468 struct qla_hw_data *ha = vha->hw;
1469
1470 if (qla2x00_isp_reg_stat(ha)) {
1471 ql_log(ql_log_info, vha, 0x803f,
1472 "PCI/Register disconnect, exiting.\n");
1473 return FAILED;
1474 }
1475
1476 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1477 ha->isp_ops->target_reset);
1478 }
1479
1480 /**************************************************************************
1481 * qla2xxx_eh_bus_reset
1482 *
1483 * Description:
1484 * The bus reset function will reset the bus and abort any executing
1485 * commands.
1486 *
1487 * Input:
1488 * cmd = Linux SCSI command packet of the command that cause the
1489 * bus reset.
1490 *
1491 * Returns:
1492 * SUCCESS/FAILURE (defined as macro in scsi.h).
1493 *
1494 **************************************************************************/
1495 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1496 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1497 {
1498 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1499 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1500 int ret = FAILED;
1501 unsigned int id;
1502 uint64_t lun;
1503 struct qla_hw_data *ha = vha->hw;
1504
1505 if (qla2x00_isp_reg_stat(ha)) {
1506 ql_log(ql_log_info, vha, 0x8040,
1507 "PCI/Register disconnect, exiting.\n");
1508 return FAILED;
1509 }
1510
1511 id = cmd->device->id;
1512 lun = cmd->device->lun;
1513
1514 if (!fcport) {
1515 return ret;
1516 }
1517
1518 ret = fc_block_scsi_eh(cmd);
1519 if (ret != 0)
1520 return ret;
1521 ret = FAILED;
1522
1523 if (qla2x00_chip_is_down(vha))
1524 return ret;
1525
1526 ql_log(ql_log_info, vha, 0x8012,
1527 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1528
1529 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1530 ql_log(ql_log_fatal, vha, 0x8013,
1531 "Wait for hba online failed board disabled.\n");
1532 goto eh_bus_reset_done;
1533 }
1534
1535 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1536 ret = SUCCESS;
1537
1538 if (ret == FAILED)
1539 goto eh_bus_reset_done;
1540
1541 /* Flush outstanding commands. */
1542 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1543 QLA_SUCCESS) {
1544 ql_log(ql_log_warn, vha, 0x8014,
1545 "Wait for pending commands failed.\n");
1546 ret = FAILED;
1547 }
1548
1549 eh_bus_reset_done:
1550 ql_log(ql_log_warn, vha, 0x802b,
1551 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1552 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1553
1554 return ret;
1555 }
1556
1557 /**************************************************************************
1558 * qla2xxx_eh_host_reset
1559 *
1560 * Description:
1561 * The reset function will reset the Adapter.
1562 *
1563 * Input:
1564 * cmd = Linux SCSI command packet of the command that cause the
1565 * adapter reset.
1566 *
1567 * Returns:
1568 * Either SUCCESS or FAILED.
1569 *
1570 * Note:
1571 **************************************************************************/
1572 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1573 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1574 {
1575 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1576 struct qla_hw_data *ha = vha->hw;
1577 int ret = FAILED;
1578 unsigned int id;
1579 uint64_t lun;
1580 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1581
1582 if (qla2x00_isp_reg_stat(ha)) {
1583 ql_log(ql_log_info, vha, 0x8041,
1584 "PCI/Register disconnect, exiting.\n");
1585 schedule_work(&ha->board_disable);
1586 return SUCCESS;
1587 }
1588
1589 id = cmd->device->id;
1590 lun = cmd->device->lun;
1591
1592 ql_log(ql_log_info, vha, 0x8018,
1593 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1594
1595 /*
1596 * No point in issuing another reset if one is active. Also do not
1597 * attempt a reset if we are updating flash.
1598 */
1599 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1600 goto eh_host_reset_lock;
1601
1602 if (vha != base_vha) {
1603 if (qla2x00_vp_abort_isp(vha))
1604 goto eh_host_reset_lock;
1605 } else {
1606 if (IS_P3P_TYPE(vha->hw)) {
1607 if (!qla82xx_fcoe_ctx_reset(vha)) {
1608 /* Ctx reset success */
1609 ret = SUCCESS;
1610 goto eh_host_reset_lock;
1611 }
1612 /* fall thru if ctx reset failed */
1613 }
1614 if (ha->wq)
1615 flush_workqueue(ha->wq);
1616
1617 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1618 if (ha->isp_ops->abort_isp(base_vha)) {
1619 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1620 /* failed. schedule dpc to try */
1621 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1622
1623 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1624 ql_log(ql_log_warn, vha, 0x802a,
1625 "wait for hba online failed.\n");
1626 goto eh_host_reset_lock;
1627 }
1628 }
1629 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1630 }
1631
1632 /* Waiting for command to be returned to OS.*/
1633 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1634 QLA_SUCCESS)
1635 ret = SUCCESS;
1636
1637 eh_host_reset_lock:
1638 ql_log(ql_log_info, vha, 0x8017,
1639 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1640 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1641
1642 return ret;
1643 }
1644
1645 /*
1646 * qla2x00_loop_reset
1647 * Issue loop reset.
1648 *
1649 * Input:
1650 * ha = adapter block pointer.
1651 *
1652 * Returns:
1653 * 0 = success
1654 */
1655 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1656 qla2x00_loop_reset(scsi_qla_host_t *vha)
1657 {
1658 int ret;
1659 struct fc_port *fcport;
1660 struct qla_hw_data *ha = vha->hw;
1661
1662 if (IS_QLAFX00(ha)) {
1663 return qlafx00_loop_reset(vha);
1664 }
1665
1666 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1667 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1668 if (fcport->port_type != FCT_TARGET)
1669 continue;
1670
1671 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1672 if (ret != QLA_SUCCESS) {
1673 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1674 "Bus Reset failed: Reset=%d "
1675 "d_id=%x.\n", ret, fcport->d_id.b24);
1676 }
1677 }
1678 }
1679
1680
1681 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1682 atomic_set(&vha->loop_state, LOOP_DOWN);
1683 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1684 qla2x00_mark_all_devices_lost(vha);
1685 ret = qla2x00_full_login_lip(vha);
1686 if (ret != QLA_SUCCESS) {
1687 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1688 "full_login_lip=%d.\n", ret);
1689 }
1690 }
1691
1692 if (ha->flags.enable_lip_reset) {
1693 ret = qla2x00_lip_reset(vha);
1694 if (ret != QLA_SUCCESS)
1695 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1696 "lip_reset failed (%d).\n", ret);
1697 }
1698
1699 /* Issue marker command only when we are going to start the I/O */
1700 vha->marker_needed = 1;
1701
1702 return QLA_SUCCESS;
1703 }
1704
1705 /*
1706 * The caller must ensure that no completion interrupts will happen
1707 * while this function is in progress.
1708 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1709 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1710 unsigned long *flags)
1711 __releases(qp->qp_lock_ptr)
1712 __acquires(qp->qp_lock_ptr)
1713 {
1714 DECLARE_COMPLETION_ONSTACK(comp);
1715 scsi_qla_host_t *vha = qp->vha;
1716 struct qla_hw_data *ha = vha->hw;
1717 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1718 int rval;
1719 bool ret_cmd;
1720 uint32_t ratov_j;
1721
1722 lockdep_assert_held(qp->qp_lock_ptr);
1723
1724 if (qla2x00_chip_is_down(vha)) {
1725 sp->done(sp, res);
1726 return;
1727 }
1728
1729 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1730 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1731 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1732 !qla2x00_isp_reg_stat(ha))) {
1733 if (sp->comp) {
1734 sp->done(sp, res);
1735 return;
1736 }
1737
1738 sp->comp = ∁
1739 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1740
1741 rval = ha->isp_ops->abort_command(sp);
1742 /* Wait for command completion. */
1743 ret_cmd = false;
1744 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1745 ratov_j = msecs_to_jiffies(ratov_j);
1746 switch (rval) {
1747 case QLA_SUCCESS:
1748 if (wait_for_completion_timeout(&comp, ratov_j)) {
1749 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1750 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1751 __func__, ha->r_a_tov/10);
1752 ret_cmd = true;
1753 }
1754 /* else FW return SP to driver */
1755 break;
1756 default:
1757 ret_cmd = true;
1758 break;
1759 }
1760
1761 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1762 if (ret_cmd && blk_mq_request_started(cmd->request))
1763 sp->done(sp, res);
1764 } else {
1765 sp->done(sp, res);
1766 }
1767 }
1768
1769 /*
1770 * The caller must ensure that no completion interrupts will happen
1771 * while this function is in progress.
1772 */
1773 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1774 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1775 {
1776 int cnt;
1777 unsigned long flags;
1778 srb_t *sp;
1779 scsi_qla_host_t *vha = qp->vha;
1780 struct qla_hw_data *ha = vha->hw;
1781 struct req_que *req;
1782 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1783 struct qla_tgt_cmd *cmd;
1784
1785 if (!ha->req_q_map)
1786 return;
1787 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1788 req = qp->req;
1789 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1790 sp = req->outstanding_cmds[cnt];
1791 if (sp) {
1792 switch (sp->cmd_type) {
1793 case TYPE_SRB:
1794 qla2x00_abort_srb(qp, sp, res, &flags);
1795 break;
1796 case TYPE_TGT_CMD:
1797 if (!vha->hw->tgt.tgt_ops || !tgt ||
1798 qla_ini_mode_enabled(vha)) {
1799 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1800 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1801 vha->dpc_flags);
1802 continue;
1803 }
1804 cmd = (struct qla_tgt_cmd *)sp;
1805 cmd->aborted = 1;
1806 break;
1807 case TYPE_TGT_TMCMD:
1808 /* Skip task management functions. */
1809 break;
1810 default:
1811 break;
1812 }
1813 req->outstanding_cmds[cnt] = NULL;
1814 }
1815 }
1816 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1817 }
1818
1819 /*
1820 * The caller must ensure that no completion interrupts will happen
1821 * while this function is in progress.
1822 */
1823 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1824 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1825 {
1826 int que;
1827 struct qla_hw_data *ha = vha->hw;
1828
1829 /* Continue only if initialization complete. */
1830 if (!ha->base_qpair)
1831 return;
1832 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1833
1834 if (!ha->queue_pair_map)
1835 return;
1836 for (que = 0; que < ha->max_qpairs; que++) {
1837 if (!ha->queue_pair_map[que])
1838 continue;
1839
1840 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1841 }
1842 }
1843
1844 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1845 qla2xxx_slave_alloc(struct scsi_device *sdev)
1846 {
1847 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1848
1849 if (!rport || fc_remote_port_chkready(rport))
1850 return -ENXIO;
1851
1852 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1853
1854 return 0;
1855 }
1856
1857 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1858 qla2xxx_slave_configure(struct scsi_device *sdev)
1859 {
1860 scsi_qla_host_t *vha = shost_priv(sdev->host);
1861 struct req_que *req = vha->req;
1862
1863 if (IS_T10_PI_CAPABLE(vha->hw))
1864 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1865
1866 scsi_change_queue_depth(sdev, req->max_q_depth);
1867 return 0;
1868 }
1869
1870 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1871 qla2xxx_slave_destroy(struct scsi_device *sdev)
1872 {
1873 sdev->hostdata = NULL;
1874 }
1875
1876 /**
1877 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1878 * @ha: HA context
1879 *
1880 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1881 * supported addressing method.
1882 */
1883 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1884 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1885 {
1886 /* Assume a 32bit DMA mask. */
1887 ha->flags.enable_64bit_addressing = 0;
1888
1889 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1890 /* Any upper-dword bits set? */
1891 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1892 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1893 /* Ok, a 64bit DMA mask is applicable. */
1894 ha->flags.enable_64bit_addressing = 1;
1895 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1896 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1897 return;
1898 }
1899 }
1900
1901 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1902 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1903 }
1904
1905 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1906 qla2x00_enable_intrs(struct qla_hw_data *ha)
1907 {
1908 unsigned long flags = 0;
1909 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1910
1911 spin_lock_irqsave(&ha->hardware_lock, flags);
1912 ha->interrupts_on = 1;
1913 /* enable risc and host interrupts */
1914 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1915 rd_reg_word(®->ictrl);
1916 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1917
1918 }
1919
1920 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)1921 qla2x00_disable_intrs(struct qla_hw_data *ha)
1922 {
1923 unsigned long flags = 0;
1924 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1925
1926 spin_lock_irqsave(&ha->hardware_lock, flags);
1927 ha->interrupts_on = 0;
1928 /* disable risc and host interrupts */
1929 wrt_reg_word(®->ictrl, 0);
1930 rd_reg_word(®->ictrl);
1931 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1932 }
1933
1934 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)1935 qla24xx_enable_intrs(struct qla_hw_data *ha)
1936 {
1937 unsigned long flags = 0;
1938 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1939
1940 spin_lock_irqsave(&ha->hardware_lock, flags);
1941 ha->interrupts_on = 1;
1942 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
1943 rd_reg_dword(®->ictrl);
1944 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1945 }
1946
1947 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)1948 qla24xx_disable_intrs(struct qla_hw_data *ha)
1949 {
1950 unsigned long flags = 0;
1951 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1952
1953 if (IS_NOPOLLING_TYPE(ha))
1954 return;
1955 spin_lock_irqsave(&ha->hardware_lock, flags);
1956 ha->interrupts_on = 0;
1957 wrt_reg_dword(®->ictrl, 0);
1958 rd_reg_dword(®->ictrl);
1959 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1960 }
1961
1962 static int
qla2x00_iospace_config(struct qla_hw_data * ha)1963 qla2x00_iospace_config(struct qla_hw_data *ha)
1964 {
1965 resource_size_t pio;
1966 uint16_t msix;
1967
1968 if (pci_request_selected_regions(ha->pdev, ha->bars,
1969 QLA2XXX_DRIVER_NAME)) {
1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1971 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1972 pci_name(ha->pdev));
1973 goto iospace_error_exit;
1974 }
1975 if (!(ha->bars & 1))
1976 goto skip_pio;
1977
1978 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1979 pio = pci_resource_start(ha->pdev, 0);
1980 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1981 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1982 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1983 "Invalid pci I/O region size (%s).\n",
1984 pci_name(ha->pdev));
1985 pio = 0;
1986 }
1987 } else {
1988 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1989 "Region #0 no a PIO resource (%s).\n",
1990 pci_name(ha->pdev));
1991 pio = 0;
1992 }
1993 ha->pio_address = pio;
1994 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1995 "PIO address=%llu.\n",
1996 (unsigned long long)ha->pio_address);
1997
1998 skip_pio:
1999 /* Use MMIO operations for all accesses. */
2000 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2001 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2002 "Region #1 not an MMIO resource (%s), aborting.\n",
2003 pci_name(ha->pdev));
2004 goto iospace_error_exit;
2005 }
2006 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2007 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2008 "Invalid PCI mem region size (%s), aborting.\n",
2009 pci_name(ha->pdev));
2010 goto iospace_error_exit;
2011 }
2012
2013 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2014 if (!ha->iobase) {
2015 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2016 "Cannot remap MMIO (%s), aborting.\n",
2017 pci_name(ha->pdev));
2018 goto iospace_error_exit;
2019 }
2020
2021 /* Determine queue resources */
2022 ha->max_req_queues = ha->max_rsp_queues = 1;
2023 ha->msix_count = QLA_BASE_VECTORS;
2024
2025 /* Check if FW supports MQ or not */
2026 if (!(ha->fw_attributes & BIT_6))
2027 goto mqiobase_exit;
2028
2029 if (!ql2xmqsupport || !ql2xnvmeenable ||
2030 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2031 goto mqiobase_exit;
2032
2033 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2034 pci_resource_len(ha->pdev, 3));
2035 if (ha->mqiobase) {
2036 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2037 "MQIO Base=%p.\n", ha->mqiobase);
2038 /* Read MSIX vector size of the board */
2039 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2040 ha->msix_count = msix + 1;
2041 /* Max queues are bounded by available msix vectors */
2042 /* MB interrupt uses 1 vector */
2043 ha->max_req_queues = ha->msix_count - 1;
2044 ha->max_rsp_queues = ha->max_req_queues;
2045 /* Queue pairs is the max value minus the base queue pair */
2046 ha->max_qpairs = ha->max_rsp_queues - 1;
2047 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2048 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2049
2050 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2051 "MSI-X vector count: %d.\n", ha->msix_count);
2052 } else
2053 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2054 "BAR 3 not enabled.\n");
2055
2056 mqiobase_exit:
2057 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2058 "MSIX Count: %d.\n", ha->msix_count);
2059 return (0);
2060
2061 iospace_error_exit:
2062 return (-ENOMEM);
2063 }
2064
2065
2066 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2067 qla83xx_iospace_config(struct qla_hw_data *ha)
2068 {
2069 uint16_t msix;
2070
2071 if (pci_request_selected_regions(ha->pdev, ha->bars,
2072 QLA2XXX_DRIVER_NAME)) {
2073 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2074 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2075 pci_name(ha->pdev));
2076
2077 goto iospace_error_exit;
2078 }
2079
2080 /* Use MMIO operations for all accesses. */
2081 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2082 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2083 "Invalid pci I/O region size (%s).\n",
2084 pci_name(ha->pdev));
2085 goto iospace_error_exit;
2086 }
2087 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2088 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2089 "Invalid PCI mem region size (%s), aborting\n",
2090 pci_name(ha->pdev));
2091 goto iospace_error_exit;
2092 }
2093
2094 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2095 if (!ha->iobase) {
2096 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2097 "Cannot remap MMIO (%s), aborting.\n",
2098 pci_name(ha->pdev));
2099 goto iospace_error_exit;
2100 }
2101
2102 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2103 /* 83XX 26XX always use MQ type access for queues
2104 * - mbar 2, a.k.a region 4 */
2105 ha->max_req_queues = ha->max_rsp_queues = 1;
2106 ha->msix_count = QLA_BASE_VECTORS;
2107 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2108 pci_resource_len(ha->pdev, 4));
2109
2110 if (!ha->mqiobase) {
2111 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2112 "BAR2/region4 not enabled\n");
2113 goto mqiobase_exit;
2114 }
2115
2116 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2117 pci_resource_len(ha->pdev, 2));
2118 if (ha->msixbase) {
2119 /* Read MSIX vector size of the board */
2120 pci_read_config_word(ha->pdev,
2121 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2122 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2123 /*
2124 * By default, driver uses at least two msix vectors
2125 * (default & rspq)
2126 */
2127 if (ql2xmqsupport || ql2xnvmeenable) {
2128 /* MB interrupt uses 1 vector */
2129 ha->max_req_queues = ha->msix_count - 1;
2130
2131 /* ATIOQ needs 1 vector. That's 1 less QPair */
2132 if (QLA_TGT_MODE_ENABLED())
2133 ha->max_req_queues--;
2134
2135 ha->max_rsp_queues = ha->max_req_queues;
2136
2137 /* Queue pairs is the max value minus
2138 * the base queue pair */
2139 ha->max_qpairs = ha->max_req_queues - 1;
2140 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2141 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2142 }
2143 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2144 "MSI-X vector count: %d.\n", ha->msix_count);
2145 } else
2146 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2147 "BAR 1 not enabled.\n");
2148
2149 mqiobase_exit:
2150 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2151 "MSIX Count: %d.\n", ha->msix_count);
2152 return 0;
2153
2154 iospace_error_exit:
2155 return -ENOMEM;
2156 }
2157
2158 static struct isp_operations qla2100_isp_ops = {
2159 .pci_config = qla2100_pci_config,
2160 .reset_chip = qla2x00_reset_chip,
2161 .chip_diag = qla2x00_chip_diag,
2162 .config_rings = qla2x00_config_rings,
2163 .reset_adapter = qla2x00_reset_adapter,
2164 .nvram_config = qla2x00_nvram_config,
2165 .update_fw_options = qla2x00_update_fw_options,
2166 .load_risc = qla2x00_load_risc,
2167 .pci_info_str = qla2x00_pci_info_str,
2168 .fw_version_str = qla2x00_fw_version_str,
2169 .intr_handler = qla2100_intr_handler,
2170 .enable_intrs = qla2x00_enable_intrs,
2171 .disable_intrs = qla2x00_disable_intrs,
2172 .abort_command = qla2x00_abort_command,
2173 .target_reset = qla2x00_abort_target,
2174 .lun_reset = qla2x00_lun_reset,
2175 .fabric_login = qla2x00_login_fabric,
2176 .fabric_logout = qla2x00_fabric_logout,
2177 .calc_req_entries = qla2x00_calc_iocbs_32,
2178 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2179 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2180 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2181 .read_nvram = qla2x00_read_nvram_data,
2182 .write_nvram = qla2x00_write_nvram_data,
2183 .fw_dump = qla2100_fw_dump,
2184 .beacon_on = NULL,
2185 .beacon_off = NULL,
2186 .beacon_blink = NULL,
2187 .read_optrom = qla2x00_read_optrom_data,
2188 .write_optrom = qla2x00_write_optrom_data,
2189 .get_flash_version = qla2x00_get_flash_version,
2190 .start_scsi = qla2x00_start_scsi,
2191 .start_scsi_mq = NULL,
2192 .abort_isp = qla2x00_abort_isp,
2193 .iospace_config = qla2x00_iospace_config,
2194 .initialize_adapter = qla2x00_initialize_adapter,
2195 };
2196
2197 static struct isp_operations qla2300_isp_ops = {
2198 .pci_config = qla2300_pci_config,
2199 .reset_chip = qla2x00_reset_chip,
2200 .chip_diag = qla2x00_chip_diag,
2201 .config_rings = qla2x00_config_rings,
2202 .reset_adapter = qla2x00_reset_adapter,
2203 .nvram_config = qla2x00_nvram_config,
2204 .update_fw_options = qla2x00_update_fw_options,
2205 .load_risc = qla2x00_load_risc,
2206 .pci_info_str = qla2x00_pci_info_str,
2207 .fw_version_str = qla2x00_fw_version_str,
2208 .intr_handler = qla2300_intr_handler,
2209 .enable_intrs = qla2x00_enable_intrs,
2210 .disable_intrs = qla2x00_disable_intrs,
2211 .abort_command = qla2x00_abort_command,
2212 .target_reset = qla2x00_abort_target,
2213 .lun_reset = qla2x00_lun_reset,
2214 .fabric_login = qla2x00_login_fabric,
2215 .fabric_logout = qla2x00_fabric_logout,
2216 .calc_req_entries = qla2x00_calc_iocbs_32,
2217 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2218 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2219 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2220 .read_nvram = qla2x00_read_nvram_data,
2221 .write_nvram = qla2x00_write_nvram_data,
2222 .fw_dump = qla2300_fw_dump,
2223 .beacon_on = qla2x00_beacon_on,
2224 .beacon_off = qla2x00_beacon_off,
2225 .beacon_blink = qla2x00_beacon_blink,
2226 .read_optrom = qla2x00_read_optrom_data,
2227 .write_optrom = qla2x00_write_optrom_data,
2228 .get_flash_version = qla2x00_get_flash_version,
2229 .start_scsi = qla2x00_start_scsi,
2230 .start_scsi_mq = NULL,
2231 .abort_isp = qla2x00_abort_isp,
2232 .iospace_config = qla2x00_iospace_config,
2233 .initialize_adapter = qla2x00_initialize_adapter,
2234 };
2235
2236 static struct isp_operations qla24xx_isp_ops = {
2237 .pci_config = qla24xx_pci_config,
2238 .reset_chip = qla24xx_reset_chip,
2239 .chip_diag = qla24xx_chip_diag,
2240 .config_rings = qla24xx_config_rings,
2241 .reset_adapter = qla24xx_reset_adapter,
2242 .nvram_config = qla24xx_nvram_config,
2243 .update_fw_options = qla24xx_update_fw_options,
2244 .load_risc = qla24xx_load_risc,
2245 .pci_info_str = qla24xx_pci_info_str,
2246 .fw_version_str = qla24xx_fw_version_str,
2247 .intr_handler = qla24xx_intr_handler,
2248 .enable_intrs = qla24xx_enable_intrs,
2249 .disable_intrs = qla24xx_disable_intrs,
2250 .abort_command = qla24xx_abort_command,
2251 .target_reset = qla24xx_abort_target,
2252 .lun_reset = qla24xx_lun_reset,
2253 .fabric_login = qla24xx_login_fabric,
2254 .fabric_logout = qla24xx_fabric_logout,
2255 .calc_req_entries = NULL,
2256 .build_iocbs = NULL,
2257 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2258 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2259 .read_nvram = qla24xx_read_nvram_data,
2260 .write_nvram = qla24xx_write_nvram_data,
2261 .fw_dump = qla24xx_fw_dump,
2262 .beacon_on = qla24xx_beacon_on,
2263 .beacon_off = qla24xx_beacon_off,
2264 .beacon_blink = qla24xx_beacon_blink,
2265 .read_optrom = qla24xx_read_optrom_data,
2266 .write_optrom = qla24xx_write_optrom_data,
2267 .get_flash_version = qla24xx_get_flash_version,
2268 .start_scsi = qla24xx_start_scsi,
2269 .start_scsi_mq = NULL,
2270 .abort_isp = qla2x00_abort_isp,
2271 .iospace_config = qla2x00_iospace_config,
2272 .initialize_adapter = qla2x00_initialize_adapter,
2273 };
2274
2275 static struct isp_operations qla25xx_isp_ops = {
2276 .pci_config = qla25xx_pci_config,
2277 .reset_chip = qla24xx_reset_chip,
2278 .chip_diag = qla24xx_chip_diag,
2279 .config_rings = qla24xx_config_rings,
2280 .reset_adapter = qla24xx_reset_adapter,
2281 .nvram_config = qla24xx_nvram_config,
2282 .update_fw_options = qla24xx_update_fw_options,
2283 .load_risc = qla24xx_load_risc,
2284 .pci_info_str = qla24xx_pci_info_str,
2285 .fw_version_str = qla24xx_fw_version_str,
2286 .intr_handler = qla24xx_intr_handler,
2287 .enable_intrs = qla24xx_enable_intrs,
2288 .disable_intrs = qla24xx_disable_intrs,
2289 .abort_command = qla24xx_abort_command,
2290 .target_reset = qla24xx_abort_target,
2291 .lun_reset = qla24xx_lun_reset,
2292 .fabric_login = qla24xx_login_fabric,
2293 .fabric_logout = qla24xx_fabric_logout,
2294 .calc_req_entries = NULL,
2295 .build_iocbs = NULL,
2296 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2297 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2298 .read_nvram = qla25xx_read_nvram_data,
2299 .write_nvram = qla25xx_write_nvram_data,
2300 .fw_dump = qla25xx_fw_dump,
2301 .beacon_on = qla24xx_beacon_on,
2302 .beacon_off = qla24xx_beacon_off,
2303 .beacon_blink = qla24xx_beacon_blink,
2304 .read_optrom = qla25xx_read_optrom_data,
2305 .write_optrom = qla24xx_write_optrom_data,
2306 .get_flash_version = qla24xx_get_flash_version,
2307 .start_scsi = qla24xx_dif_start_scsi,
2308 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2309 .abort_isp = qla2x00_abort_isp,
2310 .iospace_config = qla2x00_iospace_config,
2311 .initialize_adapter = qla2x00_initialize_adapter,
2312 };
2313
2314 static struct isp_operations qla81xx_isp_ops = {
2315 .pci_config = qla25xx_pci_config,
2316 .reset_chip = qla24xx_reset_chip,
2317 .chip_diag = qla24xx_chip_diag,
2318 .config_rings = qla24xx_config_rings,
2319 .reset_adapter = qla24xx_reset_adapter,
2320 .nvram_config = qla81xx_nvram_config,
2321 .update_fw_options = qla24xx_update_fw_options,
2322 .load_risc = qla81xx_load_risc,
2323 .pci_info_str = qla24xx_pci_info_str,
2324 .fw_version_str = qla24xx_fw_version_str,
2325 .intr_handler = qla24xx_intr_handler,
2326 .enable_intrs = qla24xx_enable_intrs,
2327 .disable_intrs = qla24xx_disable_intrs,
2328 .abort_command = qla24xx_abort_command,
2329 .target_reset = qla24xx_abort_target,
2330 .lun_reset = qla24xx_lun_reset,
2331 .fabric_login = qla24xx_login_fabric,
2332 .fabric_logout = qla24xx_fabric_logout,
2333 .calc_req_entries = NULL,
2334 .build_iocbs = NULL,
2335 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2336 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2337 .read_nvram = NULL,
2338 .write_nvram = NULL,
2339 .fw_dump = qla81xx_fw_dump,
2340 .beacon_on = qla24xx_beacon_on,
2341 .beacon_off = qla24xx_beacon_off,
2342 .beacon_blink = qla83xx_beacon_blink,
2343 .read_optrom = qla25xx_read_optrom_data,
2344 .write_optrom = qla24xx_write_optrom_data,
2345 .get_flash_version = qla24xx_get_flash_version,
2346 .start_scsi = qla24xx_dif_start_scsi,
2347 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2348 .abort_isp = qla2x00_abort_isp,
2349 .iospace_config = qla2x00_iospace_config,
2350 .initialize_adapter = qla2x00_initialize_adapter,
2351 };
2352
2353 static struct isp_operations qla82xx_isp_ops = {
2354 .pci_config = qla82xx_pci_config,
2355 .reset_chip = qla82xx_reset_chip,
2356 .chip_diag = qla24xx_chip_diag,
2357 .config_rings = qla82xx_config_rings,
2358 .reset_adapter = qla24xx_reset_adapter,
2359 .nvram_config = qla81xx_nvram_config,
2360 .update_fw_options = qla24xx_update_fw_options,
2361 .load_risc = qla82xx_load_risc,
2362 .pci_info_str = qla24xx_pci_info_str,
2363 .fw_version_str = qla24xx_fw_version_str,
2364 .intr_handler = qla82xx_intr_handler,
2365 .enable_intrs = qla82xx_enable_intrs,
2366 .disable_intrs = qla82xx_disable_intrs,
2367 .abort_command = qla24xx_abort_command,
2368 .target_reset = qla24xx_abort_target,
2369 .lun_reset = qla24xx_lun_reset,
2370 .fabric_login = qla24xx_login_fabric,
2371 .fabric_logout = qla24xx_fabric_logout,
2372 .calc_req_entries = NULL,
2373 .build_iocbs = NULL,
2374 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2375 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2376 .read_nvram = qla24xx_read_nvram_data,
2377 .write_nvram = qla24xx_write_nvram_data,
2378 .fw_dump = qla82xx_fw_dump,
2379 .beacon_on = qla82xx_beacon_on,
2380 .beacon_off = qla82xx_beacon_off,
2381 .beacon_blink = NULL,
2382 .read_optrom = qla82xx_read_optrom_data,
2383 .write_optrom = qla82xx_write_optrom_data,
2384 .get_flash_version = qla82xx_get_flash_version,
2385 .start_scsi = qla82xx_start_scsi,
2386 .start_scsi_mq = NULL,
2387 .abort_isp = qla82xx_abort_isp,
2388 .iospace_config = qla82xx_iospace_config,
2389 .initialize_adapter = qla2x00_initialize_adapter,
2390 };
2391
2392 static struct isp_operations qla8044_isp_ops = {
2393 .pci_config = qla82xx_pci_config,
2394 .reset_chip = qla82xx_reset_chip,
2395 .chip_diag = qla24xx_chip_diag,
2396 .config_rings = qla82xx_config_rings,
2397 .reset_adapter = qla24xx_reset_adapter,
2398 .nvram_config = qla81xx_nvram_config,
2399 .update_fw_options = qla24xx_update_fw_options,
2400 .load_risc = qla82xx_load_risc,
2401 .pci_info_str = qla24xx_pci_info_str,
2402 .fw_version_str = qla24xx_fw_version_str,
2403 .intr_handler = qla8044_intr_handler,
2404 .enable_intrs = qla82xx_enable_intrs,
2405 .disable_intrs = qla82xx_disable_intrs,
2406 .abort_command = qla24xx_abort_command,
2407 .target_reset = qla24xx_abort_target,
2408 .lun_reset = qla24xx_lun_reset,
2409 .fabric_login = qla24xx_login_fabric,
2410 .fabric_logout = qla24xx_fabric_logout,
2411 .calc_req_entries = NULL,
2412 .build_iocbs = NULL,
2413 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2414 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2415 .read_nvram = NULL,
2416 .write_nvram = NULL,
2417 .fw_dump = qla8044_fw_dump,
2418 .beacon_on = qla82xx_beacon_on,
2419 .beacon_off = qla82xx_beacon_off,
2420 .beacon_blink = NULL,
2421 .read_optrom = qla8044_read_optrom_data,
2422 .write_optrom = qla8044_write_optrom_data,
2423 .get_flash_version = qla82xx_get_flash_version,
2424 .start_scsi = qla82xx_start_scsi,
2425 .start_scsi_mq = NULL,
2426 .abort_isp = qla8044_abort_isp,
2427 .iospace_config = qla82xx_iospace_config,
2428 .initialize_adapter = qla2x00_initialize_adapter,
2429 };
2430
2431 static struct isp_operations qla83xx_isp_ops = {
2432 .pci_config = qla25xx_pci_config,
2433 .reset_chip = qla24xx_reset_chip,
2434 .chip_diag = qla24xx_chip_diag,
2435 .config_rings = qla24xx_config_rings,
2436 .reset_adapter = qla24xx_reset_adapter,
2437 .nvram_config = qla81xx_nvram_config,
2438 .update_fw_options = qla24xx_update_fw_options,
2439 .load_risc = qla81xx_load_risc,
2440 .pci_info_str = qla24xx_pci_info_str,
2441 .fw_version_str = qla24xx_fw_version_str,
2442 .intr_handler = qla24xx_intr_handler,
2443 .enable_intrs = qla24xx_enable_intrs,
2444 .disable_intrs = qla24xx_disable_intrs,
2445 .abort_command = qla24xx_abort_command,
2446 .target_reset = qla24xx_abort_target,
2447 .lun_reset = qla24xx_lun_reset,
2448 .fabric_login = qla24xx_login_fabric,
2449 .fabric_logout = qla24xx_fabric_logout,
2450 .calc_req_entries = NULL,
2451 .build_iocbs = NULL,
2452 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2453 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2454 .read_nvram = NULL,
2455 .write_nvram = NULL,
2456 .fw_dump = qla83xx_fw_dump,
2457 .beacon_on = qla24xx_beacon_on,
2458 .beacon_off = qla24xx_beacon_off,
2459 .beacon_blink = qla83xx_beacon_blink,
2460 .read_optrom = qla25xx_read_optrom_data,
2461 .write_optrom = qla24xx_write_optrom_data,
2462 .get_flash_version = qla24xx_get_flash_version,
2463 .start_scsi = qla24xx_dif_start_scsi,
2464 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2465 .abort_isp = qla2x00_abort_isp,
2466 .iospace_config = qla83xx_iospace_config,
2467 .initialize_adapter = qla2x00_initialize_adapter,
2468 };
2469
2470 static struct isp_operations qlafx00_isp_ops = {
2471 .pci_config = qlafx00_pci_config,
2472 .reset_chip = qlafx00_soft_reset,
2473 .chip_diag = qlafx00_chip_diag,
2474 .config_rings = qlafx00_config_rings,
2475 .reset_adapter = qlafx00_soft_reset,
2476 .nvram_config = NULL,
2477 .update_fw_options = NULL,
2478 .load_risc = NULL,
2479 .pci_info_str = qlafx00_pci_info_str,
2480 .fw_version_str = qlafx00_fw_version_str,
2481 .intr_handler = qlafx00_intr_handler,
2482 .enable_intrs = qlafx00_enable_intrs,
2483 .disable_intrs = qlafx00_disable_intrs,
2484 .abort_command = qla24xx_async_abort_command,
2485 .target_reset = qlafx00_abort_target,
2486 .lun_reset = qlafx00_lun_reset,
2487 .fabric_login = NULL,
2488 .fabric_logout = NULL,
2489 .calc_req_entries = NULL,
2490 .build_iocbs = NULL,
2491 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2492 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2493 .read_nvram = qla24xx_read_nvram_data,
2494 .write_nvram = qla24xx_write_nvram_data,
2495 .fw_dump = NULL,
2496 .beacon_on = qla24xx_beacon_on,
2497 .beacon_off = qla24xx_beacon_off,
2498 .beacon_blink = NULL,
2499 .read_optrom = qla24xx_read_optrom_data,
2500 .write_optrom = qla24xx_write_optrom_data,
2501 .get_flash_version = qla24xx_get_flash_version,
2502 .start_scsi = qlafx00_start_scsi,
2503 .start_scsi_mq = NULL,
2504 .abort_isp = qlafx00_abort_isp,
2505 .iospace_config = qlafx00_iospace_config,
2506 .initialize_adapter = qlafx00_initialize_adapter,
2507 };
2508
2509 static struct isp_operations qla27xx_isp_ops = {
2510 .pci_config = qla25xx_pci_config,
2511 .reset_chip = qla24xx_reset_chip,
2512 .chip_diag = qla24xx_chip_diag,
2513 .config_rings = qla24xx_config_rings,
2514 .reset_adapter = qla24xx_reset_adapter,
2515 .nvram_config = qla81xx_nvram_config,
2516 .update_fw_options = qla24xx_update_fw_options,
2517 .load_risc = qla81xx_load_risc,
2518 .pci_info_str = qla24xx_pci_info_str,
2519 .fw_version_str = qla24xx_fw_version_str,
2520 .intr_handler = qla24xx_intr_handler,
2521 .enable_intrs = qla24xx_enable_intrs,
2522 .disable_intrs = qla24xx_disable_intrs,
2523 .abort_command = qla24xx_abort_command,
2524 .target_reset = qla24xx_abort_target,
2525 .lun_reset = qla24xx_lun_reset,
2526 .fabric_login = qla24xx_login_fabric,
2527 .fabric_logout = qla24xx_fabric_logout,
2528 .calc_req_entries = NULL,
2529 .build_iocbs = NULL,
2530 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2531 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2532 .read_nvram = NULL,
2533 .write_nvram = NULL,
2534 .fw_dump = qla27xx_fwdump,
2535 .mpi_fw_dump = qla27xx_mpi_fwdump,
2536 .beacon_on = qla24xx_beacon_on,
2537 .beacon_off = qla24xx_beacon_off,
2538 .beacon_blink = qla83xx_beacon_blink,
2539 .read_optrom = qla25xx_read_optrom_data,
2540 .write_optrom = qla24xx_write_optrom_data,
2541 .get_flash_version = qla24xx_get_flash_version,
2542 .start_scsi = qla24xx_dif_start_scsi,
2543 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2544 .abort_isp = qla2x00_abort_isp,
2545 .iospace_config = qla83xx_iospace_config,
2546 .initialize_adapter = qla2x00_initialize_adapter,
2547 };
2548
2549 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2550 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2551 {
2552 ha->device_type = DT_EXTENDED_IDS;
2553 switch (ha->pdev->device) {
2554 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2555 ha->isp_type |= DT_ISP2100;
2556 ha->device_type &= ~DT_EXTENDED_IDS;
2557 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2560 ha->isp_type |= DT_ISP2200;
2561 ha->device_type &= ~DT_EXTENDED_IDS;
2562 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2563 break;
2564 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2565 ha->isp_type |= DT_ISP2300;
2566 ha->device_type |= DT_ZIO_SUPPORTED;
2567 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2568 break;
2569 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2570 ha->isp_type |= DT_ISP2312;
2571 ha->device_type |= DT_ZIO_SUPPORTED;
2572 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2573 break;
2574 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2575 ha->isp_type |= DT_ISP2322;
2576 ha->device_type |= DT_ZIO_SUPPORTED;
2577 if (ha->pdev->subsystem_vendor == 0x1028 &&
2578 ha->pdev->subsystem_device == 0x0170)
2579 ha->device_type |= DT_OEM_001;
2580 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2581 break;
2582 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2583 ha->isp_type |= DT_ISP6312;
2584 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2585 break;
2586 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2587 ha->isp_type |= DT_ISP6322;
2588 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2589 break;
2590 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2591 ha->isp_type |= DT_ISP2422;
2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->device_type |= DT_IIDMA;
2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2596 break;
2597 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2598 ha->isp_type |= DT_ISP2432;
2599 ha->device_type |= DT_ZIO_SUPPORTED;
2600 ha->device_type |= DT_FWI2;
2601 ha->device_type |= DT_IIDMA;
2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2603 break;
2604 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2605 ha->isp_type |= DT_ISP8432;
2606 ha->device_type |= DT_ZIO_SUPPORTED;
2607 ha->device_type |= DT_FWI2;
2608 ha->device_type |= DT_IIDMA;
2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2610 break;
2611 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2612 ha->isp_type |= DT_ISP5422;
2613 ha->device_type |= DT_FWI2;
2614 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2615 break;
2616 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2617 ha->isp_type |= DT_ISP5432;
2618 ha->device_type |= DT_FWI2;
2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2620 break;
2621 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2622 ha->isp_type |= DT_ISP2532;
2623 ha->device_type |= DT_ZIO_SUPPORTED;
2624 ha->device_type |= DT_FWI2;
2625 ha->device_type |= DT_IIDMA;
2626 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2627 break;
2628 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2629 ha->isp_type |= DT_ISP8001;
2630 ha->device_type |= DT_ZIO_SUPPORTED;
2631 ha->device_type |= DT_FWI2;
2632 ha->device_type |= DT_IIDMA;
2633 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2634 break;
2635 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2636 ha->isp_type |= DT_ISP8021;
2637 ha->device_type |= DT_ZIO_SUPPORTED;
2638 ha->device_type |= DT_FWI2;
2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 /* Initialize 82XX ISP flags */
2641 qla82xx_init_flags(ha);
2642 break;
2643 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2644 ha->isp_type |= DT_ISP8044;
2645 ha->device_type |= DT_ZIO_SUPPORTED;
2646 ha->device_type |= DT_FWI2;
2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2648 /* Initialize 82XX ISP flags */
2649 qla82xx_init_flags(ha);
2650 break;
2651 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2652 ha->isp_type |= DT_ISP2031;
2653 ha->device_type |= DT_ZIO_SUPPORTED;
2654 ha->device_type |= DT_FWI2;
2655 ha->device_type |= DT_IIDMA;
2656 ha->device_type |= DT_T10_PI;
2657 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2658 break;
2659 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2660 ha->isp_type |= DT_ISP8031;
2661 ha->device_type |= DT_ZIO_SUPPORTED;
2662 ha->device_type |= DT_FWI2;
2663 ha->device_type |= DT_IIDMA;
2664 ha->device_type |= DT_T10_PI;
2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2666 break;
2667 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2668 ha->isp_type |= DT_ISPFX00;
2669 break;
2670 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2671 ha->isp_type |= DT_ISP2071;
2672 ha->device_type |= DT_ZIO_SUPPORTED;
2673 ha->device_type |= DT_FWI2;
2674 ha->device_type |= DT_IIDMA;
2675 ha->device_type |= DT_T10_PI;
2676 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2677 break;
2678 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2679 ha->isp_type |= DT_ISP2271;
2680 ha->device_type |= DT_ZIO_SUPPORTED;
2681 ha->device_type |= DT_FWI2;
2682 ha->device_type |= DT_IIDMA;
2683 ha->device_type |= DT_T10_PI;
2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2685 break;
2686 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2687 ha->isp_type |= DT_ISP2261;
2688 ha->device_type |= DT_ZIO_SUPPORTED;
2689 ha->device_type |= DT_FWI2;
2690 ha->device_type |= DT_IIDMA;
2691 ha->device_type |= DT_T10_PI;
2692 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2693 break;
2694 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2695 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2696 ha->isp_type |= DT_ISP2081;
2697 ha->device_type |= DT_ZIO_SUPPORTED;
2698 ha->device_type |= DT_FWI2;
2699 ha->device_type |= DT_IIDMA;
2700 ha->device_type |= DT_T10_PI;
2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2702 break;
2703 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2704 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2705 ha->isp_type |= DT_ISP2281;
2706 ha->device_type |= DT_ZIO_SUPPORTED;
2707 ha->device_type |= DT_FWI2;
2708 ha->device_type |= DT_IIDMA;
2709 ha->device_type |= DT_T10_PI;
2710 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2711 break;
2712 }
2713
2714 if (IS_QLA82XX(ha))
2715 ha->port_no = ha->portnum & 1;
2716 else {
2717 /* Get adapter physical port no from interrupt pin register. */
2718 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2719 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2720 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2721 ha->port_no--;
2722 else
2723 ha->port_no = !(ha->port_no & 1);
2724 }
2725
2726 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2727 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2728 ha->device_type, ha->port_no, ha->fw_srisc_address);
2729 }
2730
2731 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2732 qla2xxx_scan_start(struct Scsi_Host *shost)
2733 {
2734 scsi_qla_host_t *vha = shost_priv(shost);
2735
2736 if (vha->hw->flags.running_gold_fw)
2737 return;
2738
2739 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2740 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2741 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2742 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2743 }
2744
2745 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2746 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2747 {
2748 scsi_qla_host_t *vha = shost_priv(shost);
2749
2750 if (test_bit(UNLOADING, &vha->dpc_flags))
2751 return 1;
2752 if (!vha->host)
2753 return 1;
2754 if (time > vha->hw->loop_reset_delay * HZ)
2755 return 1;
2756
2757 return atomic_read(&vha->loop_state) == LOOP_READY;
2758 }
2759
qla2x00_iocb_work_fn(struct work_struct * work)2760 static void qla2x00_iocb_work_fn(struct work_struct *work)
2761 {
2762 struct scsi_qla_host *vha = container_of(work,
2763 struct scsi_qla_host, iocb_work);
2764 struct qla_hw_data *ha = vha->hw;
2765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2766 int i = 2;
2767 unsigned long flags;
2768
2769 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2770 return;
2771
2772 while (!list_empty(&vha->work_list) && i > 0) {
2773 qla2x00_do_work(vha);
2774 i--;
2775 }
2776
2777 spin_lock_irqsave(&vha->work_lock, flags);
2778 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2779 spin_unlock_irqrestore(&vha->work_lock, flags);
2780 }
2781
2782 /*
2783 * PCI driver interface
2784 */
2785 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2786 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2787 {
2788 int ret = -ENODEV;
2789 struct Scsi_Host *host;
2790 scsi_qla_host_t *base_vha = NULL;
2791 struct qla_hw_data *ha;
2792 char pci_info[30];
2793 char fw_str[30], wq_name[30];
2794 struct scsi_host_template *sht;
2795 int bars, mem_only = 0;
2796 uint16_t req_length = 0, rsp_length = 0;
2797 struct req_que *req = NULL;
2798 struct rsp_que *rsp = NULL;
2799 int i;
2800
2801 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2802 sht = &qla2xxx_driver_template;
2803 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2816 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2817 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2818 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2819 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2820 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2821 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2822 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2823 mem_only = 1;
2824 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2825 "Mem only adapter.\n");
2826 }
2827 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2828 "Bars=%d.\n", bars);
2829
2830 if (mem_only) {
2831 if (pci_enable_device_mem(pdev))
2832 return ret;
2833 } else {
2834 if (pci_enable_device(pdev))
2835 return ret;
2836 }
2837
2838 /* This may fail but that's ok */
2839 pci_enable_pcie_error_reporting(pdev);
2840
2841 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2842 if (!ha) {
2843 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2844 "Unable to allocate memory for ha.\n");
2845 goto disable_device;
2846 }
2847 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2848 "Memory allocated for ha=%p.\n", ha);
2849 ha->pdev = pdev;
2850 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2851 spin_lock_init(&ha->tgt.q_full_lock);
2852 spin_lock_init(&ha->tgt.sess_lock);
2853 spin_lock_init(&ha->tgt.atio_lock);
2854
2855 atomic_set(&ha->nvme_active_aen_cnt, 0);
2856
2857 /* Clear our data area */
2858 ha->bars = bars;
2859 ha->mem_only = mem_only;
2860 spin_lock_init(&ha->hardware_lock);
2861 spin_lock_init(&ha->vport_slock);
2862 mutex_init(&ha->selflogin_lock);
2863 mutex_init(&ha->optrom_mutex);
2864
2865 /* Set ISP-type information. */
2866 qla2x00_set_isp_flags(ha);
2867
2868 /* Set EEH reset type to fundamental if required by hba */
2869 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2870 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2871 pdev->needs_freset = 1;
2872
2873 ha->prev_topology = 0;
2874 ha->init_cb_size = sizeof(init_cb_t);
2875 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2876 ha->optrom_size = OPTROM_SIZE_2300;
2877 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2878 atomic_set(&ha->num_pend_mbx_stage1, 0);
2879 atomic_set(&ha->num_pend_mbx_stage2, 0);
2880 atomic_set(&ha->num_pend_mbx_stage3, 0);
2881 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2882 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2883
2884 /* Assign ISP specific operations. */
2885 if (IS_QLA2100(ha)) {
2886 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2887 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2888 req_length = REQUEST_ENTRY_CNT_2100;
2889 rsp_length = RESPONSE_ENTRY_CNT_2100;
2890 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2891 ha->gid_list_info_size = 4;
2892 ha->flash_conf_off = ~0;
2893 ha->flash_data_off = ~0;
2894 ha->nvram_conf_off = ~0;
2895 ha->nvram_data_off = ~0;
2896 ha->isp_ops = &qla2100_isp_ops;
2897 } else if (IS_QLA2200(ha)) {
2898 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2899 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2900 req_length = REQUEST_ENTRY_CNT_2200;
2901 rsp_length = RESPONSE_ENTRY_CNT_2100;
2902 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2903 ha->gid_list_info_size = 4;
2904 ha->flash_conf_off = ~0;
2905 ha->flash_data_off = ~0;
2906 ha->nvram_conf_off = ~0;
2907 ha->nvram_data_off = ~0;
2908 ha->isp_ops = &qla2100_isp_ops;
2909 } else if (IS_QLA23XX(ha)) {
2910 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2911 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2912 req_length = REQUEST_ENTRY_CNT_2200;
2913 rsp_length = RESPONSE_ENTRY_CNT_2300;
2914 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2915 ha->gid_list_info_size = 6;
2916 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2917 ha->optrom_size = OPTROM_SIZE_2322;
2918 ha->flash_conf_off = ~0;
2919 ha->flash_data_off = ~0;
2920 ha->nvram_conf_off = ~0;
2921 ha->nvram_data_off = ~0;
2922 ha->isp_ops = &qla2300_isp_ops;
2923 } else if (IS_QLA24XX_TYPE(ha)) {
2924 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2925 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2926 req_length = REQUEST_ENTRY_CNT_24XX;
2927 rsp_length = RESPONSE_ENTRY_CNT_2300;
2928 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2929 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2930 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2931 ha->gid_list_info_size = 8;
2932 ha->optrom_size = OPTROM_SIZE_24XX;
2933 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2934 ha->isp_ops = &qla24xx_isp_ops;
2935 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2936 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2937 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2938 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2939 } else if (IS_QLA25XX(ha)) {
2940 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2941 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2942 req_length = REQUEST_ENTRY_CNT_24XX;
2943 rsp_length = RESPONSE_ENTRY_CNT_2300;
2944 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2945 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2946 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2947 ha->gid_list_info_size = 8;
2948 ha->optrom_size = OPTROM_SIZE_25XX;
2949 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2950 ha->isp_ops = &qla25xx_isp_ops;
2951 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2952 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2953 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2954 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2955 } else if (IS_QLA81XX(ha)) {
2956 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2957 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2958 req_length = REQUEST_ENTRY_CNT_24XX;
2959 rsp_length = RESPONSE_ENTRY_CNT_2300;
2960 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2961 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2962 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2963 ha->gid_list_info_size = 8;
2964 ha->optrom_size = OPTROM_SIZE_81XX;
2965 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2966 ha->isp_ops = &qla81xx_isp_ops;
2967 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2968 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2969 ha->nvram_conf_off = ~0;
2970 ha->nvram_data_off = ~0;
2971 } else if (IS_QLA82XX(ha)) {
2972 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2973 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2974 req_length = REQUEST_ENTRY_CNT_82XX;
2975 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2976 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2977 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2978 ha->gid_list_info_size = 8;
2979 ha->optrom_size = OPTROM_SIZE_82XX;
2980 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2981 ha->isp_ops = &qla82xx_isp_ops;
2982 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2983 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2984 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2985 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2986 } else if (IS_QLA8044(ha)) {
2987 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2988 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2989 req_length = REQUEST_ENTRY_CNT_82XX;
2990 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2991 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2992 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2993 ha->gid_list_info_size = 8;
2994 ha->optrom_size = OPTROM_SIZE_83XX;
2995 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2996 ha->isp_ops = &qla8044_isp_ops;
2997 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2998 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2999 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3000 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3001 } else if (IS_QLA83XX(ha)) {
3002 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3003 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3004 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3005 req_length = REQUEST_ENTRY_CNT_83XX;
3006 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3007 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3008 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3009 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3010 ha->gid_list_info_size = 8;
3011 ha->optrom_size = OPTROM_SIZE_83XX;
3012 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3013 ha->isp_ops = &qla83xx_isp_ops;
3014 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3015 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3016 ha->nvram_conf_off = ~0;
3017 ha->nvram_data_off = ~0;
3018 } else if (IS_QLAFX00(ha)) {
3019 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3020 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3021 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3022 req_length = REQUEST_ENTRY_CNT_FX00;
3023 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3024 ha->isp_ops = &qlafx00_isp_ops;
3025 ha->port_down_retry_count = 30; /* default value */
3026 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3027 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3028 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3029 ha->mr.fw_hbt_en = 1;
3030 ha->mr.host_info_resend = false;
3031 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3032 } else if (IS_QLA27XX(ha)) {
3033 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3034 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3035 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3036 req_length = REQUEST_ENTRY_CNT_83XX;
3037 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3038 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3039 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3040 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3041 ha->gid_list_info_size = 8;
3042 ha->optrom_size = OPTROM_SIZE_83XX;
3043 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3044 ha->isp_ops = &qla27xx_isp_ops;
3045 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3046 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3047 ha->nvram_conf_off = ~0;
3048 ha->nvram_data_off = ~0;
3049 } else if (IS_QLA28XX(ha)) {
3050 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3051 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3052 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3053 req_length = REQUEST_ENTRY_CNT_24XX;
3054 rsp_length = RESPONSE_ENTRY_CNT_2300;
3055 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3056 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3057 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3058 ha->gid_list_info_size = 8;
3059 ha->optrom_size = OPTROM_SIZE_28XX;
3060 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3061 ha->isp_ops = &qla27xx_isp_ops;
3062 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3063 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3064 ha->nvram_conf_off = ~0;
3065 ha->nvram_data_off = ~0;
3066 }
3067
3068 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3069 "mbx_count=%d, req_length=%d, "
3070 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3071 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3072 "max_fibre_devices=%d.\n",
3073 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3074 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3075 ha->nvram_npiv_size, ha->max_fibre_devices);
3076 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3077 "isp_ops=%p, flash_conf_off=%d, "
3078 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3079 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3080 ha->nvram_conf_off, ha->nvram_data_off);
3081
3082 /* Configure PCI I/O space */
3083 ret = ha->isp_ops->iospace_config(ha);
3084 if (ret)
3085 goto iospace_config_failed;
3086
3087 ql_log_pci(ql_log_info, pdev, 0x001d,
3088 "Found an ISP%04X irq %d iobase 0x%p.\n",
3089 pdev->device, pdev->irq, ha->iobase);
3090 mutex_init(&ha->vport_lock);
3091 mutex_init(&ha->mq_lock);
3092 init_completion(&ha->mbx_cmd_comp);
3093 complete(&ha->mbx_cmd_comp);
3094 init_completion(&ha->mbx_intr_comp);
3095 init_completion(&ha->dcbx_comp);
3096 init_completion(&ha->lb_portup_comp);
3097
3098 set_bit(0, (unsigned long *) ha->vp_idx_map);
3099
3100 qla2x00_config_dma_addressing(ha);
3101 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3102 "64 Bit addressing is %s.\n",
3103 ha->flags.enable_64bit_addressing ? "enable" :
3104 "disable");
3105 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3106 if (ret) {
3107 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3108 "Failed to allocate memory for adapter, aborting.\n");
3109
3110 goto probe_hw_failed;
3111 }
3112
3113 req->max_q_depth = MAX_Q_DEPTH;
3114 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3115 req->max_q_depth = ql2xmaxqdepth;
3116
3117
3118 base_vha = qla2x00_create_host(sht, ha);
3119 if (!base_vha) {
3120 ret = -ENOMEM;
3121 goto probe_hw_failed;
3122 }
3123
3124 pci_set_drvdata(pdev, base_vha);
3125 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3126
3127 host = base_vha->host;
3128 base_vha->req = req;
3129 if (IS_QLA2XXX_MIDTYPE(ha))
3130 base_vha->mgmt_svr_loop_id =
3131 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3132 else
3133 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3134 base_vha->vp_idx;
3135
3136 /* Setup fcport template structure. */
3137 ha->mr.fcport.vha = base_vha;
3138 ha->mr.fcport.port_type = FCT_UNKNOWN;
3139 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3140 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3141 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3142 ha->mr.fcport.scan_state = 1;
3143
3144 /* Set the SG table size based on ISP type */
3145 if (!IS_FWI2_CAPABLE(ha)) {
3146 if (IS_QLA2100(ha))
3147 host->sg_tablesize = 32;
3148 } else {
3149 if (!IS_QLA82XX(ha))
3150 host->sg_tablesize = QLA_SG_ALL;
3151 }
3152 host->max_id = ha->max_fibre_devices;
3153 host->cmd_per_lun = 3;
3154 host->unique_id = host->host_no;
3155 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3156 host->max_cmd_len = 32;
3157 else
3158 host->max_cmd_len = MAX_CMDSZ;
3159 host->max_channel = MAX_BUSES - 1;
3160 /* Older HBAs support only 16-bit LUNs */
3161 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3162 ql2xmaxlun > 0xffff)
3163 host->max_lun = 0xffff;
3164 else
3165 host->max_lun = ql2xmaxlun;
3166 host->transportt = qla2xxx_transport_template;
3167 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3168
3169 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3170 "max_id=%d this_id=%d "
3171 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3172 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3173 host->this_id, host->cmd_per_lun, host->unique_id,
3174 host->max_cmd_len, host->max_channel, host->max_lun,
3175 host->transportt, sht->vendor_id);
3176
3177 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3178
3179 /* Set up the irqs */
3180 ret = qla2x00_request_irqs(ha, rsp);
3181 if (ret)
3182 goto probe_failed;
3183
3184 /* Alloc arrays of request and response ring ptrs */
3185 ret = qla2x00_alloc_queues(ha, req, rsp);
3186 if (ret) {
3187 ql_log(ql_log_fatal, base_vha, 0x003d,
3188 "Failed to allocate memory for queue pointers..."
3189 "aborting.\n");
3190 ret = -ENODEV;
3191 goto probe_failed;
3192 }
3193
3194 if (ha->mqenable) {
3195 /* number of hardware queues supported by blk/scsi-mq*/
3196 host->nr_hw_queues = ha->max_qpairs;
3197
3198 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3199 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3200 } else {
3201 if (ql2xnvmeenable) {
3202 host->nr_hw_queues = ha->max_qpairs;
3203 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3204 "FC-NVMe support is enabled, HW queues=%d\n",
3205 host->nr_hw_queues);
3206 } else {
3207 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3208 "blk/scsi-mq disabled.\n");
3209 }
3210 }
3211
3212 qlt_probe_one_stage1(base_vha, ha);
3213
3214 pci_save_state(pdev);
3215
3216 /* Assign back pointers */
3217 rsp->req = req;
3218 req->rsp = rsp;
3219
3220 if (IS_QLAFX00(ha)) {
3221 ha->rsp_q_map[0] = rsp;
3222 ha->req_q_map[0] = req;
3223 set_bit(0, ha->req_qid_map);
3224 set_bit(0, ha->rsp_qid_map);
3225 }
3226
3227 /* FWI2-capable only. */
3228 req->req_q_in = &ha->iobase->isp24.req_q_in;
3229 req->req_q_out = &ha->iobase->isp24.req_q_out;
3230 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3231 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3232 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3233 IS_QLA28XX(ha)) {
3234 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3235 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3236 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3237 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3238 }
3239
3240 if (IS_QLAFX00(ha)) {
3241 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3242 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3243 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3244 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3245 }
3246
3247 if (IS_P3P_TYPE(ha)) {
3248 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3249 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3250 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3251 }
3252
3253 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3254 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3255 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3256 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3257 "req->req_q_in=%p req->req_q_out=%p "
3258 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3259 req->req_q_in, req->req_q_out,
3260 rsp->rsp_q_in, rsp->rsp_q_out);
3261 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3262 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3263 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3264 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3265 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3266 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3267
3268 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3269 if (unlikely(!ha->wq)) {
3270 ret = -ENOMEM;
3271 goto probe_failed;
3272 }
3273
3274 if (ha->isp_ops->initialize_adapter(base_vha)) {
3275 ql_log(ql_log_fatal, base_vha, 0x00d6,
3276 "Failed to initialize adapter - Adapter flags %x.\n",
3277 base_vha->device_flags);
3278
3279 if (IS_QLA82XX(ha)) {
3280 qla82xx_idc_lock(ha);
3281 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3282 QLA8XXX_DEV_FAILED);
3283 qla82xx_idc_unlock(ha);
3284 ql_log(ql_log_fatal, base_vha, 0x00d7,
3285 "HW State: FAILED.\n");
3286 } else if (IS_QLA8044(ha)) {
3287 qla8044_idc_lock(ha);
3288 qla8044_wr_direct(base_vha,
3289 QLA8044_CRB_DEV_STATE_INDEX,
3290 QLA8XXX_DEV_FAILED);
3291 qla8044_idc_unlock(ha);
3292 ql_log(ql_log_fatal, base_vha, 0x0150,
3293 "HW State: FAILED.\n");
3294 }
3295
3296 ret = -ENODEV;
3297 goto probe_failed;
3298 }
3299
3300 if (IS_QLAFX00(ha))
3301 host->can_queue = QLAFX00_MAX_CANQUEUE;
3302 else
3303 host->can_queue = req->num_outstanding_cmds - 10;
3304
3305 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3306 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3307 host->can_queue, base_vha->req,
3308 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3309
3310 if (ha->mqenable) {
3311 bool startit = false;
3312
3313 if (QLA_TGT_MODE_ENABLED())
3314 startit = false;
3315
3316 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3317 startit = true;
3318
3319 /* Create start of day qpairs for Block MQ */
3320 for (i = 0; i < ha->max_qpairs; i++)
3321 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3322 }
3323 qla_init_iocb_limit(base_vha);
3324
3325 if (ha->flags.running_gold_fw)
3326 goto skip_dpc;
3327
3328 /*
3329 * Startup the kernel thread for this host adapter
3330 */
3331 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3332 "%s_dpc", base_vha->host_str);
3333 if (IS_ERR(ha->dpc_thread)) {
3334 ql_log(ql_log_fatal, base_vha, 0x00ed,
3335 "Failed to start DPC thread.\n");
3336 ret = PTR_ERR(ha->dpc_thread);
3337 ha->dpc_thread = NULL;
3338 goto probe_failed;
3339 }
3340 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3341 "DPC thread started successfully.\n");
3342
3343 /*
3344 * If we're not coming up in initiator mode, we might sit for
3345 * a while without waking up the dpc thread, which leads to a
3346 * stuck process warning. So just kick the dpc once here and
3347 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3348 */
3349 qla2xxx_wake_dpc(base_vha);
3350
3351 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3352
3353 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3354 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3355 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3356 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3357
3358 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3359 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3360 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3361 INIT_WORK(&ha->idc_state_handler,
3362 qla83xx_idc_state_handler_work);
3363 INIT_WORK(&ha->nic_core_unrecoverable,
3364 qla83xx_nic_core_unrecoverable_work);
3365 }
3366
3367 skip_dpc:
3368 list_add_tail(&base_vha->list, &ha->vp_list);
3369 base_vha->host->irq = ha->pdev->irq;
3370
3371 /* Initialized the timer */
3372 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3373 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3374 "Started qla2x00_timer with "
3375 "interval=%d.\n", WATCH_INTERVAL);
3376 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3377 "Detected hba at address=%p.\n",
3378 ha);
3379
3380 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3381 if (ha->fw_attributes & BIT_4) {
3382 int prot = 0, guard;
3383
3384 base_vha->flags.difdix_supported = 1;
3385 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3386 "Registering for DIF/DIX type 1 and 3 protection.\n");
3387 if (ql2xenabledif == 1)
3388 prot = SHOST_DIX_TYPE0_PROTECTION;
3389 if (ql2xprotmask)
3390 scsi_host_set_prot(host, ql2xprotmask);
3391 else
3392 scsi_host_set_prot(host,
3393 prot | SHOST_DIF_TYPE1_PROTECTION
3394 | SHOST_DIF_TYPE2_PROTECTION
3395 | SHOST_DIF_TYPE3_PROTECTION
3396 | SHOST_DIX_TYPE1_PROTECTION
3397 | SHOST_DIX_TYPE2_PROTECTION
3398 | SHOST_DIX_TYPE3_PROTECTION);
3399
3400 guard = SHOST_DIX_GUARD_CRC;
3401
3402 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3403 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3404 guard |= SHOST_DIX_GUARD_IP;
3405
3406 if (ql2xprotguard)
3407 scsi_host_set_guard(host, ql2xprotguard);
3408 else
3409 scsi_host_set_guard(host, guard);
3410 } else
3411 base_vha->flags.difdix_supported = 0;
3412 }
3413
3414 ha->isp_ops->enable_intrs(ha);
3415
3416 if (IS_QLAFX00(ha)) {
3417 ret = qlafx00_fx_disc(base_vha,
3418 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3419 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3420 QLA_SG_ALL : 128;
3421 }
3422
3423 ret = scsi_add_host(host, &pdev->dev);
3424 if (ret)
3425 goto probe_failed;
3426
3427 base_vha->flags.init_done = 1;
3428 base_vha->flags.online = 1;
3429 ha->prev_minidump_failed = 0;
3430
3431 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3432 "Init done and hba is online.\n");
3433
3434 if (qla_ini_mode_enabled(base_vha) ||
3435 qla_dual_mode_enabled(base_vha))
3436 scsi_scan_host(host);
3437 else
3438 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3439 "skipping scsi_scan_host() for non-initiator port\n");
3440
3441 qla2x00_alloc_sysfs_attr(base_vha);
3442
3443 if (IS_QLAFX00(ha)) {
3444 ret = qlafx00_fx_disc(base_vha,
3445 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3446
3447 /* Register system information */
3448 ret = qlafx00_fx_disc(base_vha,
3449 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3450 }
3451
3452 qla2x00_init_host_attr(base_vha);
3453
3454 qla2x00_dfs_setup(base_vha);
3455
3456 ql_log(ql_log_info, base_vha, 0x00fb,
3457 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3458 ql_log(ql_log_info, base_vha, 0x00fc,
3459 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3460 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3461 sizeof(pci_info)),
3462 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3463 base_vha->host_no,
3464 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3465
3466 qlt_add_target(ha, base_vha);
3467
3468 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3469
3470 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3471 return -ENODEV;
3472
3473 return 0;
3474
3475 probe_failed:
3476 if (base_vha->gnl.l) {
3477 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3478 base_vha->gnl.l, base_vha->gnl.ldma);
3479 base_vha->gnl.l = NULL;
3480 }
3481
3482 if (base_vha->timer_active)
3483 qla2x00_stop_timer(base_vha);
3484 base_vha->flags.online = 0;
3485 if (ha->dpc_thread) {
3486 struct task_struct *t = ha->dpc_thread;
3487
3488 ha->dpc_thread = NULL;
3489 kthread_stop(t);
3490 }
3491
3492 qla2x00_free_device(base_vha);
3493 scsi_host_put(base_vha->host);
3494 /*
3495 * Need to NULL out local req/rsp after
3496 * qla2x00_free_device => qla2x00_free_queues frees
3497 * what these are pointing to. Or else we'll
3498 * fall over below in qla2x00_free_req/rsp_que.
3499 */
3500 req = NULL;
3501 rsp = NULL;
3502
3503 probe_hw_failed:
3504 qla2x00_mem_free(ha);
3505 qla2x00_free_req_que(ha, req);
3506 qla2x00_free_rsp_que(ha, rsp);
3507 qla2x00_clear_drv_active(ha);
3508
3509 iospace_config_failed:
3510 if (IS_P3P_TYPE(ha)) {
3511 if (!ha->nx_pcibase)
3512 iounmap((device_reg_t *)ha->nx_pcibase);
3513 if (!ql2xdbwr)
3514 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3515 } else {
3516 if (ha->iobase)
3517 iounmap(ha->iobase);
3518 if (ha->cregbase)
3519 iounmap(ha->cregbase);
3520 }
3521 pci_release_selected_regions(ha->pdev, ha->bars);
3522 kfree(ha);
3523
3524 disable_device:
3525 pci_disable_device(pdev);
3526 return ret;
3527 }
3528
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3529 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3530 {
3531 scsi_qla_host_t *vp;
3532 unsigned long flags;
3533 struct qla_hw_data *ha;
3534
3535 if (!base_vha)
3536 return;
3537
3538 ha = base_vha->hw;
3539
3540 spin_lock_irqsave(&ha->vport_slock, flags);
3541 list_for_each_entry(vp, &ha->vp_list, list)
3542 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3543
3544 /*
3545 * Indicate device removal to prevent future board_disable
3546 * and wait until any pending board_disable has completed.
3547 */
3548 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3549 spin_unlock_irqrestore(&ha->vport_slock, flags);
3550 }
3551
3552 static void
qla2x00_shutdown(struct pci_dev * pdev)3553 qla2x00_shutdown(struct pci_dev *pdev)
3554 {
3555 scsi_qla_host_t *vha;
3556 struct qla_hw_data *ha;
3557
3558 vha = pci_get_drvdata(pdev);
3559 ha = vha->hw;
3560
3561 ql_log(ql_log_info, vha, 0xfffa,
3562 "Adapter shutdown\n");
3563
3564 /*
3565 * Prevent future board_disable and wait
3566 * until any pending board_disable has completed.
3567 */
3568 __qla_set_remove_flag(vha);
3569 cancel_work_sync(&ha->board_disable);
3570
3571 if (!atomic_read(&pdev->enable_cnt))
3572 return;
3573
3574 /* Notify ISPFX00 firmware */
3575 if (IS_QLAFX00(ha))
3576 qlafx00_driver_shutdown(vha, 20);
3577
3578 /* Turn-off FCE trace */
3579 if (ha->flags.fce_enabled) {
3580 qla2x00_disable_fce_trace(vha, NULL, NULL);
3581 ha->flags.fce_enabled = 0;
3582 }
3583
3584 /* Turn-off EFT trace */
3585 if (ha->eft)
3586 qla2x00_disable_eft_trace(vha);
3587
3588 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3589 IS_QLA28XX(ha)) {
3590 if (ha->flags.fw_started)
3591 qla2x00_abort_isp_cleanup(vha);
3592 } else {
3593 /* Stop currently executing firmware. */
3594 qla2x00_try_to_stop_firmware(vha);
3595 }
3596
3597 /* Disable timer */
3598 if (vha->timer_active)
3599 qla2x00_stop_timer(vha);
3600
3601 /* Turn adapter off line */
3602 vha->flags.online = 0;
3603
3604 /* turn-off interrupts on the card */
3605 if (ha->interrupts_on) {
3606 vha->flags.init_done = 0;
3607 ha->isp_ops->disable_intrs(ha);
3608 }
3609
3610 qla2x00_free_irqs(vha);
3611
3612 qla2x00_free_fw_dump(ha);
3613
3614 pci_disable_device(pdev);
3615 ql_log(ql_log_info, vha, 0xfffe,
3616 "Adapter shutdown successfully.\n");
3617 }
3618
3619 /* Deletes all the virtual ports for a given ha */
3620 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3621 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3622 {
3623 scsi_qla_host_t *vha;
3624 unsigned long flags;
3625
3626 mutex_lock(&ha->vport_lock);
3627 while (ha->cur_vport_count) {
3628 spin_lock_irqsave(&ha->vport_slock, flags);
3629
3630 BUG_ON(base_vha->list.next == &ha->vp_list);
3631 /* This assumes first entry in ha->vp_list is always base vha */
3632 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3633 scsi_host_get(vha->host);
3634
3635 spin_unlock_irqrestore(&ha->vport_slock, flags);
3636 mutex_unlock(&ha->vport_lock);
3637
3638 qla_nvme_delete(vha);
3639
3640 fc_vport_terminate(vha->fc_vport);
3641 scsi_host_put(vha->host);
3642
3643 mutex_lock(&ha->vport_lock);
3644 }
3645 mutex_unlock(&ha->vport_lock);
3646 }
3647
3648 /* Stops all deferred work threads */
3649 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3650 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3651 {
3652 /* Cancel all work and destroy DPC workqueues */
3653 if (ha->dpc_lp_wq) {
3654 cancel_work_sync(&ha->idc_aen);
3655 destroy_workqueue(ha->dpc_lp_wq);
3656 ha->dpc_lp_wq = NULL;
3657 }
3658
3659 if (ha->dpc_hp_wq) {
3660 cancel_work_sync(&ha->nic_core_reset);
3661 cancel_work_sync(&ha->idc_state_handler);
3662 cancel_work_sync(&ha->nic_core_unrecoverable);
3663 destroy_workqueue(ha->dpc_hp_wq);
3664 ha->dpc_hp_wq = NULL;
3665 }
3666
3667 /* Kill the kernel thread for this host */
3668 if (ha->dpc_thread) {
3669 struct task_struct *t = ha->dpc_thread;
3670
3671 /*
3672 * qla2xxx_wake_dpc checks for ->dpc_thread
3673 * so we need to zero it out.
3674 */
3675 ha->dpc_thread = NULL;
3676 kthread_stop(t);
3677 }
3678 }
3679
3680 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3681 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3682 {
3683 if (IS_QLA82XX(ha)) {
3684
3685 iounmap((device_reg_t *)ha->nx_pcibase);
3686 if (!ql2xdbwr)
3687 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3688 } else {
3689 if (ha->iobase)
3690 iounmap(ha->iobase);
3691
3692 if (ha->cregbase)
3693 iounmap(ha->cregbase);
3694
3695 if (ha->mqiobase)
3696 iounmap(ha->mqiobase);
3697
3698 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3699 ha->msixbase)
3700 iounmap(ha->msixbase);
3701 }
3702 }
3703
3704 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3705 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3706 {
3707 if (IS_QLA8044(ha)) {
3708 qla8044_idc_lock(ha);
3709 qla8044_clear_drv_active(ha);
3710 qla8044_idc_unlock(ha);
3711 } else if (IS_QLA82XX(ha)) {
3712 qla82xx_idc_lock(ha);
3713 qla82xx_clear_drv_active(ha);
3714 qla82xx_idc_unlock(ha);
3715 }
3716 }
3717
3718 static void
qla2x00_remove_one(struct pci_dev * pdev)3719 qla2x00_remove_one(struct pci_dev *pdev)
3720 {
3721 scsi_qla_host_t *base_vha;
3722 struct qla_hw_data *ha;
3723
3724 base_vha = pci_get_drvdata(pdev);
3725 ha = base_vha->hw;
3726 ql_log(ql_log_info, base_vha, 0xb079,
3727 "Removing driver\n");
3728 __qla_set_remove_flag(base_vha);
3729 cancel_work_sync(&ha->board_disable);
3730
3731 /*
3732 * If the PCI device is disabled then there was a PCI-disconnect and
3733 * qla2x00_disable_board_on_pci_error has taken care of most of the
3734 * resources.
3735 */
3736 if (!atomic_read(&pdev->enable_cnt)) {
3737 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3738 base_vha->gnl.l, base_vha->gnl.ldma);
3739 base_vha->gnl.l = NULL;
3740 scsi_host_put(base_vha->host);
3741 kfree(ha);
3742 pci_set_drvdata(pdev, NULL);
3743 return;
3744 }
3745 qla2x00_wait_for_hba_ready(base_vha);
3746
3747 /*
3748 * if UNLOADING flag is already set, then continue unload,
3749 * where it was set first.
3750 */
3751 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3752 return;
3753
3754 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3755 IS_QLA28XX(ha)) {
3756 if (ha->flags.fw_started)
3757 qla2x00_abort_isp_cleanup(base_vha);
3758 } else if (!IS_QLAFX00(ha)) {
3759 if (IS_QLA8031(ha)) {
3760 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3761 "Clearing fcoe driver presence.\n");
3762 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3763 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3764 "Error while clearing DRV-Presence.\n");
3765 }
3766
3767 qla2x00_try_to_stop_firmware(base_vha);
3768 }
3769
3770 qla2x00_wait_for_sess_deletion(base_vha);
3771
3772 qla_nvme_delete(base_vha);
3773
3774 dma_free_coherent(&ha->pdev->dev,
3775 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3776
3777 base_vha->gnl.l = NULL;
3778
3779 vfree(base_vha->scan.l);
3780
3781 if (IS_QLAFX00(ha))
3782 qlafx00_driver_shutdown(base_vha, 20);
3783
3784 qla2x00_delete_all_vps(ha, base_vha);
3785
3786 qla2x00_dfs_remove(base_vha);
3787
3788 qla84xx_put_chip(base_vha);
3789
3790 /* Disable timer */
3791 if (base_vha->timer_active)
3792 qla2x00_stop_timer(base_vha);
3793
3794 base_vha->flags.online = 0;
3795
3796 /* free DMA memory */
3797 if (ha->exlogin_buf)
3798 qla2x00_free_exlogin_buffer(ha);
3799
3800 /* free DMA memory */
3801 if (ha->exchoffld_buf)
3802 qla2x00_free_exchoffld_buffer(ha);
3803
3804 qla2x00_destroy_deferred_work(ha);
3805
3806 qlt_remove_target(ha, base_vha);
3807
3808 qla2x00_free_sysfs_attr(base_vha, true);
3809
3810 fc_remove_host(base_vha->host);
3811 qlt_remove_target_resources(ha);
3812
3813 scsi_remove_host(base_vha->host);
3814
3815 qla2x00_free_device(base_vha);
3816
3817 qla2x00_clear_drv_active(ha);
3818
3819 scsi_host_put(base_vha->host);
3820
3821 qla2x00_unmap_iobases(ha);
3822
3823 pci_release_selected_regions(ha->pdev, ha->bars);
3824 kfree(ha);
3825
3826 pci_disable_pcie_error_reporting(pdev);
3827
3828 pci_disable_device(pdev);
3829 }
3830
3831 static inline void
qla24xx_free_purex_list(struct purex_list * list)3832 qla24xx_free_purex_list(struct purex_list *list)
3833 {
3834 struct list_head *item, *next;
3835 ulong flags;
3836
3837 spin_lock_irqsave(&list->lock, flags);
3838 list_for_each_safe(item, next, &list->head) {
3839 list_del(item);
3840 kfree(list_entry(item, struct purex_item, list));
3841 }
3842 spin_unlock_irqrestore(&list->lock, flags);
3843 }
3844
3845 static void
qla2x00_free_device(scsi_qla_host_t * vha)3846 qla2x00_free_device(scsi_qla_host_t *vha)
3847 {
3848 struct qla_hw_data *ha = vha->hw;
3849
3850 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3851
3852 /* Disable timer */
3853 if (vha->timer_active)
3854 qla2x00_stop_timer(vha);
3855
3856 qla25xx_delete_queues(vha);
3857 vha->flags.online = 0;
3858
3859 /* turn-off interrupts on the card */
3860 if (ha->interrupts_on) {
3861 vha->flags.init_done = 0;
3862 ha->isp_ops->disable_intrs(ha);
3863 }
3864
3865 qla2x00_free_fcports(vha);
3866
3867 qla2x00_free_irqs(vha);
3868
3869 /* Flush the work queue and remove it */
3870 if (ha->wq) {
3871 flush_workqueue(ha->wq);
3872 destroy_workqueue(ha->wq);
3873 ha->wq = NULL;
3874 }
3875
3876
3877 qla24xx_free_purex_list(&vha->purex_list);
3878
3879 qla2x00_mem_free(ha);
3880
3881 qla82xx_md_free(vha);
3882
3883 qla2x00_free_queues(ha);
3884 }
3885
qla2x00_free_fcports(struct scsi_qla_host * vha)3886 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3887 {
3888 fc_port_t *fcport, *tfcport;
3889
3890 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3891 qla2x00_free_fcport(fcport);
3892 }
3893
3894 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)3895 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
3896 {
3897 int now;
3898
3899 if (!fcport->rport)
3900 return;
3901
3902 if (fcport->rport) {
3903 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3904 "%s %8phN. rport %p roles %x\n",
3905 __func__, fcport->port_name, fcport->rport,
3906 fcport->rport->roles);
3907 fc_remote_port_delete(fcport->rport);
3908 }
3909 qlt_do_generation_tick(vha, &now);
3910 }
3911
3912 /*
3913 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3914 *
3915 * Input: ha = adapter block pointer. fcport = port structure pointer.
3916 *
3917 * Return: None.
3918 *
3919 * Context:
3920 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)3921 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3922 int do_login)
3923 {
3924 if (IS_QLAFX00(vha->hw)) {
3925 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3926 qla2x00_schedule_rport_del(vha, fcport);
3927 return;
3928 }
3929
3930 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3931 vha->vp_idx == fcport->vha->vp_idx) {
3932 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3933 qla2x00_schedule_rport_del(vha, fcport);
3934 }
3935 /*
3936 * We may need to retry the login, so don't change the state of the
3937 * port but do the retries.
3938 */
3939 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3940 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3941
3942 if (!do_login)
3943 return;
3944
3945 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3946 }
3947
3948 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)3949 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
3950 {
3951 fc_port_t *fcport;
3952
3953 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3954 "Mark all dev lost\n");
3955
3956 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3957 fcport->scan_state = 0;
3958 qlt_schedule_sess_for_deletion(fcport);
3959 }
3960 }
3961
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)3962 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3963 {
3964 int i;
3965
3966 if (IS_FWI2_CAPABLE(ha))
3967 return;
3968
3969 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3970 set_bit(i, ha->loop_id_map);
3971 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3972 set_bit(BROADCAST, ha->loop_id_map);
3973 }
3974
3975 /*
3976 * qla2x00_mem_alloc
3977 * Allocates adapter memory.
3978 *
3979 * Returns:
3980 * 0 = success.
3981 * !0 = failure.
3982 */
3983 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)3984 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3985 struct req_que **req, struct rsp_que **rsp)
3986 {
3987 char name[16];
3988
3989 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3990 &ha->init_cb_dma, GFP_KERNEL);
3991 if (!ha->init_cb)
3992 goto fail;
3993
3994 if (qlt_mem_alloc(ha) < 0)
3995 goto fail_free_init_cb;
3996
3997 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3998 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3999 if (!ha->gid_list)
4000 goto fail_free_tgt_mem;
4001
4002 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4003 if (!ha->srb_mempool)
4004 goto fail_free_gid_list;
4005
4006 if (IS_P3P_TYPE(ha)) {
4007 /* Allocate cache for CT6 Ctx. */
4008 if (!ctx_cachep) {
4009 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4010 sizeof(struct ct6_dsd), 0,
4011 SLAB_HWCACHE_ALIGN, NULL);
4012 if (!ctx_cachep)
4013 goto fail_free_srb_mempool;
4014 }
4015 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4016 ctx_cachep);
4017 if (!ha->ctx_mempool)
4018 goto fail_free_srb_mempool;
4019 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4020 "ctx_cachep=%p ctx_mempool=%p.\n",
4021 ctx_cachep, ha->ctx_mempool);
4022 }
4023
4024 /* Get memory for cached NVRAM */
4025 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4026 if (!ha->nvram)
4027 goto fail_free_ctx_mempool;
4028
4029 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4030 ha->pdev->device);
4031 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4032 DMA_POOL_SIZE, 8, 0);
4033 if (!ha->s_dma_pool)
4034 goto fail_free_nvram;
4035
4036 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4037 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4038 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4039
4040 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
4041 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4042 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4043 if (!ha->dl_dma_pool) {
4044 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4045 "Failed to allocate memory for dl_dma_pool.\n");
4046 goto fail_s_dma_pool;
4047 }
4048
4049 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4050 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4051 if (!ha->fcp_cmnd_dma_pool) {
4052 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4053 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4054 goto fail_dl_dma_pool;
4055 }
4056
4057 if (ql2xenabledif) {
4058 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4059 struct dsd_dma *dsd, *nxt;
4060 uint i;
4061 /* Creata a DMA pool of buffers for DIF bundling */
4062 ha->dif_bundl_pool = dma_pool_create(name,
4063 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4064 if (!ha->dif_bundl_pool) {
4065 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4066 "%s: failed create dif_bundl_pool\n",
4067 __func__);
4068 goto fail_dif_bundl_dma_pool;
4069 }
4070
4071 INIT_LIST_HEAD(&ha->pool.good.head);
4072 INIT_LIST_HEAD(&ha->pool.unusable.head);
4073 ha->pool.good.count = 0;
4074 ha->pool.unusable.count = 0;
4075 for (i = 0; i < 128; i++) {
4076 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4077 if (!dsd) {
4078 ql_dbg_pci(ql_dbg_init, ha->pdev,
4079 0xe0ee, "%s: failed alloc dsd\n",
4080 __func__);
4081 return 1;
4082 }
4083 ha->dif_bundle_kallocs++;
4084
4085 dsd->dsd_addr = dma_pool_alloc(
4086 ha->dif_bundl_pool, GFP_ATOMIC,
4087 &dsd->dsd_list_dma);
4088 if (!dsd->dsd_addr) {
4089 ql_dbg_pci(ql_dbg_init, ha->pdev,
4090 0xe0ee,
4091 "%s: failed alloc ->dsd_addr\n",
4092 __func__);
4093 kfree(dsd);
4094 ha->dif_bundle_kallocs--;
4095 continue;
4096 }
4097 ha->dif_bundle_dma_allocs++;
4098
4099 /*
4100 * if DMA buffer crosses 4G boundary,
4101 * put it on bad list
4102 */
4103 if (MSD(dsd->dsd_list_dma) ^
4104 MSD(dsd->dsd_list_dma + bufsize)) {
4105 list_add_tail(&dsd->list,
4106 &ha->pool.unusable.head);
4107 ha->pool.unusable.count++;
4108 } else {
4109 list_add_tail(&dsd->list,
4110 &ha->pool.good.head);
4111 ha->pool.good.count++;
4112 }
4113 }
4114
4115 /* return the good ones back to the pool */
4116 list_for_each_entry_safe(dsd, nxt,
4117 &ha->pool.good.head, list) {
4118 list_del(&dsd->list);
4119 dma_pool_free(ha->dif_bundl_pool,
4120 dsd->dsd_addr, dsd->dsd_list_dma);
4121 ha->dif_bundle_dma_allocs--;
4122 kfree(dsd);
4123 ha->dif_bundle_kallocs--;
4124 }
4125
4126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4127 "%s: dif dma pool (good=%u unusable=%u)\n",
4128 __func__, ha->pool.good.count,
4129 ha->pool.unusable.count);
4130 }
4131
4132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4133 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4134 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4135 ha->dif_bundl_pool);
4136 }
4137
4138 /* Allocate memory for SNS commands */
4139 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4140 /* Get consistent memory allocated for SNS commands */
4141 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4142 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4143 if (!ha->sns_cmd)
4144 goto fail_dma_pool;
4145 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4146 "sns_cmd: %p.\n", ha->sns_cmd);
4147 } else {
4148 /* Get consistent memory allocated for MS IOCB */
4149 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4150 &ha->ms_iocb_dma);
4151 if (!ha->ms_iocb)
4152 goto fail_dma_pool;
4153 /* Get consistent memory allocated for CT SNS commands */
4154 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4155 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4156 if (!ha->ct_sns)
4157 goto fail_free_ms_iocb;
4158 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4159 "ms_iocb=%p ct_sns=%p.\n",
4160 ha->ms_iocb, ha->ct_sns);
4161 }
4162
4163 /* Allocate memory for request ring */
4164 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4165 if (!*req) {
4166 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4167 "Failed to allocate memory for req.\n");
4168 goto fail_req;
4169 }
4170 (*req)->length = req_len;
4171 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4172 ((*req)->length + 1) * sizeof(request_t),
4173 &(*req)->dma, GFP_KERNEL);
4174 if (!(*req)->ring) {
4175 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4176 "Failed to allocate memory for req_ring.\n");
4177 goto fail_req_ring;
4178 }
4179 /* Allocate memory for response ring */
4180 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4181 if (!*rsp) {
4182 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4183 "Failed to allocate memory for rsp.\n");
4184 goto fail_rsp;
4185 }
4186 (*rsp)->hw = ha;
4187 (*rsp)->length = rsp_len;
4188 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4189 ((*rsp)->length + 1) * sizeof(response_t),
4190 &(*rsp)->dma, GFP_KERNEL);
4191 if (!(*rsp)->ring) {
4192 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4193 "Failed to allocate memory for rsp_ring.\n");
4194 goto fail_rsp_ring;
4195 }
4196 (*req)->rsp = *rsp;
4197 (*rsp)->req = *req;
4198 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4199 "req=%p req->length=%d req->ring=%p rsp=%p "
4200 "rsp->length=%d rsp->ring=%p.\n",
4201 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4202 (*rsp)->ring);
4203 /* Allocate memory for NVRAM data for vports */
4204 if (ha->nvram_npiv_size) {
4205 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4206 sizeof(struct qla_npiv_entry),
4207 GFP_KERNEL);
4208 if (!ha->npiv_info) {
4209 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4210 "Failed to allocate memory for npiv_info.\n");
4211 goto fail_npiv_info;
4212 }
4213 } else
4214 ha->npiv_info = NULL;
4215
4216 /* Get consistent memory allocated for EX-INIT-CB. */
4217 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4218 IS_QLA28XX(ha)) {
4219 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4220 &ha->ex_init_cb_dma);
4221 if (!ha->ex_init_cb)
4222 goto fail_ex_init_cb;
4223 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4224 "ex_init_cb=%p.\n", ha->ex_init_cb);
4225 }
4226
4227 /* Get consistent memory allocated for Special Features-CB. */
4228 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4229 ha->sf_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4230 &ha->sf_init_cb_dma);
4231 if (!ha->sf_init_cb)
4232 goto fail_sf_init_cb;
4233 memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb));
4234 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4235 "sf_init_cb=%p.\n", ha->sf_init_cb);
4236 }
4237
4238 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4239
4240 /* Get consistent memory allocated for Async Port-Database. */
4241 if (!IS_FWI2_CAPABLE(ha)) {
4242 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4243 &ha->async_pd_dma);
4244 if (!ha->async_pd)
4245 goto fail_async_pd;
4246 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4247 "async_pd=%p.\n", ha->async_pd);
4248 }
4249
4250 INIT_LIST_HEAD(&ha->vp_list);
4251
4252 /* Allocate memory for our loop_id bitmap */
4253 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4254 sizeof(long),
4255 GFP_KERNEL);
4256 if (!ha->loop_id_map)
4257 goto fail_loop_id_map;
4258 else {
4259 qla2x00_set_reserved_loop_ids(ha);
4260 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4261 "loop_id_map=%p.\n", ha->loop_id_map);
4262 }
4263
4264 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4265 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4266 if (!ha->sfp_data) {
4267 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4268 "Unable to allocate memory for SFP read-data.\n");
4269 goto fail_sfp_data;
4270 }
4271
4272 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4273 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4274 GFP_KERNEL);
4275 if (!ha->flt) {
4276 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4277 "Unable to allocate memory for FLT.\n");
4278 goto fail_flt_buffer;
4279 }
4280
4281 return 0;
4282
4283 fail_flt_buffer:
4284 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4285 ha->sfp_data, ha->sfp_data_dma);
4286 fail_sfp_data:
4287 kfree(ha->loop_id_map);
4288 fail_loop_id_map:
4289 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4290 fail_async_pd:
4291 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4292 fail_sf_init_cb:
4293 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4294 fail_ex_init_cb:
4295 kfree(ha->npiv_info);
4296 fail_npiv_info:
4297 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4298 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4299 (*rsp)->ring = NULL;
4300 (*rsp)->dma = 0;
4301 fail_rsp_ring:
4302 kfree(*rsp);
4303 *rsp = NULL;
4304 fail_rsp:
4305 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4306 sizeof(request_t), (*req)->ring, (*req)->dma);
4307 (*req)->ring = NULL;
4308 (*req)->dma = 0;
4309 fail_req_ring:
4310 kfree(*req);
4311 *req = NULL;
4312 fail_req:
4313 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4314 ha->ct_sns, ha->ct_sns_dma);
4315 ha->ct_sns = NULL;
4316 ha->ct_sns_dma = 0;
4317 fail_free_ms_iocb:
4318 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4319 ha->ms_iocb = NULL;
4320 ha->ms_iocb_dma = 0;
4321
4322 if (ha->sns_cmd)
4323 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4324 ha->sns_cmd, ha->sns_cmd_dma);
4325 fail_dma_pool:
4326 if (ql2xenabledif) {
4327 struct dsd_dma *dsd, *nxt;
4328
4329 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4330 list) {
4331 list_del(&dsd->list);
4332 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4333 dsd->dsd_list_dma);
4334 ha->dif_bundle_dma_allocs--;
4335 kfree(dsd);
4336 ha->dif_bundle_kallocs--;
4337 ha->pool.unusable.count--;
4338 }
4339 dma_pool_destroy(ha->dif_bundl_pool);
4340 ha->dif_bundl_pool = NULL;
4341 }
4342
4343 fail_dif_bundl_dma_pool:
4344 if (IS_QLA82XX(ha) || ql2xenabledif) {
4345 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4346 ha->fcp_cmnd_dma_pool = NULL;
4347 }
4348 fail_dl_dma_pool:
4349 if (IS_QLA82XX(ha) || ql2xenabledif) {
4350 dma_pool_destroy(ha->dl_dma_pool);
4351 ha->dl_dma_pool = NULL;
4352 }
4353 fail_s_dma_pool:
4354 dma_pool_destroy(ha->s_dma_pool);
4355 ha->s_dma_pool = NULL;
4356 fail_free_nvram:
4357 kfree(ha->nvram);
4358 ha->nvram = NULL;
4359 fail_free_ctx_mempool:
4360 mempool_destroy(ha->ctx_mempool);
4361 ha->ctx_mempool = NULL;
4362 fail_free_srb_mempool:
4363 mempool_destroy(ha->srb_mempool);
4364 ha->srb_mempool = NULL;
4365 fail_free_gid_list:
4366 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4367 ha->gid_list,
4368 ha->gid_list_dma);
4369 ha->gid_list = NULL;
4370 ha->gid_list_dma = 0;
4371 fail_free_tgt_mem:
4372 qlt_mem_free(ha);
4373 fail_free_init_cb:
4374 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4375 ha->init_cb_dma);
4376 ha->init_cb = NULL;
4377 ha->init_cb_dma = 0;
4378 fail:
4379 ql_log(ql_log_fatal, NULL, 0x0030,
4380 "Memory allocation failure.\n");
4381 return -ENOMEM;
4382 }
4383
4384 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4385 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4386 {
4387 int rval;
4388 uint16_t size, max_cnt;
4389 uint32_t temp;
4390 struct qla_hw_data *ha = vha->hw;
4391
4392 /* Return if we don't need to alloacate any extended logins */
4393 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4394 return QLA_SUCCESS;
4395
4396 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4397 return QLA_SUCCESS;
4398
4399 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4400 max_cnt = 0;
4401 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4402 if (rval != QLA_SUCCESS) {
4403 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4404 "Failed to get exlogin status.\n");
4405 return rval;
4406 }
4407
4408 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4409 temp *= size;
4410
4411 if (temp != ha->exlogin_size) {
4412 qla2x00_free_exlogin_buffer(ha);
4413 ha->exlogin_size = temp;
4414
4415 ql_log(ql_log_info, vha, 0xd024,
4416 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4417 max_cnt, size, temp);
4418
4419 ql_log(ql_log_info, vha, 0xd025,
4420 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4421
4422 /* Get consistent memory for extended logins */
4423 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4424 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4425 if (!ha->exlogin_buf) {
4426 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4427 "Failed to allocate memory for exlogin_buf_dma.\n");
4428 return -ENOMEM;
4429 }
4430 }
4431
4432 /* Now configure the dma buffer */
4433 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4434 if (rval) {
4435 ql_log(ql_log_fatal, vha, 0xd033,
4436 "Setup extended login buffer ****FAILED****.\n");
4437 qla2x00_free_exlogin_buffer(ha);
4438 }
4439
4440 return rval;
4441 }
4442
4443 /*
4444 * qla2x00_free_exlogin_buffer
4445 *
4446 * Input:
4447 * ha = adapter block pointer
4448 */
4449 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4450 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4451 {
4452 if (ha->exlogin_buf) {
4453 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4454 ha->exlogin_buf, ha->exlogin_buf_dma);
4455 ha->exlogin_buf = NULL;
4456 ha->exlogin_size = 0;
4457 }
4458 }
4459
4460 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4461 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4462 {
4463 u32 temp;
4464 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4465 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4466
4467 if (max_cnt > vha->hw->max_exchg)
4468 max_cnt = vha->hw->max_exchg;
4469
4470 if (qla_ini_mode_enabled(vha)) {
4471 if (vha->ql2xiniexchg > max_cnt)
4472 vha->ql2xiniexchg = max_cnt;
4473
4474 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4475 *ret_cnt = vha->ql2xiniexchg;
4476
4477 } else if (qla_tgt_mode_enabled(vha)) {
4478 if (vha->ql2xexchoffld > max_cnt) {
4479 vha->ql2xexchoffld = max_cnt;
4480 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4481 }
4482
4483 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4484 *ret_cnt = vha->ql2xexchoffld;
4485 } else if (qla_dual_mode_enabled(vha)) {
4486 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4487 if (temp > max_cnt) {
4488 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4489 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4490 temp = max_cnt;
4491 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4492 }
4493
4494 if (temp > FW_DEF_EXCHANGES_CNT)
4495 *ret_cnt = temp;
4496 }
4497 }
4498
4499 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4500 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4501 {
4502 int rval;
4503 u16 size, max_cnt;
4504 u32 actual_cnt, totsz;
4505 struct qla_hw_data *ha = vha->hw;
4506
4507 if (!ha->flags.exchoffld_enabled)
4508 return QLA_SUCCESS;
4509
4510 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4511 return QLA_SUCCESS;
4512
4513 max_cnt = 0;
4514 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4515 if (rval != QLA_SUCCESS) {
4516 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4517 "Failed to get exlogin status.\n");
4518 return rval;
4519 }
4520
4521 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4522 ql_log(ql_log_info, vha, 0xd014,
4523 "Actual exchange offload count: %d.\n", actual_cnt);
4524
4525 totsz = actual_cnt * size;
4526
4527 if (totsz != ha->exchoffld_size) {
4528 qla2x00_free_exchoffld_buffer(ha);
4529 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4530 ha->exchoffld_size = 0;
4531 ha->flags.exchoffld_enabled = 0;
4532 return QLA_SUCCESS;
4533 }
4534
4535 ha->exchoffld_size = totsz;
4536
4537 ql_log(ql_log_info, vha, 0xd016,
4538 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4539 max_cnt, actual_cnt, size, totsz);
4540
4541 ql_log(ql_log_info, vha, 0xd017,
4542 "Exchange Buffers requested size = 0x%x\n",
4543 ha->exchoffld_size);
4544
4545 /* Get consistent memory for extended logins */
4546 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4547 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4548 if (!ha->exchoffld_buf) {
4549 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4550 "Failed to allocate memory for Exchange Offload.\n");
4551
4552 if (ha->max_exchg >
4553 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4554 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4555 } else if (ha->max_exchg >
4556 (FW_DEF_EXCHANGES_CNT + 512)) {
4557 ha->max_exchg -= 512;
4558 } else {
4559 ha->flags.exchoffld_enabled = 0;
4560 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4561 "Disabling Exchange offload due to lack of memory\n");
4562 }
4563 ha->exchoffld_size = 0;
4564
4565 return -ENOMEM;
4566 }
4567 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4568 /* pathological case */
4569 qla2x00_free_exchoffld_buffer(ha);
4570 ha->exchoffld_size = 0;
4571 ha->flags.exchoffld_enabled = 0;
4572 ql_log(ql_log_info, vha, 0xd016,
4573 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4574 ha->exchoffld_size, actual_cnt, size, totsz);
4575 return 0;
4576 }
4577
4578 /* Now configure the dma buffer */
4579 rval = qla_set_exchoffld_mem_cfg(vha);
4580 if (rval) {
4581 ql_log(ql_log_fatal, vha, 0xd02e,
4582 "Setup exchange offload buffer ****FAILED****.\n");
4583 qla2x00_free_exchoffld_buffer(ha);
4584 } else {
4585 /* re-adjust number of target exchange */
4586 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4587
4588 if (qla_ini_mode_enabled(vha))
4589 icb->exchange_count = 0;
4590 else
4591 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4592 }
4593
4594 return rval;
4595 }
4596
4597 /*
4598 * qla2x00_free_exchoffld_buffer
4599 *
4600 * Input:
4601 * ha = adapter block pointer
4602 */
4603 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4604 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4605 {
4606 if (ha->exchoffld_buf) {
4607 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4608 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4609 ha->exchoffld_buf = NULL;
4610 ha->exchoffld_size = 0;
4611 }
4612 }
4613
4614 /*
4615 * qla2x00_free_fw_dump
4616 * Frees fw dump stuff.
4617 *
4618 * Input:
4619 * ha = adapter block pointer
4620 */
4621 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4622 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4623 {
4624 struct fwdt *fwdt = ha->fwdt;
4625 uint j;
4626
4627 if (ha->fce)
4628 dma_free_coherent(&ha->pdev->dev,
4629 FCE_SIZE, ha->fce, ha->fce_dma);
4630
4631 if (ha->eft)
4632 dma_free_coherent(&ha->pdev->dev,
4633 EFT_SIZE, ha->eft, ha->eft_dma);
4634
4635 if (ha->fw_dump)
4636 vfree(ha->fw_dump);
4637
4638 ha->fce = NULL;
4639 ha->fce_dma = 0;
4640 ha->flags.fce_enabled = 0;
4641 ha->eft = NULL;
4642 ha->eft_dma = 0;
4643 ha->fw_dumped = false;
4644 ha->fw_dump_cap_flags = 0;
4645 ha->fw_dump_reading = 0;
4646 ha->fw_dump = NULL;
4647 ha->fw_dump_len = 0;
4648
4649 for (j = 0; j < 2; j++, fwdt++) {
4650 if (fwdt->template)
4651 vfree(fwdt->template);
4652 fwdt->template = NULL;
4653 fwdt->length = 0;
4654 }
4655 }
4656
4657 /*
4658 * qla2x00_mem_free
4659 * Frees all adapter allocated memory.
4660 *
4661 * Input:
4662 * ha = adapter block pointer.
4663 */
4664 static void
qla2x00_mem_free(struct qla_hw_data * ha)4665 qla2x00_mem_free(struct qla_hw_data *ha)
4666 {
4667 qla2x00_free_fw_dump(ha);
4668
4669 if (ha->mctp_dump)
4670 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4671 ha->mctp_dump_dma);
4672 ha->mctp_dump = NULL;
4673
4674 mempool_destroy(ha->srb_mempool);
4675 ha->srb_mempool = NULL;
4676
4677 if (ha->dcbx_tlv)
4678 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4679 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4680 ha->dcbx_tlv = NULL;
4681
4682 if (ha->xgmac_data)
4683 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4684 ha->xgmac_data, ha->xgmac_data_dma);
4685 ha->xgmac_data = NULL;
4686
4687 if (ha->sns_cmd)
4688 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4689 ha->sns_cmd, ha->sns_cmd_dma);
4690 ha->sns_cmd = NULL;
4691 ha->sns_cmd_dma = 0;
4692
4693 if (ha->ct_sns)
4694 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4695 ha->ct_sns, ha->ct_sns_dma);
4696 ha->ct_sns = NULL;
4697 ha->ct_sns_dma = 0;
4698
4699 if (ha->sfp_data)
4700 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4701 ha->sfp_data_dma);
4702 ha->sfp_data = NULL;
4703
4704 if (ha->flt)
4705 dma_free_coherent(&ha->pdev->dev,
4706 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4707 ha->flt, ha->flt_dma);
4708 ha->flt = NULL;
4709 ha->flt_dma = 0;
4710
4711 if (ha->ms_iocb)
4712 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4713 ha->ms_iocb = NULL;
4714 ha->ms_iocb_dma = 0;
4715
4716 if (ha->sf_init_cb)
4717 dma_pool_free(ha->s_dma_pool,
4718 ha->sf_init_cb, ha->sf_init_cb_dma);
4719
4720 if (ha->ex_init_cb)
4721 dma_pool_free(ha->s_dma_pool,
4722 ha->ex_init_cb, ha->ex_init_cb_dma);
4723 ha->ex_init_cb = NULL;
4724 ha->ex_init_cb_dma = 0;
4725
4726 if (ha->async_pd)
4727 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4728 ha->async_pd = NULL;
4729 ha->async_pd_dma = 0;
4730
4731 dma_pool_destroy(ha->s_dma_pool);
4732 ha->s_dma_pool = NULL;
4733
4734 if (ha->gid_list)
4735 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4736 ha->gid_list, ha->gid_list_dma);
4737 ha->gid_list = NULL;
4738 ha->gid_list_dma = 0;
4739
4740 if (IS_QLA82XX(ha)) {
4741 if (!list_empty(&ha->gbl_dsd_list)) {
4742 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4743
4744 /* clean up allocated prev pool */
4745 list_for_each_entry_safe(dsd_ptr,
4746 tdsd_ptr, &ha->gbl_dsd_list, list) {
4747 dma_pool_free(ha->dl_dma_pool,
4748 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4749 list_del(&dsd_ptr->list);
4750 kfree(dsd_ptr);
4751 }
4752 }
4753 }
4754
4755 dma_pool_destroy(ha->dl_dma_pool);
4756 ha->dl_dma_pool = NULL;
4757
4758 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4759 ha->fcp_cmnd_dma_pool = NULL;
4760
4761 mempool_destroy(ha->ctx_mempool);
4762 ha->ctx_mempool = NULL;
4763
4764 if (ql2xenabledif && ha->dif_bundl_pool) {
4765 struct dsd_dma *dsd, *nxt;
4766
4767 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4768 list) {
4769 list_del(&dsd->list);
4770 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4771 dsd->dsd_list_dma);
4772 ha->dif_bundle_dma_allocs--;
4773 kfree(dsd);
4774 ha->dif_bundle_kallocs--;
4775 ha->pool.unusable.count--;
4776 }
4777 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4778 list_del(&dsd->list);
4779 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4780 dsd->dsd_list_dma);
4781 ha->dif_bundle_dma_allocs--;
4782 kfree(dsd);
4783 ha->dif_bundle_kallocs--;
4784 }
4785 }
4786
4787 dma_pool_destroy(ha->dif_bundl_pool);
4788 ha->dif_bundl_pool = NULL;
4789
4790 qlt_mem_free(ha);
4791
4792 if (ha->init_cb)
4793 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4794 ha->init_cb, ha->init_cb_dma);
4795 ha->init_cb = NULL;
4796 ha->init_cb_dma = 0;
4797
4798 vfree(ha->optrom_buffer);
4799 ha->optrom_buffer = NULL;
4800 kfree(ha->nvram);
4801 ha->nvram = NULL;
4802 kfree(ha->npiv_info);
4803 ha->npiv_info = NULL;
4804 kfree(ha->swl);
4805 ha->swl = NULL;
4806 kfree(ha->loop_id_map);
4807 ha->sf_init_cb = NULL;
4808 ha->sf_init_cb_dma = 0;
4809 ha->loop_id_map = NULL;
4810 }
4811
qla2x00_create_host(struct scsi_host_template * sht,struct qla_hw_data * ha)4812 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4813 struct qla_hw_data *ha)
4814 {
4815 struct Scsi_Host *host;
4816 struct scsi_qla_host *vha = NULL;
4817
4818 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4819 if (!host) {
4820 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4821 "Failed to allocate host from the scsi layer, aborting.\n");
4822 return NULL;
4823 }
4824
4825 /* Clear our data area */
4826 vha = shost_priv(host);
4827 memset(vha, 0, sizeof(scsi_qla_host_t));
4828
4829 vha->host = host;
4830 vha->host_no = host->host_no;
4831 vha->hw = ha;
4832
4833 vha->qlini_mode = ql2x_ini_mode;
4834 vha->ql2xexchoffld = ql2xexchoffld;
4835 vha->ql2xiniexchg = ql2xiniexchg;
4836
4837 INIT_LIST_HEAD(&vha->vp_fcports);
4838 INIT_LIST_HEAD(&vha->work_list);
4839 INIT_LIST_HEAD(&vha->list);
4840 INIT_LIST_HEAD(&vha->qla_cmd_list);
4841 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4842 INIT_LIST_HEAD(&vha->logo_list);
4843 INIT_LIST_HEAD(&vha->plogi_ack_list);
4844 INIT_LIST_HEAD(&vha->qp_list);
4845 INIT_LIST_HEAD(&vha->gnl.fcports);
4846 INIT_LIST_HEAD(&vha->gpnid_list);
4847 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4848
4849 INIT_LIST_HEAD(&vha->purex_list.head);
4850 spin_lock_init(&vha->purex_list.lock);
4851
4852 spin_lock_init(&vha->work_lock);
4853 spin_lock_init(&vha->cmd_list_lock);
4854 init_waitqueue_head(&vha->fcport_waitQ);
4855 init_waitqueue_head(&vha->vref_waitq);
4856
4857 vha->gnl.size = sizeof(struct get_name_list_extended) *
4858 (ha->max_loop_id + 1);
4859 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4860 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4861 if (!vha->gnl.l) {
4862 ql_log(ql_log_fatal, vha, 0xd04a,
4863 "Alloc failed for name list.\n");
4864 scsi_host_put(vha->host);
4865 return NULL;
4866 }
4867
4868 /* todo: what about ext login? */
4869 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4870 vha->scan.l = vmalloc(vha->scan.size);
4871 if (!vha->scan.l) {
4872 ql_log(ql_log_fatal, vha, 0xd04a,
4873 "Alloc failed for scan database.\n");
4874 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4875 vha->gnl.l, vha->gnl.ldma);
4876 vha->gnl.l = NULL;
4877 scsi_host_put(vha->host);
4878 return NULL;
4879 }
4880 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
4881
4882 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no);
4883 ql_dbg(ql_dbg_init, vha, 0x0041,
4884 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4885 vha->host, vha->hw, vha,
4886 dev_name(&(ha->pdev->dev)));
4887
4888 return vha;
4889 }
4890
4891 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)4892 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4893 {
4894 struct qla_work_evt *e;
4895 uint8_t bail;
4896
4897 if (test_bit(UNLOADING, &vha->dpc_flags))
4898 return NULL;
4899
4900 QLA_VHA_MARK_BUSY(vha, bail);
4901 if (bail)
4902 return NULL;
4903
4904 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4905 if (!e) {
4906 QLA_VHA_MARK_NOT_BUSY(vha);
4907 return NULL;
4908 }
4909
4910 INIT_LIST_HEAD(&e->list);
4911 e->type = type;
4912 e->flags = QLA_EVT_FLAG_FREE;
4913 return e;
4914 }
4915
4916 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)4917 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4918 {
4919 unsigned long flags;
4920 bool q = false;
4921
4922 spin_lock_irqsave(&vha->work_lock, flags);
4923 list_add_tail(&e->list, &vha->work_list);
4924
4925 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4926 q = true;
4927
4928 spin_unlock_irqrestore(&vha->work_lock, flags);
4929
4930 if (q)
4931 queue_work(vha->hw->wq, &vha->iocb_work);
4932
4933 return QLA_SUCCESS;
4934 }
4935
4936 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)4937 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4938 u32 data)
4939 {
4940 struct qla_work_evt *e;
4941
4942 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4943 if (!e)
4944 return QLA_FUNCTION_FAILED;
4945
4946 e->u.aen.code = code;
4947 e->u.aen.data = data;
4948 return qla2x00_post_work(vha, e);
4949 }
4950
4951 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)4952 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4953 {
4954 struct qla_work_evt *e;
4955
4956 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4957 if (!e)
4958 return QLA_FUNCTION_FAILED;
4959
4960 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4961 return qla2x00_post_work(vha, e);
4962 }
4963
4964 #define qla2x00_post_async_work(name, type) \
4965 int qla2x00_post_async_##name##_work( \
4966 struct scsi_qla_host *vha, \
4967 fc_port_t *fcport, uint16_t *data) \
4968 { \
4969 struct qla_work_evt *e; \
4970 \
4971 e = qla2x00_alloc_work(vha, type); \
4972 if (!e) \
4973 return QLA_FUNCTION_FAILED; \
4974 \
4975 e->u.logio.fcport = fcport; \
4976 if (data) { \
4977 e->u.logio.data[0] = data[0]; \
4978 e->u.logio.data[1] = data[1]; \
4979 } \
4980 fcport->flags |= FCF_ASYNC_ACTIVE; \
4981 return qla2x00_post_work(vha, e); \
4982 }
4983
4984 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4985 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4986 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4987 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4988 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
4989
4990 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)4991 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4992 {
4993 struct qla_work_evt *e;
4994
4995 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4996 if (!e)
4997 return QLA_FUNCTION_FAILED;
4998
4999 e->u.uevent.code = code;
5000 return qla2x00_post_work(vha, e);
5001 }
5002
5003 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5004 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5005 {
5006 char event_string[40];
5007 char *envp[] = { event_string, NULL };
5008
5009 switch (code) {
5010 case QLA_UEVENT_CODE_FW_DUMP:
5011 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5012 vha->host_no);
5013 break;
5014 default:
5015 /* do nothing */
5016 break;
5017 }
5018 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5019 }
5020
5021 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5022 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5023 uint32_t *data, int cnt)
5024 {
5025 struct qla_work_evt *e;
5026
5027 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5028 if (!e)
5029 return QLA_FUNCTION_FAILED;
5030
5031 e->u.aenfx.evtcode = evtcode;
5032 e->u.aenfx.count = cnt;
5033 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5034 return qla2x00_post_work(vha, e);
5035 }
5036
qla24xx_sched_upd_fcport(fc_port_t * fcport)5037 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5038 {
5039 unsigned long flags;
5040
5041 if (IS_SW_RESV_ADDR(fcport->d_id))
5042 return;
5043
5044 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5045 if (fcport->disc_state == DSC_UPD_FCPORT) {
5046 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5047 return;
5048 }
5049 fcport->jiffies_at_registration = jiffies;
5050 fcport->sec_since_registration = 0;
5051 fcport->next_disc_state = DSC_DELETED;
5052 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5053 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5054
5055 queue_work(system_unbound_wq, &fcport->reg_work);
5056 }
5057
5058 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5059 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5060 {
5061 unsigned long flags;
5062 fc_port_t *fcport = NULL, *tfcp;
5063 struct qlt_plogi_ack_t *pla =
5064 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5065 uint8_t free_fcport = 0;
5066
5067 ql_dbg(ql_dbg_disc, vha, 0xffff,
5068 "%s %d %8phC enter\n",
5069 __func__, __LINE__, e->u.new_sess.port_name);
5070
5071 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5072 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5073 if (fcport) {
5074 fcport->d_id = e->u.new_sess.id;
5075 if (pla) {
5076 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5077 memcpy(fcport->node_name,
5078 pla->iocb.u.isp24.u.plogi.node_name,
5079 WWN_SIZE);
5080 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5081 /* we took an extra ref_count to prevent PLOGI ACK when
5082 * fcport/sess has not been created.
5083 */
5084 pla->ref_count--;
5085 }
5086 } else {
5087 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5088 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5089 if (fcport) {
5090 fcport->d_id = e->u.new_sess.id;
5091 fcport->flags |= FCF_FABRIC_DEVICE;
5092 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5093
5094 memcpy(fcport->port_name, e->u.new_sess.port_name,
5095 WWN_SIZE);
5096
5097 fcport->fc4_type = e->u.new_sess.fc4_type;
5098 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5099 fcport->dm_login_expire = jiffies +
5100 QLA_N2N_WAIT_TIME * HZ;
5101 fcport->fc4_type = FS_FC4TYPE_FCP;
5102 fcport->n2n_flag = 1;
5103 if (vha->flags.nvme_enabled)
5104 fcport->fc4_type |= FS_FC4TYPE_NVME;
5105 }
5106
5107 } else {
5108 ql_dbg(ql_dbg_disc, vha, 0xffff,
5109 "%s %8phC mem alloc fail.\n",
5110 __func__, e->u.new_sess.port_name);
5111
5112 if (pla) {
5113 list_del(&pla->list);
5114 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5115 }
5116 return;
5117 }
5118
5119 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5120 /* search again to make sure no one else got ahead */
5121 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5122 e->u.new_sess.port_name, 1);
5123 if (tfcp) {
5124 /* should rarily happen */
5125 ql_dbg(ql_dbg_disc, vha, 0xffff,
5126 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5127 __func__, tfcp->port_name, tfcp->disc_state,
5128 tfcp->fw_login_state);
5129
5130 free_fcport = 1;
5131 } else {
5132 list_add_tail(&fcport->list, &vha->vp_fcports);
5133
5134 }
5135 if (pla) {
5136 qlt_plogi_ack_link(vha, pla, fcport,
5137 QLT_PLOGI_LINK_SAME_WWN);
5138 pla->ref_count--;
5139 }
5140 }
5141 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5142
5143 if (fcport) {
5144 fcport->id_changed = 1;
5145 fcport->scan_state = QLA_FCPORT_FOUND;
5146 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5147 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5148
5149 if (pla) {
5150 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5151 u16 wd3_lo;
5152
5153 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5154 fcport->local = 0;
5155 fcport->loop_id =
5156 le16_to_cpu(
5157 pla->iocb.u.isp24.nport_handle);
5158 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5159 wd3_lo =
5160 le16_to_cpu(
5161 pla->iocb.u.isp24.u.prli.wd3_lo);
5162
5163 if (wd3_lo & BIT_7)
5164 fcport->conf_compl_supported = 1;
5165
5166 if ((wd3_lo & BIT_4) == 0)
5167 fcport->port_type = FCT_INITIATOR;
5168 else
5169 fcport->port_type = FCT_TARGET;
5170 }
5171 qlt_plogi_ack_unref(vha, pla);
5172 } else {
5173 fc_port_t *dfcp = NULL;
5174
5175 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5176 tfcp = qla2x00_find_fcport_by_nportid(vha,
5177 &e->u.new_sess.id, 1);
5178 if (tfcp && (tfcp != fcport)) {
5179 /*
5180 * We have a conflict fcport with same NportID.
5181 */
5182 ql_dbg(ql_dbg_disc, vha, 0xffff,
5183 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5184 __func__, tfcp->port_name, tfcp->disc_state,
5185 tfcp->fw_login_state);
5186
5187 switch (tfcp->disc_state) {
5188 case DSC_DELETED:
5189 break;
5190 case DSC_DELETE_PEND:
5191 fcport->login_pause = 1;
5192 tfcp->conflict = fcport;
5193 break;
5194 default:
5195 fcport->login_pause = 1;
5196 tfcp->conflict = fcport;
5197 dfcp = tfcp;
5198 break;
5199 }
5200 }
5201 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5202 if (dfcp)
5203 qlt_schedule_sess_for_deletion(tfcp);
5204
5205 if (N2N_TOPO(vha->hw)) {
5206 fcport->flags &= ~FCF_FABRIC_DEVICE;
5207 fcport->keep_nport_handle = 1;
5208 if (vha->flags.nvme_enabled) {
5209 fcport->fc4_type =
5210 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5211 fcport->n2n_flag = 1;
5212 }
5213 fcport->fw_login_state = 0;
5214
5215 schedule_delayed_work(&vha->scan.scan_work, 5);
5216 } else {
5217 qla24xx_fcport_handle_login(vha, fcport);
5218 }
5219 }
5220 }
5221
5222 if (free_fcport) {
5223 qla2x00_free_fcport(fcport);
5224 if (pla) {
5225 list_del(&pla->list);
5226 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5227 }
5228 }
5229 }
5230
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5231 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5232 {
5233 struct srb *sp = e->u.iosb.sp;
5234 int rval;
5235
5236 rval = qla2x00_start_sp(sp);
5237 if (rval != QLA_SUCCESS) {
5238 ql_dbg(ql_dbg_disc, vha, 0x2043,
5239 "%s: %s: Re-issue IOCB failed (%d).\n",
5240 __func__, sp->name, rval);
5241 qla24xx_sp_unmap(vha, sp);
5242 }
5243 }
5244
5245 void
qla2x00_do_work(struct scsi_qla_host * vha)5246 qla2x00_do_work(struct scsi_qla_host *vha)
5247 {
5248 struct qla_work_evt *e, *tmp;
5249 unsigned long flags;
5250 LIST_HEAD(work);
5251 int rc;
5252
5253 spin_lock_irqsave(&vha->work_lock, flags);
5254 list_splice_init(&vha->work_list, &work);
5255 spin_unlock_irqrestore(&vha->work_lock, flags);
5256
5257 list_for_each_entry_safe(e, tmp, &work, list) {
5258 rc = QLA_SUCCESS;
5259 switch (e->type) {
5260 case QLA_EVT_AEN:
5261 fc_host_post_event(vha->host, fc_get_event_number(),
5262 e->u.aen.code, e->u.aen.data);
5263 break;
5264 case QLA_EVT_IDC_ACK:
5265 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5266 break;
5267 case QLA_EVT_ASYNC_LOGIN:
5268 qla2x00_async_login(vha, e->u.logio.fcport,
5269 e->u.logio.data);
5270 break;
5271 case QLA_EVT_ASYNC_LOGOUT:
5272 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5273 break;
5274 case QLA_EVT_ASYNC_ADISC:
5275 qla2x00_async_adisc(vha, e->u.logio.fcport,
5276 e->u.logio.data);
5277 break;
5278 case QLA_EVT_UEVENT:
5279 qla2x00_uevent_emit(vha, e->u.uevent.code);
5280 break;
5281 case QLA_EVT_AENFX:
5282 qlafx00_process_aen(vha, e);
5283 break;
5284 case QLA_EVT_GPNID:
5285 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5286 break;
5287 case QLA_EVT_UNMAP:
5288 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5289 break;
5290 case QLA_EVT_RELOGIN:
5291 qla2x00_relogin(vha);
5292 break;
5293 case QLA_EVT_NEW_SESS:
5294 qla24xx_create_new_sess(vha, e);
5295 break;
5296 case QLA_EVT_GPDB:
5297 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5298 e->u.fcport.opt);
5299 break;
5300 case QLA_EVT_PRLI:
5301 qla24xx_async_prli(vha, e->u.fcport.fcport);
5302 break;
5303 case QLA_EVT_GPSC:
5304 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5305 break;
5306 case QLA_EVT_GNL:
5307 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5308 break;
5309 case QLA_EVT_NACK:
5310 qla24xx_do_nack_work(vha, e);
5311 break;
5312 case QLA_EVT_ASYNC_PRLO:
5313 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5314 break;
5315 case QLA_EVT_ASYNC_PRLO_DONE:
5316 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5317 e->u.logio.data);
5318 break;
5319 case QLA_EVT_GPNFT:
5320 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5321 e->u.gpnft.sp);
5322 break;
5323 case QLA_EVT_GPNFT_DONE:
5324 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5325 break;
5326 case QLA_EVT_GNNFT_DONE:
5327 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5328 break;
5329 case QLA_EVT_GNNID:
5330 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5331 break;
5332 case QLA_EVT_GFPNID:
5333 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5334 break;
5335 case QLA_EVT_SP_RETRY:
5336 qla_sp_retry(vha, e);
5337 break;
5338 case QLA_EVT_IIDMA:
5339 qla_do_iidma_work(vha, e->u.fcport.fcport);
5340 break;
5341 case QLA_EVT_ELS_PLOGI:
5342 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5343 e->u.fcport.fcport, false);
5344 break;
5345 }
5346
5347 if (rc == EAGAIN) {
5348 /* put 'work' at head of 'vha->work_list' */
5349 spin_lock_irqsave(&vha->work_lock, flags);
5350 list_splice(&work, &vha->work_list);
5351 spin_unlock_irqrestore(&vha->work_lock, flags);
5352 break;
5353 }
5354 list_del_init(&e->list);
5355 if (e->flags & QLA_EVT_FLAG_FREE)
5356 kfree(e);
5357
5358 /* For each work completed decrement vha ref count */
5359 QLA_VHA_MARK_NOT_BUSY(vha);
5360 }
5361 }
5362
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5363 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5364 {
5365 struct qla_work_evt *e;
5366
5367 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5368
5369 if (!e) {
5370 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5371 return QLA_FUNCTION_FAILED;
5372 }
5373
5374 return qla2x00_post_work(vha, e);
5375 }
5376
5377 /* Relogins all the fcports of a vport
5378 * Context: dpc thread
5379 */
qla2x00_relogin(struct scsi_qla_host * vha)5380 void qla2x00_relogin(struct scsi_qla_host *vha)
5381 {
5382 fc_port_t *fcport;
5383 int status, relogin_needed = 0;
5384 struct event_arg ea;
5385
5386 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5387 /*
5388 * If the port is not ONLINE then try to login
5389 * to it if we haven't run out of retries.
5390 */
5391 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5392 fcport->login_retry) {
5393 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5394 fcport->disc_state == DSC_LOGIN_COMPLETE)
5395 continue;
5396
5397 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5398 fcport->disc_state == DSC_DELETE_PEND) {
5399 relogin_needed = 1;
5400 } else {
5401 if (vha->hw->current_topology != ISP_CFG_NL) {
5402 memset(&ea, 0, sizeof(ea));
5403 ea.fcport = fcport;
5404 qla24xx_handle_relogin_event(vha, &ea);
5405 } else if (vha->hw->current_topology ==
5406 ISP_CFG_NL) {
5407 fcport->login_retry--;
5408 status =
5409 qla2x00_local_device_login(vha,
5410 fcport);
5411 if (status == QLA_SUCCESS) {
5412 fcport->old_loop_id =
5413 fcport->loop_id;
5414 ql_dbg(ql_dbg_disc, vha, 0x2003,
5415 "Port login OK: logged in ID 0x%x.\n",
5416 fcport->loop_id);
5417 qla2x00_update_fcport
5418 (vha, fcport);
5419 } else if (status == 1) {
5420 set_bit(RELOGIN_NEEDED,
5421 &vha->dpc_flags);
5422 /* retry the login again */
5423 ql_dbg(ql_dbg_disc, vha, 0x2007,
5424 "Retrying %d login again loop_id 0x%x.\n",
5425 fcport->login_retry,
5426 fcport->loop_id);
5427 } else {
5428 fcport->login_retry = 0;
5429 }
5430
5431 if (fcport->login_retry == 0 &&
5432 status != QLA_SUCCESS)
5433 qla2x00_clear_loop_id(fcport);
5434 }
5435 }
5436 }
5437 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5438 break;
5439 }
5440
5441 if (relogin_needed)
5442 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5443
5444 ql_dbg(ql_dbg_disc, vha, 0x400e,
5445 "Relogin end.\n");
5446 }
5447
5448 /* Schedule work on any of the dpc-workqueues */
5449 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5450 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5451 {
5452 struct qla_hw_data *ha = base_vha->hw;
5453
5454 switch (work_code) {
5455 case MBA_IDC_AEN: /* 0x8200 */
5456 if (ha->dpc_lp_wq)
5457 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5458 break;
5459
5460 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5461 if (!ha->flags.nic_core_reset_hdlr_active) {
5462 if (ha->dpc_hp_wq)
5463 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5464 } else
5465 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5466 "NIC Core reset is already active. Skip "
5467 "scheduling it again.\n");
5468 break;
5469 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5470 if (ha->dpc_hp_wq)
5471 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5472 break;
5473 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5474 if (ha->dpc_hp_wq)
5475 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5476 break;
5477 default:
5478 ql_log(ql_log_warn, base_vha, 0xb05f,
5479 "Unknown work-code=0x%x.\n", work_code);
5480 }
5481
5482 return;
5483 }
5484
5485 /* Work: Perform NIC Core Unrecoverable state handling */
5486 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5487 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5488 {
5489 struct qla_hw_data *ha =
5490 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5491 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5492 uint32_t dev_state = 0;
5493
5494 qla83xx_idc_lock(base_vha, 0);
5495 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5496 qla83xx_reset_ownership(base_vha);
5497 if (ha->flags.nic_core_reset_owner) {
5498 ha->flags.nic_core_reset_owner = 0;
5499 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5500 QLA8XXX_DEV_FAILED);
5501 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5502 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5503 }
5504 qla83xx_idc_unlock(base_vha, 0);
5505 }
5506
5507 /* Work: Execute IDC state handler */
5508 void
qla83xx_idc_state_handler_work(struct work_struct * work)5509 qla83xx_idc_state_handler_work(struct work_struct *work)
5510 {
5511 struct qla_hw_data *ha =
5512 container_of(work, struct qla_hw_data, idc_state_handler);
5513 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5514 uint32_t dev_state = 0;
5515
5516 qla83xx_idc_lock(base_vha, 0);
5517 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5518 if (dev_state == QLA8XXX_DEV_FAILED ||
5519 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5520 qla83xx_idc_state_handler(base_vha);
5521 qla83xx_idc_unlock(base_vha, 0);
5522 }
5523
5524 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5525 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5526 {
5527 int rval = QLA_SUCCESS;
5528 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5529 uint32_t heart_beat_counter1, heart_beat_counter2;
5530
5531 do {
5532 if (time_after(jiffies, heart_beat_wait)) {
5533 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5534 "Nic Core f/w is not alive.\n");
5535 rval = QLA_FUNCTION_FAILED;
5536 break;
5537 }
5538
5539 qla83xx_idc_lock(base_vha, 0);
5540 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5541 &heart_beat_counter1);
5542 qla83xx_idc_unlock(base_vha, 0);
5543 msleep(100);
5544 qla83xx_idc_lock(base_vha, 0);
5545 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5546 &heart_beat_counter2);
5547 qla83xx_idc_unlock(base_vha, 0);
5548 } while (heart_beat_counter1 == heart_beat_counter2);
5549
5550 return rval;
5551 }
5552
5553 /* Work: Perform NIC Core Reset handling */
5554 void
qla83xx_nic_core_reset_work(struct work_struct * work)5555 qla83xx_nic_core_reset_work(struct work_struct *work)
5556 {
5557 struct qla_hw_data *ha =
5558 container_of(work, struct qla_hw_data, nic_core_reset);
5559 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5560 uint32_t dev_state = 0;
5561
5562 if (IS_QLA2031(ha)) {
5563 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5564 ql_log(ql_log_warn, base_vha, 0xb081,
5565 "Failed to dump mctp\n");
5566 return;
5567 }
5568
5569 if (!ha->flags.nic_core_reset_hdlr_active) {
5570 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5571 qla83xx_idc_lock(base_vha, 0);
5572 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5573 &dev_state);
5574 qla83xx_idc_unlock(base_vha, 0);
5575 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5576 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5577 "Nic Core f/w is alive.\n");
5578 return;
5579 }
5580 }
5581
5582 ha->flags.nic_core_reset_hdlr_active = 1;
5583 if (qla83xx_nic_core_reset(base_vha)) {
5584 /* NIC Core reset failed. */
5585 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5586 "NIC Core reset failed.\n");
5587 }
5588 ha->flags.nic_core_reset_hdlr_active = 0;
5589 }
5590 }
5591
5592 /* Work: Handle 8200 IDC aens */
5593 void
qla83xx_service_idc_aen(struct work_struct * work)5594 qla83xx_service_idc_aen(struct work_struct *work)
5595 {
5596 struct qla_hw_data *ha =
5597 container_of(work, struct qla_hw_data, idc_aen);
5598 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5599 uint32_t dev_state, idc_control;
5600
5601 qla83xx_idc_lock(base_vha, 0);
5602 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5603 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5604 qla83xx_idc_unlock(base_vha, 0);
5605 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5606 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5607 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5608 "Application requested NIC Core Reset.\n");
5609 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5610 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5611 QLA_SUCCESS) {
5612 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5613 "Other protocol driver requested NIC Core Reset.\n");
5614 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5615 }
5616 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5617 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5618 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5619 }
5620 }
5621
5622 static void
qla83xx_wait_logic(void)5623 qla83xx_wait_logic(void)
5624 {
5625 int i;
5626
5627 /* Yield CPU */
5628 if (!in_interrupt()) {
5629 /*
5630 * Wait about 200ms before retrying again.
5631 * This controls the number of retries for single
5632 * lock operation.
5633 */
5634 msleep(100);
5635 schedule();
5636 } else {
5637 for (i = 0; i < 20; i++)
5638 cpu_relax(); /* This a nop instr on i386 */
5639 }
5640 }
5641
5642 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5643 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5644 {
5645 int rval;
5646 uint32_t data;
5647 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5648 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5649 struct qla_hw_data *ha = base_vha->hw;
5650
5651 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5652 "Trying force recovery of the IDC lock.\n");
5653
5654 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5655 if (rval)
5656 return rval;
5657
5658 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5659 return QLA_SUCCESS;
5660 } else {
5661 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5662 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5663 data);
5664 if (rval)
5665 return rval;
5666
5667 msleep(200);
5668
5669 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5670 &data);
5671 if (rval)
5672 return rval;
5673
5674 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5675 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5676 ~(idc_lck_rcvry_stage_mask));
5677 rval = qla83xx_wr_reg(base_vha,
5678 QLA83XX_IDC_LOCK_RECOVERY, data);
5679 if (rval)
5680 return rval;
5681
5682 /* Forcefully perform IDC UnLock */
5683 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5684 &data);
5685 if (rval)
5686 return rval;
5687 /* Clear lock-id by setting 0xff */
5688 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5689 0xff);
5690 if (rval)
5691 return rval;
5692 /* Clear lock-recovery by setting 0x0 */
5693 rval = qla83xx_wr_reg(base_vha,
5694 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5695 if (rval)
5696 return rval;
5697 } else
5698 return QLA_SUCCESS;
5699 }
5700
5701 return rval;
5702 }
5703
5704 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5705 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5706 {
5707 int rval = QLA_SUCCESS;
5708 uint32_t o_drv_lockid, n_drv_lockid;
5709 unsigned long lock_recovery_timeout;
5710
5711 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5712 retry_lockid:
5713 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5714 if (rval)
5715 goto exit;
5716
5717 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5718 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5719 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5720 return QLA_SUCCESS;
5721 else
5722 return QLA_FUNCTION_FAILED;
5723 }
5724
5725 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5726 if (rval)
5727 goto exit;
5728
5729 if (o_drv_lockid == n_drv_lockid) {
5730 qla83xx_wait_logic();
5731 goto retry_lockid;
5732 } else
5733 return QLA_SUCCESS;
5734
5735 exit:
5736 return rval;
5737 }
5738
5739 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5740 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5741 {
5742 uint32_t data;
5743 uint32_t lock_owner;
5744 struct qla_hw_data *ha = base_vha->hw;
5745
5746 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5747 retry_lock:
5748 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5749 == QLA_SUCCESS) {
5750 if (data) {
5751 /* Setting lock-id to our function-number */
5752 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5753 ha->portnum);
5754 } else {
5755 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5756 &lock_owner);
5757 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5758 "Failed to acquire IDC lock, acquired by %d, "
5759 "retrying...\n", lock_owner);
5760
5761 /* Retry/Perform IDC-Lock recovery */
5762 if (qla83xx_idc_lock_recovery(base_vha)
5763 == QLA_SUCCESS) {
5764 qla83xx_wait_logic();
5765 goto retry_lock;
5766 } else
5767 ql_log(ql_log_warn, base_vha, 0xb075,
5768 "IDC Lock recovery FAILED.\n");
5769 }
5770
5771 }
5772
5773 return;
5774 }
5775
5776 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)5777 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
5778 struct purex_entry_24xx *purex)
5779 {
5780 char fwstr[16];
5781 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
5782 struct port_database_24xx *pdb;
5783
5784 /* Domain Controller is always logged-out. */
5785 /* if RDP request is not from Domain Controller: */
5786 if (sid != 0xfffc01)
5787 return false;
5788
5789 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
5790
5791 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
5792 if (!pdb) {
5793 ql_dbg(ql_dbg_init, vha, 0x0181,
5794 "%s: Failed allocate pdb\n", __func__);
5795 } else if (qla24xx_get_port_database(vha,
5796 le16_to_cpu(purex->nport_handle), pdb)) {
5797 ql_dbg(ql_dbg_init, vha, 0x0181,
5798 "%s: Failed get pdb sid=%x\n", __func__, sid);
5799 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
5800 pdb->current_login_state != PDS_PRLI_COMPLETE) {
5801 ql_dbg(ql_dbg_init, vha, 0x0181,
5802 "%s: Port not logged in sid=%#x\n", __func__, sid);
5803 } else {
5804 /* RDP request is from logged in port */
5805 kfree(pdb);
5806 return false;
5807 }
5808 kfree(pdb);
5809
5810 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
5811 fwstr[strcspn(fwstr, " ")] = 0;
5812 /* if FW version allows RDP response length upto 2048 bytes: */
5813 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
5814 return false;
5815
5816 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
5817
5818 /* RDP response length is to be reduced to maximum 256 bytes */
5819 return true;
5820 }
5821
5822 /*
5823 * Function Name: qla24xx_process_purex_iocb
5824 *
5825 * Description:
5826 * Prepare a RDP response and send to Fabric switch
5827 *
5828 * PARAMETERS:
5829 * vha: SCSI qla host
5830 * purex: RDP request received by HBA
5831 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)5832 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
5833 struct purex_item *item)
5834 {
5835 struct qla_hw_data *ha = vha->hw;
5836 struct purex_entry_24xx *purex =
5837 (struct purex_entry_24xx *)&item->iocb;
5838 dma_addr_t rsp_els_dma;
5839 dma_addr_t rsp_payload_dma;
5840 dma_addr_t stat_dma;
5841 dma_addr_t sfp_dma;
5842 struct els_entry_24xx *rsp_els = NULL;
5843 struct rdp_rsp_payload *rsp_payload = NULL;
5844 struct link_statistics *stat = NULL;
5845 uint8_t *sfp = NULL;
5846 uint16_t sfp_flags = 0;
5847 uint rsp_payload_length = sizeof(*rsp_payload);
5848 int rval;
5849
5850 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
5851 "%s: Enter\n", __func__);
5852
5853 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
5854 "-------- ELS REQ -------\n");
5855 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
5856 purex, sizeof(*purex));
5857
5858 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
5859 rsp_payload_length =
5860 offsetof(typeof(*rsp_payload), optical_elmt_desc);
5861 ql_dbg(ql_dbg_init, vha, 0x0181,
5862 "Reducing RSP payload length to %u bytes...\n",
5863 rsp_payload_length);
5864 }
5865
5866 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
5867 &rsp_els_dma, GFP_KERNEL);
5868 if (!rsp_els) {
5869 ql_log(ql_log_warn, vha, 0x0183,
5870 "Failed allocate dma buffer ELS RSP.\n");
5871 goto dealloc;
5872 }
5873
5874 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
5875 &rsp_payload_dma, GFP_KERNEL);
5876 if (!rsp_payload) {
5877 ql_log(ql_log_warn, vha, 0x0184,
5878 "Failed allocate dma buffer ELS RSP payload.\n");
5879 goto dealloc;
5880 }
5881
5882 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
5883 &sfp_dma, GFP_KERNEL);
5884
5885 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
5886 &stat_dma, GFP_KERNEL);
5887
5888 /* Prepare Response IOCB */
5889 rsp_els->entry_type = ELS_IOCB_TYPE;
5890 rsp_els->entry_count = 1;
5891 rsp_els->sys_define = 0;
5892 rsp_els->entry_status = 0;
5893 rsp_els->handle = 0;
5894 rsp_els->nport_handle = purex->nport_handle;
5895 rsp_els->tx_dsd_count = cpu_to_le16(1);
5896 rsp_els->vp_index = purex->vp_idx;
5897 rsp_els->sof_type = EST_SOFI3;
5898 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
5899 rsp_els->rx_dsd_count = 0;
5900 rsp_els->opcode = purex->els_frame_payload[0];
5901
5902 rsp_els->d_id[0] = purex->s_id[0];
5903 rsp_els->d_id[1] = purex->s_id[1];
5904 rsp_els->d_id[2] = purex->s_id[2];
5905
5906 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
5907 rsp_els->rx_byte_count = 0;
5908 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
5909
5910 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
5911 rsp_els->tx_len = rsp_els->tx_byte_count;
5912
5913 rsp_els->rx_address = 0;
5914 rsp_els->rx_len = 0;
5915
5916 /* Prepare Response Payload */
5917 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
5918 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
5919 sizeof(rsp_payload->hdr));
5920
5921 /* Link service Request Info Descriptor */
5922 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
5923 rsp_payload->ls_req_info_desc.desc_len =
5924 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
5925 rsp_payload->ls_req_info_desc.req_payload_word_0 =
5926 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
5927
5928 /* Link service Request Info Descriptor 2 */
5929 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
5930 rsp_payload->ls_req_info_desc2.desc_len =
5931 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
5932 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
5933 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
5934
5935
5936 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
5937 rsp_payload->sfp_diag_desc.desc_len =
5938 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
5939
5940 if (sfp) {
5941 /* SFP Flags */
5942 memset(sfp, 0, SFP_RTDI_LEN);
5943 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
5944 if (!rval) {
5945 /* SFP Flags bits 3-0: Port Tx Laser Type */
5946 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
5947 sfp_flags |= BIT_0; /* short wave */
5948 else if (sfp[0] & BIT_1)
5949 sfp_flags |= BIT_1; /* long wave 1310nm */
5950 else if (sfp[1] & BIT_4)
5951 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
5952 }
5953
5954 /* SFP Type */
5955 memset(sfp, 0, SFP_RTDI_LEN);
5956 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
5957 if (!rval) {
5958 sfp_flags |= BIT_4; /* optical */
5959 if (sfp[0] == 0x3)
5960 sfp_flags |= BIT_6; /* sfp+ */
5961 }
5962
5963 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
5964
5965 /* SFP Diagnostics */
5966 memset(sfp, 0, SFP_RTDI_LEN);
5967 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
5968 if (!rval) {
5969 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
5970 rsp_payload->sfp_diag_desc.temperature = trx[0];
5971 rsp_payload->sfp_diag_desc.vcc = trx[1];
5972 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
5973 rsp_payload->sfp_diag_desc.tx_power = trx[3];
5974 rsp_payload->sfp_diag_desc.rx_power = trx[4];
5975 }
5976 }
5977
5978 /* Port Speed Descriptor */
5979 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
5980 rsp_payload->port_speed_desc.desc_len =
5981 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
5982 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
5983 qla25xx_fdmi_port_speed_capability(ha));
5984 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
5985 qla25xx_fdmi_port_speed_currently(ha));
5986
5987 /* Link Error Status Descriptor */
5988 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
5989 rsp_payload->ls_err_desc.desc_len =
5990 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
5991
5992 if (stat) {
5993 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
5994 if (!rval) {
5995 rsp_payload->ls_err_desc.link_fail_cnt =
5996 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
5997 rsp_payload->ls_err_desc.loss_sync_cnt =
5998 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
5999 rsp_payload->ls_err_desc.loss_sig_cnt =
6000 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6001 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6002 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6003 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6004 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6005 rsp_payload->ls_err_desc.inval_crc_cnt =
6006 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6007 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6008 }
6009 }
6010
6011 /* Portname Descriptor */
6012 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6013 rsp_payload->port_name_diag_desc.desc_len =
6014 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6015 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6016 vha->node_name,
6017 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6018 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6019 vha->port_name,
6020 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6021
6022 /* F-Port Portname Descriptor */
6023 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6024 rsp_payload->port_name_direct_desc.desc_len =
6025 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6026 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6027 vha->fabric_node_name,
6028 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6029 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6030 vha->fabric_port_name,
6031 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6032
6033 /* Bufer Credit Descriptor */
6034 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6035 rsp_payload->buffer_credit_desc.desc_len =
6036 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6037 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6038 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6039 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6040
6041 if (ha->flags.plogi_template_valid) {
6042 uint32_t tmp =
6043 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6044 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6045 }
6046
6047 if (rsp_payload_length < sizeof(*rsp_payload))
6048 goto send;
6049
6050 /* Optical Element Descriptor, Temperature */
6051 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6052 rsp_payload->optical_elmt_desc[0].desc_len =
6053 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6054 /* Optical Element Descriptor, Voltage */
6055 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6056 rsp_payload->optical_elmt_desc[1].desc_len =
6057 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6058 /* Optical Element Descriptor, Tx Bias Current */
6059 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6060 rsp_payload->optical_elmt_desc[2].desc_len =
6061 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6062 /* Optical Element Descriptor, Tx Power */
6063 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6064 rsp_payload->optical_elmt_desc[3].desc_len =
6065 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6066 /* Optical Element Descriptor, Rx Power */
6067 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6068 rsp_payload->optical_elmt_desc[4].desc_len =
6069 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6070
6071 if (sfp) {
6072 memset(sfp, 0, SFP_RTDI_LEN);
6073 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6074 if (!rval) {
6075 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6076
6077 /* Optical Element Descriptor, Temperature */
6078 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6079 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6080 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6081 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6082 rsp_payload->optical_elmt_desc[0].element_flags =
6083 cpu_to_be32(1 << 28);
6084
6085 /* Optical Element Descriptor, Voltage */
6086 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6087 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6088 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6089 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6090 rsp_payload->optical_elmt_desc[1].element_flags =
6091 cpu_to_be32(2 << 28);
6092
6093 /* Optical Element Descriptor, Tx Bias Current */
6094 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6095 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6096 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6097 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6098 rsp_payload->optical_elmt_desc[2].element_flags =
6099 cpu_to_be32(3 << 28);
6100
6101 /* Optical Element Descriptor, Tx Power */
6102 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6103 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6104 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6105 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6106 rsp_payload->optical_elmt_desc[3].element_flags =
6107 cpu_to_be32(4 << 28);
6108
6109 /* Optical Element Descriptor, Rx Power */
6110 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6111 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6112 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6113 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6114 rsp_payload->optical_elmt_desc[4].element_flags =
6115 cpu_to_be32(5 << 28);
6116 }
6117
6118 memset(sfp, 0, SFP_RTDI_LEN);
6119 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6120 if (!rval) {
6121 /* Temperature high/low alarm/warning */
6122 rsp_payload->optical_elmt_desc[0].element_flags |=
6123 cpu_to_be32(
6124 (sfp[0] >> 7 & 1) << 3 |
6125 (sfp[0] >> 6 & 1) << 2 |
6126 (sfp[4] >> 7 & 1) << 1 |
6127 (sfp[4] >> 6 & 1) << 0);
6128
6129 /* Voltage high/low alarm/warning */
6130 rsp_payload->optical_elmt_desc[1].element_flags |=
6131 cpu_to_be32(
6132 (sfp[0] >> 5 & 1) << 3 |
6133 (sfp[0] >> 4 & 1) << 2 |
6134 (sfp[4] >> 5 & 1) << 1 |
6135 (sfp[4] >> 4 & 1) << 0);
6136
6137 /* Tx Bias Current high/low alarm/warning */
6138 rsp_payload->optical_elmt_desc[2].element_flags |=
6139 cpu_to_be32(
6140 (sfp[0] >> 3 & 1) << 3 |
6141 (sfp[0] >> 2 & 1) << 2 |
6142 (sfp[4] >> 3 & 1) << 1 |
6143 (sfp[4] >> 2 & 1) << 0);
6144
6145 /* Tx Power high/low alarm/warning */
6146 rsp_payload->optical_elmt_desc[3].element_flags |=
6147 cpu_to_be32(
6148 (sfp[0] >> 1 & 1) << 3 |
6149 (sfp[0] >> 0 & 1) << 2 |
6150 (sfp[4] >> 1 & 1) << 1 |
6151 (sfp[4] >> 0 & 1) << 0);
6152
6153 /* Rx Power high/low alarm/warning */
6154 rsp_payload->optical_elmt_desc[4].element_flags |=
6155 cpu_to_be32(
6156 (sfp[1] >> 7 & 1) << 3 |
6157 (sfp[1] >> 6 & 1) << 2 |
6158 (sfp[5] >> 7 & 1) << 1 |
6159 (sfp[5] >> 6 & 1) << 0);
6160 }
6161 }
6162
6163 /* Optical Product Data Descriptor */
6164 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6165 rsp_payload->optical_prod_desc.desc_len =
6166 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6167
6168 if (sfp) {
6169 memset(sfp, 0, SFP_RTDI_LEN);
6170 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6171 if (!rval) {
6172 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6173 sfp + 0,
6174 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6175 memcpy(rsp_payload->optical_prod_desc.part_number,
6176 sfp + 20,
6177 sizeof(rsp_payload->optical_prod_desc.part_number));
6178 memcpy(rsp_payload->optical_prod_desc.revision,
6179 sfp + 36,
6180 sizeof(rsp_payload->optical_prod_desc.revision));
6181 memcpy(rsp_payload->optical_prod_desc.serial_number,
6182 sfp + 48,
6183 sizeof(rsp_payload->optical_prod_desc.serial_number));
6184 }
6185
6186 memset(sfp, 0, SFP_RTDI_LEN);
6187 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6188 if (!rval) {
6189 memcpy(rsp_payload->optical_prod_desc.date,
6190 sfp + 0,
6191 sizeof(rsp_payload->optical_prod_desc.date));
6192 }
6193 }
6194
6195 send:
6196 ql_dbg(ql_dbg_init, vha, 0x0183,
6197 "Sending ELS Response to RDP Request...\n");
6198 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6199 "-------- ELS RSP -------\n");
6200 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6201 rsp_els, sizeof(*rsp_els));
6202 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6203 "-------- ELS RSP PAYLOAD -------\n");
6204 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6205 rsp_payload, rsp_payload_length);
6206
6207 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6208
6209 if (rval) {
6210 ql_log(ql_log_warn, vha, 0x0188,
6211 "%s: iocb failed to execute -> %x\n", __func__, rval);
6212 } else if (rsp_els->comp_status) {
6213 ql_log(ql_log_warn, vha, 0x0189,
6214 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6215 __func__, rsp_els->comp_status,
6216 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6217 } else {
6218 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6219 }
6220
6221 dealloc:
6222 if (stat)
6223 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6224 stat, stat_dma);
6225 if (sfp)
6226 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6227 sfp, sfp_dma);
6228 if (rsp_payload)
6229 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6230 rsp_payload, rsp_payload_dma);
6231 if (rsp_els)
6232 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6233 rsp_els, rsp_els_dma);
6234 }
6235
6236 void
qla24xx_free_purex_item(struct purex_item * item)6237 qla24xx_free_purex_item(struct purex_item *item)
6238 {
6239 if (item == &item->vha->default_item)
6240 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6241 else
6242 kfree(item);
6243 }
6244
qla24xx_process_purex_list(struct purex_list * list)6245 void qla24xx_process_purex_list(struct purex_list *list)
6246 {
6247 struct list_head head = LIST_HEAD_INIT(head);
6248 struct purex_item *item, *next;
6249 ulong flags;
6250
6251 spin_lock_irqsave(&list->lock, flags);
6252 list_splice_init(&list->head, &head);
6253 spin_unlock_irqrestore(&list->lock, flags);
6254
6255 list_for_each_entry_safe(item, next, &head, list) {
6256 list_del(&item->list);
6257 item->process_item(item->vha, item);
6258 qla24xx_free_purex_item(item);
6259 }
6260 }
6261
6262 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6263 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6264 {
6265 #if 0
6266 uint16_t options = (requester_id << 15) | BIT_7;
6267 #endif
6268 uint16_t retry;
6269 uint32_t data;
6270 struct qla_hw_data *ha = base_vha->hw;
6271
6272 /* IDC-unlock implementation using driver-unlock/lock-id
6273 * remote registers
6274 */
6275 retry = 0;
6276 retry_unlock:
6277 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6278 == QLA_SUCCESS) {
6279 if (data == ha->portnum) {
6280 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6281 /* Clearing lock-id by setting 0xff */
6282 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6283 } else if (retry < 10) {
6284 /* SV: XXX: IDC unlock retrying needed here? */
6285
6286 /* Retry for IDC-unlock */
6287 qla83xx_wait_logic();
6288 retry++;
6289 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6290 "Failed to release IDC lock, retrying=%d\n", retry);
6291 goto retry_unlock;
6292 }
6293 } else if (retry < 10) {
6294 /* Retry for IDC-unlock */
6295 qla83xx_wait_logic();
6296 retry++;
6297 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6298 "Failed to read drv-lockid, retrying=%d\n", retry);
6299 goto retry_unlock;
6300 }
6301
6302 return;
6303
6304 #if 0
6305 /* XXX: IDC-unlock implementation using access-control mbx */
6306 retry = 0;
6307 retry_unlock2:
6308 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6309 if (retry < 10) {
6310 /* Retry for IDC-unlock */
6311 qla83xx_wait_logic();
6312 retry++;
6313 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6314 "Failed to release IDC lock, retrying=%d\n", retry);
6315 goto retry_unlock2;
6316 }
6317 }
6318
6319 return;
6320 #endif
6321 }
6322
6323 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6324 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6325 {
6326 int rval = QLA_SUCCESS;
6327 struct qla_hw_data *ha = vha->hw;
6328 uint32_t drv_presence;
6329
6330 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6331 if (rval == QLA_SUCCESS) {
6332 drv_presence |= (1 << ha->portnum);
6333 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6334 drv_presence);
6335 }
6336
6337 return rval;
6338 }
6339
6340 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6341 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6342 {
6343 int rval = QLA_SUCCESS;
6344
6345 qla83xx_idc_lock(vha, 0);
6346 rval = __qla83xx_set_drv_presence(vha);
6347 qla83xx_idc_unlock(vha, 0);
6348
6349 return rval;
6350 }
6351
6352 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6353 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6354 {
6355 int rval = QLA_SUCCESS;
6356 struct qla_hw_data *ha = vha->hw;
6357 uint32_t drv_presence;
6358
6359 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6360 if (rval == QLA_SUCCESS) {
6361 drv_presence &= ~(1 << ha->portnum);
6362 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6363 drv_presence);
6364 }
6365
6366 return rval;
6367 }
6368
6369 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6370 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6371 {
6372 int rval = QLA_SUCCESS;
6373
6374 qla83xx_idc_lock(vha, 0);
6375 rval = __qla83xx_clear_drv_presence(vha);
6376 qla83xx_idc_unlock(vha, 0);
6377
6378 return rval;
6379 }
6380
6381 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6382 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6383 {
6384 struct qla_hw_data *ha = vha->hw;
6385 uint32_t drv_ack, drv_presence;
6386 unsigned long ack_timeout;
6387
6388 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6389 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6390 while (1) {
6391 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6392 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6393 if ((drv_ack & drv_presence) == drv_presence)
6394 break;
6395
6396 if (time_after_eq(jiffies, ack_timeout)) {
6397 ql_log(ql_log_warn, vha, 0xb067,
6398 "RESET ACK TIMEOUT! drv_presence=0x%x "
6399 "drv_ack=0x%x\n", drv_presence, drv_ack);
6400 /*
6401 * The function(s) which did not ack in time are forced
6402 * to withdraw any further participation in the IDC
6403 * reset.
6404 */
6405 if (drv_ack != drv_presence)
6406 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6407 drv_ack);
6408 break;
6409 }
6410
6411 qla83xx_idc_unlock(vha, 0);
6412 msleep(1000);
6413 qla83xx_idc_lock(vha, 0);
6414 }
6415
6416 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6417 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6418 }
6419
6420 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6421 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6422 {
6423 int rval = QLA_SUCCESS;
6424 uint32_t idc_control;
6425
6426 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6427 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6428
6429 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6430 __qla83xx_get_idc_control(vha, &idc_control);
6431 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6432 __qla83xx_set_idc_control(vha, 0);
6433
6434 qla83xx_idc_unlock(vha, 0);
6435 rval = qla83xx_restart_nic_firmware(vha);
6436 qla83xx_idc_lock(vha, 0);
6437
6438 if (rval != QLA_SUCCESS) {
6439 ql_log(ql_log_fatal, vha, 0xb06a,
6440 "Failed to restart NIC f/w.\n");
6441 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6442 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6443 } else {
6444 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6445 "Success in restarting nic f/w.\n");
6446 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6447 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6448 }
6449
6450 return rval;
6451 }
6452
6453 /* Assumes idc_lock always held on entry */
6454 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6455 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6456 {
6457 struct qla_hw_data *ha = base_vha->hw;
6458 int rval = QLA_SUCCESS;
6459 unsigned long dev_init_timeout;
6460 uint32_t dev_state;
6461
6462 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6463 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6464
6465 while (1) {
6466
6467 if (time_after_eq(jiffies, dev_init_timeout)) {
6468 ql_log(ql_log_warn, base_vha, 0xb06e,
6469 "Initialization TIMEOUT!\n");
6470 /* Init timeout. Disable further NIC Core
6471 * communication.
6472 */
6473 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6474 QLA8XXX_DEV_FAILED);
6475 ql_log(ql_log_info, base_vha, 0xb06f,
6476 "HW State: FAILED.\n");
6477 }
6478
6479 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6480 switch (dev_state) {
6481 case QLA8XXX_DEV_READY:
6482 if (ha->flags.nic_core_reset_owner)
6483 qla83xx_idc_audit(base_vha,
6484 IDC_AUDIT_COMPLETION);
6485 ha->flags.nic_core_reset_owner = 0;
6486 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6487 "Reset_owner reset by 0x%x.\n",
6488 ha->portnum);
6489 goto exit;
6490 case QLA8XXX_DEV_COLD:
6491 if (ha->flags.nic_core_reset_owner)
6492 rval = qla83xx_device_bootstrap(base_vha);
6493 else {
6494 /* Wait for AEN to change device-state */
6495 qla83xx_idc_unlock(base_vha, 0);
6496 msleep(1000);
6497 qla83xx_idc_lock(base_vha, 0);
6498 }
6499 break;
6500 case QLA8XXX_DEV_INITIALIZING:
6501 /* Wait for AEN to change device-state */
6502 qla83xx_idc_unlock(base_vha, 0);
6503 msleep(1000);
6504 qla83xx_idc_lock(base_vha, 0);
6505 break;
6506 case QLA8XXX_DEV_NEED_RESET:
6507 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6508 qla83xx_need_reset_handler(base_vha);
6509 else {
6510 /* Wait for AEN to change device-state */
6511 qla83xx_idc_unlock(base_vha, 0);
6512 msleep(1000);
6513 qla83xx_idc_lock(base_vha, 0);
6514 }
6515 /* reset timeout value after need reset handler */
6516 dev_init_timeout = jiffies +
6517 (ha->fcoe_dev_init_timeout * HZ);
6518 break;
6519 case QLA8XXX_DEV_NEED_QUIESCENT:
6520 /* XXX: DEBUG for now */
6521 qla83xx_idc_unlock(base_vha, 0);
6522 msleep(1000);
6523 qla83xx_idc_lock(base_vha, 0);
6524 break;
6525 case QLA8XXX_DEV_QUIESCENT:
6526 /* XXX: DEBUG for now */
6527 if (ha->flags.quiesce_owner)
6528 goto exit;
6529
6530 qla83xx_idc_unlock(base_vha, 0);
6531 msleep(1000);
6532 qla83xx_idc_lock(base_vha, 0);
6533 dev_init_timeout = jiffies +
6534 (ha->fcoe_dev_init_timeout * HZ);
6535 break;
6536 case QLA8XXX_DEV_FAILED:
6537 if (ha->flags.nic_core_reset_owner)
6538 qla83xx_idc_audit(base_vha,
6539 IDC_AUDIT_COMPLETION);
6540 ha->flags.nic_core_reset_owner = 0;
6541 __qla83xx_clear_drv_presence(base_vha);
6542 qla83xx_idc_unlock(base_vha, 0);
6543 qla8xxx_dev_failed_handler(base_vha);
6544 rval = QLA_FUNCTION_FAILED;
6545 qla83xx_idc_lock(base_vha, 0);
6546 goto exit;
6547 case QLA8XXX_BAD_VALUE:
6548 qla83xx_idc_unlock(base_vha, 0);
6549 msleep(1000);
6550 qla83xx_idc_lock(base_vha, 0);
6551 break;
6552 default:
6553 ql_log(ql_log_warn, base_vha, 0xb071,
6554 "Unknown Device State: %x.\n", dev_state);
6555 qla83xx_idc_unlock(base_vha, 0);
6556 qla8xxx_dev_failed_handler(base_vha);
6557 rval = QLA_FUNCTION_FAILED;
6558 qla83xx_idc_lock(base_vha, 0);
6559 goto exit;
6560 }
6561 }
6562
6563 exit:
6564 return rval;
6565 }
6566
6567 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6568 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6569 {
6570 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6571 board_disable);
6572 struct pci_dev *pdev = ha->pdev;
6573 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6574
6575 ql_log(ql_log_warn, base_vha, 0x015b,
6576 "Disabling adapter.\n");
6577
6578 if (!atomic_read(&pdev->enable_cnt)) {
6579 ql_log(ql_log_info, base_vha, 0xfffc,
6580 "PCI device disabled, no action req for PCI error=%lx\n",
6581 base_vha->pci_flags);
6582 return;
6583 }
6584
6585 /*
6586 * if UNLOADING flag is already set, then continue unload,
6587 * where it was set first.
6588 */
6589 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6590 return;
6591
6592 qla2x00_wait_for_sess_deletion(base_vha);
6593
6594 qla2x00_delete_all_vps(ha, base_vha);
6595
6596 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6597
6598 qla2x00_dfs_remove(base_vha);
6599
6600 qla84xx_put_chip(base_vha);
6601
6602 if (base_vha->timer_active)
6603 qla2x00_stop_timer(base_vha);
6604
6605 base_vha->flags.online = 0;
6606
6607 qla2x00_destroy_deferred_work(ha);
6608
6609 /*
6610 * Do not try to stop beacon blink as it will issue a mailbox
6611 * command.
6612 */
6613 qla2x00_free_sysfs_attr(base_vha, false);
6614
6615 fc_remove_host(base_vha->host);
6616
6617 scsi_remove_host(base_vha->host);
6618
6619 base_vha->flags.init_done = 0;
6620 qla25xx_delete_queues(base_vha);
6621 qla2x00_free_fcports(base_vha);
6622 qla2x00_free_irqs(base_vha);
6623 qla2x00_mem_free(ha);
6624 qla82xx_md_free(base_vha);
6625 qla2x00_free_queues(ha);
6626
6627 qla2x00_unmap_iobases(ha);
6628
6629 pci_release_selected_regions(ha->pdev, ha->bars);
6630 pci_disable_pcie_error_reporting(pdev);
6631 pci_disable_device(pdev);
6632
6633 /*
6634 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6635 */
6636 }
6637
6638 /**************************************************************************
6639 * qla2x00_do_dpc
6640 * This kernel thread is a task that is schedule by the interrupt handler
6641 * to perform the background processing for interrupts.
6642 *
6643 * Notes:
6644 * This task always run in the context of a kernel thread. It
6645 * is kick-off by the driver's detect code and starts up
6646 * up one per adapter. It immediately goes to sleep and waits for
6647 * some fibre event. When either the interrupt handler or
6648 * the timer routine detects a event it will one of the task
6649 * bits then wake us up.
6650 **************************************************************************/
6651 static int
qla2x00_do_dpc(void * data)6652 qla2x00_do_dpc(void *data)
6653 {
6654 scsi_qla_host_t *base_vha;
6655 struct qla_hw_data *ha;
6656 uint32_t online;
6657 struct qla_qpair *qpair;
6658
6659 ha = (struct qla_hw_data *)data;
6660 base_vha = pci_get_drvdata(ha->pdev);
6661
6662 set_user_nice(current, MIN_NICE);
6663
6664 set_current_state(TASK_INTERRUPTIBLE);
6665 while (!kthread_should_stop()) {
6666 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6667 "DPC handler sleeping.\n");
6668
6669 schedule();
6670
6671 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6672 goto end_loop;
6673
6674 if (ha->flags.eeh_busy) {
6675 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6676 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6677 goto end_loop;
6678 }
6679
6680 ha->dpc_active = 1;
6681
6682 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6683 "DPC handler waking up, dpc_flags=0x%lx.\n",
6684 base_vha->dpc_flags);
6685
6686 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6687 break;
6688
6689 if (IS_P3P_TYPE(ha)) {
6690 if (IS_QLA8044(ha)) {
6691 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6692 &base_vha->dpc_flags)) {
6693 qla8044_idc_lock(ha);
6694 qla8044_wr_direct(base_vha,
6695 QLA8044_CRB_DEV_STATE_INDEX,
6696 QLA8XXX_DEV_FAILED);
6697 qla8044_idc_unlock(ha);
6698 ql_log(ql_log_info, base_vha, 0x4004,
6699 "HW State: FAILED.\n");
6700 qla8044_device_state_handler(base_vha);
6701 continue;
6702 }
6703
6704 } else {
6705 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6706 &base_vha->dpc_flags)) {
6707 qla82xx_idc_lock(ha);
6708 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6709 QLA8XXX_DEV_FAILED);
6710 qla82xx_idc_unlock(ha);
6711 ql_log(ql_log_info, base_vha, 0x0151,
6712 "HW State: FAILED.\n");
6713 qla82xx_device_state_handler(base_vha);
6714 continue;
6715 }
6716 }
6717
6718 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6719 &base_vha->dpc_flags)) {
6720
6721 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6722 "FCoE context reset scheduled.\n");
6723 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6724 &base_vha->dpc_flags))) {
6725 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6726 /* FCoE-ctx reset failed.
6727 * Escalate to chip-reset
6728 */
6729 set_bit(ISP_ABORT_NEEDED,
6730 &base_vha->dpc_flags);
6731 }
6732 clear_bit(ABORT_ISP_ACTIVE,
6733 &base_vha->dpc_flags);
6734 }
6735
6736 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6737 "FCoE context reset end.\n");
6738 }
6739 } else if (IS_QLAFX00(ha)) {
6740 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6741 &base_vha->dpc_flags)) {
6742 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6743 "Firmware Reset Recovery\n");
6744 if (qlafx00_reset_initialize(base_vha)) {
6745 /* Failed. Abort isp later. */
6746 if (!test_bit(UNLOADING,
6747 &base_vha->dpc_flags)) {
6748 set_bit(ISP_UNRECOVERABLE,
6749 &base_vha->dpc_flags);
6750 ql_dbg(ql_dbg_dpc, base_vha,
6751 0x4021,
6752 "Reset Recovery Failed\n");
6753 }
6754 }
6755 }
6756
6757 if (test_and_clear_bit(FX00_TARGET_SCAN,
6758 &base_vha->dpc_flags)) {
6759 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6760 "ISPFx00 Target Scan scheduled\n");
6761 if (qlafx00_rescan_isp(base_vha)) {
6762 if (!test_bit(UNLOADING,
6763 &base_vha->dpc_flags))
6764 set_bit(ISP_UNRECOVERABLE,
6765 &base_vha->dpc_flags);
6766 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6767 "ISPFx00 Target Scan Failed\n");
6768 }
6769 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6770 "ISPFx00 Target Scan End\n");
6771 }
6772 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6773 &base_vha->dpc_flags)) {
6774 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6775 "ISPFx00 Host Info resend scheduled\n");
6776 qlafx00_fx_disc(base_vha,
6777 &base_vha->hw->mr.fcport,
6778 FXDISC_REG_HOST_INFO);
6779 }
6780 }
6781
6782 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6783 &base_vha->dpc_flags)) {
6784 /* Semantic:
6785 * - NO-OP -- await next ISP-ABORT. Preferred method
6786 * to minimize disruptions that will occur
6787 * when a forced chip-reset occurs.
6788 * - Force -- ISP-ABORT scheduled.
6789 */
6790 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
6791 }
6792
6793 if (test_and_clear_bit
6794 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6795 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6796 bool do_reset = true;
6797
6798 switch (base_vha->qlini_mode) {
6799 case QLA2XXX_INI_MODE_ENABLED:
6800 break;
6801 case QLA2XXX_INI_MODE_DISABLED:
6802 if (!qla_tgt_mode_enabled(base_vha) &&
6803 !ha->flags.fw_started)
6804 do_reset = false;
6805 break;
6806 case QLA2XXX_INI_MODE_DUAL:
6807 if (!qla_dual_mode_enabled(base_vha) &&
6808 !ha->flags.fw_started)
6809 do_reset = false;
6810 break;
6811 default:
6812 break;
6813 }
6814
6815 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
6816 &base_vha->dpc_flags))) {
6817 base_vha->flags.online = 1;
6818 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6819 "ISP abort scheduled.\n");
6820 if (ha->isp_ops->abort_isp(base_vha)) {
6821 /* failed. retry later */
6822 set_bit(ISP_ABORT_NEEDED,
6823 &base_vha->dpc_flags);
6824 }
6825 clear_bit(ABORT_ISP_ACTIVE,
6826 &base_vha->dpc_flags);
6827 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6828 "ISP abort end.\n");
6829 }
6830 }
6831
6832 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
6833 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
6834 qla24xx_process_purex_list
6835 (&base_vha->purex_list);
6836 clear_bit(PROCESS_PUREX_IOCB,
6837 &base_vha->dpc_flags);
6838 }
6839 }
6840
6841 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6842 &base_vha->dpc_flags)) {
6843 qla2x00_update_fcports(base_vha);
6844 }
6845
6846 if (IS_QLAFX00(ha))
6847 goto loop_resync_check;
6848
6849 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
6850 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6851 "Quiescence mode scheduled.\n");
6852 if (IS_P3P_TYPE(ha)) {
6853 if (IS_QLA82XX(ha))
6854 qla82xx_device_state_handler(base_vha);
6855 if (IS_QLA8044(ha))
6856 qla8044_device_state_handler(base_vha);
6857 clear_bit(ISP_QUIESCE_NEEDED,
6858 &base_vha->dpc_flags);
6859 if (!ha->flags.quiesce_owner) {
6860 qla2x00_perform_loop_resync(base_vha);
6861 if (IS_QLA82XX(ha)) {
6862 qla82xx_idc_lock(ha);
6863 qla82xx_clear_qsnt_ready(
6864 base_vha);
6865 qla82xx_idc_unlock(ha);
6866 } else if (IS_QLA8044(ha)) {
6867 qla8044_idc_lock(ha);
6868 qla8044_clear_qsnt_ready(
6869 base_vha);
6870 qla8044_idc_unlock(ha);
6871 }
6872 }
6873 } else {
6874 clear_bit(ISP_QUIESCE_NEEDED,
6875 &base_vha->dpc_flags);
6876 qla2x00_quiesce_io(base_vha);
6877 }
6878 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6879 "Quiescence mode end.\n");
6880 }
6881
6882 if (test_and_clear_bit(RESET_MARKER_NEEDED,
6883 &base_vha->dpc_flags) &&
6884 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
6885
6886 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6887 "Reset marker scheduled.\n");
6888 qla2x00_rst_aen(base_vha);
6889 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
6890 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6891 "Reset marker end.\n");
6892 }
6893
6894 /* Retry each device up to login retry count */
6895 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
6896 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6897 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
6898
6899 if (!base_vha->relogin_jif ||
6900 time_after_eq(jiffies, base_vha->relogin_jif)) {
6901 base_vha->relogin_jif = jiffies + HZ;
6902 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6903
6904 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
6905 "Relogin scheduled.\n");
6906 qla24xx_post_relogin_work(base_vha);
6907 }
6908 }
6909 loop_resync_check:
6910 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
6911 &base_vha->dpc_flags)) {
6912
6913 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6914 "Loop resync scheduled.\n");
6915
6916 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
6917 &base_vha->dpc_flags))) {
6918
6919 qla2x00_loop_resync(base_vha);
6920
6921 clear_bit(LOOP_RESYNC_ACTIVE,
6922 &base_vha->dpc_flags);
6923 }
6924
6925 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6926 "Loop resync end.\n");
6927 }
6928
6929 if (IS_QLAFX00(ha))
6930 goto intr_on_check;
6931
6932 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6933 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6934 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6935 qla2xxx_flash_npiv_conf(base_vha);
6936 }
6937
6938 intr_on_check:
6939 if (!ha->interrupts_on)
6940 ha->isp_ops->enable_intrs(ha);
6941
6942 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
6943 &base_vha->dpc_flags)) {
6944 if (ha->beacon_blink_led == 1)
6945 ha->isp_ops->beacon_blink(base_vha);
6946 }
6947
6948 /* qpair online check */
6949 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6950 &base_vha->dpc_flags)) {
6951 if (ha->flags.eeh_busy ||
6952 ha->flags.pci_channel_io_perm_failure)
6953 online = 0;
6954 else
6955 online = 1;
6956
6957 mutex_lock(&ha->mq_lock);
6958 list_for_each_entry(qpair, &base_vha->qp_list,
6959 qp_list_elem)
6960 qpair->online = online;
6961 mutex_unlock(&ha->mq_lock);
6962 }
6963
6964 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6965 &base_vha->dpc_flags)) {
6966 ql_log(ql_log_info, base_vha, 0xffffff,
6967 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6968 ha->nvme_last_rptd_aen);
6969 if (qla27xx_set_zio_threshold(base_vha,
6970 ha->nvme_last_rptd_aen)) {
6971 ql_log(ql_log_info, base_vha, 0xffffff,
6972 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6973 ha->nvme_last_rptd_aen);
6974 }
6975 }
6976
6977 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6978 &base_vha->dpc_flags)) {
6979 ql_log(ql_log_info, base_vha, 0xffffff,
6980 "SET ZIO Activity exchange threshold to %d.\n",
6981 ha->last_zio_threshold);
6982 qla27xx_set_zio_threshold(base_vha,
6983 ha->last_zio_threshold);
6984 }
6985
6986 if (!IS_QLAFX00(ha))
6987 qla2x00_do_dpc_all_vps(base_vha);
6988
6989 if (test_and_clear_bit(N2N_LINK_RESET,
6990 &base_vha->dpc_flags)) {
6991 qla2x00_lip_reset(base_vha);
6992 }
6993
6994 ha->dpc_active = 0;
6995 end_loop:
6996 set_current_state(TASK_INTERRUPTIBLE);
6997 } /* End of while(1) */
6998 __set_current_state(TASK_RUNNING);
6999
7000 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7001 "DPC handler exiting.\n");
7002
7003 /*
7004 * Make sure that nobody tries to wake us up again.
7005 */
7006 ha->dpc_active = 0;
7007
7008 /* Cleanup any residual CTX SRBs. */
7009 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7010
7011 return 0;
7012 }
7013
7014 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7015 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7016 {
7017 struct qla_hw_data *ha = vha->hw;
7018 struct task_struct *t = ha->dpc_thread;
7019
7020 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7021 wake_up_process(t);
7022 }
7023
7024 /*
7025 * qla2x00_rst_aen
7026 * Processes asynchronous reset.
7027 *
7028 * Input:
7029 * ha = adapter block pointer.
7030 */
7031 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7032 qla2x00_rst_aen(scsi_qla_host_t *vha)
7033 {
7034 if (vha->flags.online && !vha->flags.reset_active &&
7035 !atomic_read(&vha->loop_down_timer) &&
7036 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7037 do {
7038 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7039
7040 /*
7041 * Issue marker command only when we are going to start
7042 * the I/O.
7043 */
7044 vha->marker_needed = 1;
7045 } while (!atomic_read(&vha->loop_down_timer) &&
7046 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7047 }
7048 }
7049
7050 /**************************************************************************
7051 * qla2x00_timer
7052 *
7053 * Description:
7054 * One second timer
7055 *
7056 * Context: Interrupt
7057 ***************************************************************************/
7058 void
qla2x00_timer(struct timer_list * t)7059 qla2x00_timer(struct timer_list *t)
7060 {
7061 scsi_qla_host_t *vha = from_timer(vha, t, timer);
7062 unsigned long cpu_flags = 0;
7063 int start_dpc = 0;
7064 int index;
7065 srb_t *sp;
7066 uint16_t w;
7067 struct qla_hw_data *ha = vha->hw;
7068 struct req_que *req;
7069
7070 if (ha->flags.eeh_busy) {
7071 ql_dbg(ql_dbg_timer, vha, 0x6000,
7072 "EEH = %d, restarting timer.\n",
7073 ha->flags.eeh_busy);
7074 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7075 return;
7076 }
7077
7078 /*
7079 * Hardware read to raise pending EEH errors during mailbox waits. If
7080 * the read returns -1 then disable the board.
7081 */
7082 if (!pci_channel_offline(ha->pdev)) {
7083 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7084 qla2x00_check_reg16_for_disconnect(vha, w);
7085 }
7086
7087 /* Make sure qla82xx_watchdog is run only for physical port */
7088 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7089 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7090 start_dpc++;
7091 if (IS_QLA82XX(ha))
7092 qla82xx_watchdog(vha);
7093 else if (IS_QLA8044(ha))
7094 qla8044_watchdog(vha);
7095 }
7096
7097 if (!vha->vp_idx && IS_QLAFX00(ha))
7098 qlafx00_timer_routine(vha);
7099
7100 /* Loop down handler. */
7101 if (atomic_read(&vha->loop_down_timer) > 0 &&
7102 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7103 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7104 && vha->flags.online) {
7105
7106 if (atomic_read(&vha->loop_down_timer) ==
7107 vha->loop_down_abort_time) {
7108
7109 ql_log(ql_log_info, vha, 0x6008,
7110 "Loop down - aborting the queues before time expires.\n");
7111
7112 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7113 atomic_set(&vha->loop_state, LOOP_DEAD);
7114
7115 /*
7116 * Schedule an ISP abort to return any FCP2-device
7117 * commands.
7118 */
7119 /* NPIV - scan physical port only */
7120 if (!vha->vp_idx) {
7121 spin_lock_irqsave(&ha->hardware_lock,
7122 cpu_flags);
7123 req = ha->req_q_map[0];
7124 for (index = 1;
7125 index < req->num_outstanding_cmds;
7126 index++) {
7127 fc_port_t *sfcp;
7128
7129 sp = req->outstanding_cmds[index];
7130 if (!sp)
7131 continue;
7132 if (sp->cmd_type != TYPE_SRB)
7133 continue;
7134 if (sp->type != SRB_SCSI_CMD)
7135 continue;
7136 sfcp = sp->fcport;
7137 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7138 continue;
7139
7140 if (IS_QLA82XX(ha))
7141 set_bit(FCOE_CTX_RESET_NEEDED,
7142 &vha->dpc_flags);
7143 else
7144 set_bit(ISP_ABORT_NEEDED,
7145 &vha->dpc_flags);
7146 break;
7147 }
7148 spin_unlock_irqrestore(&ha->hardware_lock,
7149 cpu_flags);
7150 }
7151 start_dpc++;
7152 }
7153
7154 /* if the loop has been down for 4 minutes, reinit adapter */
7155 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7156 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7157 ql_log(ql_log_warn, vha, 0x6009,
7158 "Loop down - aborting ISP.\n");
7159
7160 if (IS_QLA82XX(ha))
7161 set_bit(FCOE_CTX_RESET_NEEDED,
7162 &vha->dpc_flags);
7163 else
7164 set_bit(ISP_ABORT_NEEDED,
7165 &vha->dpc_flags);
7166 }
7167 }
7168 ql_dbg(ql_dbg_timer, vha, 0x600a,
7169 "Loop down - seconds remaining %d.\n",
7170 atomic_read(&vha->loop_down_timer));
7171 }
7172 /* Check if beacon LED needs to be blinked for physical host only */
7173 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7174 /* There is no beacon_blink function for ISP82xx */
7175 if (!IS_P3P_TYPE(ha)) {
7176 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7177 start_dpc++;
7178 }
7179 }
7180
7181 /* Process any deferred work. */
7182 if (!list_empty(&vha->work_list)) {
7183 unsigned long flags;
7184 bool q = false;
7185
7186 spin_lock_irqsave(&vha->work_lock, flags);
7187 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7188 q = true;
7189 spin_unlock_irqrestore(&vha->work_lock, flags);
7190 if (q)
7191 queue_work(vha->hw->wq, &vha->iocb_work);
7192 }
7193
7194 /*
7195 * FC-NVME
7196 * see if the active AEN count has changed from what was last reported.
7197 */
7198 index = atomic_read(&ha->nvme_active_aen_cnt);
7199 if (!vha->vp_idx &&
7200 (index != ha->nvme_last_rptd_aen) &&
7201 (index >= DEFAULT_ZIO_THRESHOLD) &&
7202 ha->zio_mode == QLA_ZIO_MODE_6 &&
7203 !ha->flags.host_shutting_down) {
7204 ql_log(ql_log_info, vha, 0x3002,
7205 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7206 ha->nvme_last_rptd_aen);
7207 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7208 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7209 start_dpc++;
7210 }
7211
7212 if (!vha->vp_idx &&
7213 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7214 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7215 ql_log(ql_log_info, vha, 0x3002,
7216 "Sched: Set ZIO exchange threshold to %d.\n",
7217 ha->last_zio_threshold);
7218 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7219 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7220 start_dpc++;
7221 }
7222
7223 /* Schedule the DPC routine if needed */
7224 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7225 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7226 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
7227 start_dpc ||
7228 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7229 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7230 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7231 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7232 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7233 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7234 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7235 ql_dbg(ql_dbg_timer, vha, 0x600b,
7236 "isp_abort_needed=%d loop_resync_needed=%d "
7237 "fcport_update_needed=%d start_dpc=%d "
7238 "reset_marker_needed=%d",
7239 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7240 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7241 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
7242 start_dpc,
7243 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7244 ql_dbg(ql_dbg_timer, vha, 0x600c,
7245 "beacon_blink_needed=%d isp_unrecoverable=%d "
7246 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7247 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7248 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7249 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7250 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7251 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7252 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7253 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7254 qla2xxx_wake_dpc(vha);
7255 }
7256
7257 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7258 }
7259
7260 /* Firmware interface routines. */
7261
7262 #define FW_ISP21XX 0
7263 #define FW_ISP22XX 1
7264 #define FW_ISP2300 2
7265 #define FW_ISP2322 3
7266 #define FW_ISP24XX 4
7267 #define FW_ISP25XX 5
7268 #define FW_ISP81XX 6
7269 #define FW_ISP82XX 7
7270 #define FW_ISP2031 8
7271 #define FW_ISP8031 9
7272 #define FW_ISP27XX 10
7273 #define FW_ISP28XX 11
7274
7275 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7276 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7277 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7278 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7279 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7280 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7281 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7282 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7283 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7284 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7285 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7286 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7287
7288
7289 static DEFINE_MUTEX(qla_fw_lock);
7290
7291 static struct fw_blob qla_fw_blobs[] = {
7292 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7293 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7294 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7295 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7296 { .name = FW_FILE_ISP24XX, },
7297 { .name = FW_FILE_ISP25XX, },
7298 { .name = FW_FILE_ISP81XX, },
7299 { .name = FW_FILE_ISP82XX, },
7300 { .name = FW_FILE_ISP2031, },
7301 { .name = FW_FILE_ISP8031, },
7302 { .name = FW_FILE_ISP27XX, },
7303 { .name = FW_FILE_ISP28XX, },
7304 { .name = NULL, },
7305 };
7306
7307 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7308 qla2x00_request_firmware(scsi_qla_host_t *vha)
7309 {
7310 struct qla_hw_data *ha = vha->hw;
7311 struct fw_blob *blob;
7312
7313 if (IS_QLA2100(ha)) {
7314 blob = &qla_fw_blobs[FW_ISP21XX];
7315 } else if (IS_QLA2200(ha)) {
7316 blob = &qla_fw_blobs[FW_ISP22XX];
7317 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7318 blob = &qla_fw_blobs[FW_ISP2300];
7319 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7320 blob = &qla_fw_blobs[FW_ISP2322];
7321 } else if (IS_QLA24XX_TYPE(ha)) {
7322 blob = &qla_fw_blobs[FW_ISP24XX];
7323 } else if (IS_QLA25XX(ha)) {
7324 blob = &qla_fw_blobs[FW_ISP25XX];
7325 } else if (IS_QLA81XX(ha)) {
7326 blob = &qla_fw_blobs[FW_ISP81XX];
7327 } else if (IS_QLA82XX(ha)) {
7328 blob = &qla_fw_blobs[FW_ISP82XX];
7329 } else if (IS_QLA2031(ha)) {
7330 blob = &qla_fw_blobs[FW_ISP2031];
7331 } else if (IS_QLA8031(ha)) {
7332 blob = &qla_fw_blobs[FW_ISP8031];
7333 } else if (IS_QLA27XX(ha)) {
7334 blob = &qla_fw_blobs[FW_ISP27XX];
7335 } else if (IS_QLA28XX(ha)) {
7336 blob = &qla_fw_blobs[FW_ISP28XX];
7337 } else {
7338 return NULL;
7339 }
7340
7341 if (!blob->name)
7342 return NULL;
7343
7344 mutex_lock(&qla_fw_lock);
7345 if (blob->fw)
7346 goto out;
7347
7348 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7349 ql_log(ql_log_warn, vha, 0x0063,
7350 "Failed to load firmware image (%s).\n", blob->name);
7351 blob->fw = NULL;
7352 blob = NULL;
7353 }
7354
7355 out:
7356 mutex_unlock(&qla_fw_lock);
7357 return blob;
7358 }
7359
7360 static void
qla2x00_release_firmware(void)7361 qla2x00_release_firmware(void)
7362 {
7363 struct fw_blob *blob;
7364
7365 mutex_lock(&qla_fw_lock);
7366 for (blob = qla_fw_blobs; blob->name; blob++)
7367 release_firmware(blob->fw);
7368 mutex_unlock(&qla_fw_lock);
7369 }
7370
qla_pci_error_cleanup(scsi_qla_host_t * vha)7371 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7372 {
7373 struct qla_hw_data *ha = vha->hw;
7374 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7375 struct qla_qpair *qpair = NULL;
7376 struct scsi_qla_host *vp;
7377 fc_port_t *fcport;
7378 int i;
7379 unsigned long flags;
7380
7381 ha->chip_reset++;
7382
7383 ha->base_qpair->chip_reset = ha->chip_reset;
7384 for (i = 0; i < ha->max_qpairs; i++) {
7385 if (ha->queue_pair_map[i])
7386 ha->queue_pair_map[i]->chip_reset =
7387 ha->base_qpair->chip_reset;
7388 }
7389
7390 /* purge MBox commands */
7391 if (atomic_read(&ha->num_pend_mbx_stage3)) {
7392 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
7393 complete(&ha->mbx_intr_comp);
7394 }
7395
7396 i = 0;
7397
7398 while (atomic_read(&ha->num_pend_mbx_stage3) ||
7399 atomic_read(&ha->num_pend_mbx_stage2) ||
7400 atomic_read(&ha->num_pend_mbx_stage1)) {
7401 msleep(20);
7402 i++;
7403 if (i > 50)
7404 break;
7405 }
7406
7407 ha->flags.purge_mbox = 0;
7408
7409 mutex_lock(&ha->mq_lock);
7410 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7411 qpair->online = 0;
7412 mutex_unlock(&ha->mq_lock);
7413
7414 qla2x00_mark_all_devices_lost(vha);
7415
7416 spin_lock_irqsave(&ha->vport_slock, flags);
7417 list_for_each_entry(vp, &ha->vp_list, list) {
7418 atomic_inc(&vp->vref_count);
7419 spin_unlock_irqrestore(&ha->vport_slock, flags);
7420 qla2x00_mark_all_devices_lost(vp);
7421 spin_lock_irqsave(&ha->vport_slock, flags);
7422 atomic_dec(&vp->vref_count);
7423 }
7424 spin_unlock_irqrestore(&ha->vport_slock, flags);
7425
7426 /* Clear all async request states across all VPs. */
7427 list_for_each_entry(fcport, &vha->vp_fcports, list)
7428 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7429
7430 spin_lock_irqsave(&ha->vport_slock, flags);
7431 list_for_each_entry(vp, &ha->vp_list, list) {
7432 atomic_inc(&vp->vref_count);
7433 spin_unlock_irqrestore(&ha->vport_slock, flags);
7434 list_for_each_entry(fcport, &vp->vp_fcports, list)
7435 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7436 spin_lock_irqsave(&ha->vport_slock, flags);
7437 atomic_dec(&vp->vref_count);
7438 }
7439 spin_unlock_irqrestore(&ha->vport_slock, flags);
7440 }
7441
7442
7443 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7444 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7445 {
7446 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7447 struct qla_hw_data *ha = vha->hw;
7448
7449 ql_dbg(ql_dbg_aer, vha, 0x9000,
7450 "PCI error detected, state %x.\n", state);
7451
7452 if (!atomic_read(&pdev->enable_cnt)) {
7453 ql_log(ql_log_info, vha, 0xffff,
7454 "PCI device is disabled,state %x\n", state);
7455 return PCI_ERS_RESULT_NEED_RESET;
7456 }
7457
7458 switch (state) {
7459 case pci_channel_io_normal:
7460 ha->flags.eeh_busy = 0;
7461 if (ql2xmqsupport || ql2xnvmeenable) {
7462 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7463 qla2xxx_wake_dpc(vha);
7464 }
7465 return PCI_ERS_RESULT_CAN_RECOVER;
7466 case pci_channel_io_frozen:
7467 ha->flags.eeh_busy = 1;
7468 qla_pci_error_cleanup(vha);
7469 return PCI_ERS_RESULT_NEED_RESET;
7470 case pci_channel_io_perm_failure:
7471 ha->flags.pci_channel_io_perm_failure = 1;
7472 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7473 if (ql2xmqsupport || ql2xnvmeenable) {
7474 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7475 qla2xxx_wake_dpc(vha);
7476 }
7477 return PCI_ERS_RESULT_DISCONNECT;
7478 }
7479 return PCI_ERS_RESULT_NEED_RESET;
7480 }
7481
7482 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7483 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7484 {
7485 int risc_paused = 0;
7486 uint32_t stat;
7487 unsigned long flags;
7488 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7489 struct qla_hw_data *ha = base_vha->hw;
7490 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7491 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7492
7493 if (IS_QLA82XX(ha))
7494 return PCI_ERS_RESULT_RECOVERED;
7495
7496 spin_lock_irqsave(&ha->hardware_lock, flags);
7497 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7498 stat = rd_reg_word(®->hccr);
7499 if (stat & HCCR_RISC_PAUSE)
7500 risc_paused = 1;
7501 } else if (IS_QLA23XX(ha)) {
7502 stat = rd_reg_dword(®->u.isp2300.host_status);
7503 if (stat & HSR_RISC_PAUSED)
7504 risc_paused = 1;
7505 } else if (IS_FWI2_CAPABLE(ha)) {
7506 stat = rd_reg_dword(®24->host_status);
7507 if (stat & HSRX_RISC_PAUSED)
7508 risc_paused = 1;
7509 }
7510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7511
7512 if (risc_paused) {
7513 ql_log(ql_log_info, base_vha, 0x9003,
7514 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7515 qla2xxx_dump_fw(base_vha);
7516
7517 return PCI_ERS_RESULT_NEED_RESET;
7518 } else
7519 return PCI_ERS_RESULT_RECOVERED;
7520 }
7521
7522 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7523 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7524 {
7525 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7526 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7527 struct qla_hw_data *ha = base_vha->hw;
7528 int rc;
7529 struct qla_qpair *qpair = NULL;
7530
7531 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7532 "Slot Reset.\n");
7533
7534 /* Workaround: qla2xxx driver which access hardware earlier
7535 * needs error state to be pci_channel_io_online.
7536 * Otherwise mailbox command timesout.
7537 */
7538 pdev->error_state = pci_channel_io_normal;
7539
7540 pci_restore_state(pdev);
7541
7542 /* pci_restore_state() clears the saved_state flag of the device
7543 * save restored state which resets saved_state flag
7544 */
7545 pci_save_state(pdev);
7546
7547 if (ha->mem_only)
7548 rc = pci_enable_device_mem(pdev);
7549 else
7550 rc = pci_enable_device(pdev);
7551
7552 if (rc) {
7553 ql_log(ql_log_warn, base_vha, 0x9005,
7554 "Can't re-enable PCI device after reset.\n");
7555 goto exit_slot_reset;
7556 }
7557
7558
7559 if (ha->isp_ops->pci_config(base_vha))
7560 goto exit_slot_reset;
7561
7562 mutex_lock(&ha->mq_lock);
7563 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7564 qpair->online = 1;
7565 mutex_unlock(&ha->mq_lock);
7566
7567 base_vha->flags.online = 1;
7568 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7569 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
7570 ret = PCI_ERS_RESULT_RECOVERED;
7571 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7572
7573
7574 exit_slot_reset:
7575 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7576 "slot_reset return %x.\n", ret);
7577
7578 return ret;
7579 }
7580
7581 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7582 qla2xxx_pci_resume(struct pci_dev *pdev)
7583 {
7584 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7585 struct qla_hw_data *ha = base_vha->hw;
7586 int ret;
7587
7588 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7589 "pci_resume.\n");
7590
7591 ha->flags.eeh_busy = 0;
7592
7593 ret = qla2x00_wait_for_hba_online(base_vha);
7594 if (ret != QLA_SUCCESS) {
7595 ql_log(ql_log_fatal, base_vha, 0x9002,
7596 "The device failed to resume I/O from slot/link_reset.\n");
7597 }
7598 }
7599
7600 static void
qla_pci_reset_prepare(struct pci_dev * pdev)7601 qla_pci_reset_prepare(struct pci_dev *pdev)
7602 {
7603 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7604 struct qla_hw_data *ha = base_vha->hw;
7605 struct qla_qpair *qpair;
7606
7607 ql_log(ql_log_warn, base_vha, 0xffff,
7608 "%s.\n", __func__);
7609
7610 /*
7611 * PCI FLR/function reset is about to reset the
7612 * slot. Stop the chip to stop all DMA access.
7613 * It is assumed that pci_reset_done will be called
7614 * after FLR to resume Chip operation.
7615 */
7616 ha->flags.eeh_busy = 1;
7617 mutex_lock(&ha->mq_lock);
7618 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7619 qpair->online = 0;
7620 mutex_unlock(&ha->mq_lock);
7621
7622 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7623 qla2x00_abort_isp_cleanup(base_vha);
7624 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7625 }
7626
7627 static void
qla_pci_reset_done(struct pci_dev * pdev)7628 qla_pci_reset_done(struct pci_dev *pdev)
7629 {
7630 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7631 struct qla_hw_data *ha = base_vha->hw;
7632 struct qla_qpair *qpair;
7633
7634 ql_log(ql_log_warn, base_vha, 0xffff,
7635 "%s.\n", __func__);
7636
7637 /*
7638 * FLR just completed by PCI layer. Resume adapter
7639 */
7640 ha->flags.eeh_busy = 0;
7641 mutex_lock(&ha->mq_lock);
7642 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7643 qpair->online = 1;
7644 mutex_unlock(&ha->mq_lock);
7645
7646 base_vha->flags.online = 1;
7647 ha->isp_ops->abort_isp(base_vha);
7648 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7649 }
7650
qla2xxx_map_queues(struct Scsi_Host * shost)7651 static int qla2xxx_map_queues(struct Scsi_Host *shost)
7652 {
7653 int rc;
7654 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
7655 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
7656
7657 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
7658 rc = blk_mq_map_queues(qmap);
7659 else
7660 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
7661 return rc;
7662 }
7663
7664 struct scsi_host_template qla2xxx_driver_template = {
7665 .module = THIS_MODULE,
7666 .name = QLA2XXX_DRIVER_NAME,
7667 .queuecommand = qla2xxx_queuecommand,
7668
7669 .eh_timed_out = fc_eh_timed_out,
7670 .eh_abort_handler = qla2xxx_eh_abort,
7671 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7672 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7673 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7674 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7675
7676 .slave_configure = qla2xxx_slave_configure,
7677
7678 .slave_alloc = qla2xxx_slave_alloc,
7679 .slave_destroy = qla2xxx_slave_destroy,
7680 .scan_finished = qla2xxx_scan_finished,
7681 .scan_start = qla2xxx_scan_start,
7682 .change_queue_depth = scsi_change_queue_depth,
7683 .map_queues = qla2xxx_map_queues,
7684 .this_id = -1,
7685 .cmd_per_lun = 3,
7686 .sg_tablesize = SG_ALL,
7687
7688 .max_sectors = 0xFFFF,
7689 .shost_attrs = qla2x00_host_attrs,
7690
7691 .supported_mode = MODE_INITIATOR,
7692 .track_queue_depth = 1,
7693 .cmd_size = sizeof(srb_t),
7694 };
7695
7696 static const struct pci_error_handlers qla2xxx_err_handler = {
7697 .error_detected = qla2xxx_pci_error_detected,
7698 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7699 .slot_reset = qla2xxx_pci_slot_reset,
7700 .resume = qla2xxx_pci_resume,
7701 .reset_prepare = qla_pci_reset_prepare,
7702 .reset_done = qla_pci_reset_done,
7703 };
7704
7705 static struct pci_device_id qla2xxx_pci_tbl[] = {
7706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
7715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
7716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
7718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
7719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
7720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
7721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
7722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
7723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
7725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
7726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
7727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
7728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7730 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7731 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7732 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
7733 { 0 },
7734 };
7735 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7736
7737 static struct pci_driver qla2xxx_pci_driver = {
7738 .name = QLA2XXX_DRIVER_NAME,
7739 .driver = {
7740 .owner = THIS_MODULE,
7741 },
7742 .id_table = qla2xxx_pci_tbl,
7743 .probe = qla2x00_probe_one,
7744 .remove = qla2x00_remove_one,
7745 .shutdown = qla2x00_shutdown,
7746 .err_handler = &qla2xxx_err_handler,
7747 };
7748
7749 static const struct file_operations apidev_fops = {
7750 .owner = THIS_MODULE,
7751 .llseek = noop_llseek,
7752 };
7753
7754 /**
7755 * qla2x00_module_init - Module initialization.
7756 **/
7757 static int __init
qla2x00_module_init(void)7758 qla2x00_module_init(void)
7759 {
7760 int ret = 0;
7761
7762 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
7763 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7764 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7765 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7766 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7767 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
7768 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7769 BUILD_BUG_ON(sizeof(request_t) != 64);
7770 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
7771 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
7772 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
7773 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7774 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
7775 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7776 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7777 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7778 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7779 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7780 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7781 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7782 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344);
7783 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
7784 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
7785 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
7786 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
7787 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
7788 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7789 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
7790 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
7791 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
7792 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
7793 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
7794 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7795 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
7796 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7797 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
7798 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7799 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7800 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
7801 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
7802 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
7803 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
7804 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
7805 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
7806 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7807 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
7808 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
7809 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
7810 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
7811 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
7812 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
7813 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
7814 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
7815 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
7816 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
7817 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
7818 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
7819 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
7820 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
7821 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
7822 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
7823 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
7824 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
7825 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
7826 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
7827 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
7828 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
7829 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
7830 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7831 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
7832 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
7833 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
7834 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7835 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
7836 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7837 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
7838 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
7839 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
7840 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
7841 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
7842 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
7843 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
7844 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
7845 BUILD_BUG_ON(sizeof(target_id_t) != 2);
7846
7847 /* Allocate cache for SRBs. */
7848 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
7849 SLAB_HWCACHE_ALIGN, NULL);
7850 if (srb_cachep == NULL) {
7851 ql_log(ql_log_fatal, NULL, 0x0001,
7852 "Unable to allocate SRB cache...Failing load!.\n");
7853 return -ENOMEM;
7854 }
7855
7856 /* Initialize target kmem_cache and mem_pools */
7857 ret = qlt_init();
7858 if (ret < 0) {
7859 goto destroy_cache;
7860 } else if (ret > 0) {
7861 /*
7862 * If initiator mode is explictly disabled by qlt_init(),
7863 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7864 * performing scsi_scan_target() during LOOP UP event.
7865 */
7866 qla2xxx_transport_functions.disable_target_scan = 1;
7867 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7868 }
7869
7870 /* Derive version string. */
7871 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
7872 if (ql2xextended_error_logging)
7873 strcat(qla2x00_version_str, "-debug");
7874 if (ql2xextended_error_logging == 1)
7875 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
7876
7877 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7878 qla_insert_tgt_attrs();
7879
7880 qla2xxx_transport_template =
7881 fc_attach_transport(&qla2xxx_transport_functions);
7882 if (!qla2xxx_transport_template) {
7883 ql_log(ql_log_fatal, NULL, 0x0002,
7884 "fc_attach_transport failed...Failing load!.\n");
7885 ret = -ENODEV;
7886 goto qlt_exit;
7887 }
7888
7889 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7890 if (apidev_major < 0) {
7891 ql_log(ql_log_fatal, NULL, 0x0003,
7892 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
7893 }
7894
7895 qla2xxx_transport_vport_template =
7896 fc_attach_transport(&qla2xxx_transport_vport_functions);
7897 if (!qla2xxx_transport_vport_template) {
7898 ql_log(ql_log_fatal, NULL, 0x0004,
7899 "fc_attach_transport vport failed...Failing load!.\n");
7900 ret = -ENODEV;
7901 goto unreg_chrdev;
7902 }
7903 ql_log(ql_log_info, NULL, 0x0005,
7904 "QLogic Fibre Channel HBA Driver: %s.\n",
7905 qla2x00_version_str);
7906 ret = pci_register_driver(&qla2xxx_pci_driver);
7907 if (ret) {
7908 ql_log(ql_log_fatal, NULL, 0x0006,
7909 "pci_register_driver failed...ret=%d Failing load!.\n",
7910 ret);
7911 goto release_vport_transport;
7912 }
7913 return ret;
7914
7915 release_vport_transport:
7916 fc_release_transport(qla2xxx_transport_vport_template);
7917
7918 unreg_chrdev:
7919 if (apidev_major >= 0)
7920 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7921 fc_release_transport(qla2xxx_transport_template);
7922
7923 qlt_exit:
7924 qlt_exit();
7925
7926 destroy_cache:
7927 kmem_cache_destroy(srb_cachep);
7928 return ret;
7929 }
7930
7931 /**
7932 * qla2x00_module_exit - Module cleanup.
7933 **/
7934 static void __exit
qla2x00_module_exit(void)7935 qla2x00_module_exit(void)
7936 {
7937 pci_unregister_driver(&qla2xxx_pci_driver);
7938 qla2x00_release_firmware();
7939 kmem_cache_destroy(ctx_cachep);
7940 fc_release_transport(qla2xxx_transport_vport_template);
7941 if (apidev_major >= 0)
7942 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7943 fc_release_transport(qla2xxx_transport_template);
7944 qlt_exit();
7945 kmem_cache_destroy(srb_cachep);
7946 }
7947
7948 module_init(qla2x00_module_init);
7949 module_exit(qla2x00_module_exit);
7950
7951 MODULE_AUTHOR("QLogic Corporation");
7952 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7953 MODULE_LICENSE("GPL");
7954 MODULE_FIRMWARE(FW_FILE_ISP21XX);
7955 MODULE_FIRMWARE(FW_FILE_ISP22XX);
7956 MODULE_FIRMWARE(FW_FILE_ISP2300);
7957 MODULE_FIRMWARE(FW_FILE_ISP2322);
7958 MODULE_FIRMWARE(FW_FILE_ISP24XX);
7959 MODULE_FIRMWARE(FW_FILE_ISP25XX);
7960